8051 microcontroller tutorial

Traffic light controller - Interfacing 8255 with 8085 | 8085 Lab Program

noreply@blogger.com (belgaumboy) — Sat, 3 Oct 2026 00:00:00 +0530

Section: Hardware Interfacing Experiments

Aim: To design a traffic light controller using the 8085 microprocessor through the Programmable Peripheral Interface 8255.

Apparatus Required: 8085 µp kit, 8255 Interface board, DC regulated power supply, VXT parallel bus, Traffic light controller interface board.

Algorithm:

Start.
Write the control word to initialize the 8255 IC. Obtain the signal data for each direction and store it in memory.
Initialize a counter to indicate the number of directions.
Initialize the HL pair to the starting address of the data.
Send the control/status data to the ports.
Call a delay subroutine between signal switching.
Decrement the counter and repeat the process for all directions.

Program:

Address	Label	Mnemonics	Operand	Comment
4100		LXI	H, Data	Load the data starting address in HL register pair
4103		MVI	C, 04	Move 04 to C register for 4 directions
4105		MOV	A, M	Move control word to Accumulator
4106		OUT	CNT	Send control word to control register
4108		INX	H	Increment HL pair
4109	LOOP1	MOV	A, M	Move Port C signal data to Accumulator
410A		OUT	CPRT	Send status word to Port C
410C		INX	H	Increment HL pair
410D		MOV	A, M	Move Port B signal data to Accumulator
410E		OUT	BPRT	Send status word to Port B
4110		INX	H	Increment HL pair
4111		MOV	A, M	Move Port A signal data to Accumulator
4112		OUT	APRT	Send status word to Port A
4114		CALL	DELAY	Call delay subroutine
4117		INX	H	Increment HL pair
4118		DCR	C	Decrement direction counter C
4119		JNZ	LOOP1	Jump to LOOP1 if counter is non-zero
411C		JMP	START	Repeat traffic cycle
411F	DELAY	PUSH	B	Push BC register pair onto stack
4120		MVI	C, 0D	Move 0D to C register
4122	LOOP3	LXI	D, FFFFH	Load DE pair with FFFFH
4125	LOOP2	DCX	D	Decrement DE pair
4126		MOV	A, D	Copy D to Accumulator
4127		ORA	E	OR Accumulator with E
4128		JNZ	LOOP2	Loop until DE becomes 0
412C		JNZ	LOOP3	Loop until C becomes 0
412F		POP	B	Pop BC pair from stack
4130		RET		Return to main program

Observation:

Mode 0 (Simple I/O) control word is sent to initialize Ports A, B, and C as output ports.
Output signals are sent sequentially to Port A, Port B, and Port C to illuminate Red, Yellow, and Green LEDs for four traffic directions with designated delay intervals.

Result: Thus the design of traffic light controller using 8085 microprocessor through programmable peripheral interface 8255 is done and the output is verified.

Flowchart:

               +-------------------+
               |       START       |
               +---------+---------+
                         |
                         v
               +-------------------+
               | Initialize 8255   |
               | Write Control Word|
               +---------+---------+
                         |
                         v
               +-------------------+
               | Load Data Pointer |
               |   [HL] <- Data    |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [C] <- 04H     |
               | (4 Directions)    |
               +---------+---------+
                         |
                         v <-------------------+
               +-------------------+           |
               | Output Signals to |           |
               | Ports C, B, and A |           |
               +---------+---------+           |
                         |                     |
                         v                     |
               +-------------------+           |
               |   Call Delay      |           |
               |   Subroutine      |           |
               +---------+---------+           |
                         |                     |
                         v                     |
               +-------------------+           |
               |   [C] <- [C] - 1  |           |
               +---------+---------+           |
                         |                     |
                         v                     |
                       /   \                   |
                     /  Is   \                 |
                   /  [C] = 0? \               |
                  <             >              |
                   \ Is zero?  / --- NO -------+
                     \       /
                       \   /
                        | YES
                        v
               +-------------------+
               | Jump to START     |
               | (Continuous Loop) |
               +-------------------+

Viva Questions:

When the 8255 is reset, its I/O ports are all initialized as what?
If the programmable counter timer 8254 is set in mode 1 and is to be used to count six events, the output will remain at logic 0 for how many number of counts?
The devices that provide the means for a computer to communicate with the user or other computers are referred to as what?
What is the maximum number of I/O devices which can be interfaced in the memory-mapped I/O technique?
Interaction between a CPU and a peripheral device that takes place during an input/output operation is known as what?
What is the other name for Programmable Peripheral Input-Output port?
All the functions of the ports of 8255 are achieved by programming the bits of an internal register called what?
What is the port that is used for the generation of handshake lines in Mode 1 or Mode 2?
What is the pin that clears the control word register of 8255 when enabled?
In 8255, if A1 = 0 and A0 = 1, then from where is the input read cycle performed?

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

ASCII to Hexadecimal conversion | 8085 Lab Program

noreply@blogger.com (belgaumboy) — Fri, 2 Oct 2026 00:00:00 +0530

Section: Array Operations & Code Conversions

Aim: To write an assembly language program to convert the given ASCII number into its Hexadecimal equivalent and to verify the result.

Apparatus Required: 8085 microprocessor kit, keyboard.

Algorithm:

Step 1: Load the ASCII number from the location.
Step 2: Check for the digit or alphabet.
Step 3: Using suitable logic and instructions convert the ASCII number into Hexadecimal.
Step 4: Add the two converted values.
Step 5: Display the result.
Step 6: Stop.

Program:

Address	Label	Mnemonics	Operand	Comment
4100		LDA	4500	Load the memory content to Accumulator
4103		SUI	30	Subtract with 30
4105		CPI	0A	Compare with 0A
4107		JC	SKP	If carry skip
410A		SUI	07	Subtract with 07
410C	SKP	STA	4201	Store Accumulator content
410F		HLT		Stop

Observation:

Input:
- Address 4200: 41
Output:
- Address 4201: 0A

Result: Thus assembly language program to convert the given ASCII number into its Hexadecimal equivalent is completed and also the result is verified.

Flowchart:

               +-------------------------------+
               |             START             |
               +---------------+---------------+
                               |
                               v
               +-------------------------------+
               |     Load the ASCII number     |
               +---------------+---------------+
                               |
                               v
               +-------------------------------+
               |  Convert ASCII into Hexa-     |
               |      decimal equivalent       |
               +---------------+---------------+
                               |
                               v
               +-------------------------------+
               |      Display the result       |
               +---------------+---------------+
                               |
                               v
               +-------------------------------+
               |             STOP              |
               +-------------------------------+

Viva Questions:

What is the Hexadecimal for (35) ASCII?
What is the purpose of branch instructions in 8085 microprocessor?
Define one’s complement of an 8-bit numbers.
What is the function of CMA instruction?
What is the logic behind the conversion of ASCII number into Hexadecimal number?
Give example for Machine control instruction?
What is the need of code conversion?

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

Hexadecimal to ASCII conversion | 8085 Lab Program

noreply@blogger.com (belgaumboy) — Thu, 1 Oct 2026 00:00:00 +0530

Section: Array Operations & Code Conversions

Aim: To write an assembly language program to convert the given Hexadecimal number into its ASCII equivalent and to verify the result.

Apparatus Required: 8085 microprocessor kit, keyboard.

Algorithm:

Load the Hexadecimal number from the location.
Separate the nibbles.
Convert each nibble to its ASCII Equivalent.
Add the two converted values.
Display the result.
Stop.

Program:

Address	Label	Mnemonics	Operand	Comment
4100		LDA	4200	Get the data
4103		MOV	B, A	Move Accumulator content to B reg
4104		ANI	0F	Mask upper nibble
4106		CALL	SUB	Get ASCII code for upper nibble
4109		STA	4201	Store the value of accumulator
410B		MOV	A, B	Move B reg content to Acc
410D		ANI	F0	Mask lower nibble
410F		RLC		Rotate left without carry 4 times
4110		RLC
4111		RLC
4112		RLC
4113		CALL	SUB	Get the ASCII code
4116		STA	4202	Store the accumulator
4119		HLT		Stop
411A	SUB	CPI	0A	Compare with 0A
411C		JC	SKP	Skip if carry
411F		ADI	07	Add 07 to Acc
4121	SKP	ADI	30	Add 30 to Acc
4123		RET		Return

Observation:

Input:
- Address 4200: A5
Output:
- Address 4201: 35
- Address 4202: 41

Result: Thus assembly language program to convert the given Hexadecimal number into its ASCII equivalent is completed and also the result is verified.

Flowchart:

               +-------------------------------+
               |             START             |
               +---------------+---------------+
                               |
                               v
               +-------------------------------+
               |  Load the Hexadecimal number  |
               +---------------+---------------+
                               |
                               v
               +-------------------------------+
               |   Convert each nibble into    |
               |       ASCII equivalent        |
               +---------------+---------------+
                               |
                               v
               +-------------------------------+
               |      Display the result       |
               +---------------+---------------+
                               |
                               v
               +-------------------------------+
               |             STOP              |
               +-------------------------------+

Viva Questions:

What is ASCII number for 0AH?
What is difference between byte and word?
What is the immediate addressing mode?
What are data transfer instructions?
What is the use of immediate addressing mode?
What are branching instructions?
What is DMA?

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

Hexadecimal to Decimal conversion | 8085 Lab Program

noreply@blogger.com (belgaumboy) — Wed, 30 Sep 2026 00:00:00 +0530

Section: Array Operations & Code Conversions

Aim: To convert a given hexadecimal number to decimal number and also to verify the result.

Apparatus Required: 8085 microprocessor kit, key board.

Algorithm:

Initialize the memory location to the data pointer.
Increment B register.
Increment accumulator by 1 and adjust it to decimal every time.
Compare the given hexadecimal number with B register value.
When both match, the equivalent decimal value is in A register.
Store the resultant in memory location.

Program:

Address	Label	Mnemonics	Operand	Comment
4100		LXI	H, 4200	Initialize HL reg. to 4200H
4103		MVI	A, 00	Initialize A register
4105		MVI	B, 00	Initialize B register
4107		MVI	C, 00	Initialize C register for carry
4109	LOOP	INR	B	Increment B reg
410A		ADI	01	Increment A reg
410C		DAA		Decimal Adjust Accumulator
410D		JNC	NEXT	If there is no carry go to NEXT
4110		INR	C	Increment C register
4111	NEXT	MOV	D, A	Transfer A to D
4112		MOV	A, B	Transfer B to A
4113		CMP	M	Compare M & A
4114		MOV	A, D	Transfer D to A
4115		JNZ	LOOP	If acc and given number are not equal, then go to LOOP
4118		STA	4201	Store the result in a memory location
411B		MOV	A, C	Transfer C to A
411C		STA	4202	Store the carry in another memory location
411F		HLT		Stop the program

Observation:

Input:
- Address 4200: D5
Output:
- Address 4201: 13
- Address 4202: 02

Result: Thus an ALP program for conversion of hexadecimal to decimal was executed and the result is verified.

Flowchart:

               +-------------------+
               |       START       |
               +---------+---------+
                         |
                         v
               +-------------------+
               |   [HL] <- 4200H   |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [A] <- 00H     |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [B] <- 00H     |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [C] <- 00H     |
               +---------+---------+
                         |
                         v <------------------+
               +-------------------+          |
               |   [B] <- [B] + 1  |          |
               +---------+---------+          |
                         |                    |
                         v                    |
               +-------------------+          |
               |   [A] <- [A] + 1  |          |
               +---------+---------+          |
                         |                    |
                         v                    |
               +-------------------+          |
               |   Decimal Adjust  |          |
               |    Accumulator    |          |
               +---------+---------+          |
                         |                    |
                         v                    |
                       /   \                  |
                     /  Is   \                |
                   /  there a  \              |
                  <   Carry?   >              |
                   \  (CY = 1) /              |
                     \      /                 |
                       \  /                   |
                        |                     |
            +-----------+-----------+         |
            |                       |         |
           YES                      NO        |
            |                       |         |
            v                       |         |
  +-------------------+             |         |
  |   [C] <- [C] + 1  |             |         |
  +---------+---------+             |         |
            |                       |         |
            +-----------+-----------+         |
                        |                     |
                        v                     |
              +-------------------+           |
              |    [D] <- [A]     |           |
              |    [A] <- [B]     |           |
              +---------+---------+           |
                        |                     |
                        v                     |
                      /   \                   |
                    /  Is   \                 |
                  /   [A] =   \               |
                 <    [M]?     >              |
                  \           /               |
                    \       /                 |
                      \   /                   |
                       |                      |
           +-----------+------------+         |
           |                        |         |
          YES                       NO        |
           |                        +---------+
           v
 +-------------------+
 |    <- [A]         |
 |    [A] <- [C]     |
 |    <- [A]         |
 +---------+---------+
           |
           v
 +-------------------+
 |       STOP        |
 +-------------------+

Viva Questions:

What is meant by instruction DAA?
Why data bus is bi-directional?
Specifies the function of address bus and the direction of address bus?
How many memory location can be addressed by a microprocessor with the 14 address lines?
List various instructions that can be used to clear accumulator in 8085?
When the Ready signal of 8085 is sampled by the processor?
List out the similarities b/w the CALL_RET and PUSH_POP instructions?

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

Decimal to Hexadecimal conversion | 8085 Lab Program

noreply@blogger.com (belgaumboy) — Tue, 29 Sep 2026 00:00:00 +0530

Section: Array Operations & Code Conversions

Aim: To convert a given decimal number to hexadecimal number.

Apparatus Required: 8085 microprocessor kit, key board.

Algorithm:

Initialize the memory location to the data pointer.
Increment B register.
Increment accumulator by 1 and adjust it to decimal every time.
Compare the given decimal number with accumulator value.
When both matches, the equivalent hexadecimal value is in B register.
Store the resultant in memory location.

Program:

Address	Label	Mnemonics	Operand	Comment
4100		LXI	H, 4200	Initialize HL reg. to 4200H
4103		MVI	A, 00	Initialize A register
4105		MVI	B, 00	Initialize B register
4107	LOOP	INR	B	Increment B reg.
4108		ADI	01	Increment A reg
410A		DAA		Decimal Adjust Accumulator
410B		CMP	M	Compare M & A
410C		JNZ	LOOP	If acc and given number are not equal, then go to LOOP
410F		MOV	A, B	Transfer B reg to acc
4110		STA	4201	Store the result in a memory location
4113		HLT		Stop the program

Observation:

Input: Address 4200: 21
Output: Address 4201: 15

Result: Thus an ALP program for conversion of decimal to hexadecimal was written and executed.

Flowchart:

               +-------------------+
               |       START       |
               +---------+---------+
                         |
                         v
               +-------------------+
               |   [HL] <- 4200H   |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [A] <- 00H     |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [B] <- 00H     |
               +---------+---------+
                         |
                         v <------------------+
               +-------------------+          |
               |   [B] <- [B] + 1  |          |
               +---------+---------+          |
                         |                    |
                         v                    |
               +-------------------+          |
               |   [A] <- [A] + 1  |          |
               +---------+---------+          |
                         |                    |
                         v                    |
               +-------------------+          |
               |   Decimal Adjust  |          |
               |    Accumulator    |          |
               +---------+---------+          |
                         |                    |
                         v                    |
                       /   \                  |
                     /  Is   \                |
                   /   [A] =   \              |
                  <    [M]?     >             |
                   \           /              |
                     \       /                |
                       \   /                  |
                        |                     |
            +-----------+------------+        |
            |                        |        |
           YES                       NO       |
            |                        +--------+
            v
  +-------------------+
  |    [A] <- [B]     |
  +---------+---------+
            |
            v
  +-------------------+
  |     <- [A]  |
  +---------+---------+
            |
            v
  +-------------------+
  |       STOP        |
  +-------------------+

Viva Questions:

What is meant by ADI instruction?
What is the function of DAA instruction?
What is the function of XCHG instruction?
How you can load 16-bit data in 8500H and 8501H memory locations?
What is the difference between LHLD and SHLD instructions?
What is physical address?
Define OFFSET address.

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

Sorting an array of data in Descending order | 8085 Lab Program

noreply@blogger.com (belgaumboy) — Mon, 28 Sep 2026 00:00:00 +0530

Section: Array Operations & Code Conversions

Aim: To sort the given numbers in the descending order using 8085 microprocessor.

Apparatus Required: 8085 microprocessor kit, key board.

Algorithm:

Get the numbers to be sorted from the memory locations.
Compare the first two numbers and if the first number is smaller than second then interchange the number.
If the first number is larger, go to step 4.
Repeat steps 2 and 3 until the numbers are in required order.

Program:

Address	Label	Mnemonics	Operand	Comment
4100		MVI	B, 04	Initialize B reg with number of comparisons (n-1)
4102	LOOP3	LXI	H, 4200	Initialize HL reg. to 4200H
4105		MVI	C, 04	Initialize C reg with no. of comparisons (n-1)
4107	LOOP2	MOV	A, M	Transfer first data to acc.
4108		INX	H	Increment HL reg. to point next memory location
4109		CMP	M	Compare M & A
410A		JNC	LOOP1	If A is greater than M then go to loop1
410D		MOV	D, M	Transfer data from M to D reg
410E		MOV	M, A	Transfer data from acc to M
410F		DCX	H	Decrement HL pair
4110		MOV	M, D	Transfer data from D to M
4111		INX	H	Increment HL pair
4112	LOOP1	DCR	C	Decrement C reg
4113		JNZ	LOOP2	If C is not zero go to loop2
4116		DCR	B	Decrement B reg
4117		JNZ	LOOP3	If B is not Zero go to loop3
4118		HLT		Stop the program

Observation:

Input:
- Address 4200: 01
- Address 4201: 06
- Address 4202: 03
- Address 4203: 07
- Address 4204: 02
Output:
- Address 4200: 07
- Address 4201: 06
- Address 4202: 03
- Address 4203: 02
- Address 4204: 01

Result: Thus the descending order program is executed and the numbers are arranged in descending order.

Flowchart:

               +-------------------+
               |       START       |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [B] <- 04H     |
               +---------+---------+
                         |
                         v
               +-------------------+
               |   [HL] <- 4200H   |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [C] <- 04H     |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [A] <- [M]     |
               +---------+---------+
                         |
                         v
               +-------------------+
               |  [HL] <- [HL] + 1 |
               +---------+---------+
                         |
                         v
                       /   \
                     /  Is   \
                   / [A] >= [M]?\
                  <  (CY = 0)   >
                   \           /
                     \       /
                       \   /
                        |
            +-----------+------------+
            |                        |
           YES                       NO
            |                        |
            |                        v
            |              +-------------------+
            |              |    [D] <- [M]     |
            |              |    [M] <- [A]     |
            |              |  [HL] <- [HL] - 1 |
            |              |    [M] <- [D]     |
            |              |  [HL] <- [HL] + 1 |
            |              +---------+---------+
            |                        |
            +-----------+------------+
                        |
                        v
              +-------------------+
              |   [C] <- [C] - 1  |
              +---------+---------+
                        |
                        v
                      /   \
                    /  Is   \
                  /  [C] = 0? \
                 <            >
                  \ Is zero? / --- NO ---> (To LOOP2)
                    \      /
                      \  /
                       | YES
                       v
              +-------------------+
              |   [B] <- [B] - 1  |
              +---------+---------+
                        |
                        v
                      /   \
                    /  Is   \
                  /  [B] = 0? \
                 <            >
                  \ Is zero? / --- NO ---> (To LOOP3)
                    \      /
                      \  /
                       | YES
                       v
              +-------------------+
              |       STOP        |
              +-------------------+

Viva Questions:

Give out the purpose of the instruction DCX.
What is meant by CALL instruction?.
Briefly give out the LHLD instruction.
State the logic behind the Sorting an array of data in Descending order.
Name the various flag bits available in 8085 microprocessor?.
Give the significance of SIM and RIM instructions available in 8085?.
How do the address and data lines are demultiplexed in 8085?.

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

Sorting an array of data in Ascending order | 8085 Lab Program

noreply@blogger.com (belgaumboy) — Sun, 27 Sep 2026 00:00:00 +0530

Section: Array Operations & Code Conversions

Aim: To sort the given numbers in the ascending order using 8085 microprocessor.

Apparatus Required: 8085 microprocessor kit, key board.

Algorithm:

Get the numbers to be sorted from the memory locations.
Compare the first two numbers and if the first number is larger than the second, then interchange the numbers.
If the first number is smaller, go to step 4.
Repeat steps 2 and 3 until the numbers are in the required order.

Program:

Address	Label	Mnemonics	Operand	Comment
4100		MVI	B, 04	Initialize B reg with number of comparisons (n-1)
4102	LOOP3	LXI	H, 4200	Initialize HL reg. to 4200H
4105		MVI	C, 04	Initialize C reg with no. of comparisons (n-1)
4107	LOOP2	MOV	A, M	Transfer first data to acc.
4108		INX	H	Increment HL reg. to point next memory location
4109		CMP	M	Compare M & A
410A		JC	LOOP1	If A is less than M then go to loop1
410D		MOV	D, M	Transfer data from M to D reg
410E		MOV	M, A	Transfer data from acc to M
410F		DCX	H	Decrement HL pair
4110		MOV	M, D	Transfer data from D to M
4111		INX	H	Increment HL pair
4112	LOOP1	DCR	C	Decrement C reg
4113		JNZ	LOOP2	If C is not zero go to loop2
4116		DCR	B	Decrement B reg
4117		JNZ	LOOP3	If B is not Zero go to loop3
4118		HLT		Stop the program

Observation:

Input:
- Address 4200: 01
- Address 4201: 06
- Address 4202: 03
- Address 4203: 07
- Address 4204: 02
Output:
- Address 4200: 01
- Address 4201: 02
- Address 4202: 03
- Address 4203: 06
- Address 4204: 07

Result: Thus the ascending order program is executed and the numbers are arranged in ascending order.

Flowchart:

                  +-------------------+
                  |       START       |
                  +---------+---------+
                            |
                            v
                  +-------------------+
                  |    [B] <- 04H     |
                  +---------+---------+
                            |
                            v <-------------------------------+
                  +-------------------+                       |
                  |   [HL] <- 4200H   |                       |
                  +---------+---------+                       |
                            |                                 |
                            v                                 |
                  +-------------------+                       |
                  |    [C] <- 04H     |                       |
                  +---------+---------+                       |
                            |                                 |
                            v <-------------------+           |
                  +-------------------+           |           |
                  |    [A] <- [M]     |           |           |
                  +---------+---------+           |           |
                            |                     |           |
                            v                     |           |
                  +-------------------+           |           |
                  |  [HL] <- [HL] + 1 |           |           |
                  +---------+---------+           |           |
                            |                     |           |
                            v                     |           |
                          /   \                   |           |
                        /  Is   \                 |           |
                      / [A] < [M]?\               |           |
                     <  (CY = 1)   >              |           |
                      \           /               |           |
                        \       /                 |           |
                          \   /                   |           |
                            |                     |           |
               +------------+------------+        |           |
               |                         |        |           |
              YES                        NO       |           |
               |                         |        |           |
               |                         v        |           |
               |               +-------------------+          |
               |               |    [D] <- [M]     |          |
               |               |    [M] <- [A]     |          |
               |               |  [HL] <- [HL] - 1 |          |
               |               |    [M] <- [D]     |          |
               |               |  [HL] <- [HL] + 1 |          |
               |               +---------+---------+          |
               |                         |        |           |
               +------------+------------+        |           |
                            |                     |           |
                            v                     |           |
                  +-------------------+           |           |
                  |   [C] <- [C] - 1  |           |           |
                  +---------+---------+           |
                            |
                            v
                          /   \
                        /  Is   \
                      /  [C] = 0? \
                     <            >
                      \ Is zero? / -- NO ----------> (To LOOP2)
                        \      /
                          \  /
                           | YES
                           v
                 +-------------------+
                 |   [B] <- [B] - 1  |
                 +---------+---------+
                           |
                           v
                         /   \
                       /  Is   \
                     /  [B] = 0? \
                    <            >
                     \ Is zero? / -- NO -----------> (To LOOP3)
                       \      /
                         \  /
                          | YES
                          v
                 +-------------------+
                 |       STOP        |
                 +-------------------+


Viva Questions:
Explain the INX operation.
State the logic behind sorting an array of data in descending order.
What are the advantages of using memory segmentation in 8085?
What is a macro and when is it used?
What is the function of the direction flag?
What is DMA?
Define machine cycle and instruction cycle.
For all 2026 published articles list: click here: 
…till the next post, bye-bye & take care

‘Learn Arduino Using TinkerCAD Circuits Simulator’ eBook’s Simulation & Resource Hyperlinks list page

noreply@blogger.com (belgaumboy) — Sat, 26 Sep 2026 15:15:24 +0530

Here are all the simulation and resource hyperlinks in their appearing order throughout eBook-Learn Arduino Using TinkerCAD Circuits Simulator.pdf:
Part II: Arduino Programming Essentials (Sketch & IDE Simulation)
Bare Minimum TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/0Qxc8ay0cgU-tc01part02la01bare-minimum?sharecode=ywCrwzm_MgMqsfChrcd2h9bFOqsupy8DiTs6TLAz1lk
Hello World! Once TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/22pEnh7H6wl-tc01part02la02hello-world-once?sharecode=1_8TNIJj8aa7nTMDeNkH-i1VtKGXas34OnL_dvfp3vY
Hello World! - Infinitely TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/ddl9Agvo7L3-tc01part02la02hello-world-once?sharecode=COXro_koOE5eIl0G6k2WBafZTmSXy14tpa4Q8ISFQTU
Serial Port Interactive Program TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/1bF0xgSQ2au-tc01part02la04serialportinteractiveprogram?sharecode=WtqFUhUe6uI822M4e0WSjnLvW5suUj62R6mVuI1HDg0
Printing Integers or Numbers on Serial Monitor TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/l9A5hth02Ju-tc01part02la05printingintornumbersonserialmonito?sharecode=KxKj18VcTm6BQyv3lBfisGW5KHzx6_0Bx314XykJLo4
Part III: Core I/O and Sensing in Simulation
Real LED Blink TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/0lLqqgJObES-tc01part03la01realledblink?sharecode=4NuKbkdqqiVOr440wmUkw50q-XJFikxj-A9Je1mbkGg
Switch TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/h01Z0HIN2Yy-tc01part03la02switch0or1?sharecode=pjNdr39rop3qXWeMAGJ3x08nBbXykIVSSbYxyXpKabw
Switch TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/2MxVwPRHnPM-tc01part03la03switchpressedorreleased?sharecode=hkwD1gHVLgqy1IpRBM-0l8ExtaPB4bZBusrs3h_OuXM
Switch & Real LED TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/gaEbHNduXHv-tc01part03la04switchnrealled?sharecode=XFmuFpEFuoFO8nBamdnmLomWGK0bgWz_wdp34f7FXeE
PWM at specific pin TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/iczdsZlk9C2-tc01part03la05pwmatspecificpin?sharecode=zbQmZiWEhUEGtTrH6EHdZ6qro_satebCA7UsdRBY8Do
Analog Read Serial Out TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/gNsZVqtAy85-tc01part03la06analogreadserialout?sharecode=p2eDB_vI99r_rL2h_bXN2PcAbfFDfniu76Xgilouq7I
Analog I/O TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/bYtnmGBcQVV-tc01part03la07analogio?sharecode=NI0zuZiRZvKlEE3A5aO_HIzHt-zgQGYHPhTfQMBluc4
LED and Serial Monitor TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/0O9MivIlP1F-tc01part03la08lednserialmonitor?sharecode=XOiuOKNUDcgibcW0TsDIEHJkkYmyo7H3NJ3HyzYSuDU
LED, Flasher and Serial Monitor TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/hlNplW7TmMs-tc01part03la09ledflashnserialmonitor?sharecode=nIj-JtyzNf3X5YoLkh7Ay7K0egDqHNlcaHLGbF3BjFI
One Button Two Functions TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/7T03bYHYd0h-tc01part03la10onebuttontwofunctions?sharecode=6V0O8JDqKbthvgJez_p6kAvmTJxdL-jxbfnBWU1hZ3c
LDR as Analog Input Sensor TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/4q7qPsEhP8a-tc01part03la12ldrasanaloginputsensor?sharecode=Bjsr7ne9vDsWt147-Zd6zskyQrQyDL300kM-BbBgZ-c
Pot as Analog Input Sensor TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/gOhnmK7J58J-tc01part03la13potasanaloginputsensor?sharecode=OxGy24rtREC7P5k26Qs44tILib_wqNfvVSiC--6Gd3g
Pseudo Theremin TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/3Th2HTIeDfE-tc01part03la15pseudotheremin?sharecode=0elQWBINyg-hbp1W52NiYu7RRFpsRip9LYXnx3zS55s
Movement PIR TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/eXeyfXac8t2-tc01part03la16movementpir?sharecode=rqFzBAqVUY_Of6gLswnwmJC3r6z-g385EtEnz3dETz0
Temperature Sensor TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/3Th2HTIeDfE-tc01part03la15pseudotheremin?sharecode=0elQWBINyg-hbp1W52NiYu7RRFpsRip9LYXnx3zS55s
Part IV: Actuators, Displays, and Specialized Components
DC Motor TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/c5R6dYjfnVy-tc01part04la01dcmotor?sharecode=ndzhOIS3STymPiJU6zBF0cOOJdFqafmawpElmZL0qFI
Part V: Advanced System Design and Protocols
Servo Motor Sweep TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/90CKfih1pu3-tc01part04la02servomotor?sharecode=wSQSwUeOpa86OsD4P04tl2O0Ap3Ka5fFWl9nQ4tRzcE
LCD TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/dFK78a1kdyB-tc01part04la03lcd?sharecode=QDpvapBdAQSsUWj5q75ZyvnQbHRAxWTbEs1A2zBXacw
LDR Values On Serial Plotter TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/aUEtpe08fSV-tc01part05la01ldrvaluesonserialplotter?sharecode=jV4wf90k86bNSqQa3QV5eMqyJByi1pscNJ4gV4DE73k
Flash Without Delay – 1 LED TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/hHDeLGO0liU-tc01part05la02flashwithoutdelay1led?sharecode=VviAnINnYjgFQ2wCuq_y5IYUtgaaPNdPXfu3o9YPPzA
Flash Without Delay – 2 LED TinkerCAD Circuits Simulation Link
https://www.tinkercad.com/things/g4GLboHKTox-tc01part05la03flashwithoutdelay2led?sharecode=1VWaetr0h7s5gJsuGC-6vV77Sttl5nFCmuVUlVrHgrM
Part VI: Comprehensive Project Simulations
Spaceship Interface
https://www.tinkercad.com/learn/overview/OSQKNMSISCC2EF3?collectionId=O0K87SQL1W5N4P2&type=circuits
Love-o-Meter
https://www.tinkercad.com/learn/overview/OVANT4WISCC2EK2?collectionId=O0K87SQL1W5N4P2&type=circuits
Color Mixing Lamp
https://www.tinkercad.com/learn/overview/OLKSEUGISCC2EKW?collectionId=O0K87SQL1W5N4P2&type=circuits
Mood Cue
https://www.tinkercad.com/learn/overview/OVSD912ISCC2EMM?collectionId=O0K87SQL1W5N4P2&type=circuits
Light Theremin
https://www.tinkercad.com/learn/overview/OF1PIRKISCC2EOG?collectionId=O0K87SQL1W5N4P2&type=circuits
Motorized Pinwheel
https://www.tinkercad.com/learn/overview/OKS5OPOISCC2EUJ?collectionId=O0K87SQL1W5N4P2&type=circuits
Zoetrope
https://www.tinkercad.com/learn/overview/O73WOLIISCC2EWG?collectionId=O0K87SQL1W5N4P2&type=circuits
Knock Lock
https://www.tinkercad.com/learn/overview/OP6T6C6ISCC2VBC?collectionId=O0K87SQL1W5N4P2&type=circuits
Digital Hourglass
https://www.tinkercad.com/learn/overview/OJ4LFOTISCC2ESG?collectionId=O0K87SQL1W5N4P2&type=circuits
Crystal Ball
https://www.tinkercad.com/learn/overview/OB3B767ISCC2VA9?collectionId=O0K87SQL1W5N4P2&type=circuits
eBook Learn Arduino Using TinkerCAD Circuits Simulator purchase Link:
https://play.google.com/store/books/details?id=CQSYEQAAQBAJ [Google Play Store]
https://books.google.co.in/books?id=CQSYEQAAQBAJ [Google Books]
Learn Arduino Risk-Free with the Ultimate TinkerCAD Guide eBook
https://8051microcontrollertutorial.blogspot.com/2025/11/learn-arduino-risk-free-with-tinkerCAD.html
TinkerCAD Resources Index Page
https://8051microcontrollertutorial.blogspot.com/2025/09/TC09092025ResourcesIndexPage.html

…till the next post, bye-bye & take care!

Smallest element in an array | 8085 Lab Program

noreply@blogger.com (belgaumboy) — Sat, 26 Sep 2026 00:00:00 +0530

Section: Array Operations & Code Conversions

Aim: To find the smallest element in an array of data stored in memory and also to verify the result.

Apparatus Required: 8085 microprocessor kit, key board.

Algorithm:

Place all the elements of an array in the consecutive memory locations.
Fetch the first element from the memory location and load it in the accumulator.
Initialize a counter (register) with the total number of elements in an array.
Decrement the counter by 1.
Increment the memory pointer to point to the next element.
Compare the accumulator content with the memory content (next element).
If the accumulator content is smaller, then move the memory content to the accumulator; else continue.
Decrement the counter by 1.
Repeat steps 5 to 8 until the counter reaches zero.
Store the result (accumulator content) in the specified memory location.

Program:

Address	Label	Mnemonics	Operand	Comment
4100	START	LXI	H, 4200	Initialize HL reg. to 4200H
4103		MVI	B, 04	Initialize B reg with no. of comparisons (n-1)
4105		MOV	A, M	Transfer first data to acc.
4106	LOOP1	INX	H	Increment HL reg. to point next memory location
4107		CMP	M	Compare M & A
4108		JC	LOOP	If A is lesser than M then go to loop
410B		MOV	A, M	Transfer data from M to A reg
410C	LOOP	DCR	B	Decrement B reg
410D		JNZ	LOOP1	If B is not Zero go to loop1
4110		STA	4205	Store the result in a memory location
4113		HLT		Stop the program

Observation:

Input:
- Address 4200: 01
- Address 4201: 06
- Address 4202: 03
- Address 4203: 07
- Address 4204: 02
Output:
- Address 4205: 01

Result: Thus the smallest number in the given array is found and it is stored at location 4205.

Flowchart:

               +-------------------+
               |       START       |
               +---------+---------+
                         |
                         v
               +-------------------+
               |   [HL] <- 4200H   |
               +---------+---------+
                         |
                         v
               +-------------------+
               |     [B] <- 04H    |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [A] <- [M]     |
               +---------+---------+
                         |
                         v <------------------+
               +-------------------+          |
               |  [HL] <- [HL] + 1 |          |
               +---------+---------+          |
                         |                    |
                         v                    |
                       /   \                  |
                     /  Is   \                |
                   / [A] < [HL]? \            |
                  <   (CY = 1)    >           |
                   \             /            |
                     \         /              |
                       \     /                |
                        |   /                 |
            +-----------+--+                  |
            |              |                  |
           YES             NO                 |
            |              |                  |
            |              v                  |
            |    +-------------------+        |
            |    |    [A] <- [HL]    |        |
            |    +---------+---------+        |
            |              |                  |
            +-------+------+                  |
                    |                         |
                    v                         |
          +-------------------+               |
          |   [B] <- [B] - 1  |               |
          +---------+---------+               |
                    |                         |
                    v                         |
                  /   \                       |
                /  Is   \                     |
              /   [B] = 0? \                  |
             <              >                 |
              \  Is Zero?  / -- NO -----------+
                \        /
                  \    /
                    | YES
                    v
          +-------------------+
          |    <- [A]   |
          +---------+---------+
                    |
                    v
          +-------------------+
          |       STOP        |
          +-------------------+

Viva Questions:

What is meant by instruction JC?
Tell about the instruction SHLD.
Summarize the instruction STAX B.
State the logic behind the finding of smallest element.
Why address bus is unidirectional?
List few instructions to clear accumulator?
What is the function of NOP instruction?

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

Largest element in an array | 8085 Lab Program

noreply@blogger.com (belgaumboy) — Fri, 25 Sep 2026 00:00:00 +0530

Section: Array Operations & Code Conversions

Aim: To find the largest element in an array of data stored in memory and also to verify the result.

Apparatus Required: 8085 microprocessor kit, keyboard.

Algorithm:

Place all the elements of an array in consecutive memory locations.
Fetch the first element from the memory location and load it in the accumulator.
Initialize a counter (register) with the total number of elements in an array (or total comparisons $n-1$).
Decrement the counter by 1.
Increment the memory pointer to point to the next element.
Compare the accumulator content with the memory content (next element).
If the accumulator content is smaller, then move the memory content (largest element) to the accumulator; else continue.
Decrement the counter by 1.
Repeat steps 5 to 8 until the counter reaches zero.
Store the result (accumulator content) in the specified memory location.

Program:

Address	Label	Mnemonics	Operand	Comment
4100		LXI	H, 4200	Initialize HL reg. to data location
4103		MVI	B, 04	Initialize B reg with no. of comparisons ($n-1$)
4105		MOV	A, M	Transfer first data to accumulator
4106	LOOP1	INX	H	Increment HL reg. to point next memory location
4107		CMP	M	Compare M & A
4108		JNC	LOOP	If A is greater than M then go to loop
410B		MOV	A, M	Transfer data from M to A reg
410C	LOOP	DCR	B	Decrement B reg
410D		JNZ	LOOP1	If B is not Zero go to loop1
4110		STA	4205	Store the result in a memory location
4113		HLT		Stop the program

Observation:

Input:
- 4200: 01
- 4201: 06
- 4202: 03
- 4203: 07
- 4204: 02
Output:
- 4205: 07

Result: Thus the largest number in the given array is found and it is stored at location 4205.

Flowchart:

               +-------------------+
               |       START       |
               +---------+---------+
                         |
                         v
               +-------------------+
               |   [HL] <- 4200H   |
               +---------+---------+
                         |
                         v
               +-------------------+
               |     [B] <- 04H    |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [A] <- [M]     |
               +---------+---------+
                         |
                         v <------------------+
               +-------------------+          |
               |  [HL] <- [HL] + 1 |          |
               +---------+---------+          |
                         |                    |
                         v                    |
                       /     \                  |
                     /  Is     \                |
                   / [A] < [HL]? \            |
                  <   (CY = 1)    >           |
                   \             /            |
                     \         /              |
                       \     /                |
                        \   /                 |
            +-----------+--+                  |
            |              |                  |
           YES             NO                 |
            |              |                  |
            v              |                  |
  +-------------------+    |                  |
  |    [A] <- [HL]    |    |                  |
  +---------+---------+    |                  |
            |              |                  |
            +-------+------+                  |
                    |                         |
                    v                         |
          +-------------------+               |
          |   [B] <- [B] - 1  |               |
          +---------+---------+               |
                    |                         |
                    v                         |
                  /   \                       |
                /  Is   \                     |
              /   [B] = 0? \                  |
             <              >                 |
              \  Is Zero?  / -- NO -----------+
                \        /
                  \    /
                    | YES
                    v
          +-------------------+
          |     <- [A]  |
          +---------+---------+
                    |
                    v
          +-------------------+
          |       STOP        |
          +-------------------+

Viva Questions:

What is meant by the instruction CMP M?
What the instruction JNZ will do?
State the logic behind the finding of largest element.
List out the similarities b/w the CALL-RET and PUSH-POP instructions?
What is the need of ALE signal in 8085?
What are the addressing modes of 8085?

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

8 bit data division | 8085 Lab Program

noreply@blogger.com (belgaumboy) — Thu, 24 Sep 2026 00:00:00 +0530

Section: Arithmetic & Logic Operations

Aim: To divide two 8-bit numbers stored in memory and also to verify the result.

Apparatus Required: 8085 microprocessor kit, key board.

Algorithm:

Load Divisor and Dividend.
Subtract divisor from dividend.
Count the number of times of subtraction, which equals the quotient.
Stop subtraction when the dividend is less than the divisor. The dividend now becomes the remainder. Otherwise, go to step 2.
Stop the program execution.

Program:

Address	Label	Mnemonics	Operand	Comment
4100		MVI	B,00	Clear B reg for quotient
4102		LXI	H,4200	Initialize HL reg. to 4200H
4105		MOV	A,M	Transfer dividend to acc.
4106		INX	H	Increment HL reg. to point next mem. Location.
4107	LOOP	SUB	M	Subtract divisor from dividend
4108		INR	B	Increment B reg
4109		JNC	LOOP	Jump to LOOP if result does not yield borrow
410C		ADD	M	Add divisor to acc.
410D		DCR	B	Decrement B reg
410E		INX	H	Increment HL reg. to point next mem. Location.
410F		MOV	M,A	Transfer the remainder from acc. to memory.
4110		INX	H	Increment HL reg. to point next mem. Location.
4111		MOV	M,B	Transfer the quotient from B reg. to memory.
4112		HLT		Stop the program

Observation:

Input:
- Address 4200: 06
- Address 4201: 02
Output:
- Address 4202: 00 (Remainder)
- Address 4203: 03 (Quotient)

Result: Thus an ALP was written for 8-bit division and also the result is verified.

Flowchart:

               +-------------------+
               |       START       |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [B] <- 00H     |
               +---------+---------+
                         |
                         v
               +-------------------+
               |   [HL] <- 4200H   |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [A] <- [M]     |
               +---------+---------+
                         |
                         v
               +-------------------+
               |  [HL] <- [HL] + 1 |
               +---------+---------+
                         |
                         v <------------------+
               +-------------------+          |
               |  [A] <- [A] - [M] |          |
               +---------+---------+          |
                         |                    |
                         v                    |
               +-------------------+          |
               |   [B] <- [B] + 1  |          |
               +---------+---------+          |
                         |                    |
                         v                    |
                       /   \                  |
                     /  Is   \                |
                   /  there a  \              |
                  <   Borrow?  >              |
                   \  (CY = 1) /              |
                     \      /                 |
                       \  /                   |
                        |                     |
            +-----------+-----------+         |
            |                       |         |
           YES                      NO        |
            |                       +---------+
            v
  +-------------------+
  |  [A] <- [A] + [M] |
  +---------+---------+
            |
            v
  +-------------------+
  |   [B] <- [B] - 1  |
  +---------+---------+
            |
            v
  +-------------------+
  |  [HL] <- [HL] + 1 |
  +---------+---------+
            |
            v
  +-------------------+
  |    [M] <- [A]     |
  |    (Remainder)    |
  +---------+---------+
            |
            v
  +-------------------+
  |  [HL] <- [HL] + 1 |
  +---------+---------+
            |
            v
  +-------------------+
  |    [M] <- [B]     |
  |     (Quotient)    |
  +---------+---------+
            |
            v
  +-------------------+
  |       STOP        |
  +-------------------+

Viva Questions:

What SUB M instruction will do?
Describe SBB M instruction.
Express the use of SUI with an example.
Where SBI can be used?
Give the purpose of the instruction LDAX D.
How will you perform Division using ADD instruction?
What is the need of ALE signal in 8085?
What are the addressing modes of 8085?
List the interrupt signals of 8085?

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

8 bit data multiplication | 8085 Lab Program

noreply@blogger.com (belgaumboy) — Wed, 23 Sep 2026 00:00:00 +0530

Section: Arithmetic & Logic Operations

Aim: To multiply two 8 bit numbers stored at consecutive memory locations and also to verify the result.

Apparatus Required: 8085 microprocessor kit, key board.

Algorithm:

Initialize memory pointer to data location.
Move multiplicand to a register.
Move the multiplier to another register.
Clear the accumulator.
Add multiplicand to accumulator.
Decrement multiplier.
Repeat step 5 till multiplier comes to zero.
The result, which is in the accumulator, is stored in a memory location.

Program:

Address	Label	Mnemonics	Operand	Comment
4100	START	LXI	H, 4200	Initialize HL reg. to 4500
4103		MOV	B, M	Transfer first data to reg. B
4104		INX	H	Increment HL reg. to point next mem. Location.
4105		MVI	A, 00H	Clear the acc.
4107		MVI	C, 00H	Clear C reg for carry
4109	L1	ADD	M	Add multiplicand multiplier times.
410A		JNC	NEXT	Jump to NEXT if there is no carry
410D		INR	C	Increment C reg
410E	NEXT	DCR	B	Decrement B reg
410F		JNZ	L1	Jump to L1 if B is not zero.
4112		INX	H	Increment HL reg. to point next mem. Location.
4113		MOV	M, A	Transfer the result from acc. to memory.
4114		INX	H	Increment HL reg. to point next mem. Location.
4115		MOV	M, C	Transfer the result from C reg. to memory.
4116		HLT		Stop the program

Observation:

Input:
- Address 4200: 02
- Address 4201: 04
Output:
- Address 4202: 08
- Address 4203: 00

Result: Thus the 8-bit multiplication was done in 8085 μp using repeated addition method and also the result is verified.

Flowchart:

               +-------------------+
               |       START       |
               +---------+---------+
                         |
                         v
               +-------------------+
               |   [HL] <- 4200H   |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [B] <- [M]     |
               +---------+---------+
                         |
                         v
               +-------------------+
               |  [HL] <- [HL] + 1 |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [A] <- 00H     |
               |    [C] <- 00H     |
               +---------+---------+
                         |
                         v <------------------+
               +-------------------+          |
               |  [A] <- [A] + [M] |          |
               +---------+---------+          |
                         |                    |
                         v                    |
                       /   \                  |
                     /  Is   \                |
                   /  there a  \              |
                  <   Carry?   >              |
                   \          /               |
                     \      /                 |
                       \  /                   |
                        |                     |
            +-----------+-----------+         |
            |                       |         |
           YES                      NO        |
            |                       |         |
            v                       |         |
  +-------------------+             |         |
  |   [C] <- [C] + 1  |             |         |
  +---------+---------+             |         |
            |                       |         |
            +-----------+-----------+         |
                        |                     |
                        v                     |
              +-------------------+           |
              |   [B] <- [B] - 1  |           |
              +---------+---------+           |
                        |                     |
                        v                     |
                      /   \                   |
                    /  Is   \                 |
                  /   [B] = 0? \              |
                 <             >              |
                  \  Is zero? / -- NO --------+
                    \      /
                      \  /
                        | YES
                        v
              +-------------------+
              |  [HL] <- [HL] + 1 |
              +---------+---------+
                        |
                        v
              +-------------------+
              |    [M] <- [A]     |
              +---------+---------+
                        |
                        v
              +-------------------+
              |  [HL] <- [HL] + 1 |
              +---------+---------+
                        |
                        v
              +-------------------+
              |    [M] <- [C]     |
              +---------+---------+
                        |
                        v
              +-------------------+
              |       STOP        |
              +-------------------+

Viva Questions:

Define two’s complement of an 8-bit numbers.
What is meant by instruction ADC M?
What is the use of the instruction MOV A,M?
What is the function of program counter?
Mention the types of 8085 instruction set.
How will you perform multiplication using ADD instruction?
Describe about DAD B instruction.
What is the purpose of the instruction MOV M,A?

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

8 bit data subtraction | 8085 Lab Program

noreply@blogger.com (belgaumboy) — Tue, 22 Sep 2026 00:00:00 +0530

Section: Arithmetic & Logic Operations

Aim: To subtract two 8 bit numbers stored at consecutive memory locations and also to verify the result.

Apparatus Required: 8085 microprocessor kit, key board.

Algorithm:

Initialize memory pointer to data location.
Get the first number from memory in accumulator.
Get the second number and subtract from the accumulator.
If the result yields a borrow, the content of the acc. is complemented and 01H is added to it (2’s complement). A register is cleared and the content of that reg. is incremented in case there is a borrow. If there is no borrow the content of the acc. is directly taken as the result.
Store the answer at next memory location.

Program:

Address	Label	Mnemonics	Operand	Comment
4100	START	MVI	C, 00	Clear C reg.
4102		LXI	H, 4200	Initialize HL reg. to 4500
4105		MOV	A, M	Transfer first data to accumulator
4106		INX	H	Increment HL reg. to point next mem. Location.
4107		SUB	M	Subtract first number from acc. Content.
4108		JNC	L1	Jump to location if result does not yield borrow.
410B		INR	C	Increment C reg.
410C		CMA		Complement the Acc. Content
410D		ADI	01H	Add 01H to content of acc.
410F	L1	INX	H	Increment HL reg. to point next mem. Location.
4110		MOV	M, A	Transfer the result from acc. to memory.
4111		INX	H	Increment HL reg. to point next mem. Location.
4112		MOV	M, C	Move carry to mem.
4113		HLT		Stop the program

Observation:

Input:
- Address 4200: 04
- Address 4201: 01
Output:
- Address 4202: 03
- Address 4203: 00

Result: Thus the 8-bit numbers stored at 4200 & 4201 are subtracted and the result is stored at 4202 & 4203.

Flowchart:

               +-------------------+
               |       START       |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [C] <- 00H     |
               +---------+---------+
                         |
                         v
               +-------------------+
               |   [HL] <- 4200H   |
               +---------+---------+
                         |
                         v
               +-------------------+
               |    [A] <- [M]     |
               +---------+---------+
                         |
                         v
               +-------------------+
               |  [HL] <- [HL] + 1 |
               +---------+---------+
                         |
                         v
               +-------------------+
               |  [A] <- [A] - [M] |
               +---------+---------+
                         |
                         v
                       /   \
                     /  Is   \
                   /  there a  \
                  <   Borrow?  >
                   \          /
                     \      /
                       \  /
                        |
            +-----------+-----------+
            |                       |
           YES                      NO
            |                       |
            v                       |
  +-------------------+             |
  |  Complement [A]   |             |
  |  Add 01H to [A]   |             |
  +---------+---------+             |
            |                       |
            v                       |
  +-------------------+             |
  |   [C] <- [C] + 1  |             |
  +---------+---------+             |
            |                       |
            +-----------+-----------+
                        |
                        v
              +-------------------+
              |  [HL] <- [HL] + 1 |
              +---------+---------+
                        |
                        v
              +-------------------+
              |    [M] <- [A]     |
              +---------+---------+
                        |
                        v
              +-------------------+
              |  [HL] <- [HL] + 1 |
              +---------+---------+
                        |
                        v
              +-------------------+
              |    [M] <- [C]     |
              +---------+---------+
                        |
                        v
              +-------------------+
              |       STOP        |
              +-------------------+

Viva Questions:

What is meant by ADI instruction?
What is an instruction?
What is Mnemonic?
What is the purpose of CMA instruction?
What is the function of stack pointer?
Why ADI 01H is used in two’s complement of an 8-bit number?
How many memory locations can be addressed by a microprocessor with 14 address lines?

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

8 bit data addition | 8085 Lab Program

noreply@blogger.com (belgaumboy) — Mon, 21 Sep 2026 00:00:00 +0530

Section: Arithmetic & Logic Operations

Aim: To add two 8-bit numbers stored at consecutive memory locations and also to verify the result.

Apparatus Required: 8085 microprocessor kit, keyboard.

Algorithm:

Initialize memory pointer to data location.
Get the first number from memory into accumulator.
Get the second number and add it to the accumulator.
Store the answer at another memory location.

Program:

Address	Label	Mnemonics	Operand	Comment
4100	START	MVI	C, 00	Clear C reg.
4102		LXI	H, 4200	Initialize HL reg. to 4200
4105		MOV	A, M	Transfer first data to accumulator
4106		INX	H	Increment HL reg. to point next memory location
4107		ADD	M	Add first number to acc. content
4108		JNC	L1	Jump to location if result does not yield carry
410B		INR	C	Increment C reg.
410C	L1	INX	H	Increment HL reg. to point next memory location
410D		MOV	M, A	Transfer the result from acc. to memory
410E		INX	H	Increment HL reg. to point next memory location
410F		MOV	M, C	Move carry to memory
4110		HLT		Stop the program

Observation:

Input:
- Memory location 4200: 40
- Memory location 4201: 20
Output:
- Memory location 4202: 60 (Sum)
- Memory location 4203: 00 (Carry)

Result: Thus the two 8-bit numbers stored at 4200 & 4201 are added and the result is stored at 4202 & 4203.

Flow Chart:

+-------------------+

| START |

+---------+---------+

+-------------------+

| [C] <- 00H |

+---------+---------+

+-------------------+

| [HL] <- 4200H |

+---------+---------+

+-------------------+

| [A] <- [M] |

+---------+---------+

+-------------------+

| [HL] <- [HL] + 1 |

+---------+---------+

+-------------------+

| [A] <- [A] + [M] |

+---------+---------+

/ \

/ Is \

/ there a \

< Carry? >

\ /

+-----------+-----------+

| |

YES NO

| |

v |

+-------------------+ |

| [C] <- [C] + 1 | |

+---------+---------+ |

| |

+-----------+-----------+

+-------------------+

| [HL] <- [HL] + 1 |

+---------+---------+

+-------------------+

| [M] <- [A] |

+---------+---------+

+-------------------+

| [HL] <- [HL] + 1 |

+---------+---------+

+-------------------+

| [M] <- [C] |

+---------+---------+

+-------------------+

| STOP |

+-------------------+

Viva Questions:

What is the function of LXI H, 4000 H instruction?
How can you store data in a memory location?
What is the meaning of INX?
How can you read data from a memory location?
What are the flags available in 8085?
What is the function of the RESET key of an 8085 microprocessor kit?
What is the function of JNC instruction?
What is the difference between conditional and unconditional jump instructions?
What is multibyte addition/subtraction?

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

Interrupts in 8051 Microcontroller | 8051 Microcontroller

noreply@blogger.com (belgaumboy) — Sun, 20 Sep 2026 00:00:00 +0530

In embedded systems programming, real-time responsiveness is critical. A microcontroller must be capable of responding immediately to high-priority events, such as a sensor input or a timer overflow, without wasting valuable CPU cycles on constant polling. The Intel 8051 microcontroller solves this through a robust, hardware-driven interrupt system.

An interrupt is essentially an event that temporarily diverts the processor from its current execution path. Analogous to receiving an important phone call while performing a task, the microcontroller pauses its main work, services the immediate request, and then seamlessly returns to where it left off.

The 8051 Interrupt Execution Process

When an interrupt is triggered, the 8051 does not halt instantly. Instead, it transitions gracefully through a sequence of hardware-defined steps:

Instruction Completion: The processor completes the execution of the instruction currently in progress.
State Saving: The current contents of the Program Status Word (PSW) are pushed onto the stack to preserve status flags.
Address Preservation: The Program Counter (PC) content (the return address of the next instruction in the main program) is pushed onto the stack.
Flag Reset: The internal interrupt flag is automatically reset.
ISR Branching: The PC is loaded with the predefined starting address of the Interrupt Service Routine (ISR), forcing the program to jump to the service program.

Every ISR must conclude with the RETI (Return from Interrupt) instruction. When RETI executes, it signals the completion of the routine and performs the reverse operations:

Pops the stack top back to the Program Counter (PC).
Pops the next stack top back to the Program Status Word (PSW), successfully restoring the main program's exact execution state.

Taxonomy of Interrupts

Interrupts can be classified under three major conceptual pairings:

External vs. Internal: External interrupts are initiated by physical peripheral devices connected to the microcontroller's pins. The 8051 has two external hardware interrupts, INT0 and INT1, which trigger based on a level or edge signal applied to pins Port 3.2 and Port 3.3. Internal interrupts are triggered by on-chip peripherals, such as timers or serial communication controllers.
Maskable vs. Non-Maskable: Maskable interrupts can be dynamically enabled or disabled by software commands. Non-maskable interrupts are high-priority hardware lines that the programmer cannot disable through code.
Vectored vs. Non-Vectored: In vectored interrupts, the microcontroller automatically jumps to a predefined, hardcoded ISR address (the "vector address"). Non-vectored interrupts rely on an external handshaking process: the microcontroller acknowledges the interrupt with an INTA signal, and the peripheral device must send the target vector address back across the data bus.

All five of the standard 8051 interrupts are classified as maskable and vectored.

The 8051 Interrupt Vector Table

The starting address of the ISR is called the interrupt vector. The 8051 family features five primary interrupts (plus the system RESET line, which acts as the ultimate master interrupt). They are serviced according to a strict priority hierarchy:

Interrupt Source	Trigger Flag	Type	Vector Address	Natural Priority
RESET	—	Internal/External	0000H	Highest Priority
External Interrupt 0 (INT0)	IE0 / PORT3.2	External	0003H	Second Highest (Highest of the 5 MCUs)
Timer 0 Overflow (TF0)	TF0	Internal	000BH	Third Highest
External Interrupt 1 (INT1)	IE1 / PORT3.3	External	0013H	Fourth Highest
Timer 1 Overflow (TF1)	TF1	Internal	001BH	Fifth Highest
Serial Communication (RI/TI)	RI / TI	Internal	0023H	Lowest Priority

Control and Priority Registers

To configure and manipulate these interrupts, developers utilize three specialized Special Function Registers (SFRs):

1. IE Register (Interrupt Enable)

This 8-bit register allows developers to activate or silence individual interrupts. Setting a bit to 1 enables that interrupt, while 0 disables it.

Bit 7 (EA - Enable All): The global switch. If EA = 0, all interrupts are disabled regardless of individual settings. If EA = 1, individual interrupt settings are respected.
Bit 4 (ES): Serial interrupt enable.
Bit 3 (ET1): Timer 1 interrupt enable.
Bit 2 (EX1): External 1 interrupt enable.
Bit 1 (ET0): Timer 0 interrupt enable.
Bit 0 (EX0): External 0 interrupt enable.

2. IP Register (Interrupt Priority)

The 8051 allows developers to customize the natural priority hierarchy using the IP register. Setting a bit to 1 assigns high priority to that specific interrupt, while 0 assigns low priority:

Bit 4 (PS): High priority for serial interrupt.
Bit 3 (PT1): High priority for Timer 1 interrupt.
Bit 2 (PX1): High priority for External 1 interrupt.
Bit 1 (PT0): High priority for Timer 0 interrupt.
Bit 0 (PX0): High priority for External 0 interrupt.

Rules of Priority Resolution:

A low-priority interrupt can only be interrupted by a high-priority interrupt, never by another low-priority request.
If different priority level interrupts arrive simultaneously, the higher level is served.
If identical priority level interrupts are requested at the exact same time, an internal, hardware-level polling sequence determines which interrupt gets serviced first.

3. TCON Register (Timer Control)

The TCON register serves a dual purpose. It is primarily used to start, stop, and monitor timer overflows. However, it also contains specialized bits that specify the triggering type—either edge-activated or level-activated—for the external interrupt pins.

Conclusion

The interrupt structure of the Intel 8051 is a masterclass in deterministic hardware control. By combining a fixed vector table, prioritized execution rules, and highly configurable SFRs like IE and IP, it guarantees that critical system operations are handled with zero-latency efficiency—cementing its place as a cornerstone of embedded education and design.

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

Types of Microcontroller | 8051 Microcontroller

noreply@blogger.com (belgaumboy) — Sat, 19 Sep 2026 00:00:00 +0530

In the field of embedded engineering, selecting the appropriate controller is a critical decision that directly impacts system performance, cost, and design footprint. A microcontroller (commonly designated as an MCU, MC, UC, or μC) is essentially a small computer integrated onto a single Very Large Scale Integration (VLSI) integrated circuit chip. Unlike general-purpose computers, a microcontroller is typically dedicated to a single, specific task and runs a dedicated program stored in its read-only memory.

To help developers choose cost-effective solutions for specific applications, manufacturers provide diverse families of devices. These devices can be categorized based on their underlying memory architecture, vendor ecosystem, bus width, and memory configurations.

1. Classification by Memory Architecture

How a microcontroller's Central Processing Unit (CPU) accesses its program instructions and variable data defines its core architecture. On the basis of memory architecture, microcontrollers are divided into two primary types:

Harvard Architecture: This layout utilizes completely separate memory spaces and hardware buses for program code (ROM) and data (RAM). This design enables the CPU to fetch instructions and read/write data simultaneously, significantly increasing processing speeds. The AVR microcontroller family is a prominent example of a Harvard architecture.
Von Neumann Architecture: Also known as the Princeton architecture, this design uses a single, shared memory space and a common bus for both instructions and data. Because code and data cannot be accessed at the same time, Von Neumann systems require more machine cycles to execute instructions but feature a simpler physical chip layout.

2. Classification by Manufacturer / Vendor Ecosystem

Microcontrollers are heavily categorized by their service providers and silicon vendors. Each manufacturer offers a distinct instruction set, development environment, and hardware peripheral options:

Intel: Pioneer of the highly enduring 8051 family, a classic CISC-based 8-bit architecture widely used in basic control systems.
Atmel: Famous for the AVR family (including the Tiny, Mega, Classic, and Special Purpose lines), which are high-speed 8-bit RISC microcontrollers featuring on-chip Flash memory.
Microchip: Manufacturer of the widely used PIC family of microcontrollers.
Motorola / Freescale: Known for producing the HCS08 family and historical industry-standard chips like the Motorola 6811.
Zilog: Manufacturer of the Z8 microcontroller series.
Hitachi: Another major provider of dedicated microcontroller architectures.

3. Classification by Bus Width (Word Size)

The "word size" or bus width determines the maximum size of data that the CPU can process in a single instruction cycle.

8-Bit Microcontrollers: The absolute predominant family of microcontrollers. An 8-bit CPU works on only 8 bits of data at a time; larger data values must be broken down into 8-bit pieces to be processed. Despite this limitation, the single-byte word size is perfectly sufficient for the vast majority of embedded tasks, easily interfaces with standard logic circuitry, and aligns perfectly with byte-sized serial ASCII data communications. Low-end 8-bit chips are highly cost-effective and can integrate as little as 1000 bytes of ROM and 20 bytes of RAM on-chip.
16-Bit Microcontrollers: These devices provide a substantial jump in processing capabilities. An example is the Philips eXtended Architecture (XA) range, which features a 16-bit fully static CPU, a 24-bit program and data address range, and an enhanced instruction set optimized for multitasking and high-level programming language support.
32-Bit Microcontrollers: High-performance devices, such as the AVR32 family, designed to handle intensive data processing without the overhead of slicing data into smaller byte segments.

4. Classification by Onboard Memory Configuration

Because using a generic, "one-size-fits-all" device for all applications would introduce unnecessary complexity and cost, manufacturers classify family members by how their program memory is physically constructed:

ROMless Devices: These microcontrollers contain no on-chip read-only memory. They rely entirely on external memory expansion via off-chip ROM to load and execute their instructions.
ROM-Based Devices: These integrated circuits feature factory-programmed, non-volatile read-only memory directly on the silicon to hold permanent code.
EPROM / One-Time Programmable (OTP) Devices: These utilize electrically programmable ROM, allowing developers to program the chip. OTP variants cannot be erased once programmed, while standard EPROMs require specialized ultraviolet exposure to clear.
Flash Memory (FEEPROM) Devices: One of the most significant advancements in embedded design. These feature electrically erasable on-chip Flash memory that can be cleared and rewritten in seconds. This makes them highly reusable, cost-effective, and ideal for rapid product prototyping and iterative development.

Conclusion

Whether designing a simple microwave oven requiring low-cost 8-bit processing or a complex real-time industrial application, understanding the classifications of microcontrollers is essential. By evaluating devices based on their memory architectures, bit widths, and physical packaging options, system designers can successfully minimize operational power draw and overall hardware costs.

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

8051 Microcontroller Instruction Set | 8051 Microcontroller

noreply@blogger.com (belgaumboy) — Fri, 18 Sep 2026 00:00:00 +0530

In the field of embedded control systems, the instruction set of a microcontroller defines its operational capability and execution efficiency. The Intel 8051 microcontroller utilizes a highly structured instruction set tailored for 8-bit arithmetic, logical operations, data management, and direct hardware manipulation. Understanding how these instructions are grouped and timed is fundamental to developing highly optimized, deterministic firmware.

Instruction Timing Foundations

The internal operations and external read/write functions of the 8051 are driven directly by an oscillator clock. To analyze program execution speed, developers must evaluate three critical timing parameters:

T-state: Defined as one subdivision of an operation performed within a single clock period. The terms "T-state" and "clock period" are synonymous.
Machine Cycle: Defined as 12 oscillator periods. It consists of six states, with each state lasting for two oscillator periods. An instruction typically requires one to four machine cycles to complete its execution.
Instruction Cycle: Representing the total time required to complete the execution of an instruction, it spans between one and four machine cycles.

Execution Time Calculation (At 12 MHz Oscillator)

When the 8051 operates with a 12 MHz oscillator clock, the clock period is computed as:

The time required for a single machine cycle is calculated as:

Based on this 1 uS machine cycle, instruction execution times scale directly with their machine cycle counts:

The Six Core Instruction Groups

The 8051 instruction set is categorized into six functional groups:

1. Data Transfer Instructions

These instructions govern the movement of data between registers, internal RAM, external RAM, and program ROM:

Internal Transfers: Data can be moved from register Rn to the Accumulator (MOV A, R2), from A to register Rn (MOV R4, A), or by loading an immediate 8-bit value into registers or memory (MOV A, #45H, MOV R6, #51H, MOV @R0, #0E8H). It also supports direct and indirect memory-to-accumulator operations (e.g., MOV A, 65H, MOV A, @R0).
External Memory (MOVX): Transfers data between the Accumulator and external memory locations pointed to by registers R0, R1, or the 16-bit Data Pointer (DPTR).
Program Memory (MOVC): Enables read-only access to lookup tables stored in program code space using indexed addressing, such as MOVC A, @A+PC and MOVC A, @A+DPTR.
Stack Operations (PUSH & POP): Stack pointers default to address 07H. During a PUSH instruction, the stack pointer is incremented first (pre-increment), and then the data is written to the stack address. During a POP instruction, the data is retrieved first, and then the stack pointer is decremented (post-decrement).
Data Exchange (XCH & XCHD): XCH exchanges the entire byte of the source with the Accumulator. XCHD (Exchange Digit) swaps only the lower order nibble (bits A0–A3) of the Accumulator with the lower order nibble of an indirectly addressed internal RAM location.

2. Arithmetic Instructions

The 8051 performs fundamental mathematical operations on 8-bit unsigned numbers:

Addition and Subtraction: Addition (ADD, ADDC with carry) and subtraction with borrow (SUBB) affect the Carry (CY), Auxiliary Carry (AC), and Overflow (OV) flags in the Program Status Word.
Multiplication (MUL AB): Multiplies unsigned 8-bit numbers in registers A and B. The lower byte of the 16-bit result is stored in the Accumulator, while the higher byte is stored in register B.
Division (DIV AB): Divides register A by register B. The integer quotient is saved in the Accumulator, and the remainder is placed in register B.
Decimal Adjust (DA A): Used immediately after adding BCD numbers to format the result back into binary-coded decimal. If the lower nibble is greater than 9 or the auxiliary carry flag is set, it adds 6 to the lower nibble. If the upper nibble exceeds 9 or the carry flag is set, it adds 6 to the upper nibble.
Increment and Decrement: INC and DEC alter operands by 1. If a register holding FFH is incremented, it rolls over to 00H without setting the Carry Flag. Similarly, decrementing 00H rolls over to FFH without raising the Carry Flag. INC DPTR is a unique 16-bit operation that increments the Data Pointer, rolling over from FFFFH to 0000H.

3. Logical Instructions

These instructions perform bitwise Boolean logic directly on 8-bit targets:

Bitwise AND, OR, and EX-OR: Executed via ANL, ORL, and XRL instructions. The operations alter the destination bits based on the source but leave the source data unaffected.
Complement (CPL): Reverses the state of the target operand. It can complement the entire Accumulator (CPL A) or target a single bit, such as the Carry flag (CPL C).
Nibble Swapping (SWAP A): Swaps the upper and lower nibbles (4-bit blocks) of the Accumulator.
Rotation (RR A): Rotates the Accumulator bits to the right. Every bit is shifted one location right, and bit 0 rolls over into bit 7.

4. Branch (Jump) Instructions

Control flow is managed through three categories of jumps depending on the required address range:

Relative Jump: Replaces the Program Counter (PC) content with a relative target address located within +127 bytes forward or -128 bytes backward from the instruction following the jump. It specifies only a single-byte jump address in signed 2's complement form, reducing instruction size and speeding up execution. Programs written using relative jumps are highly relocatable. SJMP acts as the unconditional short relative jump, while all conditional jumps (e.g., JZ, JC, DJNZ) are relative jumps.
Short Absolute Jump: Restricted within the same 2 Kilobyte (KB) block. The 64 KB code space is divided into 32 pages of 2 KB each. The absolute address is formed by taking the page number of the instruction following the jump from the upper 5 bits of the PC and attaching the specified 11-bit address to it. Examples include AJMP and ACALL.
Long Absolute Jump: Uses 3-byte instructions such as LJMP and LCALL to access any memory location across the entire 64 KB code memory space (0000H to FFFFH). These jumps are not relocatable because the full 16-bit destination address is embedded within the opcode.

5. Subroutine CALL and RETURN Instructions

Subroutine execution relies on stack storage to preserve program return paths:

LCALL address (16-bit): A 3-byte unconditional call to a subroutine. During execution, the PC is incremented by 3 to point to the instruction below the call. The stack pointer is incremented and stores the lower byte of the return address (PC7–PC0). The stack pointer is incremented again to store the upper byte of the return address (PC15–PC8). Finally, the new 16-bit address is loaded into the PC. No flags are affected.
ACALL address (11-bit): A 2-byte unconditional call restricted to the local 2 KB page. It operates similarly to LCALL, but increments the PC by 2, pushes the return address onto the stack, and loads the target 11-bit address into PC10–PC0.
RET (Return): Terminates the subroutine by popping the return address back off the stack. It copies the top stack byte to the upper byte of the PC (PC15–PC8), decrements the stack pointer, copies the next stack byte to the lower byte of the PC (PC7–PC0), and decrements the stack pointer once more.

6. Bit Manipulation Instructions

The 8051 excels at hardware control due to its direct single-bit processing capability, utilizing the 128 bit-addressable memory space, bit-addressable SFRs, and direct I/O port pins:

Logical Operations: Performs bitwise operations such as ANL C, bit (or ANL C, /bit to AND with the complement of the target bit) and ORL C, bit (or ORL C, /bit), storing the outcome directly in the Carry flag.
Direct Control: Developers can directly clear (CLR bit, CLR C) or complement (CPL bit, CPL C) any bit address without altering neighboring bits in the register or memory address.

Conclusion

The 8051 microcontroller's instruction set provides developers with fine-grained control over execution timing and memory indexing. By dividing instruction classes into logical, arithmetic, and hardware-level bit manipulation directives, the 8051 maintains its status as an exceptionally deterministic and efficient tool for low-level embedded hardware applications.

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

Addressing Modes of 8051 Microcontroller | 8051 Microcontroller

noreply@blogger.com (belgaumboy) — Thu, 17 Sep 2026 00:00:00 +0530

In assembly language programming, a critical step toward writing optimized and efficient firmware is mastering how the processor accesses data. Within the Intel 8051 architecture, the various methods of accessing data are defined as addressing modes.

Before analyzing the individual addressing modes, it is essential to understand the structural foundation of an 8051 assembly instruction.

The 8051 Instruction Syntax

The general syntax for the 8051 assembly language is structured as follows:

LABEL: OPCODE OPERAND; COMMENT

LABEL: This is a symbolic address for the instruction. When the program is compiled, the assembler assigns a specific memory address to the labeled instruction. Labels are optional and only necessary if a specific line of instruction must be targeted by a branching instruction.
OPCODE: The operational code is the symbolic representation of the operation to be performed. The assembler converts this opcode into a unique binary machine language code.
OPERAND: While the opcode defines what operation to execute, the operand specifies where to perform it. Operands generally contain the source and destination of the data, which can either be a direct memory address or the raw data itself.
COMMENT: Indicated by a semicolon (;) or double-slash (//), comments are used strictly to document code and improve program quality.

The 10 Addressing Modes of the 8051

The 8051 microcontroller features ten distinct addressing modes designed to handle data operations, hardware control, and program memory branching.

1. Immediate Addressing Mode

In this mode, the target data is provided directly within the instruction itself, immediately following the opcode. The data is designated by a pound (#) symbol.

Example:
- MOV A,#30H
- ADD A, #83

2. Register Addressing Mode

In register addressing, the data is stored within one of the general-purpose registers. Programmers can specify any of the eight general registers (R0 through R7) from the active register bank. By default, the microcontroller initializes to Register Bank 0.

Example:
- MOV A,R0
- ADD A,R6

3. Direct Addressing Mode

Direct addressing provides a straightforward path to access the 8051’s internal data memory and Special Function Registers (SFRs). The instruction explicitly includes an 8-bit internal memory address, restricting the accessible address range strictly from 00H to FFH.

Example:
- MOV A,60h
- ADD A,30h

4. Indirect Addressing Mode

Instead of containing a static address, the instruction specifies a register that holds the actual target address for the data movement.

Registers Allowed: Only registers R0, R1, and the DPTR can serve as data pointers in this mode. R0 and R1 hold 8-bit addresses, while DPTR accommodates 16-bit addresses.
Limitation: Indirect addressing cannot be used to reference SFRs.
Example:
- MOV A,@R0
- ADD A,@R1
- MOVX A,@DPTR

5. Indexed Addressing Mode

Indexed addressing is highly effective for implementing lookup tables. It uses a base address register—either the Program Counter (PC) or the Data Pointer (DPTR)—and adds the value of the Accumulator (A) as an offset to calculate the final effective address. This mode is exclusively utilized with MOVC or JMP instructions.

Example:
- MOVC A, @A+DPTR (Copies the memory contents pointed to by the sum of A and DPTR into the Accumulator).
- MOVC A, @A+PC (Copies the memory contents pointed to by the sum of A and the Program Counter into the Accumulator).

6. Relative Addressing Mode

Relative addressing is reserved strictly for conditional jump instructions. It utilizes an 8-bit signed offset value that the processor automatically adds to the PC to derive the target address of the next instruction. This signed 8-bit limit allows a branching range of +127 to -128 locations. Code written this way is highly relocatable because the target address is calculated relative to the instruction's position in memory.

Example:
- SJMP LOOP1
- JC BACK

7. Absolute Addressing Mode

Used exclusively by the AJMP (Absolute Jump) and ACALL (Absolute Call) instructions, this is a 2-byte instruction format. It embeds the lowest 11 bits of the destination memory address within the instruction, while the upper 5 bits are pulled from the current Program Counter. Consequently, branching is restricted within the current 2 Kilobyte (KB) page of the program memory.

Example:
- AJMP LOOP1
- ACALL LOOP2

8. Long Addressing Mode

Long addressing is used with 3-byte instructions such as LJMP and LCALL. Because the instruction contains a full 16-bit destination address, the program can branch freely to any location within the entire 64 KB code memory space.

Example:
- LJMP FINISH
- LCALL DELAY

9. Bit Inherent Addressing Mode

In this mode, the target operand address is a single-bit flag that is directly implied by the instruction's opcode. No external address operand is needed.

Example:
- CLR C (Clears the carry flag to 0)

10. Bit Direct Addressing Mode

Unlike inherent addressing, this mode requires the programmer to explicitly specify the direct address of the target bit within the instruction. The bit-addressable area includes RAM space 20H to 2FH and most SFRs, featuring bit addresses ranging from 00H to 7FH.

Example:
- CLR 07h (Clears bit 7 of the 20h RAM space)
- SETB 07H (Sets bit 7 of the 20H RAM space)

Conclusion

The 8051 microcontroller's ten addressing modes provide engineers with a versatile toolkit to access internal registers, manipulate individual hardware bits, or manage external memory spaces. By selecting the appropriate addressing mode, developers can optimize execution speeds and reduce code size, reinforcing why this classic CISC architecture remains a masterclass in embedded system instruction design.

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

Microprocessor VS Microcontroller | 8051 Microcontroller

noreply@blogger.com (belgaumboy) — Wed, 16 Sep 2026 00:00:00 +0530

In the world of digital electronics and computer engineering, the distinction between a microprocessor and a microcontroller is fundamental. While both are integrated circuits that perform computation, they serve entirely different purposes, possess contrasting physical architectures, and target distinct types of systems. Essentially, the microprocessor is the heart of the computer system, whereas the microcontroller is the heart of the embedded system.

Understanding the Microprocessor (MPU)

A microprocessor is a multipurpose, clock-driven, register-based digital integrated circuit that contains the data processing logic and control required to perform the functions of a computer's Central Processing Unit (CPU). It accepts binary data as input, processes it according to instructions stored in its memory, and provides results in binary form as output.

To build a functioning computer system, a microprocessor must interface with external discrete components. It physically contains:

An Arithmetic Logic Unit (ALU).
General-purpose registers.
A Stack Pointer (SP) and Program Counter (PC).
Clock timing and interrupt circuitry.

Because it does not integrate memory or peripherals directly onto its silicon, it requires external RAM, ROM, and I/O devices to operate.

Common Examples: Texas Instruments TMS 1000, Intel 4004, Motorola 800 (MC 800), and AMD Ryzen.

Understanding the Microcontroller (MCU)

In contrast, a microcontroller (MCU) is a self-contained "small computer" fabricated on a single Very Large Scale Integration (VLSI) integrated circuit chip. Instead of relying on a network of external chips, a microcontroller consolidates all the essential components of a complete computer system directly onto its silicon.

A microcontroller contains:

One or more CPU cores (essentially incorporating the circuitry of a microprocessor).
On-chip program memory (such as NOR flash, ferroelectric RAM, or One-Time Programmable ROM) alongside a small amount of data RAM.
Programmable input/output (I/O) peripherals, timers, and counters.

Microcontrollers are specifically designed for embedded applications where space, cost, and physical simplicity are critical.

Common Examples: PIC 18F8720, Intel 8742, and ATmega microcontrollers.

Key Structural and Architectural Differences

The architectural divide between microprocessors and microcontrollers manifests in several distinct technical characteristics:

1. Integration vs. External Dependency

Microprocessor: Requires additional external hardware to function (external RAM, ROM, and I/O). This makes the overall system design highly flexible but physically larger and more complex.
Microcontroller: Demands very little additional hardware because its RAM, ROM, and peripherals are integrated on-chip. However, it is less flexible because these built-in circuits are fixed for any given chip.

2. Memory Organization

Microprocessor: Typically utilizes a single memory map for both data and code (program instructions).
Microcontroller: Commonly employs a separate memory map for data and code.

3. Instruction Sets and Data Handling

Microprocessor: Possesses a large number of instructions with flexible addressing modes. It is heavily optimized for moving large chunks of data between external memory and the CPU, but has few instruction sets dedicated to manipulating individual bits.
Microcontroller: Features a limited instruction set with fewer addressing modes. Crucially, because it interacts directly with physical hardware pins, it has many bit-manipulation instructions but fewer instructions for bulk CPU-to-memory data movement.

4. Execution Speed and Pin Configuration

Microprocessor: Memory and I/O access times are longer because signals must travel across external buses on a circuit board. Additionally, fewer of its physical pins are designed to be multifunctional.
Microcontroller: Built-in memory and integrated I/O access times are remarkably low. To save physical space on compact chips, a larger number of its physical pins are multifunctional (sharing roles between general I/O, timers, or communication buses).

Summary of Key Differences

Feature	Microprocessor	Microcontroller
System Role	Heart of a computer system.	Heart of an embedded system.
On-Chip Memory & I/O	None. Requires external chips.	Integrated ROM, RAM, and I/O on a single chip.
Hardware Footprint	Large; requires extensive external hardware.	Small; requires minimal external hardware.
Instruction Set Focus	General data movement and processing.	Hardware control and bit handling.
Design Flexibility	High (memory and peripherals can be scaled).	Low (on-chip resources are permanently fixed).

Conclusion

When choosing between these two components, engineers must evaluate the primary goal of the application. If the project requires raw, general-purpose processing power with massive memory requirements—such as a personal computer—the microprocessor is the correct choice. However, if the goal is to build a compact, cost-effective, and highly deterministic device to control a specific appliance or hardware task, the microcontroller is the ideal solution.

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

8051 Microcontroller Architecture - 02 | 8051 Microcontroller

noreply@blogger.com (belgaumboy) — Tue, 15 Sep 2026 00:00:00 +0530

In the landscape of embedded systems, understanding the fundamental computer engineering principles that govern processor design is essential. To appreciate how classic systems operate, we must examine the core classifications of microcontroller units (MCUs) and the underlying hardware philosophies that dictate how they process instructions and handle memory.

The Anatomy of a Microcontroller

A microcontroller is fundamentally a small computer integrated onto a single Very Large Scale Integration (VLSI) integrated circuit (IC) chip. Unlike general-purpose microprocessors that rely on various external discrete chips, a microcontroller is designed specifically for embedded applications and consolidates several critical components onto its silicon:

One or more CPUs (processor cores) to handle instruction execution.
On-chip memory, which typically includes a small amount of RAM alongside program memory (such as ferroelectric RAM, NOR flash, or One-Time Programmable ROM).
Programmable input/output peripherals to interface with external hardware.

The Intel-designed 8051 family remains one of the most prominent and historically significant 8-bit microcontrollers in this category.

The CISC Foundation of the 8051

Processors are broadly classified by their instruction set designs into Reduced Instruction Set Computers (RISC) and Complex Instruction Set Computers (CISC). The Intel 8051 is a classic example of a CISC machine, in contrast to RISC devices like the Microchip PIC 18F87X.

CISC architectures like the 8051 are characterized by several distinct structural properties:

Variable Instruction Cycles: Instructions in a CISC machine typically require multiple machine cycles to execute, whereas RISC instructions are streamlined to take only one or two cycles.
Flexible Memory Access: While RISC structures strictly limit memory access to dedicated load/store instructions, a CISC architecture allows direct memory access through a wide variety of other instructions.
Microprogram Execution: The instruction execution in CISC is driven by an internal microprogram. Consequently, the physical complexity of the machine is heavily concentrated within this microprogram rather than the hardware control logic itself.
Instruction Complexity: CISC systems feature a complex instruction set with variable instruction formats and a wide array of addressing modes to handle diverse programming tasks.
Register and Pipeline Structure: CISC machines typically utilize a single register bank and incorporate less pipelining compared to highly pipelined RISC architectures.

Memory Paradigms: Von-Neumann vs. Harvard

Beyond instruction sets, microcontroller performance is deeply tied to how the CPU interacts with memory. The industry divides these layouts into Von-Neumann (Princeton) architecture and Harvard architecture:

Feature	Von-Neumann (Princeton) Architecture	Harvard Architecture
Memory Space	Uses a single, shared memory space for both instructions and data.	Utilizes completely separate memory spaces for program instructions and data.
Data Fetching	Code and data cannot be fetched simultaneously due to the shared bus.	Code and data can be fetched simultaneously, enabling parallel operations.
Execution Speed	Requires more machine cycles to execute an instruction.	Executes instructions in fewer machine cycles.
Architectural Class	Typically paired with CISC architectures.	Typically paired with RISC architectures.
Core Principle	Known as a control-flow or control-driven computer, with instruction pre-fetching as a core feature.	Known as a data-flow or data-driven computer, emphasizing instruction parallelism.
Design Complexity	Simplifies physical chip design because of the single shared memory space.	Increases chip design complexity due to the separate hardware paths.
Examples	Classical microprocessors such as the 8085, 8086, and MC6800.	General-purpose microcontrollers and specialized Digital Signal Processing (DSP) chips.

The 8-Bit Ecosystem

The Intel 8051 is part of a diverse historical cohort of popular 8-bit microcontrollers. When selecting a hardware platform, engineers traditionally evaluate the 8051 alongside competing architectures, including Atmel's AVR family, Microchip's PIC family, Freescale's HCS08, and Zilog's Z8. Understanding these structural differences—from instruction cycles to memory access pipelines—is the key to writing highly optimized, deterministic embedded software.

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

8051 Microcontroller Architecture - 01 | 8051 Microcontroller

noreply@blogger.com (belgaumboy) — Mon, 14 Sep 2026 00:00:00 +0530

The Intel-designed 8051 microcontroller remains one of the most enduring and foundational architectures in the field of embedded hardware. Featuring a highly structured design, it is widely utilized for teaching microcontroller concepts and building robust, deterministic control systems. Understanding its internal blocks, memory layout, and pinout is essential for any hardware or embedded software engineer.

Core Architectural Features of the CPU

At the heart of the 8051 architecture lies an 8-bit CPU and an Arithmetic Logic Unit (ALU) capable of performing arithmetic and logical operations on 8-bit variables. The CPU is supported by a set of essential registers:

Accumulator (A Register): An 8-bit register that serves as the primary destination and source for arithmetic, logical, and external memory data transfer operations.
B Register: Used alongside the Accumulator to perform multiplication and division operations. Together, the A and B registers are referred to as MATH registers.
Program Status Word (PSW): An 8-bit register containing the status of the ALU. It includes flags such as the Carry (CY), Auxiliary Carry (AC), Overflow (OV), and Parity (P) flags, as well as the register bank select bits (RS1, RS0).

Comprehensive Memory Organization

One of the defining aspects of the 8051 is its highly efficient, segmented memory organization, which consists of distinct code (program) and data memory spaces:

1. Program Memory (ROM)

The standard 8051 contains 4 Kilobytes (KB) of on-chip ROM, spanning addresses from 0000h to 0FFFh. If program code exceeds 4 KB, the microcontroller is capable of automatically fetching instructions from up to 64 KB of external program memory space.

2. Data Memory (RAM)

The 8051 contains 128 bytes of internal data memory (RAM), which is divided into three distinct functional areas to maximize execution efficiency:

Working Registers (00h to 1Fh): Configured as four distinct register banks, with each bank containing eight general-purpose registers (R0 through R7). The active register bank is determined by the RS1 and RS0 bits in the PSW. On reset, the microcontroller defaults to Register Bank 0.
Bit-Addressable RAM (20h to 2Fh): A specialized 16-byte area (providing 128 individual bit variables) where bits can be individually set or cleared using direct commands such as SETB and CLR.
General-Purpose RAM (30h to 7Fh): Often referred to as scratchpad memory, this 80-byte block is ideal for general data storage using direct or indirect addressing modes.

Pointer and Control Registers

To manage program flow and data access, the 8051 employs specialized 8-bit and 16-bit pointers:

Program Counter (PC): A 16-bit register that holds the address of the next instruction to be fetched and executed. Upon a system reset, the PC is initialized to 0000h.
Data Pointer (DPTR): Consisting of two 8-bit registers—DPH (high byte) and DPL (low byte)—this 16-bit register is used to supply address information for both internal and external program memory, as well as external data memory.
Stack Pointer (SP): An 8-bit register that points to the top of the stack, which resides within the internal RAM. When a PUSH operation occurs, the SP is incremented before data is stored (pre-increment). During a POP operation, the data is retrieved first, and then the SP is decremented (post-decrement). On reset, the SP is set to 07h, allowing the stack to safely grow from address 08h onwards to protect the default registers in Bank 0.

Pin Configuration and External Interfaces

The physical 8051 microcontroller is housed in a 40-pin package. Its interface features 32 bi-directional I/O lines, which can be configured as 32 individual lines or organized as four 8-bit ports (Ports 0, 1, 2, and 3):

Port 1 (Pins 1–8): Configured strictly as general-purpose input/output lines.
Port 3 (Pins 10–17): In addition to general I/O, these pins have alternative dedicated functions, including serial communication (RXD/TXD), external interrupts (INT0/INT1), timer clock inputs (T0/T1), and external memory read/write control (RD/WR).
Port 2 (Pins 21–28) & Port 0 (Pins 32–39): When external memory is used, Port 2 outputs the higher byte of the address bus (A8–A15), and Port 0 multiplexes the lower address byte (A0–A7) and the data bus.
Control Pins: Key pins like ALE (Address Latch Enable) coordinate the multiplexing of Port 0, while PSEN (Program Store Enable) activates external ROM, and EA (External Access) forces the execution of external program memory when driven low.

Conclusion

The elegant, highly structured layout of the 8051 microcontroller architecture is the reason it remains a classic in embedded systems design. By partitioning memory into distinct program and data sectors, and providing specialized registers and pin control structures, the 8051 delivers efficient execution and deterministic operation in a remarkably compact silicon footprint.

For all 2026 published articles list: click here:

…till the next post, bye-bye & take care

AVR Microcontrollers & its Features | 8051 Microcontroller

noreply@blogger.com (belgaumboy) — Sun, 13 Sep 2026 00:00:00 +0530

Developed by Atmel in 1997, the AVR microcontroller represents a major milestone in modern embedded systems. Originally conceived by Alf-Egil Bogen and Vegard Wollan—two students at the Norwegian Institute of Technology (NTH) whose names are immortalized in the "AVR" acronym—the architecture was acquired and refined by Atmel to provide high-speed, efficient processing for embedded applications. Today, these chips are widely used for high-speed signal processing operations inside embedded systems.

Core Architecture: RISC and Harvard Principles

The AVR is an 8-bit single-chip microcontroller characterized by its high-speed performance and simplified structure. At its core, the AVR architecture leverages two key design philosophies:

Harvard Architecture: By maintaining separate memory spaces and buses for program instructions and data, the AVR can execute instructions with exceptional efficiency.
Enhanced RISC (Reduced Instruction Set Computer): Rather than simply minimizing instructions, AVR's RISC architecture streamlines and rationalizes the computer structure to maximize computing speeds.
8-bit CPU Processing: With the exception of the 32-bit AVR32, AVR microcontrollers are 8-bit devices. This means the CPU works on 8 bits of data at a time; any data larger than 8 bits must be divided into 8-bit segments for processing.

Integrated Memory Layout

AVR microcontrollers integrate three distinct types of on-chip memory to facilitate rapid data handling and robust program execution:

Program ROM (Flash Memory): The AVR was one of the first microcontrollers to implement on-chip Flash memory for program storage. This memory is ideal for rapid prototyping because it can be erased in seconds, unlike older UV-EPROM units which took 20 minutes or more. While the architecture supports a maximum program ROM space of up to 8 Megabytes (MB), individual chips typically feature program ROM ranging from 1 KB to 256 KB.
Data RAM (SRAM): The AVR supports a maximum of 64 KB of data RAM, which comprises three components: 32 general-purpose registers, I/O memory, and internal SRAM used as a read/write scratchpad.
EEPROM: A small, dedicated block of EEPROM is included to safely store critical, non-volatile data that does not require frequent modification.

Classification and the AVR Family Tree

To accommodate varying system requirements, AVR microcontrollers are broadly organized into four distinct families:

Classic AVR (AT90SXXXX): This represents the original AVR line, which has now been replaced by modern, high-performance variants.
Mega AVR (ATmegaxxxx): Designed for high-performance applications, these robust processors feature a rich instruction set of over 120 instructions. They offer program memory capacities from 4 KB to 256 KB and packages ranging from 28 to 100 pins. The ATmega32 is particularly popular in educational settings due to its availability in Dual In-line Packages (DIP).
Tiny AVR (ATtinyxxxx): Optimized for low cost and minimal power consumption, Tiny AVRs feature smaller pin packages (8 to 28 pins), a limited peripheral selection, and a restricted instruction set (some models, for instance, lack a dedicated multiply instruction). Their program memory ranges from 1 KB to 8 KB.
Special Purpose AVR: This group serves specialized applications by integrating advanced hardware controllers directly onto the silicon, such as CAN, USB, LCD, Zigbee, Ethernet, FPGA, or advanced PWM controllers.

Standard Peripherals and I/O Versatility

AVR microcontrollers are highly integrated and come equipped with an array of standard and advanced peripheral interfaces:

Input/Output (I/O) Pins: Depending on the physical package size (which ranges from 8 to 100 pins), an AVR can offer anywhere from 3 to 86 I/O pins. For example, the 8-pin AT90S2323 provides 3 I/O pins, while the 100-pin ATmega1280 supports up to 86.
On-Chip Peripherals: Standard configurations include up to 6 timers (plus a watchdog timer), a 10-bit Analog-to-Digital Converter (ADC) supporting up to 16 channels, and a USART for interfacing with serial interfaces (such as an x86 PC's COM port). Most models also support standard communication buses like SPI, I2C (also known as TWI), CAN, and USB.

Deciphering the Naming Scheme

Atmel uses a highly logical product numbering system that makes it easy to identify a chip's capacity:

Every part number starts with "AT" (standing for Atmel).
To determine the ROM size, locate the largest power of 2 at the end of the product number (reading from left to right). For example, the ATmega1280 features 128 KB of ROM, and the ATtiny44 features 4 KB. (Exceptions like the AT90PWM216, which has 16 KB of ROM instead of 2 KB, are rare).

The Software Compatibility Trade-Off

One notable drawback of the AVR architecture is that different families are not 100% software-compatible. If an engineer wishes to run code originally written for an ATtiny25 on a larger ATmega64, the program must be recompiled, and specific register locations may need to be adjusted before flashing the program.

Conclusion

By combining high-speed RISC processing, a clean Harvard architecture, and highly integrated on-chip peripherals, the AVR family has earned its place as a cornerstone of modern embedded system design. From ultra-low-power Tiny chips to highly complex Mega and Special Purpose microcontrollers, the AVR family offers a scalable, efficient solution for virtually any digital control challenge.

For all 2026 published articles list:click here:

…till the next post, bye-bye & take care

Printing Alternating Alphabet Patterns in C | Conditional Patterns

noreply@blogger.com (belgaumboy) — Sat, 12 Sep 2026 00:00:00 +0530

Combining character manipulation with row-level conditional checks allows you to build dynamic, formatted text arrangements in C. Continuing our Pattern Programming in C series, today’s article focuses on the Alternating Alphabet Triangle. This tutorial demonstrates how to use nested loops and parity logic to switch character cases or sequence types across alternating rows.

Pattern Title: Alternating Case Alphabet Triangle Pattern in C

Purpose: Strengthen your understanding of nested loops, ASCII character arithmetic, and row-index parity logic.

Prerequisites: Knowledge of basic for loops, printf, scanf, standard character types (char), and if-else control flow.

Final Output

For an input of rows = 5, the program generates:

A 
b c 
D E F 
g h i j 
K L M N O 

Deconstructing the Pattern: The Logic

Problem Statement

Write a C program that accepts an integer n for the total number of rows. The program must generate a right-angled triangle filled sequentially with alphabetic letters, where odd-numbered rows display uppercase letters (A, B, C...) and even-numbered rows display lowercase letters (a, b, c...).

Pattern Analysis & Dynamic Logic

Rows (Outer Loop): Control variable i runs from 1 to n.
Columns (Inner Loop): Control variable j runs from 1 to i, controlling how many characters appear in the current row.
Character Tracking: Maintain a continuous offset or global sequence tracker (letter_index starting at 0 for 'A'/'a').
Conditional Parity Check:
- If the row index i is odd (i % 2 != 0), output the character in uppercase: 'A' + letter_index.
- If the row index i is even (i % 2 == 0), output the character in lowercase: 'a' + letter_index.
Character Reset: Wrap the alphabet back to the start (index % 26) to avoid non-alphabetic ASCII symbols when iterating past 26 characters.

Step-by-Step Algorithm

Prompt the user to enter the number of rows n.
Initialize an integer tracking variable letterIndex = 0.
Execute an outer loop i from 1 to n.
Execute an inner loop j from 1 to i.
Evaluate i % 2:
- If i % 2 != 0 (odd row), calculate character as 'A' + (letterIndex % 26).
- If i % 2 == 0 (even row), calculate character as 'a' + (letterIndex % 26).
Print the computed character followed by a space and increment letterIndex.
Output a newline character (\n) after each row completes.

Code Implementation

#include <stdio.h>

int main() {
    int n;

    // Prompt user for input
    printf("Enter the number of rows: ");
    if (scanf("%d", &n) != 1 || n <= 0) {
        printf("Please enter a valid positive integer.\n");
        return 1;
    }

    int letterIndex = 0;

    // Outer loop for rows
    for (int i = 1; i <= n; i++) {
        // Inner loop for columns in row 'i'
        for (int j = 1; j <= i; j++) {
            // Check row parity for alternating case
            if (i % 2 != 0) {
                // Odd rows: Uppercase
                printf("%c ", 'A' + (letterIndex % 26));
            } else {
                // Even rows: Lowercase
                printf("%c ", 'a' + (letterIndex % 26));
            }
            letterIndex++;
        }
        // Move to the next line after completing the row
        printf("\n");
    }

    return 0;
}

Line-by-Line Code Breakdown

if (scanf("%d", &n) != 1 || n <= 0): Ensures clean input validation by checking for non-numeric or non-positive integer values.
int letterIndex = 0;: Serves as a continuous offset tracker across all rows.
if (i % 2 != 0): Evaluates whether the current row index is odd or even to select character casing.
'A' + (letterIndex % 26): Uses standard ASCII arithmetic to derive the correct uppercase character while wrapping around at 26 letters.
'a' + (letterIndex % 26): Derives the matching lowercase character for even rows.
printf("\n");: Terminates the current row to maintain proper triangle geometry.

Compiling & Execution

Sample Run

Enter the number of rows: 4
A 
b c 
D E F 
g h i j 

Variations & Enhancements

Column-Based Alternating Case: Evaluate j % 2 instead of i % 2 to alternate uppercase and lowercase characters across columns within the exact same row.
Alternating Alphabet Directions: Reverse letter placement on even rows to print forward on odd rows (A, B, C) and backward on even rows (f, e, d).
Inverted Triangle: Reverse the outer loop (for (int i = n; i >= 1; i--)) to output a top-heavy triangular pattern.

Common Mistakes & Troubleshooting

ASCII Overflow: Forgetting modulo arithmetic (% 26) will cause printing to extend into non-alphabetic ASCII characters (such as [, \, ]) when total letters exceed 26.
Confusing Row vs. Column Parity: Checking j % 2 instead of i % 2 toggles casing per character rather than per row.
Missing Line Break: Leaving out printf("\n"); outputs the entire character series as a single line.

Complexity Analysis

Time Complexity: $\mathcal{O}(n^2)$ — requires $n(n+1)/2$ total iterations across nested loops.
Space Complexity: $\mathcal{O}(1)$ — operates strictly using constant memory space.

Combining character arithmetic with conditional parity checks provides flexible control over ASCII output layouts.

Try modifying the program to print alternating alphabet rows forward and backward! Post your implementation in the comments below.

For all Pattern Programs list click here:

…till the next post, bye-bye & take care

Printing Conditional Alphabet Patterns (e.g., Vowels/Consonants) in C | Conditional Patterns

noreply@blogger.com (belgaumboy) — Fri, 11 Sep 2026 00:00:00 +0530

Combining character arithmetic with conditional checks inside nested loops provides a dynamic way to generate formatted text structures. Today's article in our Pattern Programming in C series covers Conditional Alphabet Patterns. This tutorial demonstrates how to apply logic to filter characters—specifically isolating vowels—to build a customized triangular pattern.

Pattern Title: Vowels-Only Triangle Pattern in C

Purpose: Enhance your nested loop logic, character handling, and conditional reasoning by generating alphabet sequences filtered by specific properties.

Prerequisites: Knowledge of basic for loops, printf, scanf, character data types (char), and if-else control flow.

Final Output

For an input of rows = 4, the program generates:

A 
E I 
O U A 
E I O U 

Deconstructing the Pattern: The Logic

Problem Statement

Write a C program that accepts an integer n for the total number of rows. The program must print a right-angled triangle where each position is filled sequentially by uppercase English vowels (A, E, I, O, U). When the sequence reaches U, it wraps around to start again at A.

Pattern Analysis & Logic

Rows (Outer Loop): i runs from 1 to n.
Columns (Inner Loop): j runs from 1 to i, dictating the total characters printed in each row.
Conditional Character Filtering: We evaluate standard uppercase characters (A–Z) sequentially. A character is printed only if it passes a vowel check (ch == 'A' || ch == 'E' || ch == 'I' || ch == 'O' || ch == 'U').
Character Reset: After finding and printing a vowel, we advance to the next character in the alphabet, wrapping back to 'A' after 'Z'.

Step-by-Step Algorithm

Prompt the user to enter the number of rows n.
Initialize a tracking character variable ch = 'A'.
Execute an outer loop with control variable i running from 1 to n.
Execute an inner loop with control variable j running from 1 to i.
Inside the inner loop, use a while loop to find the next vowel:
- Test if ch is a vowel.
- If it is not a vowel, increment ch (wrapping to 'A' if it exceeds 'Z') and re-check.
Print the valid vowel followed by a space, increment ch (handling wrap-around), and complete the inner iteration.
Print a newline character (\n) after completing each row.

Code Implementation

#include <stdio.h>
#include <stdbool.h>

// Helper function to check if a character is an uppercase vowel
bool isVowel(char c) {
    return (c == 'A' || c == 'E' || c == 'I' || c == 'O' || c == 'U');
}

int main() {
    int n;

    // Prompt user for input
    printf("Enter the number of rows: ");
    if (scanf("%d", &n) != 1 || n <= 0) {
        printf("Please enter a valid positive integer.\n");
        return 1;
    }

    char ch = 'A';

    // Outer loop for rows
    for (int i = 1; i <= n; i++) {
        // Inner loop for columns in row 'i'
        for (int j = 1; j <= i; j++) {
            // Advance until a vowel is found
            while (!isVowel(ch)) {
                ch++;
                if (ch > 'Z') {
                    ch = 'A';
                }
            }
            
            // Print the vowel
            printf("%c ", ch);

            // Move to next character for future iterations
            ch++;
            if (ch > 'Z') {
                ch = 'A';
            }
        }
        // Move to the next line after completing the row
        printf("\n");
    }

    return 0;
}

Line-by-Line Code Breakdown

bool isVowel(char c): A helper function returning true if c matches any uppercase vowel.
if (scanf("%d", &n) != 1 || n <= 0): Performs strict input validation to guard against non-numeric or non-positive input values.
while (!isVowel(ch)): Skips non-vowel characters until the next valid vowel is reached.
if (ch > 'Z') { ch = 'A'; }: Ensures the character pointer safely wraps back to the beginning of the alphabet without outputting non-alphabetic ASCII symbols.
printf("%c ", ch);: Outputs the target character followed by spacing for alignment.
printf("\n");: Moves execution to the next line after each row finishes.

Compiling & Execution

Sample Run

Enter the number of rows: 5
A 
E I 
O U A 
E I O U 
A E I O U 

Variations & Enhancements

Consonants-Only Triangle: Invert the conditional check (!isVowel(ch)) to generate patterns composed strictly of consonant letters.
Alternating Vowel/Consonant Rows: Toggle the condition on alternating rows using i % 2 to print vowels on odd rows and consonants on even rows.
Lowercase Conversion: Adapt the character check and range ('a' to 'z') to render the pattern in lowercase.

Common Mistakes & Troubleshooting

ASCII Overflow: Forgetting to wrap back to 'A' when ch exceeds 'Z' causes non-alphabetic ASCII characters (like [, \, ]) to appear in your pattern.
Missing Counter Increment: Failing to increment ch after printing causes the loop to get stuck on the same character infinitely.
Missing Line Break: Forgetting printf("\n"); outputs all characters onto a single continuous line.

Complexity Analysis

Time Complexity: $\mathcal{O}(n^2)$ — requires $n(n+1)/2$ total character output operations, with minor constant iterations for character filtering.
Space Complexity: $\mathcal{O}(1)$ — operates using constant auxiliary memory.

Mastering character arithmetic alongside conditional filtering opens up powerful possibilities for string and text-based pattern generation.

Try altering the condition to build a Consonants-Only Pattern! Share your code implementation in the comments below.

For all Pattern Programs list click here:

…till the next post, bye-bye & take care

Printing Multiplication Table Patterns in C | Conditional Patterns

noreply@blogger.com (belgaumboy) — Thu, 10 Sep 2026 00:00:00 +0530

Integrating conditional arithmetic and structured loops transforms basic multiplication tables into visually appealing numerical grids. Today’s article in our Pattern Programming in C series covers Multiplication Table Patterns. This tutorial demonstrates how to leverage nested loops to render both triangular and grid-based multiplication matrices.

Pattern Title: Triangular Multiplication Table Pattern in C

Purpose: Boost your nested loop logic by generating matrix products dynamically based on row and column index relationships.

Prerequisites: Familiarity with basic for loops, printf, scanf, and standard arithmetic operators.

Final Output

For an input of rows = 5, the program generates:

1 
4 
6 9 
8 12 16 
10 15 20 25 

Deconstructing the Pattern: The Logic

Problem Statement

Write a C program that prompts the user for the number of rows n and prints a triangular grid where the element at row i and column j represents the product of $i \times j$ .

Pattern Analysis & Dynamic Logic

Rows (Outer Loop): Control variable i runs from 1 to n (representing the base factor).
Columns (Inner Loop): Control variable j runs from 1 to i (representing the multiplier).
Cell Calculation: Each printed value is computed dynamically as i * j.
Formatting: Proper spacing or tab formatting (\t or %3d) ensures clean visual alignment regardless of single or multi-digit products.

Algorithm

Read the positive integer n from the user.
Execute an outer loop with variable i running from 1 to n.
Execute an inner loop with variable j running from 1 to i.
Compute the product: $\text{val} = i \times j$ .
Print val formatted with consistent field width for alignment.
Output a newline character (\n) after completing the inner loop to end the row.

Code Implementation

#include <stdio.h>

int main() {
    int n;

    // Prompt user for input
    printf("Enter the number of rows: ");
    if (scanf("%d", &n) != 1 || n <= 0) {
        printf("Please enter a valid positive integer.\n");
        return 1;
    }

    // Outer loop for rows (base factor)
    for (int i = 1; i <= n; i++) {
        // Inner loop for columns (multiplier)
        for (int j = 1; j <= i; j++) {
            // Print product of i and j with width formatting for alignment
            printf("%-4d", i * j);
        }
        // Move to the next line after completing the row
        printf("\n");
    }

    return 0;
}

Line-by-Line Code Breakdown

if (scanf("%d", &n) != 1 || n <= 0): Performs strict input validation to handle non-numeric or non-positive integer values gracefully.
for (int i = 1; i <= n; i++): Dictates row progression, setting i as the multiplicand.
for (int j = 1; j <= i; j++): Controls column generation up to i iterations, setting j as the multiplier.
printf("%-4d", i * j);: Multiplies i and j directly and prints the result left-aligned in a 4-character wide field.
printf("\n");: Moves the cursor to the next line to complete the triangular shape.

Compiling & Execution

Sample Run

Enter the number of rows: 5
 
 4   
 6   9   
 8   12  16  
 10  15  20  25  

Variations & Enhancements

Full Matrix Grid: Change the inner loop condition to j <= n to print a full $n \times n$ multiplication grid.
Conditional Filter: Apply an if-else block to print products only when they satisfy a condition (e.g., if ((i * j) % 2 == 0)) and print spaces or symbols otherwise.
Inverted Triangular Table: Reverse the outer loop (for (int i = n; i >= 1; i--)) to output a descending multiplication triangle.

Common Mistakes & Troubleshooting

Alignment Misalignment: Using a plain space (" ") causes grid distortion when products transition from 1-digit to 2-digit numbers. Use width specifiers (e.g., %-4d) or tabs (\t).
Confusing Factors: Swapping i * j with arbitrary variables can lead to incorrect sequence outputs.
Missing Line Breaks: Omitting printf("\n"); outputs all calculated products onto a single continuous line.

Complexity Analysis

Time Complexity: $\mathcal{O}(n^2)$ — executing $n(n+1)/2$ total product calculations across nested loops.
Space Complexity: $\mathcal{O}(1)$ — runs in constant memory space.

Mastering grid calculations and output formatting in nested loops builds strong foundational skills for complex multi-dimensional array operations.

Try expanding this code to display only odd multiplication products while hiding even ones! Drop your code in the comments section below.

For all Pattern Programs list click here:

…till the next post, bye-bye & take care

8051 microcontroller tutorial

Traffic light controller - Interfacing 8255 with 8085 | 8085 Lab Program

ASCII to Hexadecimal conversion | 8085 Lab Program

Hexadecimal to ASCII conversion | 8085 Lab Program

Hexadecimal to Decimal conversion | 8085 Lab Program

Decimal to Hexadecimal conversion | 8085 Lab Program

Sorting an array of data in Descending order | 8085 Lab Program

Sorting an array of data in Ascending order | 8085 Lab Program

‘Learn Arduino Using TinkerCAD Circuits Simulator’ eBook’s Simulation & Resource Hyperlinks list page

Part II: Arduino Programming Essentials (Sketch & IDE Simulation)

Part III: Core I/O and Sensing in Simulation

Part IV: Actuators, Displays, and Specialized Components

Part V: Advanced System Design and Protocols

Part VI: Comprehensive Project Simulations

Smallest element in an array | 8085 Lab Program

Largest element in an array | 8085 Lab Program

8 bit data division | 8085 Lab Program

8 bit data multiplication | 8085 Lab Program

8 bit data subtraction | 8085 Lab Program

8 bit data addition | 8085 Lab Program

Interrupts in 8051 Microcontroller | 8051 Microcontroller

The 8051 Interrupt Execution Process

Taxonomy of Interrupts

The 8051 Interrupt Vector Table

Control and Priority Registers

1. IE Register (Interrupt Enable)

2. IP Register (Interrupt Priority)

3. TCON Register (Timer Control)

Conclusion

Types of Microcontroller | 8051 Microcontroller

1. Classification by Memory Architecture

2. Classification by Manufacturer / Vendor Ecosystem

3. Classification by Bus Width (Word Size)

4. Classification by Onboard Memory Configuration

Conclusion

8051 Microcontroller Instruction Set | 8051 Microcontroller

Instruction Timing Foundations

Execution Time Calculation (At 12 MHz Oscillator)

The Six Core Instruction Groups

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logical Instructions

4. Branch (Jump) Instructions

5. Subroutine CALL and RETURN Instructions

6. Bit Manipulation Instructions

Conclusion

Addressing Modes of 8051 Microcontroller | 8051 Microcontroller

The 8051 Instruction Syntax

The 10 Addressing Modes of the 8051

1. Immediate Addressing Mode

2. Register Addressing Mode

3. Direct Addressing Mode

4. Indirect Addressing Mode

5. Indexed Addressing Mode

6. Relative Addressing Mode

7. Absolute Addressing Mode

8. Long Addressing Mode

9. Bit Inherent Addressing Mode

10. Bit Direct Addressing Mode

Conclusion

Microprocessor VS Microcontroller | 8051 Microcontroller

Understanding the Microprocessor (MPU)

Understanding the Microcontroller (MCU)

Key Structural and Architectural Differences

1. Integration vs. External Dependency

2. Memory Organization

3. Instruction Sets and Data Handling

4. Execution Speed and Pin Configuration

Summary of Key Differences

Conclusion

8051 Microcontroller Architecture - 02 | 8051 Microcontroller

The Anatomy of a Microcontroller

The CISC Foundation of the 8051

Memory Paradigms: Von-Neumann vs. Harvard

The 8-Bit Ecosystem

8051 Microcontroller Architecture - 01 | 8051 Microcontroller

Core Architectural Features of the CPU

Comprehensive Memory Organization

1. Program Memory (ROM)

2. Data Memory (RAM)