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Atomic Layer Etching as a Scaling Enabler: From Isotropic Chemistry to Selective, Directional, and Geometry-Driven Patterning

2025-12-23T08:12:00.005+01:00

Continued scaling in semiconductor manufacturing increasingly relies on atomic-scale control of etching for complex 3D material stacks, making patterning precision a growing industrial bottleneck. Atomic layer etching (ALE) has emerged as a key enabler, with plasma-driven anisotropy and surface-chemistry control allowing improved selectivity and profile fidelity for advanced logic and memory integration. Current approaches emphasize decoupling surface modification from material removal to enable low-temperature, highly controlled processes.

From an industry perspective, the focus is shifting toward systematic ALE process development frameworks that combine thermodynamic screening, tailored half-cycle chemistries, and experimental verification of etch rates and selectivity. These strategies are increasingly relevant as device architectures push beyond conventional materials and dimensions. At the same time, ALE is gaining attention for its potential to reduce process complexity, energy use, and chemical consumption, positioning it as both a scaling and sustainability enabler for future semiconductor manufacturing.

In a recent paper by Smith et al (reference below), Thermal ALE is described as a purely chemical, vapor- or gas-phase process in which both the surface modification and removal steps are self-limiting and thermally activated. Volatile products are typically formed through ligand-exchange reactions that generate metalorganics. Because no ions are involved, this mode of ALE is intrinsically isotropic, leading to uniform material removal in all directions. This makes thermal ALE attractive for conformal trimming, lateral recessing, and highly selective etches, but fundamentally limits its ability to produce vertical, profile-controlled features.

(a) Periodic table of the elements showing which metals, metal oxides, and metal nitrides have had ALE processes developed for them. In developing a new ALE process, determining the nature of the volatile etch product is critical, with some metals proving more favorable to etching via the formation of volatile metalorganics and others via volatile metal halides. Data compiled from the ALE Database [reference]. (b) An outline of the pathways by which reported ALE processes can proceed. Metals, metal oxides, and metal nitrides can be halogenated, with the modified layer removed by subsequent Ar⁺ sputtering or ligand exchange. Metals can be oxidized or nitrided, and the metal oxide or nitride subsequently etched. (c) Gibbs free energy minimization and volatility diagram analysis can be used to theoretically screen possible etch processes. (d) Various surfaces of Ni modified with (1) surface O, (2) mixed surface and subsurface O, and (3) subsurface O. The Gibbs free energy of reaction showed the importance of having an oxidized sublayer to achieve favorable thermodynamic etching. Adapted from ref [reference]. (e) Analysis of Gibbs free energy of reaction: nitridation of nickel could form metastable Ni3N, which can be etched through favorable reactions with formic acid, forming dimers of nickel formates. by Smith et al (reference below)

In contrast, plasma ALE introduces ions as an active control parameter, most commonly during the removal step. A plasma first forms a chemically modified surface layer, such as a halogenated or oxidized film, which is then selectively removed by directional ion bombardment within a narrow ALE energy window. The momentum of the ions provides anisotropy, enabling vertical etching with atomic-scale precision while suppressing continuous sputtering. This directionality comes at the cost of tighter process windows and increased sensitivity to ion-induced damage.

A hybrid plasma–thermal ALE approach is presented as a way to decouple anisotropy from volatilization chemistry. In this scheme, plasma exposure is used to directionally modify the surface or precisely control the thickness of the modified layer, while removal proceeds via isotropic, thermally driven ligand-exchange reactions. This allows anisotropy to be engineered through selective surface modification rather than sputtering alone. Overall, the key conclusion is that isotropic versus directional behavior in ALE is determined by how and where ions are used, not simply by whether the process is labeled thermal or plasma.

Comment on Geometry

From an industrial standpoint, atomic layer etching is emerging as a core patterning technology as device scaling shifts toward complex 3D architectures and heterogeneous material stacks where conventional plasma etching reaches its limits. Smith et al. highlight that future adoption will be driven by selective ALE, enabled by surface-chemistry engineering, controlled anisotropy, and precise balance between etching and deposition rather than brute-force sputtering. In this landscape, AlixLabs’ use of geometrical selectivity extends the ALE paradigm by exploiting feature pitch and local geometry as an additional selectivity axis, enabling pattern multiplication and critical dimension scaling without added lithography complexity. The convergence of chemical, directional, and geometrical selectivity positions ALE not as a niche technique, but as a scalable, cost- and sustainability-aligned solution for next-generation semiconductor manufacturing.

The relevance of these advances is underscored by their recent and upcoming exposure at major industry forums. Results demonstrating sub-10 nm, high-aspect-ratio patterning with APS™ were presented at the 248th Electrochemical Society (ECS) Meeting in October 2025, marking an important milestone in validating the technology on bulk silicon using mature lithography. This momentum continues at SPIE Advanced Lithography + Patterning 2026, where AlixLabs will present new APS™ results spanning nanoimprint lithography and simplified self-aligned quadruple patterning, including joint work with UMC. Together, these events signal APS™ and geometrically selective ALE moving from concept and lab validation toward broader industrial evaluation and integration.

AlixLabs announced that Dr. Dmitry Suyatin, CIPO and Co-Founder, presented new APS™ (Atomic Layer Etching Pitch Splitting) results at the 248th ECS Meeting in Chicago (October 12–16, 2025), demonstrating high-aspect-ratio, narrow-fin patterning on bulk silicon with critical dimensions below 10 nm using standard 193-nm immersion lithography. The results reinforce APS™ as a viable path to advanced logic patterning without next-generation scanners, enabling reduced process complexity and cost. Supported by recent patent milestones and progress toward a beta tool planned for operation in fall 2026, APS™ is positioned to move from lab-scale validation toward production-grade refinement, aligning with AlixLabs’ goal of making advanced semiconductor manufacturing more accessible and sustainable.

AlixLabs announced its participation at SPIE Advanced Lithography + Patterning in San Jose, where two abstracts by Reza Jafari Jam et al and Robin Athlé et al have been accepted for oral presentation, including one in collaboration with United Microelectronics Corporation (UMC). The presentations will showcase recent progress in APS™ (Atomic Layer Etching Pitch Splitting), demonstrating sub-13 nm half-pitch patterning on silicon and a simplified alternative to self-aligned quadruple patterning that delivers a 4× density increase using a streamlined three-step process. Together, the talks highlight APS™ as a precise, cost-effective, and more sustainable approach to advanced nano-patterning that reduces complexity compared with conventional multi-patterning schemes.

Reference:

AlixLabs – News

Adapted from Smith, T. G. and Chang, J. P., Atomic Layer Etching in Patterning Materials: Anisotropy, Selectivity, Specificity and Sustainability, Plasma Chemistry and Plasma Processing, 46:9 (2026), © The Author(s) 2026. Published by Springer Nature and licensed under CC BY 4.0.

Smith, T. G., Chang, J. P., Atomic Layer Etching in Patterning Materials: Anisotropy, Selectivity, Specificity and Sustainability, Plasma Chemistry and Plasma Processing, 2026, 46:9.

Atomic Layer Etching in Patterning Materials: Anisotropy, Selectivity, Specificity and Sustainability | Plasma Chemistry and Plasma Processing

Intel Foundry Advances Future Logic Scaling with Manufacturable 2D Transistors and High NA EUV Integration

2025-12-21T09:46:00.003+01:00

Intel Foundry has demonstrated concrete momentum in de-risking 2D field-effect transistors as a future scaling path beyond silicon, through long-term collaboration with Imec. Results presented at IEDM show a world-first, 300 mm fab-compatible integration of key 2DFET modules, including source/drain contacts and gate stacks, using transition-metal dichalcogenide channels (WS₂ and MoS₂ for n-type, WSe₂ for p-type devices). The core innovation is a selective oxide etch applied to high-quality Intel-grown 2D layers capped with AlOx/HfO₂/SiO₂, enabling damascene-style top contacts while preserving the integrity of atomically thin channels.

Fab-compatible 2D FET process integration on 300 mm wafers, demonstrating selectively recessed oxide caps that enable damascene-style top contacts on WS₂, MoS₂, and WSe₂ channels, along with replacement-oxide gate stacks and interlayer-selective removal that scales gate CET from 2.5 nm to 1.5 nm. The work establishes manufacturable contact and gate modules as fundamental building blocks for future 2D transistor integration (IEDM Paper 10.1, Q. Smets et al.).

By validating these processes in production-class integration flows, Intel Foundry is addressing two of the most critical barriers to 2D transistor adoption—contact resistance and gate integration—while enabling realistic benchmarking, modeling, and design pathfinding. This work showcases Intel Foundry’s strategy of emphasizing manufacturability early in research, positioning 2D transistors as a credible, scalable option for future logic nodes and stacked transistor architectures.

Fab-compatible 2D FET process integration demonstrated on 300 mm wafers. An imec-led research team reports new manufacturable process modules enabling scalable integration of 2D field-effect transistors in a 300 mm pilot line. Exploiting the strong chemical selectivity and anisotropic van der Waals structure of transition-metal dichalcogenides, the work demonstrates for the first time a selectively recessed oxide cap that enables damascene-style top contacts on monolayer WS₂, MoS₂, and multilayer WSe₂ channels, resulting in improved contact resistance. A replacement-oxide gate stack with scaled equivalent oxide thickness is also shown. In addition, a novel interlayer-selective removal process based on liquid intercalation reduces the top-gate capacitance-equivalent thickness from 2.5 nm to 1.5 nm. Together, these modules form fundamental building blocks for future 2D integration technologies. Top row: epitaxial TiN growth enabled by a 2D template (left, center) and chemical confirmation of a Ru top contact on a multilayer WSe₂ channel (right). Bottom row: schematic comparison of the baseline top-gate stack comprising interlayer, cap, and top-up oxides; full replacement-oxide process; and selective lateral interlayer removal from contact trenches. Based on Paper 10.1, “Selective Etch Process for Fab-Compatible Top Contacts, Replacement Oxide and Interlayer Removal in 2D FETs,” Q. Smets et al., presented at IEDM.

In parallel with its 2D transistor research, Intel Foundry has made significant progress in High Numerical Aperture EUV lithography as a cornerstone enabler for future device scaling. In close collaboration with ASML, Intel Foundry has completed acceptance testing of the TWINSCAN EXE:5200B, the most advanced High NA EUV scanner currently available. This system builds on the first-generation EXE:5000 platform while extending productivity to 175 wafers per hour and achieving overlay performance of 0.7 nm, metrics that are directly relevant to high-volume manufacturing rather than purely experimental use. Intel’s early access to High NA EUV, beginning with the first commercial installation in its Oregon R&D fab in 2023, positions the company as a lead development partner shaping how High NA lithography is qualified, integrated, and eventually deployed in production logic nodes.

From a technology perspective, the EXE:5200B introduces several enabling innovations that are critical for advanced transistor architectures, including gate-all-around and future stacked devices. A higher-power EUV source supports practical exposure doses and improved resist process windows, helping control line edge and line width roughness at extremely small critical dimensions. A redesigned wafer stocker architecture improves lot logistics and thermal stability, which is especially important for multipass and multiexposure flows anticipated with High NA patterning. Finally, tighter alignment control reflects advances in stage mechanics, sensing, and environmental isolation, all of which become essential as overlay tolerances approach the sub-nanometer regime. For Intel Foundry customers, these capabilities translate into more flexible design rules, reduced reliance on complex multi-patterning schemes, fewer masks and process steps, and faster yield learning. Together, Intel’s High NA EUV progress and its 2D transistor integration work reflect a coherent strategy: pairing next-generation lithography with manufacturable device innovations to ensure that future scaling paths are both technically viable and production-ready.

Sources:

How Collaboration in High NA EUV and Transistor R&D Are Shaping Future Waves of Device Innovation

IEEE IEDM 2025 | 10-1 | Selective Etch Process for Fab-compatible Top Contacts, Replacement Oxide and Interlayer Removal in 2D FETs

Nanexa and Moderna partner on ALD-based PharmaShell drug delivery platform in licensing deal with USD 3 million upfront payment

2025-12-12T07:37:00.001+01:00

Nanexa and Moderna have entered into a license and option agreement covering the development of up to five undisclosed drug compounds using Nanexa’s PharmaShell® drug delivery platform. The agreement includes an upfront payment of USD 3 million to Nanexa, with the potential for up to USD 500 million in development and commercial milestone payments, as well as tiered single-digit royalties on future product sales. Moderna receives an immediate license for the first selected compound and holds options to license up to four additional compounds following preclinical evaluation.

“We are excited to partner with Moderna, a pioneer and leader in the field of mRNA medicines, to explore the potential of our PharmaShell® platform and to support the development of improved products for Moderna,” said David Westberg, CEO of Nanexa. “This agreement underscores the versatility of PharmaShell and its potential to address key challenges in the delivery of advanced biologics.”

The collaboration focuses on evaluating PharmaShell®’s ability to improve release profiles and stability for Moderna’s compounds. PharmaShell® is based on atomic layer deposition (ALD) technology, enabling precise encapsulation of active pharmaceutical ingredients with controlled, long-acting release characteristics. The agreement highlights PharmaShell®’s applicability to advanced biologics and supports Nanexa’s strategy of combining internal development with partnerships and licensing to global pharmaceutical companies.

Background on ALD and PharmaShell

Atomic Layer Deposition (ALD) is a thin-film deposition technique originally developed for the semiconductor industry, where it is used to create extremely uniform, conformal, and precisely controlled coatings at the atomic scale. ALD is based on sequential, self-limiting surface reactions, which allow film thickness and composition to be controlled with angstrom-level precision. Because the process produces highly uniform coatings even on complex, high–surface-area structures, ALD has increasingly been adopted in life sciences and pharmaceutical applications where consistency, stability, and reproducibility are critical.

PharmaShell® is Nanexa’s proprietary drug delivery technology that applies ALD to pharmaceuticals by encapsulating active pharmaceutical ingredients with an ultrathin, inorganic coating. This coating acts as a controlled diffusion barrier, enabling precisely tuned and long-acting release profiles while also improving product stability and protection of sensitive molecules. By adjusting coating thickness and material properties at the atomic level, PharmaShell® can be tailored to specific drugs and therapeutic needs, making it particularly well suited for advanced biologics and long-acting injectable formulations.

PharmaShell® is administered as a suspended injectable formulation containing API particles coated with an ultrathin ALD-based shell. After injection, the coating gradually dissolves in vivo, enabling controlled and sustained release of the active pharmaceutical ingredient into systemic circulation. The coating materials break down into ions that are naturally eliminated via urine and feces, allowing long-acting drug delivery using thin-gauge needles and low injection volumes.

PharmaShell® is created by applying ultrathin inorganic oxide coatings to API particles using atomic layer deposition (ALD). ALD is a gentle, gas-phase process operating under dry conditions near room temperature, making it suitable for sensitive molecules such as peptides and monoclonal antibodies. The nanometer-scale coating provides precise control of drug release while maintaining a very high drug load, with no need for post-process purification.

About Nanexa

Nanexa AB (publ) is a Swedish drug delivery company specializing in long-acting injectable formulations. Its proprietary PharmaShell® technology uses atomic layer deposition to precisely encapsulate drug substances, enabling tailored release profiles, improved stability, and potentially reduced dosing frequency.

About Moderna

Moderna, Inc. (Nasdaq: MRNA) is a biotechnology company known for pioneering mRNA-based medicines and vaccines. The company focuses on developing therapeutics and vaccines across infectious diseases, oncology, rare diseases, and immune-mediated conditions using its mRNA platform.

Sources:

Nanexa AB - Nanexa and Moderna enter into license and option agreement for the development of PharmaShell®-based products

PODD-Oct-2025.pdf

Capacitive memory built on a TSMC CMOS chip (reported in Nature)

2025-12-09T07:09:00.001+01:00

Researchers led by Junmo Lee from Georgia Institute of Technology in collaboration with Taiwan Semiconductor Manufacturing Company (TSMC) have demonstrated a new type of capacitive memory integrated directly on a CMOS chip. The work uses atomic layer deposition (ALD) and a dual-gated device architecture, pointing toward higher-density, low-power memory that can be integrated into advanced logic processes

Junmo Lee and colleagues now report a dual-gated non-volatile capacitive memory fabricated on the top metal layer of a foundry CMOS chip. The fabrication process begins with the removal of the chip’s passivation layer, followed by the deposition and patterning of the bottom electrode and interconnects. A layer of hafnium zirconium oxide (HZO) is then deposited using a tungsten sacrificial layer, and a film of tungsten-doped indium oxide (In2O3) grown via atomic layer deposition. The process concludes with the formation of a palladium top electrode and back-end pads, followed by a hafnium oxide (HfO2) top dielectric and then a palladium top gate.

The device exhibits a capacitive on/off ratio of 63.1, endurance exceeding 109 cycles at a read voltage of 1 V and retention of above 104 s at 25 °C. The operational principle of the integrated two-transistor–one-capacitor (2T–1C) device was validated by demonstrating the current amplification behaviour of the capacitance-modulated 40-nm silicon transistor within the integrated structure. Based on the measured data, the researchers proposed and simulated a cell-level digital compute-in-memory circuit model.

The study was also presented at IEDM2025: Technical Highlight – Monolithic 3D Capacitive Memory for Compute-in-Memory:

This joint work by Georgia Tech & TSMC, nominated for Best Student Paper in Emerging Device Technology, describes the first monolithic 3D (M3D) integration of dual-gated non-volatile capacitive memory (nvCAP) with an ALD W-doped In₂O₃ channel on a TSMC foundry 40nm CMOS chip. The novel dual-gate design resolves the long-standing challenges of weak erase and poor retention in oxide-channel ferroelectrics, achieving a record non-destructive on/off ratio of ~64.4 at 0V on a foundry CMOS chip. In addition, the paper introduces a new capacitive digital compute-in-memory (Cap-DCIM) paradigm, showing >140x efficiency improvements versus analog CIMs and >100x lower static power than SRAM-based CIMs, pointing to a scalable and energy-efficient path for future memory-compute integration. The operational principle of M3D Cap-DCIM is experimentally validated by demonstrating BEOL capacitance-modulated FEOL transistor current amplification through the monolithically integrated DG nvCAPs on a foundry CMOS chip.

Paper 28.3, “Monolithic 3D Integration of Dual-Gated ALD Oxide-Channel Non-Volatile Capacitive Memory on 40nm Si CMOS for Digital Compute-in-Memory,” J. Lee et al, Georgia Tech

Source:

Capacitive memory built on a CMOS chip | Nature Electronics

IEEE IEDM 2025 | 28-3 | Monolithic 3D Integration of Dual-Gated ALD Oxide-Channel Non-Volatile Capacitive Memory on 40nm Si CMOS for Digital Compute-in-Memory

The 2026 Area Selective Deposition Workshop (ASD 2026)

2025-11-12T06:41:00.001+01:00

The ASD Workshop was initiated in 2016 to provide a scientific communication channel to learn and exchange about selective deposition techniques. It has since offered a forum for open discussions between researchers from academia and industry. The meeting will include one day of Tutorials followed by the Workshop at ETEC Building (University at Albany). The last day of the workshop will highlight the state of the art of SC devices and processes at NY state with invited presentation from our main industrial partners at the NY CREATES’ Albany NanoTech Complex.

The 2026 Area Selective Deposition Workshop (ASD 2026) will take place March 29-April 1, 2026, at the University at Albany in New York, but it will be in two different locations:

March 29-31, 2026: ETEC Building

April 1, 2026: NY CREATES’ Albany NanoTech Complex

Abstract submission: Abstracts

Samsung Researchers Achieve Near-Perfect Grain Orientation in Atomic Layer Deposited Ruthenium for Next-Generation Interconnects

2025-11-10T06:46:00.000+01:00

Researchers at the Samsung Advanced Institute of Technology (SAIT) have unveiled a breakthrough in interconnect materials at IEDM 2025 with their paper “Grain-Orientation-Engineering of Atomic Layer Deposited Ruthenium Interconnect Technology.” As semiconductor scaling pushes below 10 nm, conventional copper wiring faces mounting resistance and reliability challenges. The SAIT team demonstrated that ruthenium (Ru), deposited via atomic layer deposition (ALD), can serve as a superior alternative by precisely controlling its crystallographic orientation. Through tailored ALD cycles, they achieved more than 99 percent texture quality in Ru films deposited on amorphous underlayers—an unprecedented level of structural order that dramatically reduces electron scattering at grain boundaries.

The study introduces a “supercycle-based area-selective deposition” approach that enables bottom-up via filling, producing c-axis-oriented single-crystal Ru vias. This method not only delivers void-free filling in narrow, high-aspect-ratio structures but also supports excellent conformality, making it highly compatible with advanced three-dimensional BEOL (back-end-of-line) architectures. By demonstrating atomic-scale control over film orientation and growth direction, the researchers show how ALD Ru can overcome the resistivity limitations of conventional PVD methods and outperform Cu in nanoscale interconnect applications.

Beyond resistivity improvements, the findings have broader implications for the semiconductor industry’s transition toward Ru-based interconnect schemes. A highly oriented ALD Ru process could simplify integration by minimizing the need for thick diffusion barriers and improving electromigration resistance. The work reinforces ALD’s growing importance not just for conformal coatings but as an enabler of crystallographic precision at the atomic level. Samsung’s demonstration positions ruthenium as a front-runner for sub-10 nm and 3D interconnect nodes—bridging the gap between conventional BEOL metals and the emerging era of atomic-scale device engineering.

Sources:

IEEE IEDM 2025 | 33-6 | Grain-Orientation-Engineering of Atomic Layer Deposited Ruthenium Interconnect Technology

SAIT | Samsung Semiconductor Global

IEDM2025 Tutorial - Atomic layer deposited atomically thin In₂O₃ transistors for BEOL logic and memory applications

2025-11-10T06:28:00.002+01:00

The IEDM 2025 T3 tutorial session titled “Atomic-layer-deposited atomically thin In₂O₃ transistors for BEOL logic and memory applications” will focus on recent progress in oxide semiconductor thin-film transistor (TFT) technologies designed for back-end-of-line (BEOL) 3D integration. The work is closely associated with Professor Peide (Peter) Ye’s group at Purdue University, which has been leading research on atomic-layer-deposited (ALD) indium oxide (In₂O₃) as a channel material for low-temperature, monolithically integrated logic and memory devices. The presentation will likely consolidate several years of development in ALD In₂O₃ transistors and ferroelectric field-effect transistors (Fe-FETs), demonstrating how these devices can be integrated above silicon CMOS layers in BEOL-compatible processes.

The image shows diagrams and data related to an indium oxide transistor with an 8 nm channel length. This research from Purdue University focuses on developing smaller and better-performing transistors using new material New material advances lead to smaller and better-performing transistors - Elmore Family School of Electrical and Computer Engineering - Purdue University

The main motivation behind this research is to develop semiconductors that can operate effectively within the stringent temperature constraints of BEOL processing, typically below 400°C. ALD In₂O₃ stands out because it can be deposited at 200–250°C, ensuring compatibility with existing copper and low-k interconnect layers. The ALD process provides atomically precise thickness control and excellent film uniformity, enabling channel layers as thin as 0.5–0.7 nm with smooth surfaces and strong electrostatic control. In₂O₃ also possesses a favorable charge neutrality level deep in the conduction band, which leads to high electron density and low contact resistance even in ultrathin configurations. Together, these characteristics make ALD In₂O₃ an attractive candidate for BEOL transistors, offering both scalability and manufacturability advantages over 2D materials or III–V semiconductors.

In terms of device performance, ALD In₂O₃ transistors have achieved channel lengths as short as 8 nm with channel thicknesses under 1 nm, demonstrating on-currents of about 3 A/mm at 0.5 V and transconductance values near 1.5 S/mm. On/off current ratios exceeding 10⁷ have been reported, alongside good subthreshold slopes and uniformity across wafers. Planar BEOL-compatible TFT versions of these devices exhibit electron mobilities above 100 cm²/Vs and current densities exceeding 2 mA/µm at low operating voltages. Some experimental devices have also demonstrated radio-frequency performance with cutoff frequencies around 36 GHz in sub-1 V operation, highlighting their potential for low-power, high-performance logic circuits integrated on top of CMOS wafers.

The memory aspect of this research involves combining ALD In₂O₃ channels with ferroelectric HfZrO₂ (HZO) gate dielectrics to realize In₂O₃-based Fe-FETs. These devices achieve channel lengths as small as 7 nm and exhibit memory windows around 2.2 V, with retention projected beyond 10 years and endurance exceeding 10⁸ switching cycles. Importantly, these Fe-FETs are also fabricated entirely within BEOL-compatible temperature budgets. This enables their use as embedded non-volatile memories in monolithic 3D integration schemes or as building blocks for in-memory computing architectures. The combination of logic FETs and Fe-FETs based on the same material platform offers a streamlined approach to constructing stacked computing tiers with both logic and memory functionality.

Applied Materials Deepens Partnership with Besi and Launches Kinex™ – the Industry’s First Fully Integrated Die-to-Wafer Hybrid Bonding System for Next-Gen AI and Memory Chips

2025-11-08T08:14:00.002+01:00

Applied Materials announced it has acquired a 9% stake in BE Semiconductor Industries (Besi) to strengthen their ongoing collaboration on hybrid bonding technology for advanced semiconductor packaging. Building on a partnership that began in 2020, the two companies recently extended their agreement to co-develop the industry’s first fully integrated die-based hybrid bonding system—combining Applied’s front-end processing expertise with Besi’s precision die placement and assembly capabilities. Hybrid bonding, which connects chips through direct copper-to-copper interfaces, is key to improving performance, power efficiency, and cost in next-generation logic and memory chips powering AI applications. Applied emphasized the investment as a strategic, long-term commitment, made through market transactions without seeking board representation or additional share purchases.

Applied Materials and BE Semiconductor Industries (Besi) have introduced Kinex, the industry’s first integrated die-to-wafer hybrid bonding system, engineered to deliver higher performance and lower power consumption for advanced logic and memory chips. The Kinex system unites all hybrid bonding steps — surface preparation, bonding, and metrology — within a single tool, offering tighter interconnect pitches, consistent bonding quality, and improved cycle times.

The Kinex™ Bonding system is the industry’s first integrated die-to-wafer hybrid bonder. It enables production of higher performance, lower power advanced logic and memory chips by integrating all the critical hybrid bonding process steps into one system.

Kinex is Applied Materials’ fully integrated hybrid bonding system, purpose-built for HVM environments. Co-developed with BE Semiconductor Industries N.V. (Besi), the industry leader in hybrid bonding, Kinex combines best-in-class bonding accuracy, advanced queue-time control, and exceptional system cleanliness. Its modular architecture supports many chiplets per module and integrates wet clean, plasma activation, and in-situ metrology for real-time overlay control. Kinex’s smart sequencer and AIx-powered software suite enable predictive maintenance, die-level traceability, and multi-binning capabilities.

Kinex is optimized for a wide range of applications including 3D integrated circuits, HBM, co-packaged optics (CPO), and sensor integration. Its flexible configuration supports both single-layer and multi-layer bonding flows, with validated performance on silicon, III-V materials, and glass substrates. As the industry moves toward higher die counts and tighter interconnect pitches, Kinex’s roadmap includes enhanced bonding force capabilities, in-situ annealing, and expanded metrology integration. With its scalable design and deep ecosystem partnerships, Kinex is positioned to lead the next wave of innovation in die-to-wafer hybrid bonding, enabling the future of AI, HPC, and beyond.

Sources:

Applied becomes major shareholder of Besi - Bits&Chips

Applied Materials Announces a Strategic Investment in BE Semiconductor Industries | Applied Materials

Kinex

Plasma-Based Deposition Refines ALD for Next-Gen DRAM: 30% Higher k, 40× Lower Leakage

2025-10-27T15:01:00.003+01:00

Researchers from POSTECH and UNIST in Korea have unveiled a new atomic-layer process using plasma-based deposition (PDP) to significantly improve DRAM capacitors. This innovation addresses a critical challenge in semiconductor manufacturing: enhancing the performance of high-k dielectric materials without introducing defects that cause electrical leakage. The PDP process refines the deposition of aluminum-doped titanium dioxide (ATO), enabling better charge storage and stability for next-generation devices.

The PDP technique introduces a controlled plasma treatment step after standard atomic layer deposition (ALD). By exposing the capacitor film to an argon/oxygen plasma, the process reorders the crystal lattice and fills oxygen vacancies—defects that typically cause instability and increased leakage currents in conventional ALD methods. This precise atomic-scale refinement is key to achieving superior performance.

The results of this breakthrough are highly promising, with the treated DRAM capacitors showing a roughly 30% higher dielectric constant and a nearly 40-fold reduction in leakage current compared to conventional methods. This enhances DRAM retention time, improves energy efficiency, and boosts overall device reliability. Beyond DRAM, this technology has potential applications for other next-gen electronic devices and energy storage systems.

Sources:

https://www.miragenews.com/new-process-boosts-semiconductor-performance-1557957/

Researchers Develop Innovative Process to Enhance Semiconductor Device PerformanceUNIST News Center | UNIST News Center

AlixLabs presents HAR narrow-fin patterning at ECS 248

2025-10-26T09:00:00.002+01:00

AlixLabs is pleased to announce that Dr. Dmitry Suyatin, CIPO and Co-Founder, has presented the company’s latest advances in APS™ (Atomic Layer Etching Pitch Splitting) at the 248th Electrochemical Society (ECS) Meeting held in Chicago, October 12–16, 2025.

During the session, Dr. Suyatin highlighted new experimental results demonstrating high-aspect-ratio (HAR), narrow-fin patterning on bulk silicon achieved using conventional immersion lithography at a 193-nanometer wavelength. These results further confirm the viability of APS™ as an innovative method for extending fine-pitch patterning capabilities using existing lithography infrastructure.

By enabling advanced logic patterning without the need for next-generation scanners, APS™ offers a significant opportunity to reduce process complexity and cost, paving the way for broader access to advanced semiconductor manufacturing technologies.

“These new APS™ results – demonstrating high-aspect-ratio narrow-fin (CD < 10 nm) patterning on bulk silicon – go hand in hand with our recent patent successes,” said Dmitry Suyatin, CIPO and Co-Founder of AlixLabs. “Together, they validate APS™ as both a technically sound and strategically protected innovation in semiconductor manufacturing. As we prepare to install our beta tool that will become operational in fall 2026, we’re excited to take APS™ from lab-scale to production-grade refinement. Each step brings us closer to making advanced logic manufacturing simpler, more accessible, and more cost-efficient for the global industry.”

The advances presented at ECS reflect AlixLabs’ long-term mission to lower the threshold to advanced logic production, supporting a more sustainable, affordable, and globally accessible semiconductor ecosystem.

This research has been led by Dr. Dmitry Suyatin and Dr. Intu Sharma, whose work continues to push the boundaries of patterning innovation.

Source: AlixLabs presents HAR narrow-fin patterning at ECS 248 – AlixLabs

ASM Charts the Future of ALD: Scaling Innovation, Integration, and Intelligence Toward 2030

2025-09-24T06:31:00.004+02:00

ASM used its 2025 Investor Day to set a bold 2030 ambition of more than €5.7 billion revenue, operating margins above 30%, and free cash flow above €1 billion. The company has consolidated a leading position in ALD with over 55% market share in their segments they where they chose to compete and is scaling its Epi business from 12% in 2020 to 25% in 2024. ALD remains the central growth driver, with the market for single-wafer ALD expected to outpace overall wafer fab equipment and reach $5.1–6.1 billion by 2030, while Si Epi is forecast at $2.5–3.2 billion with a 9–13% CAGR.

The single-wafer ALD market is projected to grow strongly from about 3.0 billion dollars in 2024 to between 5.1 and 6.1 billion dollars by 2030, representing a 9–13 percent compound annual growth rate, outpacing the overall wafer fab equipment market, which is expected to grow at 6 percent annually from 110 billion dollars in 2024 to 155 billion dollars in 2030. This growth is driven by the increasing number of ALD layers required in leading-edge logic and foundry processes as well as in advanced DRAM, both in the cell and peripheral CMOS areas. By 2030, ASM aims to maintain a market share above 55 percent, sustaining its lead in logic and foundry while also expanding its position in memory.

Node and memory inflections significantly expand ASM’s served markets, adding $400 million in their served available market from 3nm FinFET to 2nm GAA, and a further $450–500 million from 2nm to 1.4nm, while DRAM transitions contribute another $400–450 million. FEOL ALD layers grow fastest, with roughly 60% of ALD demand at 1.4nm coming from the transistor front end. In advanced packaging, a total available market of $11.5 billion by 2030 supports ASM’s plan to double its served available market to more than 30% of that market.

Services are projected to grow at more than 12% CAGR through 2030, with half of revenues moving to outcome-based models and new “dry clean” refurbish technology delivering ~10× selectivity, ~5× part life, over 95% CO₂e reduction, and more than 2× cost-of-ownership benefits.

ASM also introduced its XP8E common platform integrating clean, treat, inhibit, and ALD steps for 2nm ASD flows, and highlighted AI/ML deployment in high-volume manufacturing for anomaly detection, predictive maintenance, and improved first-time-right performance.

ASM’s XP8E common platform is positioned as a key enabler for the 2nm and beyond era, where Area-Selective Deposition and advanced integration schemes require multiple tightly coupled process steps. By bringing clean, treat, inhibit, and ALD into a single cluster, XP8E reduces wafer handling, shortens cycle times, and improves process control. This integration is critical for scaling as the number of ALD steps grows with each node, and it directly addresses challenges in pattern fidelity, defectivity, and variability that can otherwise undermine yield at 2nm. The platform is designed to be modular and flexible, so customers can configure it for different ASD and high-k/metal gate flows, while also benefiting from a common hardware base that simplifies fab operations, service, and parts management.

Alongside new hardware, ASM is embedding AI and machine learning capabilities into high-volume manufacturing. These tools enable real-time anomaly detection to flag subtle deviations in process behavior before they impact yield, and provide “top contributor” insights that help engineers rapidly identify root causes. Predictive maintenance, including ASM’s PM-Bot automation, improves precision and ensures higher first-time-right rates, cutting downtime and labor intensity. Over time, this creates a closed-loop system where data from thousands of wafers continuously refines process windows, stabilizes tool performance, and enhances cost-of-ownership. In combination, XP8E’s process integration and AI-driven control systems aim to deliver the repeatability, selectivity, and productivity gains required for the 2nm transition and future GAA nodes.

ASMs ALD History - from 1974 to 2024, 50+ years of ALD

The timeline highlights key milestones in the history of ALD and ASM’s leadership in the field. It begins in 1974 with Dr. Tuomo Suntola’s invention of ALD, followed by the founding of Microchemistry in Helsinki in 1987. ASM entered the scene in 1998 with the release of its first 200 mm Pulsar tool and strengthened its position by acquiring Microchemistry from Neste in 1999 and securing Sherman PEALD patents in 2000. Growth continued with the acquisition of Genitech in 2004. In 2008, ASM’s Pulsar tool was recognized as Product of the Year, cementing its reputation. More recently, ASM expanded its product portfolio with the introduction of the dual-chamber Synergis ALD system in 2018, the XP8 quad chamber module in 2019, and the Prominis ALD and XP8E platform in 2024. Strategic acquisitions, such as Reno Sub-Systems in 2022, further enhanced ASM’s technology base, illustrating a steady path of innovation and consolidation in ALD leadership over five decades.

The timeline illustrates ASM’s journey in atomic layer deposition from its origins to modern platforms. ALD was invented by Dr. Tuomo Suntola in 1974, followed by the founding of Microchemistry in 1987. ASM entered the field with the release of its first 200 mm Pulsar tool in 1998, strengthened its position by acquiring Microchemistry from Neste in 1999 (Finland), and expanded its patent base with Sherman PEALD patents in 2000. Key milestones include the acquisition of Genitech (Korea) in 2004, industry recognition for Pulsar in 2008, the introduction of Synergis in 2018 and XP8 in 2019, and the acquisition of Reno Sub-Systems in 2022. Most recently, ASM launched the Prominis ALD and XP8E platform in 2024, underscoring more than 50 years of continuous innovation and leadership in ALD.

The Finnish angle in ASM’s ALD story is both historic and ongoing. Atomic Layer Deposition was invented in Finland in 1974 by Dr. Tuomo Suntola, originally called Atomic Layer Epitaxy. The technology was developed at Microchemistry Ltd., a Finnish company founded in Helsinki in 1987 under Neste. When ASM acquired Microchemistry in 1999, they started gaining the pioneering ALD patents, know-how, and expertise that underpin its leadership today. Finland continues to play an active role through the University of Helsinki and ASM’s Chemical Innovation Group in Helsinki, where precursor chemistry and process research are carried out in close collaboration with Finnish scientists. In this way, Finland provided both the origin of ALD for ASM and remains an important innovation hub supporting ASM’s growth and leadership.

The ASM Pulsar “HIG source” for solids (or the solid precursor delivery subsystem) is a core enabler for ASM’s ability to use low-vapor-pressure solid precursors in ALD. The original innovation from ASM Microchemistry has been further developed over decades and is now still a key technology on the new platform for Molybdenum ALD seen below. It involves a heated sublimation mechanism (sometimes mounted close to or integrated with the reactor), controlled inert gas valves, purge isolation, and precise flux control to feed vapor from a solid into the ALD chamber. The architecture seeks to avoid cold spots or condensation and maintain consistent, controllable precursor delivery pulses.

Genitech was a South Korean company specializing in plasma enhanced ALD and thin film deposition. ASM acquired the company in 2004 to expand its capabilities in plasma based processes and complement its existing thermal ALD portfolio. The acquisition gave ASM a stronger position in PEALD for applications such as high k dielectrics and metal gate stacks used in advanced logic and memory. Genitech’s technology was integrated into ASM’s Pulsar and subsequent platforms, helping establish ASM’s leadership in both thermal and plasma ALD.

ASM acquired Reno Sub-Systems in 2022. Reno is a US-based company specializing in RF power delivery systems and matching networks for plasma tools. Their solid-state RF technology is valued for faster response times, higher precision, and better process stability compared to legacy RF solutions. By integrating Reno’s subsystems into its platforms, ASM strengthened its capability in plasma-based ALD and PEALD, where fine RF control is critical for uniformity, repeatability, and advanced film properties.

Future Outlook

ASM ties its deposition processing capability to its tool portfolio—Pulsar, EmerALD, Synergis, Prominis, XP8E, and others—which are engineered with small-volume reactors, advanced plasma control, and integrated multi-step clustering (clean, treat, inhibit, deposit).

Looking ahead, ASM is uniquely positioned to remain the clear leader in atomic layer deposition as the semiconductor industry advances to 2nm and beyond. The company’s deep history in ALD, dating back to Dr. Tuomo Suntola’s invention in 1974, has evolved into a robust technology portfolio that now commands more than 55 percent market share where ASM chooses to compete.

With single-wafer ALD forecast to nearly double in size by 2030 and outpace overall wafer fab equipment growth, ASM is set to capture outsized value from both logic and memory inflections. Its proven expertise in solid source precursor delivery, trailing back to the the Pulsar HIG sublimation system and F120 Microchemistry research reactors, now expands to new material capabilities such as molybdenum ALD for advanced node metallization. At the same time, ASM is broadening its impact through the XP8E common platform, which integrates multiple critical steps into one cluster with embedded AI and machine learning into high-volume manufacturing for real-time control. ASM’s combination of process innovation, equipment integration, and data-driven intelligence places the company at the center of semiconductor scaling, ensuring its leadership in enabling Moore’s Law through the next decade.

Sources:

ASM InvestorDay 2025

JSR, Lam Research, and SK hynix Push the Boundaries of ASML´s EUV Semiconductor Manufacturing

2025-09-16T07:06:00.000+02:00

JSR Corporation, including its subsidiary Inpria Corporation, and Lam Research have entered into a cross-licensing and collaboration agreement to accelerate the development of next-generation semiconductor manufacturing technologies. The partnership combines JSR’s expertise in photoresists and advanced materials—anchored by Inpria’s metal-oxide resists (MORs) for extreme ultraviolet (EUV) lithography—with Lam’s leadership in wafer fabrication equipment and process technology. By sharing intellectual property and integrating complementary capabilities, the companies aim to address scaling and patterning challenges as chipmakers pursue smaller, denser, and more energy-efficient devices for advanced logic and memory applications.

Inpria’s MORs, based on spin-on tin-oxide materials, provide high EUV photon absorption, excellent etch resistance, and reduced line edge roughness compared with conventional organic resists. These materials are fully compatible with existing lithography systems, making them attractive for high-volume production. To meet growing demand, JSR is expanding its global footprint with new R&D facilities in Japan and a production plant in Korea set to begin operations in 2026. Lam Research complements this with its Aether® dry resist technology, which replaces wet spin-coating and development with fully dry, vapor-phase processes. This innovation improves uniformity, reduces stochastic defects, and strengthens EUV absorption, enabling higher resolution and sensitivity. Aether has demonstrated direct-print 28 nm pitch patterning for logic and is already being adopted by leading memory manufacturers, offering both performance advantages and sustainability gains through reduced chemical and energy use.

These advances align with a broader industry shift toward tighter integration of materials and equipment solutions, exemplified by SK hynix’s installation of the world’s first commercial High-NA EUV lithography tool, ASML’s TWINSCAN EXE:5200B, at its M16 fab in Icheon, South Korea. Featuring a numerical aperture of 0.55—compared with 0.33 in current Low-NA EUV systems—the High-NA platform boosts resolution by 40%, enabling transistors about 1.7× smaller and wafer transistor densities nearly 2.9× higher. For SK hynix, this milestone supports the development of next-generation DRAM, reduces process complexity, lowers costs, and strengthens competitiveness in AI memory and advanced compute markets.

As one of the “big three” memory makers alongside Samsung and Micron, SK hynix has established itself as the leader in high-volume DRAM manufacturing. It was the first to mass-produce DDR5 and high-bandwidth memory (HBM3), both essential for AI and high-performance computing. Its early adoption of EUV lithography for DRAM production—and now the industry-first deployment of ASML’s High-NA EUV system—underscores its position at the forefront of DRAM scaling and density. Together, the innovations from JSR, Inpria, Lam Research, and SK hynix illustrate how collaboration across the semiconductor ecosystem is driving the breakthroughs required to sustain Moore’s Law in the era of AI and advanced computing.

Do you want me to keep the headline-style opening as above, or make it read more like a press release introduction with a formal lead sentence?

Sources:

JSR Corporation/Inpria Corporation and Lam Research Enter Cross Licensing and Collaboration Agreement to Advance Semiconductor Manufacturing

Dry Resist Patterning Progress and Readiness Towards High NA EUV Lithography

INPRIA | A world leader world leader in metal oxide photoresist design, development and manufacturing

Inpria Co-Developing Metal Oxide Resist with SK hynix to Reduce Complexity of Patterning for Next-Generation DRAM | 2022 | News | JSR Corporation

SK hynix Introduces Industry’s First Commercial High NA EUV

Breaking the Copper Bottleneck: Lam Research’s Mo-ALD ALTUS Halo Enables Next-Generation Hybrid Metallization

2025-09-16T06:22:00.004+02:00

Lam Research now offers molybdenum (Mo) atomic layer deposition (ALD) with its ALTUS Halo platform, introduced in 2025 as the first high-volume ALD tool designed for Mo metallization. The system enables conformal and selective, bottom-up deposition of low-resistivity, void-free Mo films, targeting advanced logic, memory, and 3D NAND applications where conventional copper and tungsten interconnects face scaling and reliability limits. This positions Lam’s Mo-ALD as a key enabler for next-generation BEOL hybrid metallization schemes.

Current density of various metal/via schemes. Red and green areas indicate higher current density.

Hybrid metallization using Mo shows strong potential to overcome the scaling limitations of conventional copper dual damascene (Cu DD) processes in advanced semiconductor BEOL interconnects. As device dimensions shrink, Cu faces challenges such as increased resistivity, barrier thickness limitations, and stress-induced voids (SIVs), all of which degrade performance. Mo hybrid metallization, which uses bottom-up barrierless metal deposition before a conventional Cu process, significantly reduces resistance—by about 55% compared to Cu DD—and further by 15% with selective barrier deposition (SBD). This lower resistance translates into higher current densities and improved reliability. Stress distribution studies also reveal that Mo hybrid vias exhibit lower void formation risks than Cu due to smaller stress gradients at the via/barrier interfaces.

Comparison of via and line resistance for conventional Cu dual damascene and Mo hybrid metallization schemes. Mo vias reduce total resistance by ~35% without selective barrier deposition (SBD), with an additional ~20% reduction when fully replacing Cu. Applying SBD further lowers resistance, achieving up to ~55% reduction compared to the Cu baseline.

Optimization studies, performed with SEMulator3D® simulations, identified key parameters like via critical dimensions, height, and material stress properties that impact resistance, capacitance, and hydrostatic stress. Findings show that increasing Mo via height lowers resistance but raises stress, suggesting an optimal fill height around 25 nm for balancing performance and reliability. Intrinsic stress of Mo and process temperature tuning were also shown to mitigate stress-induced reliability issues, with 400°C identified as a favorable condition. Ultimately, hybrid metallization with Mo offers a scalable path forward, combining electrical and mechanical benefits, while virtual DOE and process modeling enable predictive optimization without extensive wafer-based experiments.

Sources:

Breaking the Copper Bottleneck With Molybdenum Hybrid Metallization

Lam Research Ushers in New Era of Semiconductor Metallization with ALTUS® Halo for Molybdenum Atomic Layer Deposition - Feb 19, 2025

ALD News Week 38

2025-09-15T07:43:00.007+02:00

Solid-state batteries get a boost with new protective coating

Link: https://www.anl.gov/article/solidstate-batteries-get-a-boost-with-new-protective-coating

“A thin, glass-like layer could help protect solid-state batteries from degradation, researchers say. They use a process called atomic layer deposition (ALD) to apply a protective layer.” (ANL)

Microwave enhanced atomic layer deposition (MW-ALD): Incorporating a microwave antenna into an ALD reactor
Link: https://pubs.aip.org/avs/jva/article/43/5/052403/3361679/Microwave-enhanced-atomic-layer-deposition-MW-ALD

“Atomic layer deposition (ALD) is a technique widely used for thin film deposition with excellent uniformity and conformality. In this work, we present a modification of a conventional ALD system by integrating a microwave antenna to explore how microwave energy can enhance film growth and reduce cycle times, particularly for materials that are otherwise difficult to deposit.” (AIP Publishing)

Impacts of different thickness Al2O3 and SiO2 atomic layer deposition sidewall passivation layers on GaN-based devices
Link: https://pubs.aip.org/avs/jvb/article/43/5/052209/3361926/Impacts-of-different-thickness-Al2O3-and-SiO2-atomic-layer-deposition-sidewall

“The sidewall passivation layer has a critical effect on the performance and reliability of GaN-based devices. In this study, we investigate how varying the thickness of atomic layer deposition (ALD) Al₂O₃ and SiO₂ sidewall passivation layers influences device leakage, breakdown voltage, and surface recombination. The results show that thicker layers can better suppress leakage but may lead to trade-offs in other device parameters.” (AIP Publishing)

Forge Nano to Unveil Commercial Single Module Semiconductor Wafer Fab ALD Tool at SEMICON Taiwan
Link: https://www.globenewswire.com/news-release/2025/09/04/3144564/0/en/Forge-Nano-to-Unveil-Commercial-Single-Module-Semiconductor-Wafer-Fab-ALD-Tool-at-SEMICON-Taiwan.html

DENVER, Sept. 04, 2025 (GLOBE NEWSWIRE) -- Forge Nano, Inc., a technology company pioneering domestic battery and semiconductor innovations, today announced it is unveiling a new commercial single module semiconductor wafer fab atomic layer deposition (ALD) tool – TEPHRA^{One}. The fully automated 200 mm single module platform is outfitted with features from Forge Nano’s flagship multi-process module TEPHRA in a streamlined configuration for oxide, nitride, metal and nanolaminate coatings. (GlobeNewswire)

New Tool Announcement: Thermal/Plasma ALD System Now Available for User Access
Link: https://nanofab.ucsd.edu/new-tool-announcement_thermal-plasma-ald-system/

We are happy to announce that the new Arradiance GEMStar Thermal & Plasma ALD (Atomic Layer Deposition) System is now available for user access. This advanced system supports both thermal and plasma enhanced ALD processes and is designed to allow users to explore a wide range of thin film materials and process conditions. (nanofab.ucsd.edu)

Press Release “ALD for Industry 2025” - Dresden
Link: https://efds.org/en/45604/

Dresden, March 12, 2025 – The 8th International Conference “ALD FOR INDUSTRY” has once again bridged the gap between basic research, industrialization and commercialization of atomic layer deposition (ALD). This event, which has been held annually in Dresden since 2017, once again welcomed over 100 participants from 14 countries and numerous exhibitors this year despite the strike at German airports. (efds.org)

News & Announcements: Continuous, high-speed atomic layer deposition for thin-film coatings
Link: https://www.anl.gov/amd/news-announcements

“Self-exhausting” precursor pulses enable fast, precise coating applications for … (ANL)

Global Semiconductor Sales Surge 20.6% in July, Driven by Americas and Asia Pacific

2025-09-14T08:10:00.004+02:00

Global semiconductor sales surged in July 2025, reaching $62.1 billion — a 20.6% increase from the same month last year and 3.6% higher than June. The robust expansion was fueled by strong demand in the Americas and Asia Pacific, underscoring the industry’s momentum despite regional fluctuations. With the Americas up nearly 30% and Asia Pacific/All Other climbing over 35% year-on-year, July marked one of the strongest months of growth in recent years, highlighting continued strength in advanced computing, AI, and data-driven technologies.

The Americas and Asia Pacific regions are the strongest contributors to both monthly and yearly growth.
China is still growing year-to-year but slipped month-to-month, suggesting softer short-term demand.
Japan is contracting in both comparisons, signaling structural weakness.
Europe remains modest but positive year-to-year.

Global Overview

Total sales: $62.07B
Year-to-year growth: +20.6% (vs. $51.48B in July 2024)
Month-to-month growth: +3.6% (vs. $59.91B in June 2025)
Three-month-moving average growth: +8.9%

Regional Breakdown (Year-to-Year, July 2025 vs. July 2024)

Asia Pacific/All Other: +35.6% (biggest growth driver)
Americas: +29.3%
China: +10.4%
Europe: +5.7%
Japan: -6.3% (only region in decline)

Month-to-Month (July vs. June 2025)

Americas: +8.6%
Asia Pacific/All Other: +4.9%
Europe: 0.0%
Japan: -0.2%
China: -1.3%

Source:

Global Semiconductor Sales Increase 20.6% Year-to-Year in July - Semiconductor Industry Association

EU Expands Dual-Use Export Controls to Cover Atomic Layer Deposition, Etch, Epitaxy, Lithography, EUV Components and Quantum Technologies

2025-09-14T07:26:00.000+02:00

On 8 September 2025, the European Commission adopted a Delegated Regulation updating the EU’s dual-use export control list (Annex I of Regulation (EU) 2021/821). The update aligns EU rules with commitments made in 2024 under the Wassenaar Arrangement, MTCR, Australia Group, and the Nuclear Suppliers Group, ensuring a uniform application of newly agreed controls across all Member States. The move reflects the EU’s broader strategy outlined in the 2024 White Paper on Export Controls, strengthening oversight of sensitive technologies while maintaining competitiveness and a level playing field for European industry.

The updated list introduces new controls on a range of emerging technologies. These include quantum technologies such as cryogenic components and amplifiers, advanced semiconductor manufacturing and testing equipment — notably Atomic Layer Deposition tools, epitaxial deposition systems, and EUV lithography materials — as well as high-performance computing circuits, additive manufacturing systems, peptide synthesisers, and specialized high-temperature coatings. The Delegated Regulation will enter into force following the standard two-month scrutiny period by the European Parliament and Council, reinforcing the EU’s role in safeguarding security and international stability through effective export controls.

Specifically, this update of the EU control list provides for the addition of new dual-use items, including:

Controls related to quantum technology (e.g. quantum computers, electronic components designed to work at cryogenic temperatures, parametric signal amplifiers, cryogenic cooling systems, cryogenic wafer probers);
Semiconductor manufacturing and testing equipment and materials (e.g. Atomic Layer Deposition equipment, equipment and materials for epitaxial deposition, lithography equipment, Extreme Ultra-Violet pellicles, masks and reticles, Scanning Electron Microscope equipment, etching equipment);
Advanced computing integrated circuits and electronic assemblies such as Field Programmable Logic Devices and Systems;
Coatings for high temperature applications;
Additive manufacturing machines and related materials (e.g. inoculants for powders);
Peptide synthesisers, and;
Modification of certain control parameters and update of certain technical definitions and descriptions.

By extending controls to core process equipment essential for leading-edge semiconductor production, the EU aims to close regulatory gaps and ensure uniform oversight across all Member States. For the semiconductor industry, this means that exports of critical manufacturing tools and materials outside the Union will now require authorisation, tightening compliance requirements but also ensuring fair competition and transparency within the internal market. The regulation highlights the EU’s growing focus on safeguarding supply chains for advanced chip technologies while balancing competitiveness with security concerns

For more information
Delegated Regulation
Comprehensive Change Note Summary – Update 2025: An overview of changes to the EU Dual-Use Control List across the 10 categories of Annex I

TSMC’s 2 nm Fabs Lock Out China OEMs, Securing ALD and Process Tool Demand for US, European, and Japanese Tier-1 Suppliers

2025-09-01T07:07:00.003+02:00

TSMC’s decision to exclude Chinese equipment vendors from its 2 nm fabs in Taiwan and the US reshapes the competitive landscape in favor of Japanese, American, and European suppliers. With the 2 nm node set to become the largest in history by wafer volume and revenue potential, this policy shift effectively concentrates demand among a handful of Tier 1 players —ASMI, TEL, Applied Materials, and Lam Research—who already dominate in deposition, etch, and cleaning tools essential for nanosheet GAA and backside power delivery. No need to mention ASML.

Announced in January: TSMC is advancing with its 2 nm (N2) technology, establishing a pilot line at its Hsinchu Baoshan Fab 20 with an initial monthly output of around 3,000–3,500 wafers. By combining production from Hsinchu and Kaohsiung, the company expects to exceed 50,000 wafers per month by the end of 2025 and reach about 125,000 wafers per month by the end of 2026. Output at Hsinchu should rise to 20,000–25,000 wafers per month by late 2025 and 60,000–65,000 by early 2027, while Kaohsiung is projected to produce 25,000–30,000 wafers monthly by late 2025 and also expand to 60,000–65,000 by early 2027. Chairman C.C. Wei has highlighted that demand for 2 nm exceeds that of 3 nm, driven by its 24–35% lower power consumption, 15% performance boost at the same power, and 15% higher transistor density. Apple will be the first adopter, followed by MediaTek, Qualcomm, Intel, NVIDIA, AMD and Broadcom.

TSMC will start 2 nm mass production in Taiwan in the second half of 2025, initially with Fab 22 in Kaohsiung as the anchor site for yield learning. The first ramp is set at 40,000 wafers per month, expanding to 100,000 wafers per month in 2026 and reaching 200,000 wafers per month by 2027, making N2 the largest and most profitable node in TSMC’s history.

In the US, Arizona Fab 21 is being developed in phases. Phase 1 is already producing 4 nm chips, Phase 2 will start 3 nm by late 2025 or early 2026, and Phase 3 is planned for 2 nm and A16-class chips toward the end of the decade. This ensures that while Taiwan remains the cost-optimized base for N2 production, Arizona provides premium, subsidy-supported capacity for US customers, diversifying geographic and geopolitical risk.

Overall, Taiwan will carry the bulk of N2 output and cost efficiency, while Arizona secures local supply for strategic US clients like Apple, Nvidia, AMD, and Intel. By 2027, with 200,000 wafers per month globally, N2 alone could generate nearly $50 billion annually, cementing TSMC’s central role in powering AI and HPC expansion.

The move aligns directly with Washington’s Chip EQUIP Act, which ties subsidies to avoiding “foreign entities of concern.” By pre-emptively removing Chinese tools, TSMC safeguards its access to US incentives while giving its global customers—Apple, Nvidia, AMD, and Intel—assurance that supply chains are insulated from geopolitical risk. This codifies the leading suppliers as the “trusted” baseline for advanced-node capacity worldwide, effectively reinforcing their moat at the most profitable process node ever.

For ASMI, TEL, AMAT, and Lam, the outlook is very positive. With Chinese competitors pushed out, these companies can win more business and have stronger pricing power. At the same time, 2 nm wafer prices are climbing toward $30,000, far above older smartphone-focused nodes. TSMC is reviewing its suppliers for profit margins and China ties, but these four are essential for 2 nm production, so they are more likely to gain from rising demand and higher-value tools than lose ground. Put simply, the 2 nm era is set to drive lasting growth and profits for them as AI adoption accelerates through 2027.

Chinese semiconductor equipment OEMs that are cut out from TSMC’s 2 nm fabs under the new restrictions and supplier realignment:

AMEC (Advanced Micro-Fabrication Equipment Inc.) – leading Chinese etch tool supplier, with relevance in dielectric etch and epitaxy
Naura Technology Group – broad portfolio in etch, deposition, and cleaning tools
Mattson Technology (China-owned, via E-Town Dragon Semiconductor) – focuses on dry strip, rapid thermal processing (RTP), and etch
SMEE (Shanghai Micro Electronics Equipment) – China’s only domestic lithography tool maker (far behind in capability, but relevant in domestic fabs)
Kingsemi – maker of ALD/CVD equipment, mainly for memory and advanced logic
Piotech – deposition (CVD, PECVD, ALD) equipment vendor
ACM Research (China) – cleaning and electrochemical deposition tools (though headquartered in the US, its operations are China-based and increasingly seen as China OEM)

At TSMC’s 2 nm fabs, the exclusion of Chinese equipment vendors channels ALD equipment demand entirely to US, European, and Japanese suppliers. ASM International (Europe) remains the clear leader in single-wafer ALD for high-k metal gate stacks and nanosheet spacers, with Applied Materials and Lam Research (US) competing in selective and plasma ALD for gate-all-around and backside power steps, while Tokyo Electron and Kokusai Electric (Japan) cover both single-wafer and batch ALD, particularly for spacer and liner deposition. By contrast, Chinese ALD players such as Naura, Kingsemi, and Piotech, while active in domestic logic and memory at 28–14 nm and some 7 nm non-EUV capacity, will not gain any capability at N2 and are explicitly excluded under TSMC’s supplier policy and US subsidy rules, leaving the largest and most profitable ALD opportunity in history to be divided among the established US, European, and Japanese Tier-1 suppliers.

Sources:

TSMC reportedly cuts Chinese chipmaking tools from 2nm fabs as suppliers face scrutiny due to emerging new US restrictions | Tom's Hardware

https://open.substack.com/pub/drrobertcastellano/p/tsmcs-2-nm-era-technology-leadership?r=l0uj0&utm_campaign=post&utm_medium=web&showWelcomeOnShare=false

TSMC Is Getting Ready to Launch Its First 2nm Production Line | TechPowerUp

Chipmetrics expands metrology portfolio with advanced test chips and wafer solutions for next-gen ALD semiconductor processes

2025-08-24T10:02:00.005+02:00

Finnish metrology specialist Chipmetrics has expanded its portfolio with a new range of advanced test chips and wafer solutions aimed at accelerating prototyping and enhancing precision in next-generation semiconductor process development. The new releases include the ASD-1b area-selective deposition chip, a High Surface Area wafer, and pre-coated High Aspect Ratio test structures such as PillarHall and VHAR1. These tools are designed to simulate real-world manufacturing conditions with greater accuracy, helping engineers optimise processes more efficiently and reduce development cycles in ALD and other thin-film applications.

The ASD-1b chip provides a tricolour material layout with metal, SiO₂ and Si₃N₄ surfaces, enabling detailed assessment of selectivity and defectivity across multiple deposition techniques. Meanwhile, the new HSA wafer delivers up to 300 times greater surface area sensitivity through deep trench designs, supporting ultra-sensitive material studies. By offering pre-coated HAR structures, Chipmetrics addresses the growing industry demand for realistic conformality and uniformity testing. According to CEO Mikko Utriainen, these solutions are set to streamline benchmarking of new chemistries and processes, giving development teams faster, clearer feedback to advance semiconductor innovation.

Chipmetrics’ new metrology tools for advanced thin film process development. Left: Pre-coated high aspect ratio test structures, including PillarHall® (lateral AR > 1000) and VHAR1 (vertical AR = 200), for evaluating conformality and film penetration. Centre: The ASD-1b area selective deposition test chip with tricolour material layout for testing selectivity across Cu, SiO₂ and Si₃N₄ surfaces. Right: High Surface Area (HSA) wafer combining a 150 mm VHAR1 wafer within a 300 mm pocket wafer, providing up to 300× enhanced surface area for sensitive material studies.

Source:

Chipmetrics Expands Product Line with Advanced ALD Test Chips and Wafer Solutions - Chipmetrics

Shaping the Future of Thin Films: New Trends in Thermal ALD Chemistry

2025-08-24T09:46:00.000+02:00

A new review published in the Journal of Vacuum Science & Technology A takes a detailed look at recent developments in thermal atomic layer deposition (ALD) chemistry, drawing on data from the comprehensive ALD database at atomiclimits.com. The analysis highlights how process innovations have accelerated since 2010, with more than half of all reported ALD processes emerging in the past 15 years. Binary oxides remain the dominant material group, but there has been a steady increase in the deposition of non-oxides and ternary compounds. More recently, classes such as elemental metals, two-dimensional transition metal dichalcogenides, and halides have gained prominence, driven largely by application demands in microelectronics, energy technologies, and catalysis. The study also notes the introduction of new elements into the ALD portfolio after 2010, including alkali metals and more exotic elements such as rhenium, osmium, gold, and antimony, each requiring unique process routes.

The review underscores the critical role of precursor chemistry in enabling these advances. While traditional precursors such as halides, alkoxides, and β-diketonates laid the foundation, newer processes have leaned heavily on amides and imides, followed by cyclopentadienyl compounds. However, the most significant trend is the growing reliance on heteroleptic precursors, which combine multiple ligand types to fine-tune key properties such as volatility, reactivity, and thermal stability. This flexibility has been instrumental in broadening the range of materials accessible via ALD and tailoring processes to meet the specific requirements of cutting-edge applications. Overall, the work reflects how ALD chemistry has evolved from relatively narrow beginnings into a dynamic and application-driven field with expanding industrial significance.

Source:

The review is based on ALD chemistries collected from the AtomicLimits ALD precursor database: Database of ALD processes

Popov, G.; Mattinen, M.; Vihervaara, A.; Leskelä, M. (2025). “Recent trends in thermal atomic layer deposition chemistry.” Journal of Vacuum Science & Technology A, 43, 030801. https://doi.org/10.1116/6.0004320

Beneq Secures Repeat Orders as ALD Gains Ground in MicroLED Display Market

2025-07-15T09:10:00.006+02:00

Espoo, Finland, 14 July 2025 – Beneq, a global leader in Atomic Layer Deposition (ALD) technology, has announced significant momentum in the microLED display sector, marked by repeat orders from leading tech innovators. The development highlights the growing demand for advanced manufacturing tools capable of supporting the next generation of display technologies.

MicroLED is increasingly seen as a transformative display technology across consumer electronics, augmented and virtual reality (AR/VR), and the automotive sector. Offering superior brightness, contrast, energy efficiency and durability, microLED enables ultra-fine resolution, longer device lifetimes and seamless scalability.

According to Yole Group, global microLED display shipments are expected to grow at a compound annual rate of 180.6 percent from 2022, reaching 42.4 million units by 2029. However, manufacturing challenges remain, particularly as pixel sizes shrink below 10 micrometres. ALD plays a critical role in overcoming these hurdles by delivering ultra-thin, conformal coatings that ensure uniformity, stability and surface passivation—key for improving efficiency and reliability.

Beneq Transform® is an ALD cluster tool designed for technology development and manufacturing across power electronics (SiC, GaN, Si), RF, optoelectronics, microLED, MEMS, and sensors.

“Our top-tier customers rely on ALD technology to advance monolithic integration of microLEDs and driver electronics on a single chip,” said Mikko Söderlund, Head of Semiconductor ALD Sales at Beneq. “This enables a new class of compact, high-performance display products with faster data transfer and reduced power consumption.”

Beneq’s Transform® ALD cluster platform is central to its offering, providing high-throughput production capability with a modular, multi-chamber design. The platform supports a range of materials and processes, allowing customers to optimise optical and electrical properties while scaling from lab to fab.

These developments reinforce Beneq’s commitment to supporting microLED pioneers through both early-stage development and the transition to volume manufacturing, accelerating the path toward widespread adoption of advanced display technologies.

Sources:

Beneq Advances MicroLED Leadership with Growing Demand from Industry Frontrunners | Beneq

Transform® and Transform® Lite

Atomic Scale Processing: A Key Enabler for Scalable and Coherent Quantum Technologies

2025-05-27T06:18:00.005+02:00

Recent advances in quantum computing, including IBM’s 1000-qubit chip and imec’s 300 mm wafer transmon qubits, highlight a rapid progression towards scalable, fault-tolerant quantum systems. As quantum platforms such as superconducting and spin-based qubits evolve, the reproducibility and precision of fabrication processes have become essential. Atomic Layer Deposition (ALD) and Atomic Layer Etching (ALE) are emerging as critical tools to meet these demands. ALD’s conformal coating capabilities are particularly well-suited for developing 3D structures like through-silicon vias (TSVs), which are essential for high-density, low-loss interconnects in large-scale qubit arrays. However, transitioning ALD to 3D geometries requires careful adjustment of plasma conditions to maintain superconducting properties on vertical sidewalls. Despite these challenges, early successes with materials like TiN and NbN suggest strong potential for ALD in quantum manufacturing.

At the same time, improving surface and interface quality remains central to boosting qubit coherence times. Qubits are highly sensitive to material defects and interfacial contamination, which are known sources of decoherence. ALE’s self-limiting, smooth etching capabilities offer a superior alternative to conventional dry and wet etching by reducing surface roughness and enabling high selectivity. This process can mitigate damage and defects at key interfaces such as metal-air and substrate-air, which are critical loss points in superconducting qubits. The ability of ALE to tailor etch behaviour with high precision makes it a promising method for refining material interfaces and improving device performance. As these atomic-scale techniques continue to mature, they are poised to play a foundational role in the future scalability and reliability of quantum computing platforms.

Sources:

How atomic scale processing can help to pave the way for future quantum devices: A Workshop to bridge ALD/ALE and Quantum communities – Atomic Limits

SiCarrier Seeks $2.8 Billion to Advance Chipmaking Equipment

2025-05-18T10:30:00.004+02:00

SiCarrier, a Chinese chip equipment manufacturer closely associated with Huawei and owned by the Shenzhen city government, is seeking $2.8 billion in funding to advance its ambitions of becoming China's leading chipmaking equipment provider. Founded in 2021, the company aims to surpass domestic rivals such as Naura and AMEC, amid U.S. export restrictions that have fueled China's drive for semiconductor self-sufficiency. The fundraising, targeting a valuation of $11 billion, is expected to conclude soon, with proceeds allocated primarily to R&D. State-owned firms and domestic investors have shown strong interest. Despite showcasing 30 products at Semicon China 2025, most of its tools remain under development and are not yet production-ready. SiCarrier has filed 92 patents, indicating plans to offer a comprehensive suite of chipmaking tools, including lithography and AI-driven inspection systems. However, its deep ties to Huawei have raised concerns among potential customers over data security and trade secret protection. Industry experts suggest full operational independence from Huawei is essential for broader market acceptance and long-term growth.

"Founded in 2021 and owned by the Shenzhen city government, SiCarrier is largely seen as a Huawei supplier. But it wants to become the leading domestic provider of chipmaking equipment in China, surpassing Naura and Advanced Micro-Fabrication Equipment China (AMEC), according to four people with knowledge of its goals."

A Reuters review of 92 patents filed by Shenzhen SiCarrier Industry Machines and its parent Shenzhen SiCarrier Technologies between October 2022 and March 2025 reveals the company’s ambitious plan to establish itself as a comprehensive supplier of semiconductor manufacturing equipment. Unlike domestic peers such as Naura and AMEC, which have taken more focused approaches, SiCarrier is pursuing an expansive product roadmap that spans the entire chip production chain—from wafer metrology and defect inspection to etching and atomic layer deposition (ALD) systems. These filings, verified through Anaqua’s AcclaimIP database, illustrate SiCarrier’s intention to compete head-on with established global players such as KLA, Lam Research, and Tokyo Electron, particularly in process-critical segments like thin-film deposition and etch uniformity control. Notably, SiCarrier is investing in AI-powered wafer defect recognition, a frontier area aimed at enhancing production yields, especially important in advanced nodes where precision is paramount. Industry observers cited by Reuters suggest metrology and inspection tools offer SiCarrier the most immediate opportunity, given the absence of a dominant Chinese competitor in that space. The patent portfolio also reveals efforts to close the technological gap in lithography by focusing on components for deep ultraviolet (DUV) systems and multi-patterning techniques. These are presented as domestic alternatives to extreme ultraviolet (EUV) lithography, which remains out of reach due to US export controls. However, experts like Dan Hutcheson of TechInsights caution that the multi-patterning approach—though pioneered by Intel and used by TSMC at 7 nm—carries known drawbacks such as increased complexity and yield challenges, stemming from its reliance on sequential deposition and several etch processes.

Sources:

Exclusive: SiCarrier - Huawei partner in chips - seeks $2.8 billion in funds, sources say | Reuters

AlixLabs Secures Notice of Allowance for US Patent for Innovative Semiconductor Manufacturing Technology

2025-05-06T17:00:00.005+02:00

Swedish semiconductor startup’s APS™ patent portfolio continues to grow with xth U.S. patent, marking the company’s 10th pending global patent.

Stockholm, Sweden – May 6th, 2025 – AlixLabs is excited to announce that the US Patent and Trademark Office has issued the notice of allowance for the company’s latest patent application, US20250087487A1, titled Formation of an array of nanostructures. This milestone marks the next step in AlixLabs’ commitment to advancing semiconductor manufacturing technologies.

Internally referred to as the “Tetris” patent, in honor of Alexey Pajitnov, the new patent integrates self-aligned double patterning (SADP) with atomic layer etching (ALE)-based pitch splitting (APS™) technology. This innovative approach, being industrialized by AlixLabs since its founding in 2019, combines elements of both classical and leading-edge techniques to deliver superior performance for semiconductor manufacturing.

The invention arose from AlixLabs’ efforts to develop a process for precise sidewall angle control in APS™, a key component in silicon-based processes. By leveraging plasma etch process selectivity and combining features from complex plasma processes, AlixLabs has pioneered a method that blends the traditional SADP process with the advanced APS technology.

This allows the company to utilize mature industrial technologies while benefiting from the advanced control and improved performance of cyclic processes and topographical selectivity. As a result, AlixLabs’ solution offers semiconductor manufacturers an enhanced ability to address the challenges of patterning at sub-5 nm nodes.

This breakthrough is significant for the integration of APS™ technology into existing semiconductor production workflows, preserving the use of existing Process Design Kits (PDKs) which are essential tools for chip designers. By doing so, it reduces the barrier for APS adoption in high-volume manufacturing (HVM), easing the transition to next-generation semiconductor technologies.

The patented innovation provides semiconductor manufacturers with greater flexibility, offering a new way to fine-tune the APS™ process to meet the needs to cut capital and operational expenditure (CapEx and OpEx) as well as emissions for customers at advanced technology nodes, while allowing for broader compatibility with different materials. This new method further strengthens AlixLabs’ core APS™ patent portfolio, positioning the company as a leading enabler of next-generation semiconductor manufacturing.

Moreover, this invention not only supports the development of leading-edge logic, memory, and photonics but also simplifies the semiconductor manufacturing process by reducing CapEx and OpEx for semiconductor fabs.

“We remain committed to advancing semiconductor manufacturing with innovations that significantly enhance the precision, flexibility, and efficiency of our technologies,” commented Dmitry Suyatin, co-founder and CTO of AlixLabs. “This patent represents a critical step forward in our mission to drive the next generation of semiconductor processes and further solidify our position as a leader in the field.”

AlixLabs Secures Notice of Allowance for US Patent for Innovative Semiconductor Manufacturing Technology – AlixLabs

Tokyo Electron Delivers Record FY2025 Results Amid AI Boom, Eyes Growth Through CVD Innovation and Geopolitical Resilience

2025-05-06T07:29:00.004+02:00

Tokyo Electron (TEL) achieved a record-breaking financial year in FY2025, with strong top- and bottom-line growth driven by robust global demand for advanced semiconductor equipment. Net sales rose by 32.8% year-on-year to approximately ¥2.43 trillion (around $15.7 billion USD), marking the highest in the company's history. Operating profit surged to ¥697.3 billion (about $4.5 billion USD), supported by an improved operating margin of 28.7%. Growth was underpinned by increased investment in leading-edge logic and memory, particularly High Bandwidth Memory (HBM) and advanced DRAM nodes, where TEL maintained or expanded market share through key Process of Record (POR) wins in etch and wafer bonding technologies. Revenue contributions diversified geographically, with notable gains in South Korea and Taiwan, even as China remained a key market. TEL also demonstrated strong cash flow, increased its R&D and capital investments, and returned significant value to shareholders through dividends and buybacks. Looking ahead, TEL forecasts continued growth in FY2026, positioning itself to capitalise on accelerating AI, 2nm logic, and heterogeneous integration trends.

Tokyo Electron TEL has demonstrated strong financial performance and strategic market expansion through FY2025, according to their investor presentation dated April 30, 2025. Their net sales, gross profit, operating profit, and net income have all reached record highs, signaling both operational efficiency and favorable market conditions.

LINK: Tokyo Electron Limited 2025 Q4 - Results - Earnings Call Presentation (OTCMKTS:TOELY) | Seeking Alpha

Tokyo Electron's Q4 FY2025 earnings call highlighted strong financial performance and an optimistic forward outlook amid geopolitical uncertainties. Despite global concerns around US tariffs and export controls—particularly in China, which saw its WFE market share fall to 35%—TEL stated that it has not observed any significant changes in customer investment sentiment or competitive dynamics. The company reaffirmed its strategy of focusing on long-term innovation rather than short-term regulatory shifts, underscoring its commitment to developing higher-productivity tools to offset potential external headwinds. Looking ahead, TEL forecasts continued double-digit WFE market growth into calendar 2026, driven by AI infrastructure demand, 2nm logic, and HBM scaling. The company plans record-high investments of ¥300 billion in R&D and ¥240 billion in CapEx for FY2026, reflecting confidence in sustained momentum across DRAM, advanced logic, and packaging technologies. TEL aims to expand global market share and reach ambitious mid-term goals, including over ¥1 trillion in operating profit and 35%+ OPM, by capitalising on technology transitions such as GAA, backside PDN, and heterogeneous integration.

LINK: Tokyo Electron Limited (TOELY) Q4 2025 Earnings Call Transcript | Seeking Alpha

Revenue and Profitability Growth:

Net sales increased significantly from ¥1,399.1 billion in FY2021 to ¥2,431.5 billion in FY2025, a 74% increase over four years. The gross profit also rose steadily, reaching ¥1,146.2 billion in FY2025, up from ¥564.9 billion in FY2021. Operating profit followed suit, more than doubling from ¥320.6 billion to ¥697.3 billion. These trends underscore TEL’s ability to scale profitably, with operating margins rising from 22.9% in FY2021 to 28.7% in FY2025. Return on equity (ROE) also remained strong, peaking at 37.2% in FY2022 and settling at 30.3% in FY2025, a testament to effective capital management.

Regional Sales Composition:

The revenue breakdown by region from Q1 FY2024 to Q4 FY2025 shows growing diversification. Notably, China has remained the single largest market, although its share declined from 47.4% in Q4 FY2024 to 34.3% in Q4 FY2025, reflecting a strategic balancing across geographies. South Korea, Taiwan, and North America significantly increased their contributions, with South Korea reaching ¥147.0 billion and Taiwan ¥135.8 billion in Q4 FY2025. This reflects growing demand from advanced logic and memory fabrication customers in these regions.

In FY2025, Tokyo Electron’s semiconductor production equipment (SPE) sales reached ¥1.86 trillion, driven by a sharp rise in DRAM-related investments, particularly for high-bandwidth memory (HBM), which accounted for 31% of total sales. Non-volatile memory (NAND) remained stable at 7%, while non-memory segments, including logic and foundry, continued to dominate with 62%, reflecting robust demand from both advanced and mature nodes. The overall recovery and expansion of customer investments across segments underpinned this strong performance.

Market Segment Performance

Tokyo Electron’s global market share in CY2024 demonstrates its leadership across multiple core segments of the semiconductor production equipment market. The company holds a commanding 92% share in coater/developer systems, underlining its unparalleled position in photoresist processing for advanced lithography applications. It also leads the wafer prober segment with a 38% share and maintains robust positions in key deposition categories, including 38% in CVD and 37% in oxidation/diffusion systems. In contrast, TEL’s market share in ALD stands at 16%, notably behind ASM International, highlighting an opportunity for expansion in this strategically important technology as the industry moves towards GAA and other 3D device structures. Performance in dry etch (27%), cleaning systems (21%), and wafer bonding (32%) rounds out a broadly competitive portfolio that positions TEL to effectively support ongoing advancements in scaling, heterogeneous integration, and high-performance packaging across logic, memory, and AI-related applications.

To further expand our future profit, we made steady progress in penetrating into new technology domains. Specifically, we released multiple new outstanding products contributing to the semiconductor technology innovation. For example, penetration to untapped segments such as single-wafer plasma CVD and PVD, gas cluster beam system which improves efficiency of leading-edge lithography, and laser-lift-off system to drastically decrease environmental footprint of processing. In fiscal 2025, we conducted share repurchase of about ¥150 billion in total.

- Toshiki Kawai - Representative Director, President and CEO

New product 2025 Episode™ single-wafer CVD platform

Episode™ 1 is Tokyo Electron's latest single-wafer CVD platform, launched in 2024 to address the challenges of advanced device scaling in logic, DRAM, and future AI processors. It supports up to eight process modules, enabling complex, uninterrupted multi-step processing. The system integrates the OPTCURE™ module for native oxide removal and ORTAS™ for titanium CVD, allowing immediate Ti deposition to minimise contact resistance in advanced interconnects. Episode™ 1 replaces traditional PVD with CVD to achieve uniform, low-resistivity films in high aspect ratio structures such as deep contact holes. With a 45% smaller footprint than its predecessor and advanced edge computing, data analytics, and environmental tracking capabilities, the system enhances fab productivity, engineer efficiency, and readiness for new materials in next-generation device manufacturing.

The TEL Episode™ 1 system shown in the image seems to feature twin or dual single-wafer process chambers, which is typical in modular CVD tools designed for high throughput. Each visible module (with two load ports per unit) likely contains two process chambers within the same footprint to maximise wafer handling efficiency and enable parallel processing—common in tools aimed at advanced logic and memory manufacturing.

Episode™ 1 offers a reduced footprint. Compared with the Triase+™ series, twice as many smaller modules can be installed in a system. With the same number of modules installed, Episode™ 1 takes up about 45% less fab space than its predecessor

LINK: Episode™ 1 Single-Wafer Deposition System for Semiconductors: Driving the Evolution of AI Semiconductors to Transform Everyday Life | Blog | Tokyo Electron Ltd.

ASM International Strengthens ALD Market Leadership Amid Strong Q1 Results, Growing GAA Adoption, and Strategic Positioning for Advanced Node Demand

2025-05-05T08:13:00.004+02:00

ASM International’s Q1 2025 results reaffirm its leadership in Atomic Layer Deposition (ALD), a technology central to enabling advanced semiconductor nodes such as 2nm and beyond. With ALD accounting for more than half of its equipment revenue and strong customer engagement in leading-edge logic and memory, ASM is well-positioned to capitalise on rising demand driven by GAA architectures, high-bandwidth memory, and ongoing technology node transitions.

ASM International’s Q1 2025 results reinforce its leadership in ALD, a foundational technology for enabling advanced semiconductor nodes. ALD represented more than half of ASM’s equipment revenue, with the market expected to grow at a compound annual rate of 10–14% through 2027, and ASM maintaining a leading market share above 55% in the segments they compete in:

Single-Wafer ALD Tools

ASM’s flagship ALD platforms are single-wafer systems, which provide high precision, conformality, and process flexibility. These are used primarily in leading-edge logic and memory production.

Key Platforms:
- XP8 and XP8 QCM: High-productivity platforms supporting multiple process chambers; widely used for high-volume manufacturing.
- Previum and Previum Pro: Previum systems incorporate an integrated epitaxial (EPI) pre-clean step that effectively removes 15–20 monolayers of native oxide from the substrate surface. This step is crucial for ensuring high-quality EPI film growth.
- Pulsar®: Specialised for high-k dielectrics, such as hafnium oxide (HfO₂) typically used in gate stacks.
- Eagle® XP8: Designed for advanced metal ALD (e.g. TiN, W), often used in logic and memory applications including barrier and liner layers.

ASM International’s strategic alignment with the prevailing trends in the wafer fab equipment (WFE) market and its concentrated customer base. Logic and foundry applications are set to remain the dominant segment of WFE spending through 2026, reinforcing ASM’s focus on enabling advanced nodes such as FinFET and GAA, where Epitaxy (Epi) and atomic layer deposition (ALD) are critical. The company’s FY24 revenue profile shows that its top five customers accounted for 51% of sales, while the top ten represented 70%, indicating strong relationships with leading-edge semiconductor manufacturers. These likely include TSMC, Samsung, Intel, SK hynix, and Micron—ASM’s probable top customers given their leading-edge node adoption and high ALD utilisation. Others may include GlobalFoundries, UMC, SMIC, and select IDMs.

The industry’s shift to gate-all-around (GAA) transistor architectures at 2 nm and beyond is driving increased demand for single-wafer ALD and silicon epitaxy (Si Epi) processes, which are essential for integrating high-k dielectrics, advanced metals, and high aspect ratio features in both logic and memory devices. ASM’s deep engagement with leading-edge customers—particularly in logic/foundry and high-bandwidth memory (HBM) DRAM—has already translated into strong revenue contributions. Additionally, early tool shipments for the 1.4nm node reflect continued confidence from top-tier clients and extend ASM’s growth visibility as chipmakers prepare for more complex architectures requiring precise material deposition.

ASMI presented a robust growth trajectory of the single-wafer Atomic Layer Deposition (ALD) market, projected to reach between US$4.2 billion and US$5.0 billion by 2027, with a compound annual growth rate (CAGR) of 10–14% from 2022.

Summary from ASM International Q1 2025 Earnings Call:

1. ALD Market Outlook:
ALD continues to be a key growth driver for ASM, with equipment sales led by ALD and expectations of a strong increase in GAA (gate-all-around) related demand throughout 2025. ALD intensity is rising as leading-edge nodes (2 nm and 1.4 nm) require more deposition steps for complex 3D structures, high-k dielectrics, and metal gate stacks. ASM confirmed ongoing R&D engagement for 1.4nm and highlighted that ALD demand will further accelerate in next-gen nodes, backside power delivery, and in advanced DRAM (e.g. HBM), which increasingly adopt logic-like ALD layers. ASM remains confident in long-term ALD market growth, forecasting double-digit increases in application layers per node.

2. Trade, Tariffs, and Geopolitical Risk:
ASM addressed potential impacts from new US tariff announcements, noting no immediate effect on equipment, but acknowledging possible indirect macroeconomic consequences. The company has prepared multiple mitigation scenarios, including flexible global manufacturing—already expanding in Korea and establishing capability in Arizona (set to scale in 2H 2026). ASM emphasised its ability to localise production quickly if needed. While there’s been no pull-forward of tool orders due to tariff concerns, the company is monitoring the situation closely and maintaining optionality in its supply chain to navigate shifting trade conditions.

ASM International NV (ASMIY) Q1 2025 Earnings Call Transcript | Seeking Alpha

"ASM International: Upgrade To Strong Buy On Better Growth Visibility And Strength"

ASM International (ASMIY) delivered a strong Q1 FY25, exceeding expectations in revenue, margins, and orders, driven by robust AI infrastructure demand, early ramp-up of 2nm nodes, and resilient performance in China. Despite macroeconomic risks and export controls, ASM saw solid contributions from mature logic foundries and high-bandwidth memory (HBM), which relies on advanced techniques like ALD and Epi. The company’s improved operational efficiency, growing AI demand, and clearer long-term growth visibility led the author to upgrade the stock to a “strong buy,” supported by a belief that ASM can reach the high end of its FY27 revenue target with continued margin expansion.

LINK: ASM International: Upgrade To Strong Buy On Better Growth Visibility And Strength (OTCMKTS:ASMIY) | Seeking Alpha