tag:blogger.com,1999:blog-25167174502664818892012-02-15T14:11:38.395+05:30ASIC-SoC-VLSI DesignMuralihttp://www.blogger.com/profile/05927561262168582763noreply@blogger.comBlogger16813http://creativecommons.org/images/public/somerights20.gifAsic-systemOnChipsoc-vlsiDesignhttp://feedburner.google.comtag:blogger.com,1999:blog-2516717450266481889.post-79291911123745268472011-12-01T11:37:00.001+05:302011-12-02T21:44:30.709+05:302011-12-02T21:44:30.709+05:30Synopsys Acquires Magma Design Automation
<p><a href="http://feedads.g.doubleclick.net/~a/GVIxRVQnoIxmPEFV6XmY4s3KCYs/0/da"><img src="http://feedads.g.doubleclick.net/~a/GVIxRVQnoIxmPEFV6XmY4s3KCYs/0/di" border="0" ismap="true"></img></a><br/>
<a href="http://feedads.g.doubleclick.net/~a/GVIxRVQnoIxmPEFV6XmY4s3KCYs/1/da"><img src="http://feedads.g.doubleclick.net/~a/GVIxRVQnoIxmPEFV6XmY4s3KCYs/1/di" border="0" ismap="true"></img></a></p><div dir="ltr" style="text-align: left;" trbidi="on">
Well...... Finally the predicted is happening ! EDA major <a href="http://www.synopsys.com/home.aspx" target="_blank">Synopsys</a> is acquiring <a href="http://www.magma-da.com/" target="_blank">Magma Design Automation</a>.<br>
Here is the press release: <a href="http://synopsys.mediaroom.com/index.php?s=43&item=982" target="_blank">Synopsys to Acquire Magma Design Automation</a><br>
<br>
</div><a href="http://asic-soc.blogspot.com/2011/12/synopsys-to-acquire-magma-design.html#more">Read more »</a><div class="blogger-post-footer"><img width='1' height='1' src='https://blogger.googleusercontent.com/tracker/2516717450266481889-7929191112374526847?l=asic-soc.blogspot.com' alt='' /></div><img src="http://feeds.feedburner.com/~r/Asic-systemOnChipsoc-vlsiDesign/~4/bf_4pRbuUOY" height="1" width="1"/>Muralihttp://www.blogger.com/profile/05927561262168582763noreply@blogger.com2http://asic-soc.blogspot.com/2011/12/synopsys-to-acquire-magma-design.htmltag:blogger.com,1999:blog-2516717450266481889.post-53049773597159458532011-11-27T14:17:00.001+05:302011-11-27T14:47:48.070+05:302011-11-27T14:47:48.070+05:30Verilog HDL: Data Types
<p><a href="http://feedads.g.doubleclick.net/~a/uJDnp82V2kK4JzSPvaoL-XyIlVU/0/da"><img src="http://feedads.g.doubleclick.net/~a/uJDnp82V2kK4JzSPvaoL-XyIlVU/0/di" border="0" ismap="true"></img></a><br/>
<a href="http://feedads.g.doubleclick.net/~a/uJDnp82V2kK4JzSPvaoL-XyIlVU/1/da"><img src="http://feedads.g.doubleclick.net/~a/uJDnp82V2kK4JzSPvaoL-XyIlVU/1/di" border="0" ismap="true"></img></a></p><div dir="ltr" style="text-align: left;" trbidi="on">
<span style="font-size: large;"><strong>Value Set:</strong></span> <br>
---> Four values to model the functionality<br>
<br>
<div>
---> Eight strengths of real hardware</div>
<br>
<div>
</div>
<strong> <span style="background-color: #f4cccc;"> <u><span style="color: purple;">Value level</span>---------<span style="color: magenta;"> Condition in hardware circuits</span></u></span></strong><br>
<br>
<div>
</div>
0 ------------- > Logic zero, false condition<br>
1 ------------- > Logic one, true condition<br>
X ------------ > Unknown logic value<br>
Z ------------- > High impedance ,floating state<br>
<br>
<div>
</div>
</div><a href="http://asic-soc.blogspot.com/2011/11/verilog-hdl-data-types.html#more">Read more »</a><div class="blogger-post-footer"><img width='1' height='1' src='https://blogger.googleusercontent.com/tracker/2516717450266481889-5304977359715945853?l=asic-soc.blogspot.com' alt='' /></div><img src="http://feeds.feedburner.com/~r/Asic-systemOnChipsoc-vlsiDesign/~4/_zlh_JPbtco" height="1" width="1"/>Muralihttp://www.blogger.com/profile/05927561262168582763noreply@blogger.com0http://asic-soc.blogspot.com/2011/11/verilog-hdl-data-types.htmltag:blogger.com,1999:blog-2516717450266481889.post-75862886998910459442011-11-27T09:37:00.001+05:302011-11-27T10:12:53.984+05:302011-11-27T10:12:53.984+05:30Verilog HDL: Expressions, Operators and Operands
<p><a href="http://feedads.g.doubleclick.net/~a/LxVmZecgB0gokVuRTTOQL2Z9MjY/0/da"><img src="http://feedads.g.doubleclick.net/~a/LxVmZecgB0gokVuRTTOQL2Z9MjY/0/di" border="0" ismap="true"></img></a><br/>
<a href="http://feedads.g.doubleclick.net/~a/LxVmZecgB0gokVuRTTOQL2Z9MjY/1/da"><img src="http://feedads.g.doubleclick.net/~a/LxVmZecgB0gokVuRTTOQL2Z9MjY/1/di" border="0" ismap="true"></img></a></p><div dir="ltr" style="text-align: left;" trbidi="on">
Dataflow modeling in Verilog describes the design in terms of expressions, instead of primitive gates. ‘expressions,, ‘operators’ and ‘operands’ form the basis of Verilog dataflow modeling.<br>
<br>
<span style="font-size: large;"><strong>Arithmetic:</strong></span><br>
<br>
<span style="color: blue;"> <strong>*</strong> </span><span style="color: black;"> ---> Multiplication</span><br>
<span style="color: blue;"> <strong> /</strong> </span><span style="color: black;"> ---> Division</span><br>
<span style="color: blue;"> <strong> +</strong> </span><span style="color: black;">---> Addition</span><br>
<span style="color: blue;"> <strong> -</strong> </span><span style="color: black;"> ---> Subtraction</span><br>
<span style="color: blue;"> <strong> %</strong> </span><span style="color: black;">---> Modulo</span><br>
<span style="color: blue;"> <strong>**</strong> </span><span style="color: black;">---> Power or exponent</span><br>
</div><a href="http://asic-soc.blogspot.com/2011/11/verilog-hdl-expressions-operators-and.html#more">Read more »</a><div class="blogger-post-footer"><img width='1' height='1' src='https://blogger.googleusercontent.com/tracker/2516717450266481889-7586288699891045944?l=asic-soc.blogspot.com' alt='' /></div><img src="http://feeds.feedburner.com/~r/Asic-systemOnChipsoc-vlsiDesign/~4/5KrnVsCVOV8" height="1" width="1"/>Muralihttp://www.blogger.com/profile/05927561262168582763noreply@blogger.com0http://asic-soc.blogspot.com/2011/11/verilog-hdl-expressions-operators-and.html