VLSI World

BIST STRUCTURE

2013-02-21T18:32:00.001+05:30

Power optimization of Linear Feedback Shift Register (LFSR) for Low Power BIST

This paper proposes a low power Linear Feedback Shift Register (LFSR) for Test Pattern Generation (TPG) technique with reducing power dissipation during testing. The correlations between the consecutive patterns are higher during normal mode during testing. The proposed approach uses the concept of reducing the transitions in the test pattern generated by conventional LFSR. The transition is reduced by increasing the correlation between the successive bits. The simulation result show that the interrupt controller benchmark circuit's testing power is reduced by 46% with respect to the power consumed during the testing carried by conventional LFSR.

BIST ARCHITECTURE

It is very important to choose the proper LFSR architecture consumes different power even for same polynomial. Another .Problem associated with choosing LFSR is LFSR design issue, which includes LFSR partitioning, in this the LFSR are differentiated on the basis of the basis of hardware cost and testing time cost.

A typical BIST architecture consists of a test pattern generator (TPG), usually implemented as a linear feedback shift register (LFSR), a test response analyzer (TRA), implemented as a multiple input shift register (MISR), and a BIST control unit (BCU), all implemented on the chip (Figure 1). This approach allows applying at-speed tests and eliminates the need for an external tester. The BIST architecture components are given below

Circuit under Test (CUT): It is the portion of the circuit tested in BIST mode. It can be sequential, combinational or a memory. Their Primary Input (PI) and Primary output (PO) delimit it.

Test pattern Generator(TPG): It generates the test patterns for CUT. It is a dedicated circuit or a microprocessor. The patterns may be generated in pseudo random or deterministically.
Multiple input signatures registers (MISR): it is designed for signature analysis, which is a technique for data compression. MISR efficiently map different input streams to different signatures with every small probability of alias. MISR are frequently implemented in built-in-self-test (BIST) designs, in which output responses are compressed by MISR
Test Response Analysis (TRA): It analyses the value sequence on PO and compares it with the expected output BIST Controller Unit (BCU): It controls the test execution; it manages the TPG, TRA and reconfigures the CUT and the multiplexer. It is activated by the Normal/Test signal
ALGORITHM FOR LOW POWER LFSR
As discussed in the previous section LFSR is used to generate test patterns for BIST. In this, test patterns are generated externally by LFSR, which is inexpensive and high speed LFSR is a circuit consists of flip-flops in series. LFSR is shift register where output bit is an XOR function of input bits. The initial value of LFSR is called seed value. LFSR's seed value has a significant effect on energy consumption. [3]. The output that influence the input are Called tap. A LFSR is represented by as polynomial, which is also known as characteristic polynomial used to determine the feedback taps, which determine the length of random pattern generation. The output of LFSR is combination of I's and O's. A common clock signal is applied to all flip-flops, which enable the propagation of logical values from input to output of flip-flops. Increasing the correlation between bits reduces the power dissipation. This can be achieved by adding more number of test vectors, which decreases the switching activity. LFSR is characterized by the polynomial by its characteristics polynomial and inverse of characteristics polynomial is generated polynomial.

Blocking / Non-Blocking Assignments in Verilog

2012-04-25T17:35:00.000+05:30

Blocking vs. Non-Blocking Assignment

A Blocking Statement must executed before the execution of statements that follow it in a sequential block.It can be used in Procedural assignments like initial,always and continious statements like assign statements.It is recommended to use within combinattional always block.it is represented by "=" operator sign

Example :
module block();
integer a,b,c,d;

// Blocking Assignments

initial
begin
a = 5; b = 3;
#15 c = 8;
#20 d = 15;
end
endmodule

In Above Example ,
At time '0' a and b have the value 5 and 3 respectively
At time '15' c have the value 8 and
At time '35' d have the value 15

A Non Blocking Statement first evaluate the value and then assigns it in the next event change,just the ways sequential circuits work.They always the sample the value of rising/falling edge of clock.It can be used in the procedural blocks like initial and always. assign statement is not permitted .It is recommended to use within sequential always block .It is represented by "<=" operator sign


   Example :
module non_block();
integer a,b,c,d;

   // Non-Blocking Assignments

initial
begin
a <= 5;
#10 b <= 3;
#15 c <= 8;
#20 d <= 15;
end
endmodule

  In Above Example ,
At time '0'   a have the value 5 .
At time '10' b have the value 3.
At time '15' c have the value 8 and
At time '20' d have the value 15

Front End Design Tools and Future of VLSI

2012-04-21T16:00:00.005+05:30

FRONT END VLSI DESIGN TOOLS

1.XILINX TOOL

ISE® WebPACK™ design software is the industry´s only FREE, fully featured front-to-back FPGA design solution for Linux, Windows XP, and Windows Vista. ISE WebPACK is the ideal downloadable solution for FPGA and CPLD design offering HDL synthesis and simulation, implementation, device fitting, and JTAG programming. ISE WebPACK delivers a complete, front-to-back design flow providing instant access to the ISE features and functionality at no cost. Xilinx has created a solution that allows convenient productivity by providing a design solution that is always up to date with error-free downloading and single file installation.

Download Link: http://www.xilinx.com/tools/webpack. htm

2. ModelSim PE Student Edition - HDL Simulation

ModelSim PE Student Edition is a free download of the industry leading ModelSim HDL simulator for use by students in their academic coursework

Download Link:http://portal.model.com/modelsim/downloads/license_agreement_form_gen.asp

3. Active HDL-8.2

Completely integrated FPGA design entry and verification environment for mixed VHDL, Verilog, SystemC, System Verilog, and EDIF designs

Download Link: http://www.aldec.com/Products/

FUTURE OF VLSI

VLSI Industry in INDIA started in early 80s with Texas Instruments (TI) and ST Microelectronics setting up their design centers. In the last five years this industry has grown five times faster than the global average. According to ISA-IDC report 2010 Indian IC Industry will reach $10 Billion in 2010. Currently it's the second fastest growing industry in India (23%) after the Automation industry (26%). The total design services market is expected to grow at a CAGR of 21.7% to US$ 10.96 billion in 2010. The total workforce in this industry will grow from 129,900 in 2007 to 218,800 thousand in 2010, at a CAGR of 18.8%. Out of the total Digital VLSI design projects undertaken in India approximately 9% were on 60 and 45 nm. The IC market is getting catalyzed by the increased sales of mobile phones, iPODs, MP3/4 players, PCs, Laptops etc.

There will be an increased emphasis on IP development, as third party design services companies look to move up the value chain. The industry will continue to face significant challenge to manage the demand and workforce churn. It will have to constantly evolve, upgrade and innovate while keeping the costs down in order to stay cost competitive in the global market. Increasing proximity between the third party service providers and OEMs for end-to-end product design will impose a bigger challenge. This will also lead to fabs aligning themselves with the service providers leading to the creation of "Virtual Fabs". Which will further fuel the Software and EDA companies to strengthen the existing investments and start up new ventures the business in India. But all this will happen when India can provide skilled professional in VLSI Design.

Scope of Employment

India needs 7.5 Lakh skilled professionals in this industry by 2015

But there are few bottlenecks
-Lack of Skilled Professionals in this domain
-Conventional Methods of Education in Indian Academy
-Lack of good quality faculty in Indian Academy
-Industry – Academics gap
-Low employability rate

FPGAs along with EDA Tools have changed the VLSI Design scenario. These tools are finding extensive applications in areas like Consumer Electronics, Aerospace, Set Top Entertainment Boxes, Computer Peripherals, Defense, Satellites, Communication and Cell Phone. The FPGA market is increasing and is about to grow more than the ASIC market, both in terms of devices and value. Companies like Xilinx, Altera, Quick Logic, Vantis, Lattice and Cypress are the major players in this market. Million gate devices from them are already available

VLSI Technology : Design Flow

2012-04-21T14:17:00.000+05:30

VLSI Technology

With the advent of discrete semiconductor devices such as bipolar transistors, unijunction transistors, field effect transistors, etc., miniaturization started in full-swing, replacing bulky systems that used vacuum tubes. Vacuum tubes are even now used in high power applications. Since the invention of the first IC (Integrated Circuit) in the form of a Flip Flop by Jack Kilby in 1958, our ability to pack more and more transistors onto a single chip has doubled roughly every 18 months, in accordance with the Moore’s Law. Gradually, attempts were made to integrate several circuits, be it analog or digital, in a single package. These attempts succeeded in producing both analog and digital ICs, as well as mixed signal ICs. Analog ICs offered operational amplifiers, multipliers, modulators/demodulators, etc., while digital ICs integrated AND, OR, XOR gates and so on

Chips falling under the category of small scale integration (SSI) contain up to 10 independent gates in a single package. Example of SSI includes flip flops, decoder, Multiplexer.With the improvement in technology, 10-100 gates is integrated in a single substrate that comes under the category of Medium scale integration (MSI).Example of MSI includes RAM, Adders, registers etc.In the mid of 1970s, Technology improves again and 1000 gates is integrated in a single substrate, which is called LSI.Example of LSI includes digital clock, calculators etc.Finally in 80s,comes the VLSI(Very large scale integration),which comprises of Thousands of gates in a single package. Personal Computer chips comes down in this category. VLSI circuits are everywhere ... your computer, your car, your brand new state-of-the-art digital camera, the cell-phones. Since then Integration has been growing in a very highly manner and currently millions of gates is occupying in a single package going into ULSI, System level integration and SOC. VLSI is dominated by the CMOS technology. The output switching levels from CMOS ICs is higher than TTL.CMOS having very less power consumption than TTL.74 Series (74LS) comes under the category of TTL

FIELD OF VLSI

VLSI DESIGN

VLSI Design today is the most happening field in Electronics. This is a highly specialized field that has the power of integrating billions of transistors on a Silicon Chip.VLSI chiefly comprises of Front End Design and Back End design these days. While front end design includes digital design using HDL, design verification through simulation and other verification techniques, the design from gates and design for testability, backend design comprises of CMOS library design and its characterization. It also covers the physical design and fault simulation.

VLSI IC DESIGN FLOW

Front End Design Flow

Back End Design Flow

PRBS Generator using VHDL

2012-04-20T13:32:00.001+05:30

Abstract

Pseudo random binary sequence is essentially a random sequence of binary numbers. So PRBS generator is nothing but random binary number generator. It is ‘random’ in a sense that the value of an element of the sequence is independent of the values of any of the other elements. It is 'pseudo' because it is deterministic and after N elements it starts to repeat itself, unlike real random sequences. The implementation of PRBS generator is based on the linear feedback shift register (LFSR). The PRBS generator produces a predefined sequence of 1's and 0's, with 1 and 0 occurring with the same probability. A sequence of consecutive n*(2^n -1) bits comprise one data pattern, and this pattern will repeat itself over time. In this project, the entire design of the PRBS generator was implemented using VHDL programming language and the simulation were done and tested on the XILINX ISE 9.1i simulator

VHDL Code for D Flip Flop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
--library UNISIM;
--use UNISIM.VComponents.all;

entity dff is
Port ( CLK : in std_logic;
RSTn : in std_logic;
D : in std_logic;
Q : out std_logic);
end dff;

architecture Behavioral of dff is
begin
process(CLK)
begin
if CLK'event and CLK='1' then
if RSTn='1' then
Q <= '1';
else
Q <= D;
end if;
end if;
end process;
end Behavioral;

VHDL CODE FOR PRBS

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
--library UNISIM;
--use UNISIM.VComponents.all;

entity lfsr is
Port ( CLK : in std_logic;
RSTn : in std_logic;
data_out : out std_logic_vector(15 downto 0));
end lfsr;

architecture Behavioral of lfsr is

component dff
Port ( CLK : in std_logic;
RSTn : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
signal data_reg : std_logic_vector(15 downto 0);
signal tap_data : std_logic;

begin
process(CLK)
begin
tap_data <= (data_reg(1) xor data_reg(2)) xor (data_reg(4) xor
data_reg(15));
end process;

stage0: dff
port map(CLK, RSTn, tap_data, data_reg(0));

g0:for i in 0 to 14 generate

stageN: dff
port map(CLK, RSTn, data_reg(i), data_reg(i+1));

end generate;

data_out <= data_reg after 3 ns;
end Behavioral;

Design of UART Transmitter in VERILOG

2012-04-19T12:37:00.001+05:30

Abstract

UART is usually an individual integrated circuit used for serial communications over a computer or peripheral device serial port. This UART is designed to make an interface between RS232 line and a micro controller or an IP core. It works fine connected to a serial port of a PC for data exchange with custom electronic. UARTs are now commonly included in micro controllers. In this paper we will design Uart transmitter and Uart Receiver module .Design coding can be done either by Verilog or VHDL by using Xilinx ISE. Examples of such are optical fiber, IrDA (infrared), and (wireless) Bluetooth in its Serial Port Profile (SPP). Some signaling schemes use modulation of a carrier signal (with or without wires). Examples are modulation of audio signals with phone line modems, RF modulation with data radios, and the DC line for power line communication

VERILOG CODING FOR UART TRANSMITTER

TOP MODULE:

module uart_tx(

clk,

rst_n,

write,

data,

txrdy,

tx);

// Port declarations

input clk;

input rst_n;

input write;

input [7:0] data;

output txrdy;

output tx;

// Internal signal declarations

reg txdatardy;

reg [12:0] cnt;

reg [9:0]txdat;

wire [7:0] data_in;

reg baud_clk;

wire txrdy;

reg tx_sts;

always @ (posedge clk)

begin

if(~rst_n) tx_sts <= 1'b0;

else if(write&txrdy) tx_sts <= 1'b1;

else if(txrdy) tx_sts <= 1'b0;

end

always @ (posedge clk)

begin

if(~rst_n) cnt <= 13'b0;

else if(tx_sts & (cnt[12:0] == 5208)) cnt <= 13'b0;

else if(tx_sts) cnt <= cnt + 1;

else cnt <= 13'b0;

end

always @ (posedge clk)

begin

if(~rst_n) baud_clk <= 1'b0;

else if(cnt[12:0] == 2601) baud_clk <= 1'b1;

else baud_clk <= 1'b0;

end

always @ (posedge clk)

begin

if(~rst_n) txdat <= 10'h0;

else if(write & txrdy) txdat <= {1'b1,data,1'b0};

else if(baud_clk) txdat <= txdat>>1;

end

//assign data_in = {data[0],data[1],data[2],data[3],data[4],data[5],data[6],data[7]};

assign tx = txrdy ? 1'b1 : txdat[0];

assign txrdy = (!(|txdat));

endmodule

TEST BENCH:

module uart_tx_tb_v;

// Inputs

reg clk;

reg rst_n;

reg write;

reg [7:0] data;

// Outputs

wire txrdy;

wire tx;

// Instantiate the Unit Under Test (UUT)

uart_tx uut (

.clk(clk),

.rst_n(rst_n),

.write(write),

.data(data),

.txrdy(txrdy),

.tx(tx)

);

initial begin

// Initialize Inputs

clk = 0;

rst_n = 0;

write = 0;

data = 0;

// Wait 100 ns for global reset to finish

#100;

rst_n = 1;

#20

write = 1'b1;

data = 8'b00011111;

#120 data = 8'b10101010;

// Add stimulus here

end

always

begin

#5 clk<=1'b0;

#5 clk<=1'b1;

end

endmodule