CAD LAB MANUAL

Experiment No.-4 Synthesis and simulation of Half Adder and full Adder.

2013-02-20T22:19:00.000-08:00

Experiment No.-4

Aim: Synthesis and simulation of Half Adder and full Adder.

Apparatus Used:-

S.No	Items	Specification	Quantity
1	Computer set	P-4, 2GB DDR	01
2	Software (Tool)	Xilinx 10.1	01

Theory:-
Half Adder:

The half adder is an example of a simple, functional digital circuit built from two logic gates. The half adder adds to one-bit binary numbers (AB). The output is the sum of the two bits (S) and the carry (C). Note how the same two inputs are directed to two different gates. The inputs to the XOR gate are also the inputs to the AND gate. The input "wires" to the XOR gate are tied to the input wires of the AND gate; thus, when voltage is applied to the A input of the XOR gate, the A input to the AND gate receives the same voltage

Full adder:

The full-adder circuit adds three one-bit binary numbers (C A B) and outputs two one-bit binary numbers, a sum (S) and a carry (C1). The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. binary numbers. The carry input for the full-adder circuit is from the carry output from the circuit "above" itself in the cascade. The carry output from the full adder is fed to another full adder "below" itself in the cascade. If you look closely, you'll see the full adder is simply two half adders joined by an OR.

HDL Coding:-

HALF ADDER

library ieee;

use ieee.std_logic_1164.all;

entity andGate is

port( A, B : in std_logic;

S: out std_logic;

C: out stc_logic);

end andGate;

architecture func of andGate is

begin

S<= A xor B;

C<= A and B;

end func;

FULL ADDER

I-method:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity fa is

Port ( a : in std_logic;

b : in std_logic;

c : in std_logic;

s : out std_logic;

cr : out std_logic);

end fa;

architecture Behavioral of fa is

begin

s<= (a xor b) xor c;

cr<= (a and b) or (b and c) or (c and a);

end Behavioral;

II-method:-

library ieee;

use ieee.std_logic_1164.all;

entity andGate is

port( A, B : in std_logic;

F : out std_logic);

end andGate;

architecture func of andGate is

begin

F <= A and B;

end func;

library ieee;

use ieee.std_logic_1164.all;

entity xorGate is

port( A, B : in std_logic;

F : out std_logic);

end xorGate;

architecture func of xorGate is

begin

F <= A xor B;

end func;

-- At this point we construct the half adder

-- using the AND and XOR gates

library ieee;

use ieee.std_logic_1164.all;

entity halfAdder is

port( A, B : in std_logic;

sum, Cout : out std_logic);

end halfAdder;

architecture halfAdder of halfAdder is

component andGate is -- import AND Gate

port( A, B : in std_logic;

F : out std_logic);

end component;

component xorGate is -- import XOR Gate

port( A, B : in std_logic;

F : out std_logic);

end component;

begin

G1 : xorGate port map(A, B, sum);

G2 : andGate port map(A, B, Cout);

end halfAdder;

--*======================*=================== END HALF ADDER

-- Now we define the OR gate that we need for the Full Adder

library ieee;

use ieee.std_logic_1164.all;

entity orGate is

port( A, B : in std_logic;

F : out std_logic);

end orGate;

architecture func of orGate is

begin

F <= A or B;

end func;

--*==============================*

-- We are finally ready to build the Full Adder

library ieee;

use ieee.std_logic_1164.all;

entity fullAdder is

port( A, B, Cin : in std_logic;

sum, Cout : out std_logic);

end fullAdder;

architecture fullAdder of fullAdder is

component halfAdder is --import Half Adder entity

port( A, B : in std_logic;

sum, Cout : out std_logic);

end component;

component orGate is --import OR Gate entity

port( A, B : in std_logic;

F : out std_logic);

end component;

signal halfTohalf, halfToOr1, halfToOr2: std_logic;

begin

G1: halfAdder port map(A, B, halfTohalf, halfToOr1);

G2: halfAdder port map(halfTohalf, Cin, sum, halfToOr2);

G3: orGate port map(halfToOr1, halfToOr2, Cout);

end fullAdder;

----------------------------------------------------------END

Observation/ Analysis:-

RTL schematic of Half adder

RTL schematic of Full adder

2013-02-20T22:14:00.001-08:00

Experiment No.-3 (Value Added)

Aim: Synthesis and simulation of XOR and XNOR gate.

Apparatus Used:-

S.No	Items	Specification	Quantity
1	Computer set	P-4, 2GB DDR	01
2	Software (Tool)	Xilinx 10.1	01

Theory:-

XOR Gate:

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two inputs are high. An encircled plus sign ( ) is used to show the EOR operation.

XNOR Gate:

The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle on the output. The small circle represents inversion.

HDL Coding:

EX-OR Gate implementation:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity EXORGATE is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC);

end EXORGATE;

architecture Behavioral of EXORGATE is

begin

Y<= A XOR B;

end Behavioral;

EX-NOR Gate implementation:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity EXNORGATE is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC);

end EXNORGATE;

architecture Behavioral of EXNORGATE is

begin

Y<= A XNOR B;

end Behavioral;

Observation/ Analysis

RTL schematic of EX-OR Gate

RTL schematic of EX-NOR Gate

Results:

EX-OR GATE SIMULATION

EX-NOR GATE SIMULATION

Experiment-AND Gate & NAND Gate

2012-04-12T00:51:00.014-07:00

Experiment No.-2

Aim: Synthesis and simulation of AND and NAND gate

Apparatus Used:-

S.No	Items	Specification	Quantity
1	Computer set	P-4, 2GB DDR	01
2	Software (Tool)	Xilinx 10.1	01

Theory:-

AND Gate:

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes omitted i.e. AB

NAND Gate:

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion

HDL Coding:

AND Gate implementation:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity ANDGATE is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC);

end ANDGATE;

architecture Behavioral of ANDGATE is

begin

Y<= A AND B;

end Behavioral;

NAND Gate implementation:-

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity NANDGATE is

Port

( A : in STD_LOGIC;

B : in STD_LOGIC;

Y : out STD_LOGIC);

end NANDGATE;

architecture Behavioral of NANDGATE is

begin

Y<= A NAND B;

end

Behavioral;

Observation/ Analysis:-

RTL schematic of AND Gate

RTL schematic of NAND Gate

Results:

AND GATE SIMULATION

NAND GATE SIMULATION

Experiment-NOT, OR, & NOT GATES

2012-04-11T02:58:00.011-07:00

Experiment No.-1

Aim: Synthesis and simulation of NOT, OR, NOR GATE.

Apparatus Used:-

S.No	Items	Specification	Quantity
1	Computer set	P-4, 2GB DDR	01
2	Software (Tool)	Xilinx 10.1	01

Theory:-

NOT Gate:

The NOT gate is an electronic circuit that produces an inverted version of the input at its output. It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A. This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams below show two ways that the NAND logic gate can be configured to produce a NOT gate. It can also be done using NOR logic gates in the same way.

OR Gate:

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high. A plus (+) is used to show the OR operation.

NOR Gate:

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high.The symbol is an OR gate with a small circle on the output. The small circle represents inversion.

HDL Coding:

          NOT Gate implementation:

library ieee;

use ieee.std_logic_1164.all;

entity NOTGATE is

port( A: in std_logic;

C: out std_logic);

end NOTGATE;

architecture func of NOTGATE is

begin

C <= NOT A;

end func;

OR Gate implementation:

library ieee;

use ieee.std_logic_1164.all;

entity orGate is

port( A, B : in std_logic;

F : out std_logic);

end orGate;

architecture func of orGate is

begin

F <= A or B;

end func;

NOR Gate implementation:-

library ieee;

use ieee.std_logic_1164.all;

entity norGate is

port( A, B : in std_logic;

F : out std_logic);

end norGate;

architecture func of norGate is

begin

F <= A nor B;

end func;

Observation/ Analysis

RTL schematic of NOT Gate

RTL schematic of OR Gate

RTL schematic of NOR Gate

Results:

NOT GATE SIMULATION

OR GATE SIMULATION

NOR GATE SIMULATION