Scientific context:

Future supercomputers will be equipped with heterogenous hardware as multicore chips and accelerators. While hardware tends to become massively parallel providing hundreds of cores, parallel programming must provide a way to exploit both the heterogeneity and the potential scalability of the hardware.

High Pperformance Computing community has a long experience of parallel programming. The most popular programming standard in HPC are directive-programming with OpenMP for shared-memory architectures and message-passing programming with MPI for distributed-memory architectures.

There is an important need for these standard to evolve to take into account heterogeneous hardware where different parts of a single program will be executed on different kinds of hardware.

Various programming models can be studied as:

directives, components, skeletons or any vendor languages.

Goal:

The goal of this PhD thesis is to work on a programming model to increase parallel programming productivity. Our proposition is based on high-level directive programming combining the programmer expertise and static program analyses. This thesis should increase this model to take into account hybrid or heterogeneous architectures.

Required skills:

The candidate must have excellent knowledge in:

- Parallel programming

- Compilation

- C language and Unix systems

Contact: frederique.silber-chaussumier@it-sudparis.eu

Candidates should reply to this mail providing the photocopy of the original degree certificate, the list of courses and grades, a letter of motivation and a recommandation letter.

Please don’t hesitate to contact us for further information.

–

Frédérique Silber-Chaussumier Tél: +33(0)160764565 Institut Télécom, Télécom SudParis (ex GET/INT) Computer Science Department, 9 rue C. Fourier 91011 Évry, France

Applications are invited from students with backgrounds in computer science or electronic engineering for a PhD studentship at the Computer Laboratory, University of Cambridge. The successful candidate will join an EPSRC funded project which is investigating a novel massively-parallel single-chip processor architecture targeting high-performance embedded applications. Research is currently being pursued at the language, compiler and architecture levels. Future work will aim to perform a detailed exploration of the on-chip network and microarchitectural design space and explore the application of novel circuit-level techniques. A successful applicant would join a small, but highly motivated, group of researchers exploring a broad range of exciting problems.

A few more details about the Loki project can be found here:

http://www.cl.cam.ac.uk/~rdm34/loki/

An excellent academic track record is essential (1st class honours degree). Projects exist for students with both computer science or electronics/VLSI backgrounds, although a good understanding of computer architecture is necessary in either case.

The EPSRC studentship offers full costs (fees plus stipend) for 36 months for UK and EU citizens, who satisfy the eligibility criteria of the UK Research Councils. The studentship is not available to citizens of non-EU countries. There is also an additional EPSRC CASE funded studentship available with ARM Ltd. in a related area.

Informal enquiries may be made to Dr. Robert Mullins, Computer Laboratory, University of Cambridge (Robert.Mullins@cl.cam.ac.uk).

Eindhoven University of Technology

Faculty of Electrical Engineering

Eindhoven

The Netherlands

FTE 1.0

Application Deadline: 15-09-2010

Vacancy Number: V36.1075

The Faculty of Electrical Engineering delivers education and performs scientific and technological research in the broad discipline of Electrical Engineering. Electrical Engineering covers the application of electrical phenomena with respect to energy, information processing and telecommunication, as well as, electrical and electronic components, and the technology involved. Both hardware, in the form of electronic circuits and accessories, and software, in the form of system software for electro-technical applications, are the subject of study. Existing or new electrical devices, components and systems are analyzed, designed, implemented, controlled and realized. In addition, the maintenance of these systems is the subject of research, as is the societal relevance of electrical engineering and information technology.

Position

The position is in the Section of Digital Circuits and Formal Design Methods (DCFDM) of the Electronic Systems (ES) Group. The mission of the ES Group is to provide a scientific basis for design trajectories of digital electronic circuits and systems ‘from (generalized) algorithm to realization’. To identify the key problems, and verify the validity, robustness and completeness of our results, we develop, implement and maintain consistent and complete flows, and use them for realizing innovative hardware, with emphasis on video processing and embedded architectures. The mission of the DCFDM Section is research and development of theory, methods and EDA tools for modeling, analysis, synthesis and optimization of digital circuits and systems to adequately cope with the increasing complexity and challenges of the nano-electronic technologies. It has an internationally recognized expertise in design theory, methodology and electronic design automation for embedded system design and hardware synthesis. It has also experience with FPGA-based design, (re-)configurable architectures, multi-objective circuit and system optimization and automatic architecture synthesis for (heterogeneous) platform-based systems.

Project

The research work will be performed in the scope of the Architecture Synthesis and Application Mapping (ASAM) project, being a part of the European research program ARTEMIS. The ASAM project addresses the problem of an automatic coherent architecture synthesis and application mapping for heterogeneous multi-processor embedded systems based on configurable application-specific instruction-set processors (ASIPs). It aims at defining a new unified design methodology, as well as, related synthesis and prototyping tool-chains for: multi-objective design space exploration for configurable heterogeneous multi-ASIP systems and identification of the application-tailored system architectures; automatic architecture instantiation or customization of particular application-tailored processors, memories and communication structures of the system architecture; optimal hardware synthesis of the created platform; automatic application mapping on the resulting multi-processor heterogeneous platform; and software compiler retargeting and automatic software compilation, all when accounting for the platform hardware characteristics and for the functional and extra-functional requirements and trade-offs.

The research work will be focused on the automatic architecture instantiation or customization of the application-tailored ASIPs, including their extension with new application-specific instructions and related hardware, optimal synthesis of the ASIPs’ hardware, and collaboration of these micro-architecture and hardware synthesis tasks with the memory and communication architecture synthesis, as well as, with the macro-architecture synthesis of the whole heterogeneous multi-processor system.

Tasks

The main tasks include:

• research work in the scope of the above described project involving development of new design methods, and related electronic design automation (EDA) analysis and synthesis flows and tools, software implementation of the prototype EDA tools and flows, and experimental research with their use;
• assistance to the project coordinator in implementation of the coordination decisions, as well as, coordination, organization, communication and reporting activities, and in supervision of the junior researchers and students;
• establishing and adequately running of the project web-page.

Requirements

Candidates for this Post-doc researcher position should meet the following requirements:

• MSc in Embedded Systems, Computer Engineering, Electronics, Electrical Engineering, Information Technology or related area, with an advanced knowledge or minor/majors in subjects related to electronic design automation, (embedded) processor architectures and/or SoC design;
• Ph.D. degree preferably or P.D. Eng. Degree and an equivalent amount of experience, or MSc degree and a proven large amount of experience and substantial achievements in research and development related to electronic design automation, (embedded) processor architectures and/or SoC design;
• a solid knowledge of and substantial experience in software design and programming, including knowledge of and experience with programming in C++ and/or C;
• excellent invention and learning abilities;
• excellent analytical, organizational and communication skills, including an ability of effective and efficient individual work, as well as, easy cooperation in a team with supervisors, students, other researchers and companies, and excellent English language capabilities both in writing and speaking;
• a substantial knowledge of or experience with ASIP processors, instruction-set synthesis, (re-)configurable systems, FPGA-based design and prototyping, and related EDA tools will be a premium.

Appointment and Salary

The appointment is of immediately and can start as soon as possible. The appointment will be for three years. The gross monthly salary will be in accordance with the Collective Labor agreement of the Dutch Universities (CAO NU) and amounts to at least € 2861 per month (initially, scale 10.4) depending on prior experience. An offer will be based on your knowledge and experience. An attractive package of fringe benefits (including excellent work facilities, end of the year allowance and sport facilities). Moreover an 8% bonus share (holiday supplement) is provided annually.

Information

For more information on the project, tasks or requirements please contact Dr. ir. L. Józwiak, tel. +31-(0)40-2473645, e-mail: L.Jozwiak@tue.nl.

For terms on employment please contact: Mr. P.F.M. Tiel Groenestege, HR advisor of the Faculty of Electrical Engineering tel. +31-(0)40-2472004, e-mail: p.f.m.tiel.groenestege@tue.nl .

More information and on-line application form can be found on the TU/e web-pages:

http://jobs.tue.nl/wd/plsql/wd_portal.search_results?p_web_site_id=3085&p_category_id=3713&p_show_results=Y&p_form_type=CHECKBOX&p_no_days=999&p1=6047&p1_val=Any&p2=6048&p2_val=Department+of+Electrical+Engineering&p_text=&p_save_search=N

and

http://w3.tue.nl/en/services/dpo/excellent_jobs_for_excellent_people

1) Communication Protocols and Network Architectures

2) Exascale Technologies

3) Parallel Discrete Event Simulations

Work Location:

The IBM Technology Campus, Dublin, Ireland.

Description:

The successful candidate will join a research team working with IBM internal and external partners towards the creation of a novel Exascale computing system, targeted towards Smarter Planet applications. Responsibilities include working closely with the Principal Investigator to create and evaluate novel ideas, co-advising PhD students, supervising research projects with PostDocs and university faculty, and preparing publications and presentations. In addition, the successful candidate will be expected to work with and maintain close connections with other teams around IBM.

Required background for all three positions:

• Proven extensive publication record in appropriate journals and conferences
• Ph.D. in Electrical Engineering or Computer Science
• 5-10 years industrial/academic experience past PhD – Associate Professor or equivalent
• Good communication skills (English) verbal and written

For further details please contact Dr. Eugen Schenfeld at eugen@us.ibm.com

Additional requirements for Communication Protocols and Network Architectures:

• Conducting Research and specializing in LANs routing, communication protocols (e.g. 10G/100G Ethernet routing and protocols) and innovation transport mechanisms and structures for future supercomputers
• Proven extensive publication record in appropriate journals and conferences

You can apply online Learn more

Additional requirements for Exascale Technologies:

• Conducting Research and specializing in multiple technologies for future supercomputers, with a deep understanding of the computer system needs, e.g. WDM, dense packaging technologies (3DI), optical transceivers, FPGA for prototyping of novel communication systems.
• Proven extensive publication record in journals and conferences on supercomputer physical technologies.

You can apply online Learn more

Additional requirements for Parallel Discrete Event Simulations:

• Conducting Research and specializing in Parallel Discrete Event Simulations (PDES) for extreme system, innovative simulation approaches and modelling of applications, technology and architecture of large systems.
• Proven extensive publication record in journals and conferences on PDES

You can apply online Learn more

The research group led by Prof. Lieven Eeckhout at the Department of Electronics and Information Systems at Ghent University is a partner in the ExaScience Lab and focuses on architectural simulation and modeling of future exascale systems. New architectural modeling and simulation approaches will be developed as well as workload scale-down and scale-up methodologies in order for architects to enable making design decisions and explore the architectural design space of future exascale systems.

There are two open post-doctoral research positions for highly motivated individuals: one for immediate start and one for Jan 2011.

Candidates should have strong backgrounds in at least one of the following areas:

? Computer architecture

? Architectural simulation and modeling

? Power and reliability modeling

? Workload analysis and characterization

? Scientific computing

The researchers will have access to a stimulating research environment at Ghent University and within the ExaScience Lab. There will be a close collaboration with other Intel labs in Europe and the US.

Employment details:

? Duration: One year, renewable after positive evaluation.

? Application closing date: Positions will be filled as soon as possible.

? Ghent University is committed to equality of opportunity.

An application should include:

? A cover letter expressing the applicant?s research background,

including a clear indication of the level of expertise in the areas mentioned in the job description above;

? A curriculum vitae detailing contact information, degrees obtained

and major research achievements, publication list;

? The names of three contact persons willing to provide a

recommendation letter;

? A statement of availability.

Please send applications to Lieven Eeckhout (Lieven.Eeckhout@UGent.be).

For more information about Lieven Eeckhout?s research activities, please visit http://www.elis.ugent.be/~leeckhou/.

For more information about the ExaScience Lab, please visit http://www.exascience.com/.

The main project topics to be developed in Siena will be a) the exploration CMP architectures that take advantage from on-chip photonic interconnection networks, in conjunction with b) the development of specific compiler and/or OS and/or runtime optimizations to maximize the utilization of the available on-chip resources.

The three-year PHOTONICA project aims at exploring architectures endowed with both passive and active (reconfigurable) photonic networks, studied by the research group at the Universita’ di Ferrara, and employing the advanced photonic low-level devices studied by the Politecnico di Bari research group.

Research activities in Siena will be performed in collaboration with the Universita’ di Pisa (www.iet.unipi.it) and with other European institutions.

Call url: http://www.dii.unisi.it/~bartolini/201007-PhotonicaPhd.html

We are seeking applicants with strong motivation in computer architecture and, in particular, in the following topics:

- CMP architectures, memory hierarchies and system simulation

- Performance evaluation

- profile-guided feedback-driven optimization

Good knowledge of written and oral English is required and the following skills are positively considered:

- good programming abilities (C/C++, Java)

- experience in using/modifying architectural simulators

- ability to work autonomously and in team

NOTE

Due to project funding constraints, the applicant should be less than 32 years old.

SALARY and LOGISTIC

As the salary will be paid directly from the project so, please, neglect the standard salary indications in the PhD call documentation. It will be in the 18-20 keuro range, per year. For further details send in an email.

A personal laptop will be available to the PhD student from the second year.

Our PhD school is part of the ITALIAN EXCELLENCE CENTER "Superior School Santa Chiara" http://www.unisi.it/santachiara/ Candidates are welcome to apply for a hosting in this facility which is 100 meters from our Faculty.

HOW TO APPLY (*)

1) Please, send an email as soon as possible (and before the July 28th application deadline) to the main investigator of the University of Siena research group, Sandro Bartolini (bartolini@dii.unisi.it), including a covering letter, curriculum vitae and, possibly, contact details (email) of one or more referees.

Don’t wait till the last day because bureaucratic procedures (see point

2) need a bit of time.

2) The next step will be the formal application, by *July 28th*, to the PhD selection procedure of the University of Siena (see

http://dottorati.unisi.it/bandi/bando_traduzione_xxvi_giugno_ing.pdf)

preferably through the on-line procedure (http://dottorati.unisi.it/domande/elenco_proposte_26_giugno_ing.asp).

Further info: http://www.unisi.it/v0/pagina_en.htm?fld=2871

(*) NOTE: the position is open also to MSc graduates, younger than 32 years old, not wishing to go through the PhD program in Siena and not having the PhD degree yet. In that case, simply go through the step 1).

IMPORTANT DATES

- selection dates: to appear at http://dottorati.unisi.it/concorsi

- formal start of PhD program: October 1st

ADDITIONAL INFO

- Our research group is part of the HiPEAC NETWORK OF EXCELLENCE:

http://www.hipeac.net

- UNIVERSITY OF SIENA: http://www.unisi.it

- DEPARTMENT OF INFORMATION ENGINEERING: http://www.dii.unisi.it

- ABOUT SIENA: http://en.wikipedia.org/wiki/Siena

<http://jobs.st.com/HROnline/HROnlineJobReq.nsf/JobReqAllWeb?SearchView&Query=(([Form]=JobReq)AND(compiler*)AND([region_b]=EU)AND([country_b]=EU_FRA)AND([site_b]=EU_FRA_02))&Country=France&Site=Grenoble&Keyword=compiler&JobFunction=&JFEnd&SearchOrder=3&SearchMax=199&Count=10&Start=1>

The two jobs titles are:

- Job Id 110734 : Interprocedural optimization of embedded Linux

applications

- Job Id 110707 : Optimization of Flash(R) and JavaScript Just-In-Time

compilers

Jobs can be found also by http://jobs.st.com -> Search -> Keyword:

"compilation"

The DEPARTMENT OF INFORMATION ENGINEERING (UNIVERSITY OF SIENA, ITALY) is pleased to announce the availability of 1 postdoc position in the framework the EUROPEAN RESEARCH (FP7): MULTICORE ARCHITECTURE http://www.teraflux.eu

We are looking for motivated, talented candidates for a post-doc research position in COMPUTER ARCHITECTURE. Specifically, the research topics are closely related to MULTICORE SYSTEMS.

………………………………………………………………

REQUESTED EXPERTISE (MOSTLY COMPUTER ARCHITECTURE) The required profile includes a background/interest in COMPUTER ARCHITECTURE and a good knowledge of written and oral English.

The following expertise is especially considered:

- experience in multicore systems

- experience in performance evaluation

- experience in system simulation

- experience in virtual machine based simulation and modeling

- experience in programming in C and C++

- experience in Linux/Windows internals

- experience in working independently AND in team

- publications in IEEE/ACM Journals or conferences

………………………………………………………………

MORE DETAILS ABOUT THE ERA RESEARCH PROJECT http://www.teraflux.eu Please contact the project coordinator if you need more information.

Roberto Giorgi giorgi@dii.unisi.it

………………………………………………………………

APPLICATION

This research position is open to citizens of any nationality.

However, the application should be prepared in Italian: if you need some assistance for this, please contact Gabriele Cecchetti (gabriele.cecchetti@dii.unisi.it ), who is supervising the application process.

Updates and news on how to apply to this call will be available at:

http://teraflux.eu/PostDocAtUNISI-Call

*** PLEASE NOTE THE APPLICATION DEADLINE IS JULY 29th, 2010 ***

………………………………………………………………

DURATION AND SALARY

Currently, we have 1 available position that can extend up to 3 and half years with a yearly salary of 30keuro **NET**.

The research activity can start almost immediately after the completion of the selection process (01 September 2010).

………………………………………………………………

MORE INFO ABOUT THE UNIVERSITY OF SIENA

- We are part of the HiPEAC NETWORK OF EXCELLENCE and coordinating the TERAFLUX project:

http://www.hipeac.net – http://www.teraflux.eu

- UNIVERSITY OF SIENA: http://www.unisi.it Student services: http://www.unisi.it/v0/pagina_en.htm?fld=2880

- DEPARTMENT OF INFORMATION ENGINEERING: http://www.dii.unisi.it Our Faculty ranks the highest score in Italy for Industrial and Information Engineering (Independent Valuation from the Ministry of University and Research – CIVR 2006)

- ABOUT SIENA: http://en.wikipedia.org/wiki/Siena

A description by Prof. Cetin K. Koc, UCSB:

"To me, the best city in the best region of the world."

- FOR ANY FURTHER INFORMATION

Please contact: Gabriele Cecchetti ( gabriele.cecchetti@dii.unisi.it )

Hardware Based Computational Biology: (Dr Andy Nisbet, Dr Helen Ji, Dr Qiuyu Wang and Dr Martyn Amos).

Computational biology is concerned with the application of algorithmic techniques to the solution of problems in the life and health sciences.

The various genome projects currently underway are generating massive amounts of raw data, which, combined with other data, must be understood within a systems framework if we are to understand and treat disease.

Many algorithms in common use are computationally intensive, and require expensive hardware clusters. In addition, many of the operations required by bio-based algorithms do not translate well to existing processor instruction sets. However, reconfigurable hardware accelerators (FPGAs) offer an alternative framework for the development of optimised hardware for computational biology. This project will investigate methods for the automated solution of biological problems, using such a hardware platform.

The successful candidate will be based in the Novel Computation Group within Computing and Mathematics.

Start date: no later than 1st September 2010

Applicants with backgrounds in one or more of electronic engineering, computer science and computational biology are encouraged. The minimum qualification required is an upper-second class degree (or equivalent) in a relevant discipline (a relevant Master’s qualification would be ideal). Experience of hardware design (using high or low-level synthesis

tools) and/or computational biology would be extremely beneficial. The studentship fully covers University tuition fees (at EU/UK level) and provides a tax-free bursary of £12K p.a. This vacancy is only available to U.K. or EU citizens.

To apply, in the first instance please e-mail Dr Andy Nisbet

(a.nisbet@mmu.ac.uk) with a covering letter, curriculum vitae and contact details (preferable e-mail) of at least two referees.

Deadline for applications is July 16th

******************************************************

Two Early Stage Researcher (ESR) positions are available at the Institute of Computer Science (ICS), Foundation for Research and Technology-Hellas (FORTH), Heraklion, Crete Island, Greece. These positions are funded by the European Commission under the Marie Curie Initial Training Network Programme (project TransForm).

We address (pre-PhD) researchers with an MSc aiming at significantly improving their career perspectives from both the PUBLIC and PRIVATE sector.

The duration of the appointment is 3 years with a possibility of extension funded from other sources. Applications for smaller periods will also be considered. Applicants may also request to be considered as candidates for the PhD program at the Department of Computer Science, University of Crete, Greece.

RESEARCH TOPIC

————–

The ESR will pursue research on concurrent computing (with emphasis on the Theoretical Foundations of Transactional Memory).

The recruited ESR will work in close collaboration with the other academic partners of the project:

* EPFL, Switzerland (Prof. Rachid Guerraoui)

* Technische Universitaet of Berlin, Germany (Dr. Petr Kuznetsov)

* Technion, Israel (Prof. Hagit Attiya)

* University of Rennes I, France (Prof. Michel Raynal)

and with the possibility of collaboration with researchers from the industry:

* Deutsche Telekom, Germany

* Microsoft Research, Cambridge, UK

* Sun Microsystems Labs, Massachusetts, USA

* IBM T.J. Watson Research Center, USA

ELIGIBILITY

———–

The recruited researchers should be, at the time of selection, in the first four years of their research careers (measured from the date when they obtained the degree which would formally entitle them to embark on a doctorate). Also:

* ESR should not already have a PhD and they should have the qualifications

to embark on a PhD program (i.e., s/he should have an MSc by the time

of the recruitment).

* ESR should be nationals of a country other than Greece or,

in case they are Greek, they should have legally resided

and have had their principal activities (work, studies, etc.)

in a country other than Greece for at least 3 out of the last 4 years, and

* ESR (regardless of their nationalities) must not have resided or carried out

their main activities (work, studies, etc.) in Greece for more

than 12 months in the last 3 years.

The positions are open until appropriate candidates are found.

The next cut-off date is June 30, 2010.

FINANCIAL PROVISIONS

——————–

Marie Curie fellows enjoy good salaries and working conditions, career development opportunities and work-life balance.

More specifically, the financial support of Marie Curie ITN to the ESR includes:

* a fair monthly living and mobility allowance,

* a yearly travel allowance (i.e., a fixed amount of money based upon

the direct distance between the location of origin of the researcher

and Heraklion, Greece, where FORTH-ICS is located),

* a career exploratory allowance (i.e., a single payment for attending job interviews,

additional courses, job fairs, etc.), and

* coverage of the expenses related to the participation of the ESR in research

and training activities (contribution to research-related costs, meetings,

conference attendance, training actions, etc.).

HOW TO APPLY

————

Please send an e-mail to <faturu AT csd DOT uoc DOT gr> containing your curriculum vitae.

Then, she will contact you asking for more documents if required.

GENDER EQUALITY

—————

FORTH is an equal opportunity employer. Female candidates are particularly

encouraged to apply. Panagiota Fatourou (the coordinator of TransForm) is

a woman, as well as half of the project researchers. This identifies the

extra sensitivity of TransForm to gender equality issues; all possible

efforts will be made to increase participation of women researchers in

the project.

MORE INFORMATION

—————-

http://www.ics.forth.gr/~faturu/