Chip Guru

AHB

2013-03-12T09:44:00.002-07:00

Must a read after a write to the same address return the newly written data?

Scenario

When there is an AHB write followed by a read from the same address, should the read return the old or the new data when the read address phase is in same cycle of the write data phase?

Answer

The answer to this question is dependent on the design of the slave.

A simple slave will not be buffering any data, so the returned read data will be the latest. A more complex slave could implement buffering for write data (if allowed by HPROT[2]) and so it could "snoop" the write buffer contents before returning read data, or it might just return the previously stored data regardless of what might be buffered.

In conclusion, all the AHB specification requires is that data is returned.

What system support is required if a slave can be powered down or have its clock stopped?

Answer

If a slave access is attempted while that slave is in a power down state or has had its clock stopped, you must ensure that an access will cause the power/clock to be restored, or else configure the AHB decoder up to redirect any such accesses to the dummy slave so that the system does not hang forever when an access to the device is made when it is disabled.

Redirecting the access in this way will ensure that random "IDLE" addresses are treated with the HREADY high and HRESP=OKAY default response, but real accesses (NONSEQ or SEQ) will be detected with an ERROR response.

When can Early Burst Termination occur ?

Answer

Bursts can be early terminated either as a result of the Arbiter removing the HGRANT to a master part way through a burst, or after a slave returns a non-OKAY response to any beat of a burst. Note however that a master cannot decide to terminate a defined length burst unless prompted to do so by the Arbiter or Slave responses.

All AHB Masters, Slaves and Arbiters must be designed to support Early Burst Termination.

Can HTRANS change whilst HREADY is low?

Answer

In general, an AHB master should not change control signals whilst HREADY is low. However it is allowable to change HTRANS in the following conditions:

HTRANS=IDLE
The AHB master is performing internal operations and has not yet committed to a bus transfer. However during the AHB wait states (HREADY low) the master may determine that a bus transfer is required and change HTRANS on the next cycle to NONSEQ.
HTRANS=BUSY
HTRANS is being used to give the master time to complete internal operations, which may be entirely independent of HREADY (i.e. wait states on the AHB). Therefore HTRANS can change on the next cycle to any legal value, i.e. SEQ if the burst is to continue, IDLE if the burst has completed, NONSEQ if a separate burst is to begin.
HRESP=SPLIT/RETRY
As stated in the AHB specification, a master must assert IDLE on HTRANS during the second cycle of the two-cycle SPLIT or RETRY slave response so HTRANS will change value from the first cycle to the second cycle of the response.
HRESP=ERROR
The master is permitted to change HTRANS in reaction to an ERROR response in the same way as in reaction to a SPLIT/RETRY response and cancel any further beats in the current burst (even if HBURST is indicating a defined-length burst). In this case HTRANS changes to IDLE on the second cycle of the response. Alternatively, the master is permitted to continue with the current transfers

Can a BUSY transfer occur at the end of a burst?

Answer

A BUSY transfer can only occur at the end of an undefined length burst (INCR). A BUSY transfer cannot occur at the end of a fixed length burst (SINGLE, INCR4, WRAP4, INCR8, WRAP8, INCR16, WRAP16).

Can a master change the address/control signals during a waited transfer?

Answer

Yes. If the address/control signals are indicating an IDLE transfer then the master can change to a real transfer (NONSEQ) when HREADY is low.

However, if a master is indicating a real transfer (NONSEQ or SEQ) then it cannot cancel this during a waited transfer unless it receives a SPLIT, RETRY or ERROR response.

Can an AHB master be connected directly to an AHB slave?

Answer

Any slave which does not use SPLIT responses can be connected directly to an AHB master. If the slave does use SPLIT responses then a simplified version of the arbiter is also required.

If an AHB master is connected directly to an AHB slave it is important to ensure that the slave drives HREADY high during reset and that the select signal HSEL for the slave is tied permanently high.

Do all slaves have to support the BUSY transfer type?

Answer

Yes. All slaves must support the BUSY transfer type to ensure they are compatible with any bus master.

Does the address have to be aligned, even for IDLE transfers?

Answer

Yes. The address should be aligned according to the transfer size (HSIZE) even for IDLE transfers. This will prevent spurious warnings from bus monitors used during simulation.

How many masters can there be in an AHB system?

Answer

The AHB specification caters for up to 16 masters. However, allowing for a dummy bus master means the maximum number of real bus masters is actually 15. By convention bus master number 0 is allocated to the dummy bus master.

Is HREADY an input or an output from slaves?

Answer

An AHB slave must have the HREADY signal as both an input and an output.

HREADY is required as an output from a slave so that the slave can extend the data phase of a transfer.

HREADY is also required as an input so that the slave can determine when the previously selected slave has completed its final transfer and the first data phase transfer for this slave is about to commence.

Each AHB Slave should have an HREADY output signal (conventionally named HREADYOUT) which is connected to the Slave-to-Master Multiplexer. The output of this multiplexer is the global HREADY signal which is routed to all masters on the AHB and is also fed back to all slaves as the HREADY input.

Is a default slave really necessary?

Answer

If the entire 4 gigabyte address space is defined then a default slave is not required. If, however, there are undefined areas in the memory map then it is important to ensure that a spurious access to a non-existent address location will not lock up the system. The functionality of the default slave is extremely simple and it will often make sense to implement this within the decoder.

Is a dummy master really necessary?

Answer

A dummy master is necessary in any system which has a slave that can give SPLIT transfer responses. The dummy master is required so that something can be granted the bus if all the other masters have received a SPLIT response.

No logic is required for the dummy master and it can be implemented by simply tying off the inputs to the master address/control multiplexer for the dummy master position. The requirements for a dummy master are that HTRANS is driven to IDLE, HLOCK is driven low, and all other master outputs are driven to legal values.

Is it legal for a master to change HADDR when a transfer is extended?

Answer

If a master is indicating that it wants to do a NONSEQ, SEQ or BUSY transfer then it cannot change the address during an extended transfer (when HREADY is low) unless it receives an ERROR, RETRY or SPLIT response. If the master is indicating that it wants to do an IDLE transfer then it may change the address.

Is it specified that HPROT, HSIZE and HWRITE remain constant throughout a burst?

Answer

Yes, the control signals must remain constant throughout the duration of a burst.

The specification recommends that only 16 wait states are used. What should you do if more than 16 cycles are needed?

Answer

For some slaves it is acceptable to insert more than 16 wait states. For example, a serial boot ROM which is only ever accessed at initial power up could insert a larger number of wait states and it would not affect the calculation of the system performance and latency once system power up has been completed.

For other slaves a number of options exist. A SPLIT or RETRY response could be used to indicate that the slave is not yet able to perform the requested data transfer, or the slave could be accessed either in response to interrupts or after polling a status register, in either case indicating that the slave is now able to respond in an acceptable number of cycles.

What are the different bursts used for?

Answer

Typically a master would use wrapping bursts for cache line fills where the master wants to access the data it requires first and then it completes the burst to fetch the remaining data it requires for the cache line fill. Incrementing bursts are used by masters, such as DMA controllers, that are filling a buffer in memory which may not be aligned to a particular address boundary.

What default state should be used for the HREADY and HRESP outputs from a slave?

Answer

It is recommended that the default value for HREADY is high and the default value for HRESP is OKAY. This combination ensures that the slave will respond correctly to IDLE transfers to the slave, even if the slave is in some form of power saving mode.

What is the difference between a dummy bus master and a default bus master?

Answer

The term default bus master is used to describe the master that is granted when none of the masters in the system are requesting access to the bus. Usually the bus master which is most likely to request the bus is made the default master.

The dummy bus master is a master which only performs IDLE transfers. It is required in a system so the arbiter can grant a master which is guaranteed not to perform any real transfers. The two cases when the arbiter would need to do this are when a SPLIT response is given to a locked transfer and when a SPLIT response is given and all other masters have already been SPLIT.

What is the recommended default value for HPROT?

Answer

Many bus masters will not be able to generate accurate protection information and for these bus masters it is recommended that the HPROT encoding shows, Non-cacheable, Non-bufferable, Privileged, Data Accesses which corresponds to HPROT[3:0] = 4'b0011.

What is the state of the AHB signals during reset?

Answer

The specification states that during reset the bus signals should be at valid levels. This simply means that the signals should be logic '0' or '1', but not Hi-Z. The actual logic levels driven are left up to the designer. HTRANS is the only signal specified during reset, with a mandatory value of IDLE.

It is important that HREADY is high during reset. If all slaves in the system drive HREADY high during reset then this will ensure that this is the case. However, if slaves are used which do not drive HREADY high during reset it should be ensured that a slave which does drive HREADY high is selected at reset.

What sequences of transfers types (HTRANS) can occur on the bus?

Answer

The following examples show some of the sequences of HTRANS that can occur on the bus:

A large burst of four transfers followed by an IDLE.

N - S - S - S - I

A large burst of four transfers which includes BUSY transfers.

N - S - B - S - B - S - I

A burst of four transfers followed by another burst.

N - S - S - S - N - S - S - S - I

A single transfer followed by a burst of four transfers.

N - N - S - S - S - I

A single transfer followed by an IDLE

N - I

An undefined length burst which concludes with a BUSY transfer.

N - B - S - B - S - B - I

An undefined length burst which concludes with a BUSY transfer and is followed immediately by another burst.

N - B - S - B - S - B - N – S

When a master rebuilds a burst which has been terminated early are there any limitations on how it rebuilds the burst?

Answer

The only limitation is that the master uses legal burst combinations to rebuild the burst. For example, if a master was performing an 8 beat burst, but had only completed 3 transfers before losing control of the bus, then the remaining 5 transfers could be performed either by using a 1 beat SINGLE burst followed by a 4 beat INCR4 burst, or it could be performed using a 5 beat undefined length INCR burst.

For simplicity it is recommended that masters use INCR bursts to rebuild the remaining transfers.

How does the AHB handle LOCKed SPLITs?

Answer

When a transfer is SPLIT the arbiter degrants and removes the SPLIT master out of the arbitration until the slave indicates that the transfer can complete. When an access is LOCKed the access cannot be interrupted by an access from another master.

The only possible way that an AHB system can handle these two requirements simultaneously is to grant a "dummy master" when the LOCKed access is SPLIT. The dummy master will only perform IDLE transactions, which are allowable during a locked transfer. To grant any other master would violate the LOCK protocol, for the arbiter to ignore the SPLIT would violate the SPLIT protocol - the dummy master is the only option.

The dummy master is also used when all masters are have received a SPLIT response (the dummy master cannot receive a SPLIT response).

It is recommended that the designer of the split-capable slave(s) makes sure that the slave monitors its HMASTLOCK input so that it doesn't return a SPLIT on a LOCKed transfer, as this serves no purpose.

How many clock cycles should the reset signal in an AMBA system be asserted for?

Answer

It is recommended that master and slave components should clearly state if they have a reset requirement greater than 1 or 2 cycles. It is also recommended that the system design should hold reset asserted for at least 16 cycles, unless it is known that a master or slave component has a longer reset requirement.

Is it legal for an AHB wrapping burst to be aligned with respect to the total number bytes in the burst, such that it does not wrap?

Answer

Yes, this behavior is compliant with the AHB protocol.

Consider a four-beat wrapping burst of word (4-byte) transfers (which will wrap at 16-byte boundaries).

If the start address of the transfer is 0x30, then the burst consists of four transfers to addresses 0x30, 0x34, 0x38, and 0x3C.

Again, although HBURST is set to WRAP4, the burst will not actually wrap, which is allowed.

When should a master assert and deassert the HLOCK signal for a locked transfer?

Answer

The HLOCK signal must be asserted at least one cycle before the start of the address phase of a locked transfer. This is required so that the arbiter can sample the HLOCK signal as high at the start of the address phase.

The master should deassert the HLOCK signal when the address phase of the last transfer in the locked sequence has started.

When should a master deassert its HBUSREQ signal?

Answer

For an undefined length burst (INCR) a master must keep its HBUSREQ signal asserted until it has started the address phase of the last transfer in the burst. This will mean that if the penultimate transfer in the burst is zero wait state then the master may be granted the bus for an additional transfer at the end of an undefined length burst.

For a defined length burst the master can deassert the HBUSREQ signal once the master has been granted the bus for the first transfer. This can be done because the arbiter is able to count the transfers in the burst and keep the master granted until the burst completes.

However it is not a mandatory requirement for an Arbiter to allow a burst to complete, so the master will have to re-assert HBUSREQ if the Arbiter removes HGRANT before the burst has been completed.

When will the arbiter grant another master after a locked transfer?

Answer

The arbiter will always grant the master an extra transfer at the end of a locked sequence, so the master is guaranteed to perform one transfer with the HMASTLOCK signal low at the end of the locked sequence. This coincides with the data phase of the last transfer in the locked sequence.

During this time the arbiter can change the HGRANT signals to a new bus master, but if the data phase of the last locked transfer receives either a SPLIT or RETRY response then the arbiter will drive the HGRANT signals to ensure that either the master performing the locked sequence remains granted on the bus for a RETRY response, or the Dummy master is granted the bus for the SPLIT response.

Can a master deassert HLOCK during a burst?

Answer

The AHB specification requires that all address phase timed control signals (other than HADDR and HTRANS) remain constant for the duration of a burst.

Although HLOCK is not an address phase timed signal, it does directly control the HMASTLOCK signal which is address phase timed.

Therefore HLOCK must remain high for the duration of a burst, and can only be deasserted such that the following HMASTLOCK signal changes after the final address phase of the burst.

Can a master perform transfers other than IDLE when the bus was granted to it, but not requested by the master?

Answer

Yes. A master can perform transfers other than IDLE when it had not requested the bus. Please note that in this case it is still recommended that the master asserts its request signal so that the arbiter does not change ownership of the bus to a lower priority master while the transfers are in progress.

If a master is currently granted the bus by default, how many cycles before starting an non-IDLE transfer does it have to assert HBUSREQ?

Answer

None. It can start a non IDLE transfer immediately.

What is the relationship between the HLOCK signal and the HMASTLOCK signal?

Answer

At the start of the address phase of every transfer the arbiter will sample the HLOCK signal of the master that is about to start driving the address bus and if HLOCK is asserted at this point then HMASTLOCK will be asserted by the arbiter for the duration of the address phase of the transfer.

When can the HGRANT signal change?

Answer

The HGRANT signal can change in any cycle and the following cases are possible:

It is possible that the HGRANT signal may be asserted and then removed before the current transfer completes. This is acceptable because the HGRANT signal is only sampled by masters when HREADY is high.
A master can be granted the bus without requesting it.
The above point also means that it is possible to be granted the bus in the same cycle that it is requested. This can occur if the master is coincidentally granted the bus in the same cycle that it requests it.

Why is HADDR sometimes shown as an input to the arbiter?

Answer

The address bus, HADDR, is not required as an input to the arbiter but in some system designs it may be useful to use the address bus to determine a good point to change over between bus masters. For example, the arbiter could be designed to change bus ownership when a burst of transfers reaches a quad word boundary.

Can an arbiter be designed to always allow bursts to complete?

Answer

A SPLIT, RETRY or ERROR response from a slave can always cause a burst to be early terminated. This is outwith the control of the Arbiter and so must be supported.

Undefined length INCR bursts cannot have their end point predicted, so there is no efficient way that an Arbiter design can allow the burst to complete before granting another master. INCR bursts must be arbitrated on a cycle by cycle basis.

Defined length INCRx and WRAPx bursts can have their beats counted, and so allowed to complete by the Arbiter. However because of the AHB arbitration synchronous timing, there is no way to avoid possibly terminating a burst immediately after the first transfer of the burst has been indicated.

The Arbiter only knows that a defined length burst is in progress by sampling the HBURST bus. However the first point at which HBURST can be sampled is after the first clock cycle of the first burst beat, by which time the Arbiter may already have decided to grant another master and will have changed the HGRANT outputs accordingly. Only a combinatorial path from HBURST to HGRANT would allow the burst to be detected in time to avoid early termination in this scenario, but combinatorial paths in the AHB bus are not allowed.

Why is there a 1KB restriction in AHB?

Answer

The 1KB restriction you refer to is not a restriction on maximum slave size but a constraint within AHB that says that a burst must not cross a 1KB boundary. The limit is designed to prevent bursts crossing from one device to another and to give a reasonable trade-off between burst size and efficiency. In practise, this means that a master must ALWAYS break a burst that would otherwise cross the 1KB boundary and restart it with a non-sequential transfer, thus:

Address: 0x3F0 0x3F4 0x3F8 0x3FC 0x400 0x404 0x408

Transfer: NSEQ SEQ SEQ SEQ NSEQ SEQ SEQ

What's the difference between retry and split in AHB?

Answer

The SPLIT and RETRY responses provide a mechanism for slaves to release the bus when they are unable to supply data for a transfer immediately. Both mechanisms allow the transfer to finish on the bus and therefore allow a higher-priority master to get access to the bus.

When a master initiates a transaction on the AMBA bus, if the target detects that the transfer will take a large number of cycles to perform, it can issue a SPLIT signal. What happens now is that the arbiter can grant the bus to other masters even before the SPLIT transaction is complete. The master to which the SPLIT has been issued has to then wait and complete the entire transaction.

During the address phase of a transfer the arbiter generates a tag, or bus master number, on HMASTER[3:0] which identifies the master that is performing the transfer. Any slave issuing a SPLIT response must be capable of indicating that it can complete the transfer, and it does this by making a note of the master number on the HMASTER[3:0] signals.

Later, when the slave can complete the transfer, it asserts the appropriate bit, according to the master number, on the HSPLITx[15:0] signals from the slave to the arbiter. The arbiter then uses this information to unmask the request signal from the master and in due course the master will be granted access to the bus to retry the transfer. The arbiter samples the HSPLITx bus every cycle and therefore the slave only needs to assert the appropriate bit for a single cycle in order for the arbiter to recognize it.

The basic stages of a SPLIT transaction are:
1. The master starts the transfer in an identical way to any other transfer and
issues address and control information
2. If the slave is able to provide data immediately it may do so. If the slave
decides that it may take a number of cycles to obtain the data it gives a SPLIT
transfer response. During every transfer the arbiter broadcasts a number, or
tag, showing which master is using the bus. The slave must record this number,
to use it to restart the transfer at a later time.
3. The arbiter grants other masters use of the bus and the action of the SPLIT
response allows bus master handover to occur. If all other masters have also
received a SPLIT response then the default master is granted.
4. When the slave is ready to complete the transfer it asserts the appropriate bit of
the HSPLITx bus to the arbiter to indicate which master should be regranted
access to the bus.
5. The arbiter observes the HSPLITx signals on every cycle, and when any bit of
HSPLITx is asserted the arbiter restores the priority of the appropriate master.
6. Eventually the arbiter will grant the master so it can re-attempt the transfer. This
may not occur immediately if a higher priority master is using the bus.
7. When the transfer eventually takes place the slave finishes with an OKAY
transfer response.

For a SPLIT transfer the arbiter will adjust the priority scheme so that any other
master requesting the bus will get access, even if it is a lower priority. In order
for a SPLIT transfer to complete the arbiter must be informed when the slave has
the data available.

For RETRY the arbiter will continue to use the normal priority scheme and
therefore only masters having a higher priority will gain access to the bus.

What value should be used for HTRANS when an AHB master gets a RETRY

response from a slave in the middle of burst?

Whenever a transfer is restarted it must use HTRANS set to NONSEQ and it

may also be necessary to adjust the HBURST information (usually just to

indicate INCR).

What address should be on the bus during the IDLE cycle after a SPLIT or

RETRY?

It does not matter what address is driven onto the bus during this cycle.

The slave selected by the driven address should not take any action and

must respond with a zero wait state OKAY response.

In many cases it will be simpler for the master to leave the address

unaltered during this cycle, so that it remains at the address of the next

transfer that the master wishes to perform and only in the following cycle

does the master return the address to that of the transfer that must be

repeated because of the SPLIT or RETRY response.

In some designs it may be possible for the master to return the address to

that required to repeat the previous transfer during the IDLE cycle and

this behaviour is also perfectly acceptable.

Do all masters have to support SPLIT and RETRY?

Yes. All masters must support SPLIT and RETRY responses to ensure they are

compatible with any bus slave. A master will handle both SPLIT and RETRY

responses in an identical manner.

Can a SPLIT or RETRY response be given at any point during a burst?

Yes. A SPLIT, RETRY or ERROR response can be given by a slave to any

transfer during a burst. The slave is not restricted to only giving these

responses to the first transfer.

Will a master always lose the bus after a SPLIT response?

Yes. A slave must not assert the relevant bit of the HSPLIT bus in the same

cycle that it gives the SPLIT response and therefore the master will always

lose the bus.

Can a slave assert HSPLITx in the same cycle that it gives a SPLIT

response?

No. The specification requires that HSPLITx can only be asserted after the

slave has given a SPLIT response.

Do all slaves have to support the SPLIT and RETRY responses?

No. A slave is only required to support the response types that it needs to

use. For example, a simple on-chip memory block which can respond to all

transfers in just a few wait states does not need to use either the SPLIT

or RETRY responses.

Can a slave use both SPLIT and RETRY responses?

Normally a slave will not use both the SPLIT and RETRY responses. The SPLIT

response should be used by any slave that may be accessed by many different

masters at the same time. The RETRY response is intended to be used by

peripherals that are only accessed by one bus master.

Explain Lock Transfer in AHB ?

Answer

LOCK tells the arbiter to keep the current master granted, SPLIT tells the arbiter to grant another master, so the only possible action the arbiter can take for these contradictory requests is to grant the dummy master that must exist in any system with SPLIT capable slaves.

The dummy master will only perform IDLE transfers (i.e. no data transfers), so cannot corrupt the LOCKed sequence that is ongoing.

When the original slave is able to complete the SPLIT transfer, it will signal this to the arbiter on HSPLIT and the arbiter can then re-grant the original master, and the LOCKed sequence can then continue.

However as the slave has an HMASTLOCK input telling it that the current transfer is part of a LOCKed sequence, it should know that there is no system advantage in returning a SPLIT.

So yes, a slave can return a SPLIT response to a LOCKed transfer, and the arbiter must then grant the dummy master, but the slave should use the HMASTLOCK input to see that a SPLIT response is not useful at this time.

Explain Wrap Boundary Calculation in AHB ? WRAP4,WRAP8,WRAP16 ?

Answer

Wrap boundary depends on both Hsize and the No of beats(4 ,8,16)

"For wrapping bursts, if the start address of the transfer is not aligned to the total number of bytes in the burst (size x beats) then the address of the transfers in the burst will wrap when the boundary is reached"

Case1: Start Address is 0x4,Wrap4,Hsize is 2.

0000 0100 - beat1 - 0x4

0000 1000 - beat2 - 0x8

0000 1100 - beat3 - 0xc

0000 0000 - beat4 - 0x0

Here as Hsize is 2,it means 4 bytes are to be transfered. As it is Wrap4 no of beats are 4. Total no of bytes is 16(beats*Hsize in bytes). Therefore 4bit alignment is to be done.

In beat3 the address is 0000 1100.Now as Hsize is 2,address shld be incremented by 4.

0000 1100

+0000 0100

---------------

0001 0000 ( it is crossing the address boundary(4 bits) )

So we are aligning it to 0000 0000.-beat4

Case2: Start Address is 0x4,Wrap4,Hsize is 1.

0000 0100 - beat1 - 0x4

0000 0110 - beat2 - 0x6

0000 0000 - beat3 - 0x0

0000 0010 - beat4 - 0x2

Here as Hsize is 1,it means 2bytes are to be transfered. As it is Wrap4 no of beats are 4. Total no of bytes is 8(beats*Hsize in bytes).

Therefore 3 bit alignment is to be done. In beat2 the address is 0000 0110. Now as Hsize is 1,address shlould be incremented by 2.

0000 0110

+0000 0010

--------------

0000 1000 ( it is crossing the address boundary(3 bits).)

So we are aligning it to 0000 0000.-beat3

Case3: Start Address is 0x4,Wrap8,Hsize is 1.

0000 0100 - beat1 - 0x4

0000 0110 - beat2 - 0x6

0000 1000 - beat3 - 0x8

0000 1010 - beat4 - 0xa

0000 1100 - beat5 - 0xc

0000 1110 - beat6 - 0xe

0000 0000 - beat7 - 0x0

0000 0010 - beat8 - 0x2

Here as Hsize is 1,it means 2 bytes are to be transfered.

As it is Wrap8 no of beats are 8.

Total no of bytes is 16 (beats*Hsize in bytes).

Therefore 4bit alignment is to be done.

In beat6 the address is 0000 1110.Now as Hsize is 1,address shld be incremented by 2.

0000 1110

+0000 0010

---------------

0001 0000 ( it is crossing the address boundary(4 bits)).

So we are aligning it to 0000 0000.-beat7

Another Wrap Boundry Calculation :

1) convert hex addr to decimal - 0x38 = 56 (dec)
2) as its a word transfer (4 bytes) and WRAP 4 so 4 x 4 = 16
3) 56 / 16 = 3.5
4) take the whole number from previous calculation as 3
5) now 3 x 16 = 48 ( dec )
6) your roll over addr is 48 (dec ) = 0x30 (hex) !!!

so the address goes as 38 - 3c - 30 and 34

Exaplain Wrap Beat Calulation in AHB ?

Answer

Following Tasks will Give Information About Wrap Boundary Beat Location Calculation

//-------------------------------------------------------

// wrap4_beat_info()

//-------------------------------------------------------

task wrap4_beat_info (logic [2:0] hburst,logic [31:0] haddr,logic [2:0] hsize);

if(hsize==3'b010 && hburst==`AHB_WRAP4 )

begin

if(haddr[3:2]==2'b00) wrap4_boundry_location=0 ; // No Wrap

else if(haddr[3:2]==2'b01) wrap4_boundry_location=3 ; // Wrap at 3rd Beat

else if(haddr[3:2]==2'b10) wrap4_boundry_location=2 ; // Wrap at 2nd Beat

else if(haddr[3:2]==2'b11) wrap4_boundry_location=1 ; // Wrap at 1st Beat

end

endtask : wrap4_at_info

//--------------------------------------------------------

// wrap8_beat_info()

//--------------------------------------------------------

task wrap8_beat_info (logic[2:0] hburst,logic[31:0] haddr,logic[2:0] hsize);

if(hsize==3'b010 && hburst==`AHB_WRAP8 )

begin

if(haddr[5:3]==3'b000) wrap8_boundry_location=0 ;

else if(haddr[5:3]==3'b001) wrap8_boundry_location=7 ;

else if(haddr[5:3]==3'b010) wrap8_boundry_location=6 ;

else if(haddr[5:3]==3'b011) wrap8_boundry_location=5 ;

else if(haddr[5:3]==3'b100) wrap8_boundry_location=4 ;

else if(haddr[5:3]==3'b101) wrap8_boundry_location=3 ;

else if(haddr[5:3]==3'b110) wrap8_boundry_location=2 ;

else if(haddr[5:3]==3'b110) wrap8_boundry_location=1 ;

end

endtask : wrap8_beat_info

//---------------------------------------------------------

// wrap16_at_info()

//---------------------------------------------------------

task wrap16_beat_info (logic[2:0] hburst, logic[31:0] haddr,logic[2:0] hsize);

if(hsize==3'b010 && hburst==`AHB_WRAP16 )

begin

if(haddr[7:4]==4'b0000) wrap8_boundry_location=0 ;

else if(haddr[7:4]==4'b0001) wrap8_boundry_location=15 ;

else if(haddr[7:4]==4'b0010) wrap8_boundry_location=14 ;

else if(haddr[7:4]==4'b0011) wrap8_boundry_location=13 ;

else if(haddr[7:4]==4'b0100) wrap8_boundry_location=12 ;

else if(haddr[7:4]==4'b0101) wrap8_boundry_location=11 ;

else if(haddr[7:4]==4'b0110) wrap8_boundry_location=10 ;

else if(haddr[7:4]==4'b0111) wrap8_boundry_location=9 ;

else if(haddr[7:4]==4'b1000) wrap8_boundry_location=8 ;

else if(haddr[7:4]==4'b1001) wrap8_boundry_location=7 ;

else if(haddr[7:4]==4'b1010) wrap8_boundry_location=6 ;

else if(haddr[7:4]==4'b1011) wrap8_boundry_location=5 ;

else if(haddr[7:4]==4'b1100) wrap8_boundry_location=4 ;

else if(haddr[7:4]==4'b1101) wrap8_boundry_location=3 ;

else if(haddr[7:4]==4'b1110) wrap8_boundry_location=2 ;

else if(haddr[7:4]==4'b1111) wrap8_boundry_location=1 ;

end

endtask : wrap16_beat_info

TKTCL

2013-02-15T21:13:00.002-08:00

Comming soon

DIVIDE BY 3 COUNTER

2011-07-14T11:53:00.000-07:00

module div_by_3(clk,reset,clk_3);
input    clk      ;
input    reset    ;
output   clk_3    ;

wire       Da     ;
reg        Qa     ;
reg        Qb     ;
reg        Qc     ;

  assign Da   =~Qa && ~Qb  ;
  assign clk_3= Qb ||  Qc  ;

  always@(posedge clk or negedge reset ) begin
    if(~reset)begin
     Qa<=1'b0 ;
    end
    else begin
     Qa<=Da   ;
    end
  end

  always@(posedge clk or negedge reset ) begin
    if(~reset)begin
     Qb<=1'b0 ;
    end
    else begin
     Qb<=Qa   ;
    end
  end
  
  always@(negedge clk or negedge reset ) begin
    if(~reset)begin
     Qc<=1'b0 ;
    end
     else begin
     Qc<=Qb   ;
    end
  end
endmodule

Setup and Hold Time

2011-07-04T09:43:00.000-07:00

Following the Analogy for Explaining Setup and Holdtime :-

If the train leaves at 8:00 and you live 20 minutes away from the station, when should you leave your house?

At 7:40 (“setup time” is 20 minutes) If you leave after 7:40, you will miss the train. If you leave before 7:40, you should have enough time to get to the station before it leaves. Your friend needs help boarding the train and the train allows only 5 minutes for boarding.

How long should you stay after you have arrived?
At least five minutes (“hold time” is 5 minutes) or 8:05 at the earliest. Without your help for the full 5 minutes, your friend is not able to board and will miss the train.

AHB FAQ

2011-06-29T11:09:00.000-07:00

Must a read after a write to the same address return the newly written data? See

Write Data Interleaving in AXI

2009-12-01T03:17:00.000-08:00

Write data interleave happen when two AXI bus masters generate sequence of write data to the same slave, but the write data doesn't arrive every clock cycle. In this case, instead of waiting for one sequence to complete before the other sequence start, the AXI infrastructure can interleave the write data sequences together to avoid wasting idle cycles on the bus.

Diffrence between AXI and AHB Bus

2009-12-01T03:02:00.001-08:00

AXI, the third generation of AMBA interface defined in the AMBA 3 specification, is targeted at high performance, high clock frequency system designs and includes features which make it very suitable for high speed sub-micron interconnect:
Seprate Channels for Read Data,Read Address,Write Data,Write Address and Write Response Channel.In Burst Transfer Only Start Address is issued .support for unaligned data transfers using byte strobes,issuing of multiple outstanding addresses . Easy addition of Register Slice to provide timing close .

While AHB is single clock edge protocol . First should be Address phase and then data phase should come .It supportSplit and Retry Commands , there can be Serveral Bus Masters .It also support Busrt Transfer however bus requere all the address on address lines .

Out of Order in AXI

2009-12-01T02:56:00.000-08:00

In AXI, a transfer is not completed until the bus master receive the response from the read data channel or write response channel. Also after a bus master issue a transfer, it can issue another transfer without waiting for the first one to complete. If the order of the responses coming back from the slaves arrived in different order from the order that the transfers were issued, we can call it out of order completion.

Functional Coverage

2009-11-30T03:24:00.001-08:00

Functional Coverage From its name it checks the Functionality of your Design unit. PSL & SV are used for Functional Coverage , They provide Assertions and Covergroups for that.

Scenario's for SPLIT and RETRY

2009-10-06T23:36:00.000-07:00

In AMBA 2.0 Slave will issue SPLIT and RETRY Response on HRESP Output in following Scenario :

When the command or data Buffer is full or filled enough, and slave will analyse it will take more cycle to finish then slave has to Stop the master , so slave will issue SPLIT or RETRY Command .
SPLIT and RETRY Can be issued as per System Architecture.

If you have any question regarding then please contact me on shobhitkapoor@gmail.com

String tasks in verilog

2009-10-06T23:04:00.000-07:00

Note : If you are planning to use these Tasks with SystemVerilog then Please change byte to byte1 & char to char1 because both are keywords in system verilog .

Calculate the length(length) of string(str) in verilog .

Usage : strlen(str, length);
[sourcecode language='python']
// get the number of char in the string
task strlen;
input [1024*8-1:0] str;
output [10:0] length;
reg [7:0] byte;
reg yes;
reg [10:0] i;
begin
length = 0;
i = 0;
get_byte(str, i, byte);
ischar(byte, yes);
while(yes&&(i<1024)) i =" i" length =" i;" style="font-weight:bold;">Calculate the length(length) of string(str) in verilog .
[/sourcecode]

Usage : strclr(str);

// clear string
task strclr;
output [1024*8-1:0] str;
reg [10:0] i;
begin
for(i = 0; i<1024; i =" i" style="font-weight:bold;">Copy the first numbers(length) of input string(str_in) to output string(str_out) in verilog.

Usage : strcpy(str_out, str_in, length);

// copy part of input string to output string
task strcpy;
output [1024*8-1:0] str_out;
input [1024*8-1:0] str_in;
input [9:0] length;
reg [10:0] str_length;
reg [10:0] i;
reg [7:0] byte;
reg [10:0] diff;
begin
strclr(str_out);
strlen(str_in, str_length);

if(length > str_length)
diff = 0;
else
diff = str_length - length;

for(i = str_length; i > diff; i = i - 1)
begin
get_byte(str_in, i-1, byte);
put_byte(str_out, i-1-diff, byte);
end
end
endtask

Cascade two input strings(str_1, str_2) to one output string(str_out)in verilog

Usage : strcat2(str_out, str_1, str_2);

// cascade two strings
task strcat2;
output [1024*8-1:0] str_out;
input [1024*8-1:0] str_1;
input [1024*8-1:0] str_2;
reg [10:0] str_1_length;
reg [10:0] str_2_length;
reg [10:0] str_3_length;
reg [10:0] length;
reg [9:0] index;
reg [7:0] byte;
begin
strclr(str_out);
strlen(str_1, str_1_length);
strlen(str_2, str_2_length);
str_3_length = str_1_length + str_2_length;
if( str_3_length > 1024 )
begin
$display("The length of cascade string is larger than 1024");
$display("%s", str_1);
$display("%s", str_2);
end
else
begin
for(length = str_1_length; length > 0; length = length -1)
begin
index = length - 1;
get_byte(str_1, index, byte);
put_byte(str_out, index+str_2_length, byte);
end
for(length = str_2_length; length > 0; length = length -1)
begin
index = length - 1;
get_byte(str_2, index, byte);
put_byte(str_out, index, byte);
end
end
end
endtask

cascade three input strings(str_1, str_2, str_3) to one output string(str_out)in verilog

Usage : strcat2(str_out, str_1, str_2, str_3 );

//Author : Jarod, jarod@benz.ee.nthu.edu.tw

Delete a file of certain date in Unix

2009-07-23T05:15:00.000-07:00

Following is the Simplest method of Deleting a file of particular date/month , just three lines of code will delete all the files of particular month (date )

#!/bin/sh
ls -ltr | grep '10 May' | awk -F '(print$10)' > tmp
xarg rm 
rm -f tmp

User can change a date or month according to his/her need for any comment/errors please contact me on shobhitkapoor@gmail.com

PERL ONE LINERS

2009-06-11T23:03:00.000-07:00

Just enough perl to do most everything! Tom Christianson (spelling?)
once posted a canonical list of one line perl programs to do many common
command-line tasks.
It included:
# run contents of "my_file" as a program
perl my_file

# run debugger "stand-alone"
perl -d -e 42

# run program, but with warnings
perl -w my_file

# run program under debugger
perl -d my_file

# just check syntax, with warnings
perl -wc my_file

# useful at end of "find foo -print"
perl -nle unlink

# simplest one-liner program
perl -e 'print "hello world!\n"'

# add first and penultimate columns
perl -lane 'print $F[0] + $F[-2]'

# just lines 15 to 17
perl -ne 'print if 15 .. 17' *.pod

# in-place edit of *.c files changing all foo to bar
perl -p -i.bak -e 's/\bfoo\b/bar/g' *.c

# command-line that prints the first 50 lines (cheaply)
perl -pe 'exit if $. > 50' f1 f2 f3 ...

# delete first 10 lines
perl -i.old -ne 'print unless 1 .. 10' foo.txt

# change all the isolated oldvar occurrences to newvar
perl -i.old -pe 's{\boldvar\b}{newvar}g' *.[chy]

# command-line that reverses the whole file by lines
perl -e 'print reverse <>' file1 file2 file3 ....

# find palindromes
perl -lne 'print if $_ eq reverse' /usr/dict/words

# command-line that reverse all the bytes in a file
perl -0777e 'print scalar reverse <>' f1 f2 f3 ...

# command-line that reverses the whole file by paragraphs
perl -00 -e 'print reverse <>' file1 file2 file3 ....

# increment all numbers found in these files
perl i.tiny -pe 's/(\d+)/ 1 + $1 /ge' file1 file2 ....

# command-line that shows each line with its characters backwards
perl -nle 'print scalar reverse $_' file1 file2 file3 ....

# delete all but lines beween START and END
perl -i.old -ne 'print unless /^START$/ .. /^END$/' foo.txt

# binary edit (careful!)
perl -i.bak -pe 's/Mozilla/Slopoke/g' /usr/local/bin/netscape

# look for dup words
perl -0777 -ne 'print "$.: doubled $_\n" while /\b(\w+)\b\s+\b\1\b/gi'
# command-line that prints the last 50 lines (expensively)
perl -e 'lines = <>; print @@lines[ $#lines .. $#lines-50' f1 f2 f3 ...

AWK One Liners

2009-06-11T22:56:00.000-07:00

FILE SPACING:

 # double space a file

 awk '1;{print ""}'

 awk 'BEGIN{ORS="\n\n"};1'

 # double space a file which already has blank lines in it. Output file

 # should contain no more than one blank line between lines of text.

 # NOTE: On Unix systems, DOS lines which have only CRLF (\r\n) are

 # often treated as non-blank, and thus 'NF' alone will return TRUE.

 awk 'NF{print $0 "\n"}'

 # triple space a file

 awk '1;{print "\n"}'

NUMBERING AND CALCULATIONS:

 # precede each line by its line number FOR THAT FILE (left alignment).

 # Using a tab (\t) instead of space will preserve margins.

 awk '{print FNR "\t" $0}' files*

 # precede each line by its line number FOR ALL FILES TOGETHER, with tab.

 awk '{print NR "\t" $0}' files*

 # number each line of a file (number on left, right-aligned)

 # Double the percent signs if typing from the DOS command prompt.

 awk '{printf("%5d : %s\n", NR,$0)}' 

 # number each line of file, but only print numbers if line is not blank

 # Remember caveats about Unix treatment of \r (mentioned above)

 awk 'NF{$0=++a " :" $0};1'

 awk '{print (NF? ++a " :" :"") $0}'

 # count lines (emulates "wc -l")

 awk 'END{print NR}'

 # print the sums of the fields of every line

 awk '{s=0; for (i=1; i<=NF; i++) s=s+$i; print s}'

 # add all fields in all lines and print the sum

 awk '{for (i=1; i<=NF; i++) s=s+$i}; END{print s}'

 # print every line after replacing each field with its absolute value

 awk '{for (i=1; i<=NF; i++) if ($i < i =" -$i;">

 awk '{for (i=1; i<=NF; i++) $i = ($i <>

 # print the total number of fields ("words") in all lines

 awk '{ total = total + NF }; END {print total}' file

 # print the total number of lines that contain "Beth"

 awk '/Beth/{n++}; END {print n+0}' file

 # print the largest first field and the line that contains it

 # Intended for finding the longest string in field #1

 awk '$1 > max {max=$1; maxline=$0}; END{ print max, maxline}'

 # print the number of fields in each line, followed by the line

 awk '{ print NF ":" $0 } '

 # print the last field of each line

 awk '{ print $NF }'

 # print the last field of the last line

 awk '{ field = $NF }; END{ print field }'

 # print every line with more than 4 fields

 awk 'NF > 4'

 # print every line where the value of the last field is > 4

 awk '$NF > 4'

STRING CREATION:

 # create a string of a specific length (e.g., generate 513 spaces)

 awk 'BEGIN{while (a++<513 s="s">

 # insert a string of specific length at a certain character position

 # Example: insert 49 spaces after column #6 of each input line.

 gawk --re-interval 'BEGIN{while(a++<49 s="s">


ARRAY CREATION:

 # These next 2 entries are not one-line scripts, but the technique

 # is so handy that it merits inclusion here.

 # create an array named "month", indexed by numbers, so that month[1]

 # is 'Jan', month[2] is 'Feb', month[3] is 'Mar' and so on.

 split("Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Dec", month, " ")

 # create an array named "mdigit", indexed by strings, so that

 # mdigit["Jan"] is 1, mdigit["Feb"] is 2, etc. Requires "month" array

 for (i=1; i<=12; i++) mdigit[month[i]] = i


TEXT CONVERSION AND SUBSTITUTION:

 # IN UNIX ENVIRONMENT: convert DOS newlines (CR/LF) to Unix format

 awk '{sub(/\r$/,"")};1'   # assumes EACH line ends with Ctrl-M

 # IN UNIX ENVIRONMENT: convert Unix newlines (LF) to DOS format

 awk '{sub(/$/,"\r")};1'

 # IN DOS ENVIRONMENT: convert Unix newlines (LF) to DOS format

 awk 1

 # IN DOS ENVIRONMENT: convert DOS newlines (CR/LF) to Unix format

 # Cannot be done with DOS versions of awk, other than gawk:

 gawk -v BINMODE="w" '1' infile >outfile

 # Use "tr" instead.

 tr -d \r outfile            # GNU tr version 1.22 or higher

 # delete leading whitespace (spaces, tabs) from front of each line

 # aligns all text flush left

 awk '{sub(/^[ \t]+/, "")};1'

 # delete trailing whitespace (spaces, tabs) from end of each line

 awk '{sub(/[ \t]+$/, "")};1'

 # delete BOTH leading and trailing whitespace from each line

 awk '{gsub(/^[ \t]+|[ \t]+$/,"")};1'

 awk '{$1=$1};1'           # also removes extra space between fields

 # insert 5 blank spaces at beginning of each line (make page offset)

 awk '{sub(/^/, "     ")};1'

 # align all text flush right on a 79-column width

 awk '{printf "%79s\n", $0}' file*

 # center all text on a 79-character width

 awk '{l=length();s=int((79-l)/2); printf "%"(s+l)"s\n",$0}' file*

 # substitute (find and replace) "foo" with "bar" on each line

 awk '{sub(/foo/,"bar")}; 1'           # replace only 1st instance

 gawk '{$0=gensub(/foo/,"bar",4)}; 1'  # replace only 4th instance

 awk '{gsub(/foo/,"bar")}; 1'          # replace ALL instances in a line

 # substitute "foo" with "bar" ONLY for lines which contain "baz"

 awk '/baz/{gsub(/foo/, "bar")}; 1'

 # substitute "foo" with "bar" EXCEPT for lines which contain "baz"

 awk '!/baz/{gsub(/foo/, "bar")}; 1'

 # change "scarlet" or "ruby" or "puce" to "red"
 awk '{gsub(/scarlet|ruby|puce/, "red")}; 1'

 # reverse order of lines (emulates "tac")
 awk '{a[i++]=$0} END {for (j=i-1; j>=0;) print a[j--] }' file*

 # if a line ends with a backslash, append the next line to it (fails if
 # there are multiple lines ending with backslash...)
 awk '/\\$/ {sub(/\\$/,""); getline t; print $0 t; next}; 1' file*

 # print and sort the login names of all users
 awk -F ":" '{print $1 | "sort" }' /etc/passwd

 # print the first 2 fields, in opposite order, of every line
 awk '{print $2, $1}' file

 # switch the first 2 fields of every line
 awk '{temp = $1; $1 = $2; $2 = temp}' file

 # print every line, deleting the second field of that line
 awk '{ $2 = ""; print }'

 # print in reverse order the fields of every line
 awk '{for (i=NF; i>0; i--) printf("%s ",$i);print ""}' file

 # concatenate every 5 lines of input, using a comma separator
 # between fields
 awk 'ORS=NR%5?",":"\n"' file

SELECTIVE PRINTING OF CERTAIN LINES:
 # print first 10 lines of file (emulates behavior of "head")
 awk 'NR <>

 # print first line of file (emulates "head -1")
 awk 'NR>1{exit};1'

 # print the last 2 lines of a file (emulates "tail -2")
 awk '{y=x "\n" $0; x=$0};END{print y}'

 # print the last line of a file (emulates "tail -1")
 awk 'END{print}'

 # print only lines which match regular expression (emulates "grep")
 awk '/regex/'
 # print only lines which do NOT match regex (emulates "grep -v")
 awk '!/regex/'

 # print any line where field #5 is equal to "abc123"
 awk '$5 == "abc123"'

 # print only those lines where field #5 is NOT equal to "abc123"
 # This will also print lines which have less than 5 fields.
 awk '$5 != "abc123"'
 awk '!($5 == "abc123")'

 # matching a field against a regular expression
 awk '$7  ~ /^[a-f]/'    # print line if field #7 matches regex
 awk '$7 !~ /^[a-f]/'    # print line if field #7 does NOT match regex

 # print the line immediately before a regex, but not the line
 # containing the regex
 awk '/regex/{print x};{x=$0}'
 awk '/regex/{print (NR==1 ? "match on line 1" : x)};{x=$0}'

 # print the line immediately after a regex, but not the line
 # containing the regex
 awk '/regex/{getline;print}'
 # grep for AAA and BBB and CCC (in any order on the same line)
 awk '/AAA/ && /BBB/ && /CCC/'
 # grep for AAA and BBB and CCC (in that order)
 awk '/AAA.*BBB.*CCC/'

 # print only lines of 65 characters or longer
 awk 'length > 64'

 # print only lines of less than 65 characters
 awk 'length <>

 # print section of file from regular expression to end of file
 awk '/regex/,0'
 awk '/regex/,EOF'

 # print section of file based on line numbers (lines 8-12, inclusive)
 awk 'NR==8,NR==12'

 # print line number 52
 awk 'NR==52'
 awk 'NR==52 {print;exit}'          # more efficient on large files

 # print section of file between two regular expressions (inclusive)
 awk '/Iowa/,/Montana/'             # case sensitive

SELECTIVE DELETION OF CERTAIN LINES:
 # delete ALL blank lines from a file (same as "grep '.' ")
 awk NF
 awk '/./'

 # remove duplicate, consecutive lines (emulates "uniq")
 awk 'a !~ $0; {a=$0}'

 # remove duplicate, nonconsecutive lines
 awk '!a[$0]++'                     # most concise script
 awk '!($0 in a){a[$0];print}'      # most efficient script

Learn VHDL in One Day

2009-06-11T22:55:00.000-07:00

Learn VHDL in One Day is simple tutorial for quick Learning of VHDL

Comming Soon

SystemVerilog in One Day

2009-06-11T22:54:00.000-07:00

This is Simple tutorial of learning SystemVerilog in one Day

Comming soon...

Learn Verilog in One Day

2009-06-11T22:52:00.000-07:00

This is very simple and Easy Tutorial for Verilog Learn , With the help of this tutorial anyone can understand basics of verilog .

Comming Soon ....

Learn C in One Day

2009-06-11T22:49:00.000-07:00

Usally this website is Only for Chip Designers , And Mostly all the Chip Designers are not good in C Language , But If you Really have to learn C in a nutshell then this is very simple Tutorial .

Coming Soon...

Create a table of contents in Microsoft Word

2009-05-11T23:54:00.000-07:00

The easiest way to create a table of contents is to use the built-in outline-level (outline level: Paragraph formatting you can use to assign a hierarchical level (Level 1 through Level 9) to paragraphs in your document. For example, after you assign outline levels, you can work with the document in outline view or in the Document Map.) formats or heading styles (heading style: Formatting applied to a heading. Microsoft Word has nine different built-in styles: Heading 1 through Heading 9.). If you are already using outline-level formats or built-in heading styles, follow these steps:

1. Click where you want to insert the table of contents.
2. On the Insert menu, point to Reference, and click Index and Tables.
3. Click the Table of Contents tab.
4. To use one of the available designs, click a design in the Formats box.
5. Select any other table of contents options you want.

ARM AMBA 2.0 AHB Split and Retry

2008-06-26T04:04:00.001-07:00

What is the diffrence between split and retry ?

Both the Split and Retry responses are used by slaves which require a large number of cycles to complete a transfer. These responses allow a data phase transfer to appear completed to avoid stalling the bus, but at the same time indicate that the transfer should be re-attempted when the master is next granted the bus.

The difference between them is that a SPLIT response tells the Arbiter to give priority to all other masters until the SPLIT transfer can be completed (effectively ignoring all further requests from this master until the SPLIT slave indicates it can complete the SPLIT transfer), whereas the RETRY response only tells the Arbiter to give priority to higher priority masters.

A SPLIT response is more complicated to implement than a RETRY, but has the advantage that it allows the maximum efficiency to be made of the bus bandwidth.

The master behaviour is identical to both SPLIT and RETRY responses, the master has to cancel the next access and re-attempt the current failed access.

Do all slaves have to support the SPLIT and RETRY responses ?

No. A slave is only required to support the response types that it needs to use. For example, a simple on-chip memory block which can respond to all transfers in just a few wait states does not need to use either the SPLIT or RETRY responses.

Do all masters have to support SPLIT and RETRY ?

Yes. All masters must support SPLIT and RETRY responses to ensure they are compatible with any bus slave. A master will handle both SPLIT and RETRY responses in an identical manner.

Note that if the system is based on AHB-Lite, SPLIT and RETRY responses are not supported. AHB-lite is a single master solution, so SPLIT and RETRY responses would have no meaning.

Can a SPLIT or RETRY response be given at any point during a burst ?

Yes. A SPLIT, RETRY or ERROR response can be given by a slave to any transfer during a burst. The slave is not restricted to only giving these responses to the first transfer.

Can a slave assert HSPLITx in the same cycle that it gives a SPLIT response ?

No. The specification requires that HSPLITx can only be asserted after the slave has given a SPLIT response.

Address: 0x3F0 0x3F4 0x3F8 0x3FC 0x400 0x404 0x408
Transfer: NSEQ SEQ SEQ SEQ NSEQ SEQ SEQ

Can a slave use both SPLIT and RETRY responses ?

Normally a slave will not use both the SPLIT and RETRY responses. The SPLIT response should be used by any slave that may be accessed by many different masters at the same time. The RETRY response is intended to be used by peripherals that are only accessed by one bus master.

What address should be on the bus during the IDLE cycle after a SPLIT or RETRY ?

It does not matter what address is driven onto the bus during this cycle. The slave selected by the driven address should not take any action and must respond with a zero wait state OKAY response.

In many cases it will be simpler for the master to leave the address unaltered during this cycle, so that it remains at the address of the next transfer that the master wishes to perform and only in the following cycle does the master return the address to that of the transfer that must be repeated because of the SPLIT or RETRY response.

In some designs it may be possible for the master to return the address to that required to repeat the previous transfer during the IDLE cycle and this behaviour is also perfectly acceptable.

What value should be used for HTRANS when an AHB master gets a RETRY response from a slave in the middle of burst ?

Whenever a transfer is restarted it must use HTRANS set to NONSEQ and it may also be necessary to adjust the HBURST information (usually just to indicate INCR).

Will a master always lose the bus after a SPLIT response ?

Yes. A slave must not assert the relevant bit of the HSPLIT bus in the same cycle that it gives the SPLIT response and therefore the master will always lose the bus.

Multiply and Divide Tricks

2008-06-25T22:01:00.002-07:00

// Binary Multiplication Algorithm
// Simple Multiplication Hardware
// Streamlined Multiplication Hardware
// Booth Recoding for Higher-Radix and Signed Multiplication
// Binary Division Algorithm
// Division Hardware (Simple and Streamlined)
// "Real" Arithmetic Circuits
/// References
/// Binary Multiplication Algorithm
// :PH: 4.6
/// Long Hand Procedure Review
//
// Multiply 5 times 12 in binary:
//
// 0101 Multiplicand
// 1100 Multiplier
// """"
// 0000
// 0000
// 0101
// 0101
// """""""
// 0111100 Product
////////////////////////////////////////////////////////////////////////////////
/// Simple Multiplication Hardware
// :PH: 4.6
/// Simple Multipliers
//
// Designed to show basic techniques, but are inefficient.
// Following sections show improved multipliers.
/// Multipliers in this section:
//
// Simple Unsigned Combinational Multiplier
// See :PH: Figure 4.25
// Multiplies using combinational logic only.
// Cost of n-bit multiplier: proportional to n^2.
// Speed of n-bit multiplier: time needed for n additions:
// Proportional to n.
//
// Simple Unsigned Multiplier
// Unlike combinational multiplier, uses a clock.
// Cost of n-bit multiplier:
// Proportional to n.
// Includes 5n bits of register storage.
// Speed of n-bit multiplier:
// Product in n clocks.
// Clock period includes 2n-bit add.
// Uses more hardware than streamlined multipliers in next section.
// :Example:
//
// Simple Unsigned Combinational Multiplier
// Based on :PH: Figure 4.25
//
// This is a straightforward coding of the longhand multiplication
// technique.
module simple_combinational_mult(product,multiplier,multiplicand); //P
input [15:0] multiplier, multiplicand;
output product;
reg [31:0] product;
integer i;
always @( multiplier or multiplicand )
begin

product = 0;

for(i=0; i<16; i=i+1)
if( multiplier[i] == 1'b1 ) product = product + ( multiplicand << i );

end

endmodule
// :Example:
//
// Simple Unsigned Multiplier
//
// Sequential multiplier. Handshaking signals are added to command
// multiplier to start and to indicate when finished. Registers are
// provided for shifted versions of the multiplier and multiplicand.
module simple_mult(product,ready,multiplier,multiplicand,start,clk); //P
input [15:0] multiplier, multiplicand;
input start, clk;
output product;
output ready;
reg [31:0] product;
reg [15:0] multiplier_copy;
reg [31:0] multiplicand_copy;

reg [4:0] bit;
wire ready = !bit;

initial bit = 0;
always @( posedge clk )
if( ready && start ) begin
bit = 16;
product = 0;
multiplicand_copy = { 16'd0, multiplicand };
multiplier_copy = multiplier;

end else if( bit ) begin
if( multiplier_copy[0] == 1'b1 ) product = product + multiplicand_copy;
multiplier_copy = multiplier_copy >> 1;
multiplicand_copy = multiplicand_copy << 1;
bit = bit - 1;
end
endmodule
////////////////////////////////////////////////////////////////////////////////
/// Streamlined Multiplication Hardware
// :PH: 4.6
/// Streamlined Multipliers
//
// Uses less hardware than simple multiplier.
// Much slower than "real" multipliers.
/// Multipliers in this section:
//
// Streamlined Unsigned Multiplier
// See :PH: Figure 4.31
// Less register storage than simple multiplier.
// Cost of n-bit multiplier:
// Proportional to n.
// Includes 2n bits of register storage.
// Speed of n-bit multiplier: (Same as simple.)
// Product in n clocks.
// Clock period includes a 2n-bit add.
//
// Streamlined Signed Multiplier
// Like previous multiplier, but handles signed numbers.
// A better signed multiplier covered later (using Booth recoding).
// Cost of n-bit multiplier:
// Proportional to n.
// Includes 3n bits of register storage.
// Speed of n-bit multiplier:
// Product in n clocks.
// Clock period includes 2n-bit add.
// :Example:
//
// Streamlined Unsigned Multiplier
// Based on :PH: Figure 4.31
//
// Improvements:
//
// The product register also holds the multiplier.
// Only the product register is shifted.
// A register is not needed to hold the multiplicand.
// Wow, you save 2n bits! (To multiply n-bit numbers.)
module streamlined_mult(product,ready,multiplier,multiplicand,start,clk);
input [15:0] multiplier, multiplicand;
input start, clk;
output product;
output ready;
reg [31:0] product;
reg [4:0] bit;
wire ready = !bit;

initial bit = 0;
always @( posedge clk )
if( ready && start ) begin
bit = 16;
product = { 16'd0, multiplier };

end else if( bit ) begin:A

reg lsb;
lsb = product[0];
product = product >> 1;
bit = bit - 1;
if( lsb ) product[31:15] = product[30:15] + multiplicand;
end
endmodule
// :Example:
//
// Streamlined Signed Multiplier
//
// Multiplies absolute value of multiplier and multiplicand.
// Negates product if multiplier and multiplicand differ in sign.
// Otherwise similar to streamlined unsigned multiplier.
module streamlined_signed_mult(product,ready,multiplier,multiplicand,
start,clk);
input [15:0] multiplier, multiplicand;
input start, clk;
output product;
output ready;
reg [31:0] product;
reg [15:0] abs_multiplicand;
reg [4:0] bit;
wire ready = !bit;

initial bit = 0;
always @( posedge clk )
if( ready && start ) begin
bit = 16;
product = { 16'd0, multiplier[15] ? -multiplier : multiplier };
abs_multiplicand = multiplicand[15] ? -multiplicand : multiplicand;

end else if( bit ) begin:A

reg lsb;
lsb = product[0];
product = product >> 1;
bit = bit - 1;
if( lsb ) product[31:15] = product[30:15] + abs_multiplicand;
if( !bit && multiplicand[15] ^ multiplier[15] ) product = -product;
end
endmodule
////////////////////////////////////////////////////////////////////////////////
/// Booth Recoding for Higher-Radix and Signed Multiplication
// :PH: 4.6 Only describes Radix-2 Booth Recoding
/// Basic Idea
//
// Rather than repeatedly adding either 0 or 1 times multiplicand,
// repeatedly add 0, 1, -1, 2, -2, etc. times the multiplicand.
//
/// Benefits
//
// Performs signed multiplication without having to first compute the
// absolute value of the multiplier and multiplicand.
//
// Improved performance (when radix higher than 2).
/// Multipliers Described Here
//
// Ordinary Radix-4 Unsigned Multiplier
// Presented for pedagogical reasons, Booth multipliers better.
// Twice as fast as earlier multipliers.
// Uses more hardware than Booth multipliers below.
//
// Booth Recoding Radix-4 Multiplier
// Multiplies signed numbers.
// Twice as fast as earlier multipliers.
//
// Booth Recoding Radix-2 Multiplier
// Multiplies signed numbers.
// Uses about the same amount of hardware than earlier signed multiplier.
/// Ordinary Radix-4 Multiplier Idea
//
// Review of Radix-2 Multiplication
//
// Multiply 5 times 12. Radix-2 multiplication (the usual way).
//
// 0101 Multiplicand
// 1100 Multiplier
// """"
// 0000 0 x 0101
// 0000 0 x 0101
// 0101 1 x 0101
// 0101 1 x 0101
// """""""
// 0111100 Product
//
// Radix-4 Multiplication
// Let "a" denote the multiplicand and b denote the multiplier.
// Pre-compute 2a and 3a.
// Examine multiplier two bits at a time (rather than one bit at a time).
// Based on the value of those bits add 0, a, 2a, or 3a (shifted by
// the appropriate amount).
//
// Uses n/2 additions to multiply two n-bit numbers.
//
// Two Radix-4 Multiplication Examples
//
// Multiply 5 times 12. Radix-4 multiplication (the faster way).
//
// Precompute: 2a: 01010, 3a: 01111
//
// 0101 Multiplicand
// 1100 Multiplier
// """"
// 00000 00 x 0101
// 01111 11 x 0101
// """""""
// 0111100 Product
//
// Multiply 5 times 9. Radix-4 multiplication (the faster way).
//
// 0101 Multiplicand
// 1001 Multiplier
// """"
// 00101 01 x 0101
// 01010 10 x 0101
// """""""
// 0101101 Product
// Ordinary Radix-2^d Multiplier
//
// This is a generalization of the Radix-4 multiplier.
//
// Let "a" denote the multiplicand and b denote the multiplier.
// Pre-compute 2a, 3a, 4a, 5a, ..., (2^d-1)a
// Examine multiplier d bits at a time.
// Let the value of those bits be v.
// Add v shifted by the appropriate amount.
//
// Uses n/d additions to multiply two n-bit numbers.
// :Example:
//
// A Radix-4 multiplier. Takes unsigned numbers.
module imult_ord_radix_4(prod,ready,multiplicand,multiplier,start,clk);
input [15:0] multiplicand, multiplier;
input start, clk;
output prod;
output ready;
reg [32:0] product;
wire [31:0] prod = product[31:0];
reg [4:0] bit;
wire ready = !bit;
reg [17:0] pp;

initial bit = 0;
wire [17:0] multiplicand_X_1 = {1'b0,multiplicand};
wire [17:0] multiplicand_X_2 = {multiplicand,1'b0};
wire [17:0] multiplicand_X_3 = multiplicand_X_2 + multiplicand_X_1;
always @( posedge clk )
if( ready && start ) begin
bit = 8;
product = { 16'd0, multiplier };

end else if( bit ) begin
case ( {product[1:0]} )
2'd0: pp = {2'b0, product[31:16] };
2'd1: pp = {2'b0, product[31:16] } + multiplicand_X_1;
2'd2: pp = {2'b0, product[31:16] } + multiplicand_X_2;
2'd3: pp = {2'b0, product[31:16] } + multiplicand_X_3;
endcase
product = { pp, product[15:2] };
bit = bit - 1;
end
endmodule
/// Booth Recoding
//
// Goal: Reduce the number of pre-computed multiples of the multiplicand.
// Bonus: Handles signed numbers.
//
// Idea: Use something like carries.
//
// Why It's Called Recoding
// Numbers like 3 are recoded into 4-1, avoiding the need to deal with 3.
//
// Consider need to compute multiplicand_X_3 for radix-4 multiplier.
// Instead:
// Subtract multiplicand and add 4 times multiplicand.
// The subtraction is done in the "current" step.
// The addition is done in the "next" step.
// Multiply 5 times 3. Booth radix-4 multiplication.
//
// 0101 Multiplicand
// 0011 Multiplier
// """""""
// 1111011 -1 x 0101 Multiplier bits 11 -> -1 + 4 -> -1 now, +1 next step
// 00101 (00+1) x 0101 Multiplier bits 00 -> 0 (now) + 1 (from last step)
// """""""
// 0001111 Product
// The table below indicates:
//
// MB: Multiplier bits value.
// C: Carry bit (lostbit in modules) from previous step.
// x: Amount to multiply multiplicand by.
// c: Carry bit to next step.
//
// Radix-4 Booth Table
//
// MB C x c
// """""""""""""""""
// 00 0 0 + 0 0
// 00 1 1 + 0 0
// 01 0 1 + 0 0
// 01 1 2 + 0 0
// 10 0 -2 + 4 1
// 10 1 -1 + 4 1
// 11 0 -1 + 4 1
// 11 1 0 + 4 1
//
// For example above:
// Step 1: MB -> 11, C -> 0, lookup reveals x -> -1, c -> 1
// Step 2: MB -> 00, C -> 1, lookup reveals x -> 1, c -> 0
//
// Radix-2 Booth Table
//
// MB C x c
// """""""""""""""""
// 0 0 0 + 0 0
// 0 1 1 + 0 0
// 1 0 -1 + 2 1
// 1 1 0 + 2 1
// Note:
// The carry out is the same as the MSB of the multiplier bits examined.
// That's intentional, so that no special storage or computation is need
// for the carry.
//
// The carry out of the last step is not used.
//
// Construction of higher-radix tables is straightforward.
// :Example:
//
// A Booth radix-4 multiplier. This takes signed numbers.
module imult_Booth_radix_4(prod,ready,multiplicand,multiplier,start,clk); // P
input [15:0] multiplicand, multiplier;
input start, clk;
output prod;
output ready;
reg [32:0] product;
wire [31:0] prod = product[31:0];
reg [4:0] bit;
wire ready = !bit;
reg lostbit;

initial bit = 0;
wire [16:0] multsx = {multiplicand[15],multiplicand};
always @( posedge clk )
if( ready && start ) begin
bit = 8;
product = { 17'd0, multiplier };
lostbit = 0;

end else if( bit ) begin:A
case ( {product[1:0],lostbit} )
3'b001: product[32:16] = product[32:16] + multsx;
3'b010: product[32:16] = product[32:16] + multsx;
3'b011: product[32:16] = product[32:16] + 2 * multiplicand;
3'b100: product[32:16] = product[32:16] - 2 * multiplicand;
3'b101: product[32:16] = product[32:16] - multsx;
3'b110: product[32:16] = product[32:16] - multsx;
endcase
lostbit = product[1];
product = { product[32], product[32], product[32:2] };
bit = bit - 1;
end
endmodule
// :Example:
//
// Radix-2 Booth multiplier. Unlike signed multiplier, does not
// require time or hardware for taking absolute value of operands.
module imult_Booth(product,ready,multiplicand,multiplier,start,clk); // P
input [15:0] multiplicand, multiplier;
input start, clk;
output product;
output ready;
reg [31:0] product;
reg [4:0] bit;
wire ready = !bit;
reg lostbit;

initial bit = 0;
always @( posedge clk )
if( ready && start ) begin
bit = 16;
product = { 16'd0, multiplier };
lostbit = 0;

end else if( bit ) begin:A
case ( {product[0],lostbit} )
2'b01: product[31:16] = product[31:16] + multiplicand;
2'b10: product[31:16] = product[31:16] - multiplicand;
endcase
lostbit = product[0];
product = { product[31], product[31:1] };
bit = bit - 1;
end
endmodule
////////////////////////////////////////////////////////////////////////////////
/// Binary Division Algorithm
// :PH: 4.7
// Binary Version of Longhand Division Technique
//
// 11 divided by 3:
//
// 11 (1011) is dividend.
// 3 (0011) is divider.
//
// """"""""
// 1011
// -0011
// """""""" 0 Difference is negative: copy dividend and put 0 in quotient.
// 1011
// -0011
// """""""" 00 Difference is negative: copy dividend and put 0 in quotient.
// 1011
// -0011
// """""""" 001 Difference is positive: use difference and put 1 in quotient.
// 0101
// -0011
// """""""" 0011 Difference is positive: use difference and put 1 in quotient.
// 10
//
// Quotient, 3 (0011); remainder 2 (10).
////////////////////////////////////////////////////////////////////////////////
/// Division Hardware (Simple and Streamlined)
// :PH: 4.7
/// Division Hardware
//
// Simple Divider
// See :PH: Figure 4.36
// A straightforward translation of binary division algorithm into hardware.
// Cost of n-bit divider:
// Proportional to n.
// Uses 5n bits of register storage.
// Speed of n-bit divider:
// Quotient in n clock cycles.
//
// Streamlined Divider
// See :PH: Figure 4.41
// Less storage needed.
// Cost of n-bit divider:
// Proportional to n.
// Uses 2n bits of register storage.
// Speed of n-bit divider:
// Quotient in n clock cycles.
// :Example:
//
// Simple divider.
// Based on :PH: Figure 4.36
module simple_divider(quotient,remainder,ready,dividend,divider,start,clk);

input [15:0] dividend,divider;
input start, clk;
output quotient,remainder;
output ready;
// """"""""
// 1011 <---- dividend_copy
// -0011 <---- divider_copy
// """""""" 0 Difference is negative: copy dividend and put 0 in quotient.
// 1011 <---- dividend_copy
// -0011 <---- divider_copy
// """""""" 00 Difference is negative: copy dividend and put 0 in quotient.
// 1011 <---- dividend_copy
// -0011 <---- divider_copy
// """""""" 001 Difference is positive: use difference and put 1 in quotient.
// quotient (numbers above)
reg [15:0] quotient;
reg [31:0] dividend_copy, divider_copy, diff;
wire [15:0] remainder = dividend_copy[15:0];
reg [4:0] bit;
wire ready = !bit;

initial bit = 0;
always @( posedge clk )
if( ready && start ) begin
bit = 16;
quotient = 0;
dividend_copy = {16'd0,dividend};
divider_copy = {1'b0,divider,15'd0};
end else begin
diff = dividend_copy - divider_copy;
quotient = quotient << 1;
if( !diff[31] ) begin
dividend_copy = diff;
quotient[0] = 1'd1;
end
divider_copy = divider_copy >> 1;
bit = bit - 1;
end
endmodule
// :Example:
//
// Streamlined divider.
// Based on :PH: Figure 4.41
//
// Uses less register storage than simple divider.
module streamlined_divider(quotient,remainder,ready,dividend,divider,start,clk);

input [15:0] dividend,divider;
input start, clk;
output quotient,remainder;
output ready;
reg [31:0] qr;
reg [16:0] diff;
//
// 0000 1011
// """"""""
// 1011 0001 0110 <- qr reg
// -0011 -0011 <- divider (never changes)
// """"""""
// 1011 0010 110o <- qr reg
// -0011 -0011
// """"""""
// 1011 0101 10oo <- qr reg
// -0011 -0011
// """""""" 0010 1000 <- qr reg before shift
// 0101 0101 0ooi <- after shift
// -0011 -0011
// """""""" 0010 ooii
// 10
//
// Quotient, 3 (0011); remainder 2 (10).

wire [15:0] remainder = qr[31:16];
wire [15:0] quotient = qr[15:0];
reg [4:0] bit;
wire ready = !bit;

initial bit = 0;
always @( posedge clk )
if( ready && start ) begin
bit = 16;
qr = {16'd0,dividend};
end else begin
diff = qr[31:15] - {1'b0,divider};
if( diff[16] )
qr = {qr[30:0],1'd0};
else
qr = {diff[15:0],qr[14:0],1'd1};

bit = bit - 1;
end
endmodule
////////////////////////////////////////////////////////////////////////////////
/// "Real" Arithmetic Circuits
// :HP: Appendix A
/// Adders
//
// Multiple-level CLA covered in class reasonably close to adders used
// in processors.
//
// Other fast adder techniques also used. (See :PH: problems.)
/// Multipliers
//
// The multiplication hardware presented above is much slower than
// the hardware used in real processors.
//
// "Real" n-bit Multiplier Features
//
// Multiplication done in one or two cycles (assume one cycle).
// Uses higher-radix (say 4) Booth recoding or something similar.
// Enough adders are provided so that product computed in one cycle.
// These adders can add n numbers quickly without the cost of n CLA's.
// Cost may be something like 3/2 n ripple adders plus 1 CLA.
// Delay through each adder is only a handful of gates.
// Adders may be connected as a tree, so that number of adders
// from input to output is proportional to log n (rather than n).
/// Dividers
//
// The division hardware presented above is slower than hardware used
// in real processors.
//
// Division trickier than multiplication because result of step i
// needed for i+1. This precludes the tree structures used in
// fast multipliers.
//
// FP Dividers in general-purpose processors typically take 10-20 cycles.
//
// Several division techniques used. Examples:
// SRT: Sweeney, Robertson, Tocher
// Newton Iteration
// Goldschmidt's Algorithm
x

Floating Point Arithmatic

2008-06-17T19:23:00.000-07:00

There are two possible methods that can be used for representing binary numbers in A computer. They are the fixed point and floating point systems. In practice, in a fixed Point system, binary numbers are expressed as fractions with the radix point positioned Immediately right of the sign digit.

For e.g. in a machine using 8-bit registers 1110.0 would be represented as

0.1110000 -1110 x 2 -4 by moving the radix point four places to the left. Unfortunately there are problems associated with fixed point arithmetic. that if the sum of two 8-bit numbers is > 127 or < -127 an additional bit is generated and an incorrect answer is obtained. Assuming 8-bit registers are being used in the machine, the range of the registers has been exceeded. The same problem exists for the multiplication and division operations.

If two 8-bit numbers are multiplied, one by the other, then in many cases a double- length product will be formed and this would require a 16-bit register. Similarly, for the division operations, a fractional quotient can only be formed if the divisor is greater than the dividend.

To overcome the range problems experienced with fixed point representation a floating point system can be used. Numbers in this system are expressed in the following form: n=m x 2e Where m, the mantissa, is the fractional representation of n and e is the exponent.

When performing a computation, a normalized form of the mantissa is used. Normalization is achieved by adjusting the exponent so that the mantissa has a 1 in its most significant digit position. When this condition is satisfied: 0.5 <= m <>

+1492.9187= +.14929187 x 10
+4 -.00034123 = -.34123000 x 10 -3

Which have been normalized an alternative way of expressing these numbers would be

+. 14929187 x 10
+4 =- +. 14929187e
+ 4 -.34123000 x 10
-3 = -.34123000e - 3

Assuming that the bias constant to be added to the exponent is 16 and that the exponent part of the numbers is positioned to the left of the fractional part, the two numbers would have the following form:

14929187 x 10+4 =-+20,
14929187 -.34123000 x 10
-3 =-13, 34123000

The addition of the constant 16 to the exponent expresses in two decimal digits any exponent between 10 +15 and 10 -16 and consequently increases the range of numbers the machine can handle.

define vs parameter

2008-06-17T09:40:00.000-07:00

there are two ways to define constants: the parameter, a constant that is local to a module and macro definitions, created using the `define compiler directive. A parameter, after it is declared, is referenced using the parameter name. A `define macro definition, after it is defined, is
referenced using the macro name with a preceding ` (back-tic) character. It is easy to distinguish between parameters and macros in a design because macros have a `identifier_name while a parameter is just the identifier_name without back-tic.

Parameters must be defined within module boundaries using the keyword parameter.
A parameter is a constant that is local to a module that can optionally be redefined on an instance-byinstance basis. For parameterized modules, one or more parameter declarations typically precede the port declarations in a Verilog-1995 style model, such as the simple register model in Example 1.

module register (q, d, clk, rst_n);
parameter SIZE=8;
output [SIZE-1:0] q;
input [SIZE-1:0] d;
input clk, rst_n;
reg [SIZE-1:0] q;
always @(posedge clk or negedge rst_n)
if (!rst_n) q <= 0; else q <= d;

endmodule

The Verilog-2001[5] version of the same model can
take advantage of both the ANSI-C style ports and module
header parameter list, as shown in Example 2.

module register2001

#(parameter SIZE=8)
(output reg [SIZE-1:0] q,
input [SIZE-1:0] d,
input clk, rst_n);
always @(posedge clk, negedge rst_n)
if (!rst_n) q <= 0; else q <= d;

endmodule

4. Parameters and Parameter Redefinition
When instantiating modules with parameters, in
Verilog-1995 there are two ways to change the parameters
for some or all of the instantiated modules; parameter
redefinition in the instantiation itself, or separate
defparam statements.
Verilog-2001 adds a third and superior method to
change the parameters on instantiated modules by using
named parameter passing in the instantiation itself (see
section 7).
5. Parameter redefinition using #
Parameter redefinition during instantiation of a module
uses the # character to indicate that the parameters of the
instantiated module are to be redefined.
In Example 3, two copies of the register from Example
1 are instantiated into the two_regs1 module. The SIZE
parameter for both instances is set to 16 by the #(16)
parameter redefinition values on the same lines as the
register instantiations themselves.

module two_regs1 (q, d, clk, rst_n);
output [15:0] q;
input [15:0] d;
input clk, rst_n;
wire [15:0] dx;
register #(16) r1 (.q(q), .d(dx),
.clk(clk), .rst_n(rst_n));
register #(16) r2(.q(dx), .d(d),
.clk(clk), .rst_n(rst_n));
endmodule

`define Inclusion
One popular technique to insure that a macro definition
exists before its usage is to use an `ifdef, or the new
Verilog-2001 `ifndef compiler directives to query for
the existence of a macro definition followed by either a
`define macro assignment or a `include of a file name
that contains the require macro definition.

`ifdef CYCLE
// do nothing (better to use `ifndef)
`else
`define CYCLE 100
`endif
`ifndef CYCLE
`include "definitions.vh"
`endif

The `undef compiler directive
Verilog has the `undef compiler directive to remove a
macro definition created with the `define compiler
directive.
Bergeron recommends avoiding the use of macro
definitions[11]. I agree with this recommendation.
Bergeron further recommends that all macro definitions
should be removed using `undef when no longer
needed[11]. I disagree with this recommendation. This
seems to be overkill to correct a problem that rarely exists.
Using the `define compiler directive to create global
macros where appropriate is very useful. Losing sleep
over the existence of global macro definitions and
tracking all of the `undef's in a design is not a good use
of time.
For the rare occasion where it might make sense to
redefine a macro, use `undef in the same file and at the
end of the file where the `define macro was defined.
Make sure that the last compiled macro definition is
likely to be the macro that you might want to access from
a testbench, because only one macro definition can exist
during runtime debug.
Again, using a `define-`undef pair should be
considered the last resort to a problem that could probably
be better handled using a better method.

CODE COVERAGE

2008-06-02T08:09:00.000-07:00

Code Coverage It is a process of validating or finding the quality of the test bench for RTL code for a particular design. This is a measurement which tells how good the design has been exercised with the test bench / test cases.
Code coverage is applied to DUT (Design under Test) to check how thoroughly the HDL exercised by test suite. Code coverage points the portion of code which did not exercised, it also points the corner/edge cases, unused/dead code.
There are varieties of tools available in the market for code coverage. Models (From Mentor Graphics) and ICC (From Cadence) are some examples of those.
With out code coverage tools designer can only say the simulation output is the expected one or not. But he will not know whether he needs more test cases or not. With help of code coverage it is very easy to know how well the HDL code exercised. From the code coverage result it is easy to determine how more TCs needed for a complete test.
Well, what are the things to be checked during code coverage? Or what are the types of code coverage? Following text describes the types of coverage which are applied together or separately. There will be a possibility to enable or disable any one particular type of the coverage during the process.
Block coverage - When block coverage enabled the tool monitors all exercisable blocks in the HDL code. Block is a statement or sequence of statements that executes with no branches and delays. Assume there are 100 blocks in one design but only 75 blocks are exercised with test suite then the block coverage is 75%. So it is sure that the design needs more test cases to exercise the complete logic.
Branch coverage- In a 'case' or 'if-else' there may be more the one branch in the design. Test case should exercise all branches for the completeness. Often some cases in a case statement of else part of 'if-else' statement will be missed. Branch coverage will identify those errors. A snippet of code considered 100% covered with branch coverage when all the branches of code executed at least once. Some time it is referred as decision coverage. Branch coverage also applied to case statements, like the following:
In this example, branch coverage will identify whether each of the three branches of the Case statement is taken.
case (z)
1 : x=0;
2 : x=10;
3 : x=20;
endcase
Condition coverage - Some tools support this feature. This is an extension of branch coverage. Condition coverage breaks down branch conditions into the elements that make the result true or false. If there are any conditions in an ‘if’ statement are missed during executing then the tool will notify.
Statement coverage - It count all executable statements in a code and makes ratio of unexecuted statement during the current simulation. Executable statements are those that have a definite action during runtime and do not include comments, compile directives or declarations. At end of this document there is a worked example for this type of coverage.
Variable coverage - Multi bit variables are monitored in this coverage. It allow to track toggles, range and values on vector (more than one bit) variables
FSM coverage - Finite state machine coverage, it helps to analyze variety of styles of state machine written in RTL.
Expression coverage - Expression coverage brings statistics for all expressions in the HDL code. Expression can be continues or procedural assignments. It identifies the expressions which are not sufficiently exercised.
Toggle coverage - A design includes various objects like bit, reg, wire, signals. These objects might or might not change during simulation run. Toggle coverage measures these signals' activities. It is very useful in gate level testing. It also gives approximate power consumption of the circuit.
Example for code coverage.
There are two modules,
mux.v - This is DUT, it is a 4 to 1 mux.
tb_mux.v - Test bench for mux which generates test vectors for DUT. The quality of this test bech for DUT is going to be checked now.

module mux (sel_a,sel_b,data_4bit,out);
input sel_a;
input sel_b;
input [3:0] data_4bit;
output out;
reg out;
always @ (sel_a or sel_b or data_4bit)begin case ({sel_a,sel_b}) 2'b00 : out <= data_4bit[0];
2'b00 : out <= data_4bit[1];
2'b00 : out <= data_4bit[2];
2'b00 : out <= data_4bit[3];
default : out <= 1'b0;
endcaseendendmodule

module tb_mux;
reg sel_a;
reg sel_b;
reg [3:0]data_4bit;
wire out;
initial
begin
data_4bit = 4'b1001;
// input set 1
sel_a = 1'b0;
sel_b = 1'b0;
// input set 2
sel_a = 1'b0;
sel_b = 1'b1;
// input set 3
sel_a = 1'b1;
sel_b = 1'b1;
// input set 4
sel_a = 1'b1;
sel_b = 1'b0;
// input set 5
sel_a = 1'bx;
sel_b = 1'bx;
end
mux dut (.sel_a(sel_a),
.sel_b(sel_b),
.data_4bit(data_4bit),
.out(out));
Endmodule
Since this example is just to get an idea about code coverage only statement coverage is enabled. Other coverage options can be enabled if it is needed.
Run 1
For the first run input set 1,2 and 3 are enabled 4 and 5 are disabled (disable in the sense comment the lines under the input set 4 and input set 5). For this run the code statement coverage is only 71.4%. How this is calculated

Code Coverage runs one
In the above figure, there are two status bars for two modules. tb_mux and dut. Measuring code coverage for test bench is not important. Only the DUT has to be checked thoroughly for it is functionality that is the job of TB. So in the above picture don’t worry about tb_mux. Our interested module is DUT and it shows 71.4%. The number of executable line in the DUT is 7. Current inputs from test bench exercises only 5 statements. So 5/7 * 100 = 74.1%

Code Coverage run one Code
Above figure shows the missing statements the case items 2'b10 and default. It is clear that the design is not tested completely. So the test bench has to be improved.
Run 2
For the second run input set 1,2,3 and 4 are enabled, 5 is disabled. For this run the code statement coverage is 85.7%.
Code Coverage run two
Calculation for second run 6/7 * 100 = 85.7%. See the following diagram for more details
Code Coverage run two Code
Run 3
For the third run all input sets 1 to 5 are enabled in the test bench. For this run the code statement coverage is 100%.
Code Coverage run three
Note that for some complex design it may not be possible to bring 100% for all types of coverage.

Linting

2008-05-30T04:38:00.000-07:00

In general Lint tools that flag suspicious and non- portable usage of language construct in any programming language. It points out the code where it likely to be bugs. In chip design world Lint tools (some time referred as Design Rule Checker) check the cleanness and portability of the HDLs code for various EDA tools. Usually compiler does not show the errors and warnings which detected by lint tools. There are many advantages of it, for example when design style enforced by lint tool it avoids a situation where the synthesis tools implements something different than expected from RTL code.
For example consider the following Verilog code. Lint Check example

module lint_check (x, y, z);
input x;
input y;
output z;
assign z= x + y;

Endmodule

This example is completely ok with compiler. Complier does not generate warning. In the above code by default the output variable ‘z’ is a wire. It is not necessary declare it as a wire. But some (not every) synthesis tools may need it to be declared it as a wire.

If Lint tool applied on the code before the synthesis, it points out the above mistake. This is just one example. There are many standards and lint check rules are available. Here are some example for rules, coding style, DFT, design style, language constructs, synthesis and also possible to include custom rule checking. It is possible to select/deselect the rules/standards during lint checking. It completely depends on the need of the particular environment and design. Lint check rule can be stand alone or it can be integrated with come verification environment. Spyglass is a stand alone Lint tool, nLint integrated with Verdi and Debussy debug systems. Leda (Synopsys call it ‘RTL checker’) Black-Tie from cadence are some other Lint tools in the market.

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