Computer Hardware Networking Workstation

Identifying the Beginning Sector of a Track

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 16:32:00 +0000

The two main methods of identifying the beginning sector of a track are

• Hard Sectored Floppy

In hard sectored, the start of each sector is identified by a physical hole. A light is shone through the hole and picked up on the other side by a detector. As the disk rotates, this causes a sequence of pulses to occur as the sector ID holes allow the light to pass through to the detector. The holes are called index holes. This method was used in the Apple II computer.

• Soft Sectored Floppy

In soft sectored, only one index hole is used, and each sector is preceded with data bytes which identify the sector number. This format is used in IBM-PC compatible computers.

Fig 5.6: Floppy Drive

Cleaning Kit The image on the TOP shows a floppy diskette cleaning system. It consists of a floppy disk containing a cleaning disk and some cleaning fluid. The fluid is placed on the floppy disk and then the disk is inserted. Any foriegn material on the read/write heads are transferred to the disk. The cleaning disk can only be used a limited number of times.

Floppy Drives

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 16:27:00 +0000

The floppy drive uses a thin circular ceramic disk for data storage. The disk is coated with magnetic particles and is flexible (hence the term floppy).
The disk rotates at 360rpm. A read/write head makes physical contact with the disk surface. Data is recorded as a series of tracks subdivided into sectors. Typical values for an IBM-PC compatible are

Size Capacity Tracks Sectors
5¼ 360KB 40 9
5¼ 1.2MB 80 15
3½ 720KB 40 18
3½ 1.44MB 80 18

stepper motor. The stepper motor moves a small amount for each pulse applied to it. A mechanical switch detects when the read/write head is in the outermost position (track 00).

Disk Drive Types

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 16:26:00 +0000

This section discusses the various drive types available for IBM-PC compatible computers.

mfm (modified frequency modulation)
These drive types were the first to be made for the IBM-XT model. Storage capacity was 30MB with access types of about 30ms. Capacity ranges from about 10MB to 80MB. Due to their design, it was costly to make drives any larger. MFM refers to the encoding technique used to store data on the disk. They are all but replaced by IDE.

rll (run length encoding)
This is similar to MFM drives except that the encoding technique used to store data essentially doubles the capacity of an MFM drive. Few, if any, manufacturers still make MFM or RLL drives today.

esdi (enhanced small disk interface)
These drive types range in capacity from about 80MB to about 300MB. They are becoming less common. The advantage they have over RLL or MFM drives is higher data transfer rates (about twice as fast).

scsi (small computer systems interface)
The common drive choice for servers or high end workstations, drive capacities range from 100MB to 4GB. They have fast access times and high data transfer rates, but are expensive. One advantage of these drives is that a single controller can handle seven drives.

ide (integrated disk electronics)
A common drive used today for workstations with capacities of 40MB to 1000MB. Good access times of about 20ms, but slower data transfer rates than SCSI drives. Drives are reasonably cheap, but the controllers can only handle a maximum of two drives (some will handle only one).

Hard Drive Construction

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 16:18:00 +0000

This picture shows the physical construction of a hard disk drive.

Fig 5.4: Hard Disk Drive Construction

Disk Drive Characteristics

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 15:32:00 +0000

This section discusses the terminology and characteristics of disk drives.

Tracks and Sectors

The disk is divided into concentric rings called tracks. A track is thus one complete rotation of the disk underneath the read/write head. The width of a track is determined by the size of the read/write head, and the distance between tracks determined by the mechanics of the stepper motor which controls the positioning of the arm to which the read/write head is attached.

Each track is subdivided into a number of sectors. Each sector contains a specific number of bytes or characters. Typical sector capacities are 128, 256, 512, 1024 and 4096 bytes.

Increasing the number of tracks is one way to increase the storage capacity of a disk drive. Often the physical size of the disk imposes space restrictions which make this impractical. The most common choice is increasing the number of sectors per track (from 17 to 34), or increasing the number of bytes stored in each sector.

Bad Blocks

The drive maintains an internal table which holds the sectors or tracks which cannot be read or written to because of surface imperfections. This table is called the bad block table, and is created when the disk surface is initially scanned during a low level format.

Partitions

A disk partition is a sub-division of the disk into one or more areas. Each partition can be used to hold a different operating system. The computer system boots from the active partition , and software provided allows the user to select which partition is the active one.

Sector Interleave

This refers to the numbering of the sectors located in a track. A one to one interleave has sectors numbered sequentially, 0, 1, 2, 3, 4, etc. The disk drive rotates at a fixed speed, 3600rpm, which means that there is a fixed time interval between each sector. A slow computer can issue a command to read sector 0, storing it in an internal buffer. Whilst it is doing this, the drive makes available sector 1, but the computer is still busy storing sector 0. Thus the computer will now have to wait one full revolution till sector 1 becomes available again.
Renumbering the sectors like 0, 8, 1, 9, 2, 10, 3, 11 etc gives a 2:1 interleave. This means that sectors are alternated, giving the computer slightly more time to store sectors internally than previously.

Drive Controller

The drive is managed by a special peripheral card called a drive controller. It may handle multiple drives or only a single drive. The controller is often responsible for issuing commands to position the read/write head (especially in MFM and RLL drives).
In SCSI and IDE drives, the controller is simplified, and the intelligence is placed onto the drive itself. These drive offer sophisticated features like caching and hot fix (write errors are redirected to another free sector).

Rotation Speed

This refers to the speed of rotation of the disk. Most hard disks rotate at 3600rpm. To increase data transfer rates, higher rotational speeds are required, or multiple read/write heads arranged in parallel, or disk arrays (multiple disks arranged in parallel).

Low/High level Formatting

Low level formatting is placing track and sector information, plus bad block tables and other timing information on the disk. Sector interleave can also be specified at this time.

High level formatting involves writing directory structures and file allocation tables to the disk. Often this also means transferring the boot file for the operating system onto the hard disk.

Access Time

Access time refers to how soon the drive makes data available once issued with the command to read the data. Once a read command is issued, the drive must position the read/write head at the appropriate track number and wait for the correct sector to arrive.

Latency
This refers to the delay between the read/write request, and the appearance of the required sector under the read/write head.

Timing tracks

In larger drives used on main frame computers, the disk drives often had timing tracks written. These tracks were used for alignment purposes, to ensure that the read/write head was accurately positioned over the track.

The read/write head was moved until the pulses picked up from the timing head were at a maximum. This meant that the read/write head was correctly positioned over the data track.

Newer more accurate mechanisms have tended to make this obsolete.

Disk Storage

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 15:23:00 +0000

Disks are used to store data, applications software and operating systems software. Whereas the primary form of storage in the early days of computing was magnetic tape, this has been replaced by predominantly disk based medium today. The reasons for this trend has been
.Decreasing cost per bit.
.Reliability.
.Reduced access times.
.Higher transfer rates (more data per second).
.Reduced size and power requirements.
.Increased capacity.

One trend that is appearing is a move to CDROM and optical storage medium. Many software companies offer both operating systems software and application software on CDROM today.

Disk storage systems are essentially based on magnetic properties. This is the same principle as used in cassette tape recorders. A rotating disk is coated with fine magnetic particles. When writing data, a write head magnetises the particles on the disk surface as either north or south poles. When reading data, a read head converts the magnetic polarisation's on the disk surface to a sequence of pulses.

The read and write heads are generally combined into a single head unit. There may be more than one read/write head. Consider the example shown below, where a group of heads is used to write data onto concentric rings on the magnetic drum. In this example, the heads are fixed (non-moveable).

Fig 5.1: Magnetic Drum

The problem with this drum approach is limited capacity. To increase the capacity requires an increase in the circumference size of the drum, or more read/write heads.
A more common approach used today is to use a read/write head attached to a moveable arm, which steps across (by small increments) the surface of the disk. The disk is a platter coated with magnetic particles. This arrangement is shown below.

Fig 5.2: Hard Disk Drive

Early drives were large. IBM developed a smaller rigid disk drive with one fixed and one removable pack. Each pack held about 30 megabytes (MB) of data, so it was dubbed model '3030', and became known as the Winchester drive.
Most Winchester drives have common features
. The disk and read/write heads are enclosed in a sealed airtight unit
. The disk(s) spin at 3600 revolutions per minute
. The read/write heads do not actually touch the disk surface
. The disk is lubricated (heads fly above when the disk is up to speed)
. The disk surface contains a magnetic coating
. The disk surface (platters) is fixed

Data is arranged as a series of concentric rings. Each ring (called a track) is subdivided into a number sectors, each sector holding a specific number of data elements (bytes or characters).

Fig 5.3: A track subdivided into sectors

The smallest unit that can be written to or read from the disk is a sector. Once a read or write request has been received by the disk unit, there is a delay involved until the required sector reaches the read/write head. This is known as rotational latency, and on average is one half of the period of revolution.

The storage capacity of the disk is determined as (number of tracks * number of sectors * bytes per sector * number of read/write heads)

Base Units

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 15:18:00 +0000

The computer base unit houses the CPU, memory, floppy disk, hard disk drive, power supply unit, and peripheral cards which support printers and modems.

Fig 4_9: Computer Base Unit
The expansion slots are used to plug in additional peripheral cards like sound cards, TV Tuners cards, video capture cards etc. The two main types of expansion slots are PCI and ISA

STORAGE DEVICES

The objective of this section is to

Discuss various storage devices, Explain the characteristics and terminology of selected storage, devices At the end of this section, you should be able to, compare storage devices using a number of criteria, describe the operation of storage devices

The Programming Model of a CPU

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 15:09:00 +0000

The programming model of a processor defines the registers within the processor which are visible and programmable by the user.

These include

1. general purpose registers.
2. flag (condition code or status) register.
3. program counter or instruction pointer.
4. stack register.

Executing a program: An example

Lets consider the operation of the following program at the processor level.
Assembler High Level Language
MOV AX, #1 A := 1;
MOV BX, #2 B := 2;
ADD AX, BX C := A + B;
PUSH AX Writeln( C );
CALL WRITELN

Assume that the instruction pointer contains the address of the first instruction.

1. Place the address of the instruction (IP) on the address bus
2. Read the value from that location into the instruction register.
3. Decode the instruction (Mov AX, #1), increment the instruction pointer
4. Read the operand from the next location and transfer it into the AX register
5. Place the address of the instruction (IP) on the address bus
6. Read the value from that location into the instruction register.
7. Decode the instruction (Mov BX, #2), increment the instruction pointer
8. Read the operand from the next location and transfer it into the BX register
9. Place the address of the instruction (IP) on the address bus
10. Read the value from that location into the instruction register.
11. Decode the instruction (Add AX,BX), increment the instruction pointer
12. Transfer BX to the ALU, and add with AX. Move the result back into AX
13. Place the address of the instruction (IP) on the address bus
14. Read the value from that location into the instruction register.
15. Decode the instruction (Push AX), increment the instruction pointer
16. Put the value of the stack pointer on the address bus
17. Write the value of AX to that location
18. Increment the stack pointer register value
19. Place the address of the instruction (IP) on the address bus
20. Read the value from that location into the instruction register.
21. Decode the instruction (Call WRITELN), increment the instruction pointer
22. Read the operands from the next two locations into an internal hold register
23. Transfer the operands into the instruction pointer.

Register Banks

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 15:07:00 +0000

To provide for the temporary storage of variables or results, most (if not all) processors provide a number of internal hold latches called registers. The number of registers can range from 1 to several hundred, depending upon the architecture of the processor.

The reason why internal register banks (a group of registers) are used is speed. Data inside the processor is manipulated significantly faster than data external to the processor (ie, located in system memory). This is because of the time required to fetch the data from system memory and transfer it into an internal hold latch before it can be manipulated.

For instance, to multiply the contents of a memory location by 2, the processor needs to first read the memory location value to an internal register, transfer it to the accumulator, multiply it by 2, then write the ALU contents back to the memory location. The two memory cycles consume time.

In contrast, to multiply an internal register by 2 requires no external system memory access, and the lack of this overhead means that instructions of this type execute faster than those which make external references to system memory.

The purpose of internal processor register banks is to provide temporary storage for variables and calculations.

Instruction Register/Decoder

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 15:05:00 +0000

Once the instruction has been copied from system memory to the instruction register inside the processor, the decode cycle starts. The instruction is decoded. This means that the processor figures out precisely the sequence of operations (both internal and external) that must be performed next.

The decoded instruction might look like

o Move the A register contents to the ALU.
o Left shift the ALU three times.
o Move the contents of the ALU to the A register.
o Add one to the instruction pointer register.

The purpose of the instruction register is to hold a copy of the instruction which the processor is about to execute.

Instruction Pointer/Program Counter

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 15:02:00 +0000

As discussed earlier, the processor uses an internal counter to keep track of the instruction it is executing from the system memory. The contents of the counter is the location of where the instruction is found (its address number).

During the fetch cycle, the processor places the contents of this counter on the address bus. A read signal is issued on the control bus, then timing signals are generated to transfer (copy) the instruction from the memory location in system memory to an internal hold latch inside the processor (called the instruction register).

During the decode cycle, the instruction counter is adjusted to point to the next instruction to be executed from system memory (calculated from the current instruction).

The purpose of the instruction pointer is to hold the address of the instruction the processor is about to execute from system memory.

Internal Operation of the CPU

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 14:45:00 +0000

We shall now look at the internal operation of the CPU, and how it performs the fetch, decode, execute cycle. Internally, the CPU is made up of a number of discrete sections.

Arithmetic Logic Unit

The ALU performs arithmetic calculations. Typical operations performed by the ALU are
1. Add
2. Subtract
3. Negate
4. Divide
5. Shift/Rotate
6. Multiply

The ALU normally works on two numbers at a time. Often, one of the numbers is found in an internal location of the processor, whilst the other is a constant or found in the memory system. The reason for most arithmetic and logic operations using operand's which are located inside the processor is speed. This is due to not having to perform a fetch cycle for transferring the operand from the memory system to an internal hold point (called latch) in order to execute the instruction.

The purpose of the ALU is to perform arithmetic and logic operations .

Graphical Animation of Instruction Fetch

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 14:43:00 +0000

The following graphic animation illustrates typical operation of an instruction by the processor. It places the contents of the instruction pointer onto the address bus and fetches the instruction. Once decoded, the instruction is executed and the instruction pointer altered to point to the next instruction.

Fig 4_8: Animation of Instruction Fetch

Execute Cycle

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 14:37:00 +0000

In the last phase, the processor executes the instruction. In the example above, this involves setting the contents of the internal register AX to the constant value 0.

Fig 4_7: Execute cycle, executing the instruction
In the above image, the processor executes the series of macro instructions related to the instruction MOV AX,0. The final part is to adjust the Instruction Counter to point to the next instruction to be executed, which is found at address 0102.

Decode Cycle

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 14:28:00 +0000

The instruction is decoded by the processor. During this cycle, the processor, if required by the instruction, will get any operand's required by the instruction. For instance, the instruction MOV AX, 0 sets the value of the AX register of the processor to the constant value 0. The processor has the instruction (MOV AX), but now needs the constant value 0 to complete the instruction before executing it. In this instance, the processor will fetch the constant value 0 from the next location in memory (it is found immediately after the instruction, in the next memory location 0101).

Fig 4_6: Decode cycle, decoding the instruction

In the above image, the processor transfers the instruction from the instruction register to the Decode Unit. It compares the instruction to an internal table, and when a match is found, the table contains the list of macro instructions (a number of steps) which are required to perform the instruction. In our case, the instruction means place the value 0 into the AX register. The decode unit now has all the details of how to do this.

The Central Processor Revisited

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 14:10:00 +0000

We shall now take a closer look at how the processor functions internally.

The Fetch, Decode, Execute Cycle

Most modern processors work on the fetch, decode, execute principle. This is also called the Von Nuemen Architecture. The execution of an instruction by a processor is split into THREE distinct phases, Fetch, Decode, and Execute.

Fetch Cycle

In the first phase, the processor generates the necessary timing signals to fetch the next instruction from the memory system. The instruction is transferred from memory to an internal location inside the processor (the instruction register).

Fig 4_5: Fetch Cycle, reading the instruction

In the above image, the processor is ready to begin the Fetch cycle. The current contents of the instruction counter is address 0100. This value is placed on the address bus, and a READ signal is activated on the control bus. The memory receives this and finds the contents of the memory location 0100, which happens to be the instruction MOV AX, 0.

The memory places the instruction on the Data Bus, and the processor then copies the instruction from the Data Bus to the Instruction Register.

IO CHANNEL COPROCESSOR (IBM)

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 09:26:00 +0000

To allow concurrent operation of the CPU and I/O devices requires the use of a special I/O processor. The main CPU instructs the I/O processor to perform the required data transfer. When the transfer is completed, the I/O processor informs the main processor of the status of the operation.

This method frees the main processor to perform other tasks whilst I/O is being done (tasks requesting I/O are blocked by the OS and thus not scheduled for processor time).

Typical features of an I/O channel processor system are

1. data transfer between main memory and peripherals.
2. have priority access to main memory.
3. operate in byte, word or burst mode.
4. use direct memory access techniques.
5. transfer data at rates > 1Mbps.

There are two main types of IO channels

1. Selector.
2. Multiplexor

Both channels support a number of devices on a bus called a sub-channel.
The selector channel operates in burst mode only. It handles a single sub-channel at a time, and has very high transfer rates. Typically, it controls high speed disk units.

The multiplexor channel handles more than one sub-channel at a time by interleaving requests. It operates in byte and word mode, but does support burst at a much lower rate than a selector channel. Typically, it handles devices like printers and character terminals.

Channel Operation

The processor initiates an I/O transfer by setting up a special IOC program in main memory. It then issues a START IO instruction, which identifies the channel and sub-channel.

The channel then accesses and runs the channel program (the address of which is in location 72). When finished, the channel updates the IO flag in the processors status register to signal command completion. The processor then checks the channel status register for results.

Each channel gets informed of

.subchannel number
.number of bytes to transfer
.direction of transfer
.where in memory the data or buffer is located
.mode of transfer (bit, byte or word)

Input/Output Processors

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 09:25:00 +0000

An input output processor is a special processor dedicated to handling peripheral devices like terminals, tape and disk units, and printers.

Mainframe systems like the IBM 370 use I/O processors to off load work from the system processor. This lets the system processor get more work done executing user programs without having to worry about handling data input and output to terminals or printing documents.

The PC has an I/O processor in the keyboard, which handles the complex operations of scanning the keys.

In addition, it is now becoming common to have I/O processors on graphics cards. The S3 graphics card is a good example of this, which supports hardware support for scrolling, sizing and moving windows. This removes these tasks from the system processor, and performs them at a much higher rate (up to 30 times faster).

Input/Output Peripheral Devices

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 09:22:00 +0000

Peripheral devices allow input and output to occur. Examples of peripheral devices are

1. Disk Drive Controllers.
2. Keyboards.
3. Mouse.
4. video cards.
5. parallel and serial cards.
6. real-time clocks.

The processor is involved in the initialisation and servicing of these peripheral devices.

Input/Output Bus

noreply@blogger.com (Usha) — Sun, 20 Jan 2008 09:16:00 +0000

The IO bus is the interconnection path between the processor and input/output devices (including memory). The bus is divided into THREE main sections

Address

The address bus is used by the processor to select a specific memory location. This memory location may be in the memory subsystem (either RAM or ROM), or a peripheral device. The address bus is one way only (unidirectional).

Data

The data bus is used to transfer data between the processor and memory or peripheral devices. The data bus is two-way (read/write, bi-directional).

Control

The control bus is like the traffic signals. It provides timing, clock, and directional signals for each operation. Most of these signals are generated by the processor, as the processor generally controls the read or write operation.
In more complex systems, the memory subsystem or peripheral devices also provide timing signals to complete data transfers, or initiate requests that the processor responds to (called interrupts).

Cache Memory

noreply@blogger.com (Usha) — Sat, 15 Dec 2007 05:30:00 +0000

Cache memory is high speed memory which interfaces between the processor and the system memory. Dynamic memory is used to implement large memory systems in modern computers. This is due to features like low power consumption, high chip densities and low cost.

Dynamic memory is however slow, and cannot keep up with modern fast processors. When a processor requests data from a memory chip, it expects to receive that data within a specific time. This is expressed as a number of clock cycles.

It is common for processors to run what is called a FOUR STAGE BUS CYCLE (which is four processor clocks long). Essentially, during the first processor clock cycle, the address is placed on the address bus. the second processor clock cycle is used to latch the address internally within the memory chip. The third processor clock cycle is used by the chip to find the data and place it on the data bus. The fourth processor clock cycle is used by the processor to latch the data on the data bus into its own internal hold register.

Dynamic memory is currently too slow to keep up with processors running at clock rates of 50MHz or greater (each cycle is 20no's). To use dynamic memory with fast processors requires extending the third processor clock cycle by another (or multiples thereof) processor clock cycle. The name for this extra processor clock cycle is called a wait state. What this does is change a four stage bus cycle into a five stage bus cycle (or greater), meaning that the fast processor is actually running just as fast as a slower processor (its being slowed down by the memory subsystem, whenever it accesses memory).

It is too expensive to use static memory in place of dynamic memory. To use slow dynamic memory with a fast processor requires an extra hardware subsystem (called cache memory) which fits between the processor and the memory subsystem.

All memory accesses by the processor are fed through the cache system. It comprises an address comparator which monitors the address requests by the processor, high speed static ram, and extra hardware chips.

The cache system starts off by trying to read as much data as possible from the dynamic memory subsystem. It stores this data in its own high speed static memory (or cache). When a processor request arrives, it checks to see if the address request is the same as that which it has already read from the memory sub-system. If it is, it supplies the data directly from its static cache. If the address is not cached, then it lets the processor access the main memory system directly (but the processor does this slower). The cache system then updates its own address counter it uses to read from system memory to that of the processors, and tries to read as much data as possible before the next processor request arrives.

When the cache system can respond to the processor request, its called a cache hit. If the cache system cannot service the processor request, its called a cache miss.

Types of Computer Memory

noreply@blogger.com (Usha) — Mon, 22 Oct 2007 14:34:00 +0000

System memory consists of two main types.

• ROM (Read Only Memory)

This form of memory contains programs which do not change. Examples of these are routines which initialise the computer system hardware when power is turned on.
ROM is non-volatile. This means the contents do not disappear when the power to the system is turned off.
EPROM is a special type of ROM which can be programmed by the user. Its contents can also be erased by exposing it to ultra-violet light.
EEPROM is another special type of ROM which can be programmed by the user. It contents are erased by applying a specific voltage to one of its input pins whilst providing the appropriate timing signals.

• RAM (Random Access Memory)

This form of memory is used to store data and application programs. The memory is read-write, and volatile. This means the contents disappear when the power to the system is turned off. There are TWO main types of RAM used in computer systems today.

Dynamic

This memory is based on capacitor technology, and requires the contents of each storage cell within the chip to be periodically refreshed (about every 4ms). It consumes very little power, but suffers from slow access times. Another advantage is the large capacity offered by this technology per chip (16Mbit).

Static

This memory is based on transistor technology, and does not require refreshing. It consumes more power (thus generates more heat) than the dynamic type, and is significantly faster. It is often used in high speed computers or as cache memory. Another disadvantage is that the technology uses more silicon space per storage cell than dynamic memory, thus chip capacities are a lot less than dynamic chips.

Advantages Disadvantages
Dynamic RAM 1. Cheaper 1. Slower
2. Low Power 2. Needs refreshing
3. High Density

Static RAM 1. Faster 1. More Expensive
2. No need to refresh 2. Consumes More Power
3. Low Density

Computer Memory

noreply@blogger.com (Usha) — Mon, 22 Oct 2007 14:29:00 +0000

Memory contains data or instructions for the processor to execute. All memory has common features.

Address Locations

Memory consists of a sequential number of locations, each of which are a specific number of bits wide.
o byte wide memory 8 bits (PC-8088).
o word wide 16 bits (XT-8086, AT-80286).
o double word 32 bits (386DX, 486SX, 486DX).
o quad word 64 bits (pentium).

The more number of bits per location affects the speed at which data can be moved from one location to another in a computer system. In general, the more bits per location the faster data can be transferred.

Each memory location is referred to as an address, and generally expressed in hexadecimal notation (using base 16 numbers).

The processor selects a specific address in memory by placing the address on a special multi-bit bus called the address bus . The value on this address bus is used by the memory system to find the specific location within the chip which the processor is requiring access to.

The total number of address locations which can be accessed by the processor is known as its physical address space. How large this is determined by the size of the address bus, and is often expressed in terms of Kilobytes (x1024) or Megabytes.
o 16 bits address bus = 64K (65536 locations)
o 20 bits address bus = 1MB (IBM PC)
o 32 bits address bus = 4GB (486DX)

• Access Times

Access time refers to how long it takes the processor to read or write to a specific memory location within a chip. The limiting factor is the type of technology used to implement the memory cells inside the chip.

• Volatility

This refers to whether or not the contents of the memory is lost when power is turned off. If the contents are lost, the memory is volatile. If the contents are retained, then the memory is non-volatile.

Stored Program Control

noreply@blogger.com (Usha) — Mon, 22 Oct 2007 12:23:00 +0000

Most computer systems today are stored program control systems. This means that the processor executes instructions which are stored in a memory subsystem. SPC systems are popular, because the processor does is simply changed by altering the instruction in the memory system. This makes for a general purpose computer system, capable of performing a wide variety of different tasks dependant upon the stored program contents.

Programs: Instructions and Operand's

noreply@blogger.com (Usha) — Mon, 22 Oct 2007 12:15:00 +0000

A program consists of a number of CPU instructions. Each instruction consists of

* an instruction code
* one or more operand's (data which the instruction manipulates)

The instruction code specifies to the CPU what to do, where the data is located, and where the output data (if any) will be put.

Instructions are held in the memory section of the computer system. Instructions are transferred one at a time into the CPU, where they are decoded then executed. Instructions follow each other in successive memory locations.

Fig 4_2: Program Instructions

Memory locations are numbered sequentially. The processor unit keeps track of the instruction it is executing by using a internal counter. This counter holds the location in memory of the instruction it is executing. Its name is the program counter (sometimes called instruction pointer).