Crazy world of chips

Anandtech forums on trial: The corruption runs deep.

2014-03-11T05:40:00.004-07:00

An excellent article written by SilliconWars about AnandTech forums and "unbiased" moderators who run the forums. A must read!

http://techsoda.com/anandtech-forum-moderators-biased-corrupt/

AMD Kaveri Tech Day!

2014-01-05T12:29:00.004-08:00

Original source:
http://www.purepc.pl/amd_kaveri_tech_day/amd_kaveri_tech_day_relacja_na_zywo#

Backup:
http://apusilicon.com/amd-tech-day-and-kaveri-details-abound/

Die shot:

IPC up to 20% better:

Kaveri's die shot from the presentation(tried to fix perspective):

Some crude module comparison with "leaked" module of unknown AMD core from 5 months back:

Image of Kaveri's module from tech day(bad quality due to low res. of orig. imae):

Leaked module of unknown core:

Now two overlapped with the 2nd image set with high opacity:

Seems it doesn't match so well. It might be that the unknown module shot is Excavator module(?).

2nd Kaveri leak from China

2014-01-03T14:13:00.000-08:00

More benchmarks here:
http://tieba.baidu.com/p/2795083406

Imgur album with all benchmarks:
http://imgur.com/a/OYWL0#0

1st Kaveri leak from JP

2013-12-29T15:51:00.002-08:00

I have found something for you guys, posted it on SA and here for now . Hope you like it. The scores are not out of this world like previous time, so this is looking like a legit screenshot. Magic date is January 14.
http://www.gdm.or.jp/voices/2013/1230/56219

Enjoy!

PS It takes 4.2Ghz PD to match 3.7Ghz SR in C15 . 7850K runs C15 at 3.7Ghz, it doesn't turbo up in this workload (at least not in the run that you see in the image above ).

Kaveri is launching soon. What to expect?

2013-12-11T17:29:00.001-08:00

Long time since my last blog post. Since AMD is about to launch desktop Kaveri soon (in ~January) I wanted to write a couple of lines about what *I* think about this product launch.

During this year we have had a few "leaks" regarding Kaveri's performance. Conveniently none of these were solid enough to draw any meaningful conclusion regarding actual core performance or clock capabilities. We had a few low clocking and disproportionally low performing mobile parts listed at cosmology.org website and a few geekbench scores of desktop ES parts(single ch. memory). And that's it. Pretty vague and inconclusive.

Now people do have high expectations when it comes to Steamroller cores that power Kaveri, and the "blame" largely lies on AMD themselves. I know since I had them too. AMD did build up a hype with their presentations on HC last year and in a few interviews after that. We had hints of "solid" IPC jumps, new ISA support (turns out it's a few more instructions and not AVX2), quad channel IMC(GDDR5 mode ,4x32bit), 3 module parts, big iGPU perf. gains etc. What we have now is roughly the following:
1) 3 module version is scrapped due to reasons that will be obvious at launch;
2)quad channel GDDR5 support is gone also although IMC has the support sitting idle on-die(deactivated); figure that...
3)"IPC" can be substantially better BUT only if one was to cherry pick benchmarks and filter the "bad" ones(also related to number 1) and what constitutes a total performance of a chip )
4) If Richland had memory BW problem then it will be a minor one when compared to Kaveri.
I think I've said enough.

I've always expected that the 3rd iteration of Bulldozer core will bring us the most tangible results when it comes to removing bottlenecks and bringing the best from the concept of CMT core but due to wrong decisions on AMD's part this I'm afraid will just remain a dream.
As for me I have my Piledriver based X4 and it's doing fine at 4.2Ghz. I personally see nothing that Kaveri will bring on CPU side to sway me over and swap it in my board. Yeah, sorry folks.

AMD Richland (desktop) reviews

2013-06-06T13:52:00.001-07:00

AMD officially launched Richland APUs for desktop PCs. The chips are solid improvement over Trinity, not earth shattering but a good perf./watt (and straight x86 performance) uprgade over Trinity parts.

Here is a summary of most relevant reviews in one topic.
Enjoy!

What is FX @ 5Ghz exactly and why is it listed as "next generation" FX core by Gigabyte?

2013-06-04T18:20:00.003-07:00

Good question huh? Yep sure is. Also what is "TJ" :) ??

Had a better look at the Gigabyte sheet.

It says "AMD next generation FX".
Vishera is no next gen, it is almost two years old already

I assume Gigabyte refers to "TJ", which still should pop into AM3r2.

The sheet is for Rev 3.0 990FXA-UD7 which has some changes to the VRM.
Yet it appears to be a multiplied analog VRM.

Interesting times ahead ;).

AMD's 5Ghz "next generation" FX models under way!

2013-06-03T15:54:00.003-07:00

Ok guys, finally some computex news (still not official by AMD though). Thanks goes to Hexus' and overclocknet's CPU forums .
It's semi-official, there will be a "high-TDP" FX models presented soon, gigabyte lists it as 5Ghz AMD FX lol
Original source is donanimhaber.

Some rough perf. and power estimates :

I've just read sweclocker's review of 4770K/4670K. I wanted to see what kind of difference, power wise, are we looking at Vs 8350. It turns out that in OCCT 4770K draws 140W vs 210W for 8350, both at stock. When OCed to 4.4Ghz, the power draw of 4770K spikes to 190W while performance increases roughly by ~11% or so (logical since the chip almost always tries to run at full turbo of 3.9Ghz).

Now when we look at the rumored OCed-out-of-the-box FX models, we see them having the rather high TDP of 220W. This is 95W higher than official TDP spec for 8350 (or a bit less than that considering 8350 can actually go above 125W). Now looking at sweclocker's link I posted above, the FX9000 @ 5Ghz should be sitting at 210+95~=305W. This is with 20% clock (performance) increase since both rumored stock and Turbo clock are ~20% higher than on 8350. 305W of "stock" FX9000 vs 190W of OCed to rather expected/normal 4.4Ghz for 4770K on air- that's 115W of difference, roughly of course. Since the jump with FX9000 is 20% vs the perf. increase of 10% the OC of 4700K nets, we have the FX9000 actually closing the gap when compared to OCed 4770K. Versus stock 4770K, new "stock" FX should be winning some of the benchmarks and closing the gap significantly in others. In some situations the gap will still be there though and with a hefty power difference at that.

Finally the pricing structure. If AMD prices these parts at lower range than 4770K, somewhere close to 4670K or a bit higher (250-260$), it could be an "OK" purchase for those wanting great MTed performance and somewhat competitive ST performance (5Ghz Vishera is pretty fast chip in ST tasks, still slower than IB and co though). Lastly those buyers should be ready to accept the fact their chip will be drawing >120W more than OCed IB/Haswell setup,but will be cheaper ~100$ or so.

__________________

4770K/4670K (Haswell) reviews

2013-06-03T14:09:00.002-07:00

Haswell has launched and brought us fastest yet x86 performance. It's great to think we have come so far from 2006. Still, the performance jump from IvyBridge core is pretty disappointing in legacy code( FMA3/AVX2 is another story, yet to be written when software support arrives).

Here is a XS topic that covers most if not all reviews so far.
Enjoy.

Kaveri is FM2 compatible?

2013-06-01T03:20:00.000-07:00

Roy Taylor spoke for newegg TV about Richland. Interesting remark from him at around 3:23 in to the video . Kaveri will be compatible with FM2 boards according to him .We know that AMD lists Kaveri as FM2+ so my guess is that it's compatible BUT you would want FM2+ board with GDDR5 or DDR4 (whichever it supports) in order to get the best possible performance.

AMD Steamroller die shot leaked?

2013-05-26T06:35:00.000-07:00

Poster Fellix_Bg posted an interesting picture on the Xtreme systems.

It looks like it could be legit die shot but anything is possible. The changes to the core are massive, especially the front end, branch prediction,instr. and data caches and FP unit as well(massively bigger dedicated die area - 2x the die area dedicated for FP in BD/PD).


Higher res. image

There is also some discussion on SA forum about it and comparison of functional units in this die shot and the BD/PD ones.
SA forum member sdlvx made a nice comparison image:

EDIT:

Two posts from knowledgeable people. 1st is Hans de Vries at SA forum:

This seems quite legit and it's a big module indeed.... It seems many resources are doubled:
Floating point: dual 256 bit FMA instead of dual 128 bit FMA.
Integer: 8 ALU's and 8 AGU's instead of 4 both. Dual 32kB data caches instead of dual 16 kB.
Many other resources are also doubled like rename hardware and so on.

This is how I understand this design (on inf64's request):

The single Bulldozer decoder somehow couldn't handle 2 threads running
at 100% and for benchmarks we see at most a 50% performance increase
when the "second core" becomes active. So it doesn't work good enough
for CMT (but it's more than OK for dual threaded SMT)

Now why not double up the decoder and use the capability to decode
2 threads for SMT instead?

The dual 6 cycle 256 bit FMA FP units "cry out loud" for more threads,
they will be idle and unused otherwise for most of the cycles since you
need 2x6=12 FP operations to go on simultaneously to fully utilize them.
Even with 4 threads that's still 3 FP operations in parallel per thread.

The old 128 bit FMA units used the hardware more efficiently with two
cycles used per AVX operations but I guess one needs full 256 bit AVX
units to score well at these specially designed synthetic, but otherwise
pretty useless, benchmarks.

A single "Integer core" now has 4 ALU's and 4 AGU's which can improve
the integer performance somewhat, but not a lot. Actually I hope they
can still function as dual 2 ALU/AGU integer execution cores to support
4 threads in parallel. That would really help multithreaded performance,
and a little bit of the CMT ideas would survive.

Over time, in subsequent versions, they can now incrementally improve
single threaded performance using 4 ALU as much as possible. But even
then. Integer performance wasn't really Bulldozers problem as can be
seen in the Boinc Dhrystone benchmarks which showed a similar integer
IPC as the Athlon/Phenom cores (as long as the benchmark fits in L1D)

The L1D caches are doubled to 32kB to support 256 bit reads and writes.
A single cache line of 512 bit can now be read and written in a single
cycle freeing up cycles for more program reads and writes. The double
width also reduces bank conflicts.

This strategy to improve Bulldozer/Piledriver is pretty much as I would
have done it. I hope it's indeed AMD's way as well.

Hans.

Second is from 3dilettante B3D forum:

For fun, I'll just assume this is a true representation of a future core, or someone put a decent amount of effort into making this up.
There isn't a good shot of this core and Bulldozer of equivalent quality, but here's what it sort of looks like to me.

The L1 has two sections, separated by a pink section that could be the microcode ROM. There is what appears to be a fetch buffer for both sections, so I am left wondering if this is one big L1 I$ or two.
For the instruction section there are two of everything, save the predecoder, branch predictor, and microcode. It think there's a little pink rectangle below the microcode that is a microcode-related engine, and even this is duplicated.

A single integer core looks to have twice the integer ALUs, twice the AGUs, but the multiplier and divider sections don't look replicated. The physical register file doesn't appear to be doubled. If it is bigger, it's not significant enough to split it into new sections or appear to be more than incremental growth.
The portions of the pipeline related to gathering operands and immediates for each instruction are doubled.
Interestingly, it looks like the rename tables and retire structures are doubled in size.
The table that might have to do with waking up/picking instructions could be bigger, but it isn't doubled.
The odd thing from a single-threaded perspective is that the scheduler logic outside of the tables is either much denser or not much larger. It's also not really necessary to have double the retirement tracking or rename tables for a core whose decoder is still 4-wide--if the core is single-threaded.
Perhaps it isn't.
If the integer pipeline is partitioned into halves, it might make the bypassing network less of a nightmare than expanding it from 2 ALUs and 2 AGUs to 4x4 single-cycle.

I've only had fuzzy BD shots to compare with, which makes the load/store section particularly hard to analyze.
The L1 data cache appears to be different, but not necessarily much bigger in area. If it's not bigger, it may be more aggressively banked. The interfacing logic on the side of the L1 doesn't appear to have more subunits, which might mean the port count hasn't changed. I don't know if its bandwidth has changed, but the fuzzily pictured width of that interface doesn't seem to be much different.
The L/S section appears relatively narrower compared to the sections that did grow, which could indicate it has been slightly modified.
There are a few duplicated/grown structures, which might be queues for loads and stores. My die-shot-fu isn't good enough to know which one is which. The more obviously duplicated structure may be a pair of store queues.

The FP unit appears to have rotated a bunch of components 90 degrees, and doubled the capacity of the register file. The two halves of each bank of registers aren't physically identical. This may be a legacy/full vector set distinction.
For what it's worth, what watchimpress stated is the retire control is duplicated. There were already two banks, one per thread with the original dual-threaded FPU. This could mean it's now able to support four.

I think there is still an upper/lower data path split, but I'm not sure which way is best to handle it.
The units themselves have a double pink line through the middle, which may be a way to separately gate each half.
It may be better to rotate the whole FPU 90 degrees. Instead of it being left:right=Hi:Lo, it's left=register file 0, right=register file 1.
Each half would have its own Hi:Lo split. There seems to be some extra routing going on between the upper and lower halves of each side to permit shuffling between them.
There's a slight break in the symmetry of the left and right sides, however, particularly in the lower right. There may be some special functions that use different hardware there. There is some additional routing in the lower half that could explain how one half could still use whatever special hardware is on the other side.
This may also explain the potentially narrower depiction of the FPU in some slides, which went form 2 FMAC+ 2MMX(one being also FSTORE) to 2 FMAC + 1MMX. The hardware would be mostly the same, but the common case would be that each thread can only see its side of the FPU and other ops that could cross to the other side have the one port doing double-duty.

AMD Vishera launches,finally. Bulldozer done right

2012-10-29T13:51:00.000-07:00

1 year has passed since my last post which covered ,you guessed it,a Piledriver core. I predicted 4.2Ghz base clock (overstated by 5%) and 5% higher IPC( understated by 3% on average,it varies between 5% and 20% depending on workload). So basically I predicted 4.2Ghz Vishera and expected 20% higher performance. What we get is 4Ghz Vishera that is ~15% faster,pretty much what I said minus the higher clock ;). Also Vishera, as we will see later, outperforms Bulldozer core on the same clock in games by a very high 13.5%,a feat I didn't expect! On to the Piledriver launch details then. But first a little bit of history.

AMD promised a lot of things when it comes to long awaited Bulldozer core. On many levels they didn't deliver but on some they did. Now,one year after Bulldozer version1 ,we finally have a "quick fixed" Enhanced Bulldozer(how AMD called it 1 year ago). Does it deliver? Yes it does. On many important levels,this core is what Bulldozer should have been when it launched. But AMD needed something last year and they went with what they have. Now finally,albeit late, the Piledriver delivers. It's faster per clock,consumes less power at the same targeted clock and does this without Resonant Clock Mesh or a smaller node. It's a tick+ in intel's terminology since what it delivers in IPC and clocking is more than what IvyBridge did with a uarchitectural tweaks and a die shrink.

Some relevant links to reviews(there are many reviews, for a complete list go to this topic @ XS where Flanker did a great summary of all the data):

http://www.planet3dnow.de/vbulletin/showthread.php?t=408737
http://www.hardware.fr/articles/880-1/amd-fx-8350-retour-amd.html
http://www.tomshardware.com/reviews/fx-8350-vishera-review,3328.html
http://www.anandtech.com/show/6396/the-vishera-review-amd-fx8350-fx8320-fx6300-and-fx4300-tested

Models summary:

Piledriver die shot:

Here are slides that detail uarchitectural improvements:

And how does it do in reality versus Bulldozer version1 you ask? Look for yourself:
Hardware.fr chart

7.7% average IPC gain in application workloads and 13.5% average IPC gain in gaming workloads. Job well done AMD! This core does work more efficiently AND clocks higher within same power envelope which results in greater power efficiency.

For comparison between 3770K,Thuban,Bulldozer and Piledriver (all @ 3.6Ghz) check planet3dnow review linked above. Piledriver comes really close to 3770K in many real life workloads and offers great bang for the buck.

Average performance in applications:

FX8350 @ stock offers 94.4% of 3770K stock performance for 100$ less. The above is average from many workloads some of which are not multithreaded. A 15% improvement versus 8150 is very good result and is close to what I speculated 1 year ago. FX8150 has very high full core/half core turbo of 3.9Ghz and this is why the difference is not more than 20%. If it ran closer to 3.6Ghz in most workloads(as it doesn't,it's at 3.9Ghz most of the time), the difference between 8350 and 8150 would be >20%.

Gaming performance average:

FX8350 is considerably slower (at stock) than intel parts in selected gaming benchmark suite hardware.fr used(very CPU bound games and Skyrim is one that particularly doesn't like AMD CPUs for some reason so the average is dragged down quite a bit). Still FX8350 does very nicely compared to all other AMD CPUs and now has a respectable score ,basically on par with 3240 i3 and some 15% lower than Quad core Ivy Bridge 3330. This is more than enough level of performance for modern games and unless one plays exclusively those few titles that run bad on AMD hardware(like SC2 or Skyrim), FX8350 will be a great budget gaming processor. Once OCed to ~4.6Ghz which is common for 8350/8320, this chip would be ~18% slower than what 3770K offers in games hardware.fr used,for 100$ less.

In summary of this short post, FX8350 is what AMD promised: a better Bulldozer in every way you can think of. It has considerably higher IPC ( for a tick or a "quick fix"), it clocks higher and does it within same power budget on the same (bad) 32nm GloFo process node. Let's hope AMD brings SR core to FX line and doesn't abandon this market segment like some rumors are suggesting. Even with Haswell on the 2013 horizon I believe Steamroller has a chance of coming ever closer to intel desktop lineup since it massively improves single thread execution ,an area in which AMD still lags intel by a quite a margin. Multithread performance is good now and is very competitive. The last "bad" thing about BD/PD is power draw and this won't be fixed until 28nm node is ready. For those who don't mind about higher power draw (most don't since PC idles 95% the time anyway and difference is zero there), the FX8xxx line is the perfect choice for a mainstream PC desktop user on a budget.

What comes after FX? FX Next

2011-10-26T08:03:00.000-07:00

After not so successful launch of their new flagship desktop processor,AMD started talking up their next chip that will succeed Bulldozer Ver1. Say hello to FX Next ,based on Piledriver core :

Piledriver is supposed to fix certain shortcomings in BDver1 processors. I summed up some of them in my previous blog so I won't reiterate those.
What will AMD have to offer before Piledriver arrives? The following roadmap gives us some clues:

FX8170 is supposedly launching in Q1 2012. It will be based on new (somewhat improved) B3 stepping. Hopefully B3 will be enough to polish speed path issues (if there are any) and bring up clock speed. The rumored 8170 is supposed to run at 3.9/4.2/4.5Ghz clocks. This is a very solid uplift(~7.7% over 8150). Bad news is that there is no "8190" on the current roadmaps and 8170 is supposed to tide AMD over until PD arrives in Q3. That is 2 quarters... Good news is that PD will be overall 10-15% faster than what AMD has at the moment of its introduction (so 8170). This lines up well with rumored ~5% IPC increase over BD with the rest being clock speed.
So:
Q1-Q2 2012: 3.9/4.2/4.5Ghz FX8170
Q3-onward : 4.2?/4.5?/4.8?Ghz FX8280?
Effectively 4.2/3.9=1.07 or 7% clock uplift with PD. Now count in the IPC uplift of 5% or so : 1.07x1.05=1.12 or 12% overall faster than 8170. AMD said 10-15% more x86 performance with PD so this slides right in the middle of this projected figure. How much is this faster than current 8150? 8170 should be around 7% faster than 8150 so 4.2Ghz(base) PD based FX is going to be roughly 20% or so faster than 8150. Not a bad upgrade if you look at it from time perspective : 8 months after BDver1 we will get 20% faster FX part (stock vs stock). It's not unreasonable to expect better OC and thermal characteristics too,so all in all it will be a good "fix" for current BD desktop competitive situation.

PS All info above is my interpretation of available data. I used "best case scenario" above. Real PD core and 8170 may turn out to be totally different than what I speculated. We have seen this happen with BD core. Since back then I also based my predictions on publicly available data coming from AMD(which turned out to be a bit optimistic on their side) , this may happen again with PD and 8170. So take it as it is,just speculation.

Zambezi : 2nd look.

2011-10-13T17:18:00.000-07:00

OK, I have read a lot of reviews now. Some things are clearer now.
I suppose I overreacted a bit in my previous blog. Zambezi is hot ,but overall it's not a slow chip. It performs rather well in MT applications. It does have some weaknesses which AMD must correct. Some of the weaknesses are not solely AMD's fault,but GloFo's too.

So this is what ,in my humble opinion , AMD must focus on in the future ( think Piledriver and Steamroller):
1) First and foremost AMD must invest heavily in relationship with developers. They must hire a brand new team of both young and motivated guys who will literary go out and help developers in order to maximize the potential of Bulldozer design. This first iteration is just that ,first. It has some flaws which AMD will try to fix and hopefully succeed in that task. But underlying design ,which is truly revolutionary , will need GOOD software support in order to give best performance to the end users. This means FMA4,XOP,BMI and the rest will need to be properly supported in future multimedia desktop workloads. Notice I'm speaking about DESKTOP space here. Server is in no such need since recompiling is a norm there.

2) AMD must improve the cache performance,especially L1 and L2 writes. This is a major bottleneck and it shows its ugly face in many workloads. AMD is aware of this and hopefuly Piledriver has at least somewhat better write performance with these two levels of cache. L3 looks fine,even more than that. It is much faster than L3 on Thuban.
They also need to work on improving the FP unit. It may be great in FMA4 stuff but it's much less impressive in legacy SSE or AVX128 workloads. Maybe expanding it a bit and expanding the buffers could help. Single thread performance is not anywhere near what this thing SHOULD be capable of so there must be a bottleneck somewhere since in numerous SIMD workloads it's not faster than K10's single core(and its 128b unit).

3) AMD must twist GloFo's arm very hard and very fast. Not only their 32nm production is bringing many defective Llano parts (which is truly a shame since most of the time GPU is broken and then it's not APU any more), but now they can't brake 3.6Ghz barrier on a design that was SPECIFICALLY DESIGNED FOR CLOCK speed (while it does have some IPC improvements in certain areas too). So original goal set by AMD was 30% clock uplift with the same power draw as previous design. We get this ONLY in limited Turbo mode now. We should have 4.1Ghz 125W stock clocked Zambezi parts with 4.7Ghz half core turbo and 4.5Ghz full core turbo. This Zambezi would effectively be 12% faster than 8150 with same power draw. This Zamebezi would allow AMD to use SMT core affinity scheme and release a patch for windows 7 that would force threads first to modules and not cores. Performance uplift is ranging from 5% to massive 40% in some cases,averaging to around 15-20%,depending on benchmark selection.

So what we need is 95W 3.6Ghz FX8150, 125W 4Ghz 8170 and 4-4.2 Ghz 125W 8270 (Piledriver).
This lineup would hold off SB and IB ,at least in mid and mid-high performance segments,without many problems.

4) AMD should work closely with MS and release a patch to windows scheduler. As in link I've provided above, performance uplift is not a small number but a very nice 15-20%.
Trade-off is power draw though. All is explained well in this great review by harware.fr .

So there you have it. Bulldozer is not what we expected,but it's not a complete failure either. It's a solid chip which will shine in future applications ,which are going for multiple threads. Single core speed ,while still important,is not the main selling point any more. For those who want a good single core performance while having great MT performance (but still slower MT performance than FX8150) ,they can pick 2500K . It's the best chip by intel currently from perf./$ POV. 8150 is not as good but very close! It needs 10% shave from it's MSRP and AMD may sell a sh*t load of these things :).

Zambezi launched. 2 words : hot and slow .

2011-10-12T08:15:00.000-07:00

How else to describe AMD's latest "high-end" desktop CPU? Well 2 words are enough : hot and slow. Nuff said. You can find reviews via google,best one is definitely lost circuits one:

http://www.lostcircuits.com/mambo//index.php?option=com_content&task=view&id=102&Itemid=42

I'm going to quote the LS author MS since he summed it up great:

Final Thoughts
Bulldozer has been in the works for so long that I don’t even remember when was the first time I heard about it. The concept, at first somewhat odd, gradually started making sense but sometimes these things happen by assimilation. Or, too many geeks who are “in the know” really knew that this was not only a great but a grand design. And who was I to doubt them?
Still, all things considered, there was still more than a shadow of a doubt. Especially when Intel re-introduced HyperThreading and got enormous mileage out of it – for the cost of essentially nothing in terms of real estate which directly translates into cost per die. But we were told over and again that none of this would make sense in light of the analyses performed by AMD’s engineering team. And now we are supposed to believe that Zambezi was designed as a direct competition to the Core i5. That was not a question but a statement.
Of course, this begs the old question, how predictable is performance on a new design? Apparently, it is hit and miss and in so far, my argument still stands, even if it is against the personal religion of some of the decision makers at AMD. This is at the end of a frustrating week, trying to find that one application that would justify buying an FX processor.

Good luck AMD,you are going to need it :( .

Now a bit of fun :) (found it on amdzone) :
http://www.f150online.com/forums/off-roading/395038-stuck-work-pic.html

so this loader gets stuck, then other dozer comes to help, then he gets stuck coming out, so another dozer comes over and pushes him out ,hen gets stuck himself and in-turn pushed out by the cat dozer (first dozer stuck. see a trend? i got fed up so, i go swimming for the winch cable (it was under over 2ft of mud and water) and pull it out with my work truck. done.

Repost : Crazy blogger with an ego problem

2011-09-16T13:04:00.000-07:00

Due to popularity of this one single post I will re-post it again ^^. Since I was notified via PM on XS forum about the lies and crap he is writing about me and others,I will be re-posting the truth about this guy. "The blogger with mental disorder" will be exposed again,and again if needed Enjoy :).

Many of you have already heard about the notorious blogger from Czech republic. A guy that goes by the username "OBR". Well in his latest posts he went completely overboard with insults and bad mouthing,insulting groups of internet forum users,accusing many folks of lying(mostly AMD's people),some guys that he even personally knows, AMD's PR department,AMD's John Fruehe - the guy that stands behind the server division and posts occasionally on the tech forums, etc.

Now some forum posters found this very amusing ,especially knowing that OBR himself admitted he lied and purposely faked Zambezi results and fed the fake results to many IT websites.They all took the results seriously and posted them citing "genuine sources". Then the FUD train started to roll and we have what we can call today a mess. This guy is a pure hypocrite.
A picture is worth a thousand words:

SB-E 3690X benchmarked by THG,Bulldozer controversy continues

2011-09-15T11:56:00.000-07:00

Looks like THG got a pre-production SB-E system and run some tests on it. Nothing spectacular compered to 990x/980x,around 10% faster . Still pretty good improvement for a same core count part.

On the other hand ,controversy regarding Zambezi (desktop Bulldozer part) continues. We have some new data that points at in between 2500K and 2600K multithread performance and abysmal single thread performance. Nothing is final yet,but don't expect some sort of SB killer from Zambezi. Even in its strongest performance department which is multithread performance,it looks it will even fail to beat X6 Thuban by a decent margin. Performance is indeed just a little better,if better at all. Price is still hard to figure out. AMD plans to charge 250$ ,approximately, for the FX8150. Unless they are just counting on more OC headroom,nothing else warrants this higher price than existing X6 1100T. This is indeed kind of a let down. It turns out that 4 module part is closer to 4 core part with SMT in performance than to a 8 or even 6 core part. Performance,especially in floating point applications is all over the place,ranging to much slower (linpack) to even("8C" FX @ 3.6Ghz vs 1100T in C11.5) to slightly faster (wprime) . This uncertainty when it comes to performance kind of defeats the whole module concept because AMD touted it as much more consistent performance uplift versus intel's SMT approach. As it turns out,it is not so different after all... Good thing about Zambezi is that it will at least clock high. Some reports point to 4.8Ghz as "normal" overclock across 4 modules,on air.

update: I've just read on XS(thanks chew*) that Zambezi will have even higher OC potential than 4.8Ghz. On air(stock cooling),supposedly one can expect 5+Ghz - regular daily use and benchmarking . By chew*:

I think that any info other than what I or AMD have personally offered which is not much if any can be discarded until further notice.

There are still peices to the puzzle missing that I can assure you 99.9% don't have yet regarding CPU rev and bios support and agesa.

To sum up BD facts

BD is physically a 4 core 8 thread part.

It has no coldbug

Samples can bench at 5+ on stock cooler, 6+ on phase change and 8.4 on lhe.

And most important of all SATA works

Like i said before the joke is on that guy we won't name, he was sent intentionally quite possilby the worst chip ever produced. 6.4 on ln2,
or he needs to learn how to OC, 6.4 is my validation speed on phase change......he who laughs last laughs best.............

So with phase change 6+Ghz and with LN2 7+ Ghz and maybe 8Ghz. For water cooling ,I suppose 5.5Ghz is not out of the realm of possibility. So with this latest information in mind ( which is very reliable), Zambezi may be pretty competitive with OCed SB 2600K. Since 2600K reaches around 4.5Ghz-4.8Ghz on good air cooling,Zambezi will have some frequency potential under similar conditions. This may equate to better performance in MT applications for those who actually use their overclocked machines for something useful .

Opterons and Sisoft benchmarks-what does it all mean?

2011-09-11T19:17:00.000-07:00

Ok a small update on sisoft numbers for Opterons.Here is 6282SE and here is 6220 . I'm pretty sure now about following things:

1)Both Opteron sisoft results are real. Some features are turned off though.

2) 6220 part has a correct SIMD throughput,while 6282SE has somewhat inflated number (memory configuration is maybe specced higher there).

3) Both 6282SE and 6220 servers had Turbo off in integer tests. First ran at 2.5Ghz(2x 16C) ,second at 3Ghz(2x8C). Multimedia test uses AVX and gives 11% better score than legacy SSE.

4) The Opterons that will launch very soon will have roughly(2P top bin next gen vs 2P top bin previous gen) : 28-30% higher spec_int_rate score and 33-35% higher spec_fp_rate score. This is 2.3Ghz(2.8Ghz Turbo on all cores for integer workloads) Interlagos Vs 2.5Ghz 12C Magny Cours. In IPC numbers this is ~7-8% higher integer IPC and 8-10% higher floating point/SIMD IPC -all in non recompiled workloads. AVX 256/128brings ~10% more in floating point and FMA brings up to 2x more over AVX,but this is "what if case" and not the norm(we have to wait for applications to be written with FMA in mind). I guess XOP will bring similar speedups to AVX ,10% or maybe more,in integer recompiled workloads.

5) Zambezi's Sisoft results that were leaked are not correct. I don't know whether the Turbo was on or off in that test,but even if it was off the results are ~17-20% lower in integer part than what the opterons show. FP part is more or less correct since Opterons score the same per core and clock, but the test was run on ES platform with 1333Mhz DDR3 memory and unknown BIOS settings. Even if we take the legacy SSE score of 132Mpix/s,which was scored at fix clock of 2.8Ghz (100% sure about this) and correct it for launch clock of FX8150 part we arrive at 170Mpix/s.This is 54% more than 1100T.If we take best for Zambezi then it will be AVX. Now it is 71% faster than 1100T (stock versus stock => 189Mpix/s Vs 110Mpix/s).
Integer throughput is around 35% higher on FX8150 versus 1100T (stock+Turbo Versus stock=>88Gops Vs 65Gops).

I suppose numbers can be higher for desktop version,by about 5% ,compared to the ones I posted in point 5). As for Opterons,I'm 99% sure this will be the speed up that SPEC benchmarks will show. Oh and STREAM(memory BW) will be around 50% faster on Interlagos ,but this is already known.

PS And yes,this means Zambezi shouldn't score lower than Thuban 1100T in Cinebench... At least not according to above. But who knows,anything is possible. Leaks so far point that top Zambezi should get score of around 6pts in C11.5 64bit test. According to sisoft numbers it should get >9pts or close to 9pts.

Bulldozer in October;new leaks point to grim performance picture

2011-09-09T08:10:00.000-07:00

Last week or so has been full of Bulldozer news. It started shipping(finally!) in server segment and we have a confirmation that desktop launch is in Q4,presumably mid October.

We have a few more leaks,none of which point in good direction(performance wise). Whether or not the leaks are genuine and the platform is final, to me it looks like Bulldozer will have a tough time against even previous X6 cores in desktop space. Not only the integer performance is abysmal ,fp/SIMD looks to be equally bad. There still is some hope that things can get better with B2G or whatever the launch stepping will be,but I'm now pessimistic when it comes to Zambezi and its desktop performance. Zambezi X8 @ 2.8Ghz base and 4Ghz Turbo cannot beat X6 1100T @ default (with its own Turbo). This is what some leaks are showing and some guys in the know kinda confirm. The level of performance of FX8150 will then be slightly below 2500K (without SMT,just plain QC Sandy bridge with 4 threads). In single thread workloads even Thuban @ 3.7Ghz(turbo) may end up being faster . I don't know if this is a design decision or some problem in the design,but performance picture does look grim. 6-7 years of development and a lot of R&D money invested and we get something like this?

Blogger with an ego problem

2011-08-25T13:53:00.000-07:00

Many of you have already heard about the notorious blogger from Czech republic. A guy that goes by the username "OBR". Well in his latest posts he went completely overboard with insults and bad mouthing,insulting groups of internet forum users,accusing many folks of lying(mostly AMD's people),some guys that he even personally knows, AMD's PR department,AMD's John Fruehe - the guy that stands behind the server division and posts occasionally on the tech forums, etc.

Now some forum posters found this very amusing ,especially knowing that OBR himself admitted he lied and purposely faked Zambezi results and fed the fake results to many IT websites.They all took the results seriously and posted them citing "genuine sources". Then the FUD train started to roll and we have what we can call today a mess. This guy is a pure hypocrite.
A picture is worth a thousand words:

New Zambezi leaks from Far East

2011-08-22T08:32:00.001-07:00

Check this out:
http://diybbs.zol.com.cn/11/11_100430.html <- supposedly 4C 3.9Ghz Zambezi (with power limit removed?)

Same thread page six:
http://diybbs.zol.com.cn/11/11_100430_6.html
8C 2.8Ghz ,A1 revision?? So the samples seem to work fine(bug-wise) but have been power limited to stay within certain power cap.

Quote from the guy who posted this:

8-core results here

Bulldozer and then check the performance of eight threads can not pay would in 9000, the main reason for the test problems is power supply and motherboard BIOS issue, bulldozers high demand for power, and now the BIOS only 60-70% of shipments performance only.

The logic above is the following: first silicon revisions (A1,B0,B1,B2?) were functioning performance-wise (mostly) as simulations predicted BUT they were very leaky and were gobbling power like crazy.So in order to validate the platform,AMD has used the new feature in Bulldozer design called "power cap" in order to limit the power draw of the CPU and still make it work on latest 900 and 800 series AM3+ boards (check the official Bulldozer blog about this useful feature in Interlagos variant ). The effect of this was that those early Bulldozer samples were throttling down aggressively (voltage and frequency wise) in order to stay within the spec. This resulted in much lower clocks then what applications like CPU-z reported- in the range of 60-70% of specification.Turbo functionality was impaired also.
After the platform is validated, AMD was already producing the B3(C0?) which supposedly has the leakage/power draw problems fixed and clock target was being met within the 95/125W specs( say 3.6Ghz 8150 8C is now hitting all targeted specifications,Turbo included,all within 125W -unlike the early A1/B0/B1 which were gobbling power like crazy with poorer yields). So after all things said,retail will perform 40-60% better than what the latest leak from chiphell showed and what the two images above (kinda) illustrate-if they are genuine that is.

As for the numbers for both 4C and 8C they kinda confirm it's possible. 4C 3.9Ghz allegedly gets 18.9K,8C 2.8Ghz allegedly gets 23K. Scaling is probably not perfect going from 4C to 8C ( i assume around 1.7x,software and hardware limitations):
18.9K / 3.9 x 2.8 x 1.7 =23K. So the scores kinda align. But the problem is that scores are roughly 1.9x higher per core than Phenom... I can't see from where this speedup comes. So take with salt

Opteron 6200 up for preorder,ETA 08-05-2011!

2011-08-01T17:02:00.000-07:00

As you can see here , next gen Opteron 6200 series parts are up for a preorder( 1240+ units already ordered).
Part info: OPTERON 6200 SERIES PROCESSORS 2.1G 16MB 115WT G34 TRAY

Click for larger view

This is not the top model though.There is 115W part that runs at 2.3ghz base clock and 2.7Ghz on all cores with Turbo(and 3.3Ghz for half cores/one core active). This one will have 35% higher throughput in HPC workloads than 2.5Ghz 12C Magny Cours we have today.
Enjoy!

2011/2012 Clash of the CPU Titans : SB,SB-E,Zambezi,Komodo

2011-07-20T01:43:00.000-07:00

Update: some new leaks have occurred on zol.com.cn,so I have included them just for fun.New leaked clock speeds are a bit unrealistic IMO.

Since I've already speculated enough about Zambezi,why not make a small table with my estimates for desktop performance that we can expect from intel and AMD's chips in 2011/2012.
We have quite a few contenders:Nehalem 4C,Westmere 6C,Sandy Bridge 4C,Sandy Bridge E (6C and maybe 8C),Zambezi 8C/6C and Komodo 10C. Some of these are available now,some will be soon and some will be available in Q1 2012.
Points in the chart are based on hardware.fr testing results and are consistent across few generations of the chips.


Click for larger view

Some of the CPUs are not on public roadmaps ,like 2800K ,Zambezi 8170(3.8Ghz?) and 8C SB-E for desktop.I still included these since they may launch eventually.
As can be seen,I expect pretty even fight in desktop segment with intel having a slight lead with SB-E until Komodo launches. In mainstream and performance segments,Zambezi 8C/6C and SandyBridge will be logical choices while Westmere 6C is going to be too much pricey for what it offers.

On zol.com.cn we have 3 new leaked images of what is supposed to be AMD's Zambezi roadmap all with clockspeeds,stepping info and time-to market .Take with salt of course.

If these turn out to be real(highly unlikely), corrected numbers for Zambezi in the estimated performance chart above are :
8C models - Zambezi 8C 8100 3.5/4Ghz 220pts, Zambezi 8C 8110 3.6/4Ghz 223pts ,Zambezi 8C 8120 3.7/4.2Ghz 232pts, Zambezi 8C 8130P 3.8/4.2Ghz 235pts ,Zambezi 8C 8150P 4/4.5GHz 249pts ,Zambezi 8C 8170P 4.2/4.7Ghz 261pts . Models in red will launch in Q3.

6C models- no data on clock speed
4C models- no data on clock speed

If somehow AMD manages to pull off these frequencies for base and Turbo then not only Bulldozer will be impressive ,the wait for it(with all the delays) will be well worth it.It will be the top performance chip,beating even SB-E cores,Komodo will not be needed for this feat.But ONLY if the sky high clocks are correct,which is not very likely to happen.

Bulldozer errata document points to Turbo core and cache issues in B0/B1

2011-07-20T00:32:00.000-07:00

Looks like someone from Far East leaked the errata document that points to possible reasons why we had so poor performing B0 and B1 samples in the wild. Since the original source(forum post on ZOL) from China is gone here is a post by Fellix @ Beyond3d forum.

As I have speculated before,in my original 2 blogs about Zambezi ES,we have some Turbo core issues (among other things). Good news is that the launch stepping has everything working properly and is on track for September launch.

My Zambezi desktop performance estimate

2011-07-18T06:58:00.000-07:00

Disclaimer: everything written here is pure speculation by me based on what we already know about past and future AMD cores

Update : corrected some wrong figures towards the end of the post
Update #2: put the final estimates in concrete numbers,for all Zambezi models
Update #3: if you want to see my estimate for all desktop chips in 2011/2012,I wrote a new blog covering this.

There has been a lot of rumors and fake data about Zambezi lately.One "blogger" seeded many websites with his rigged Zambezi results and had practically spread massive amount of FUD.Maybe he has some agenda? Anyway,I will try to dissect a few public statements and see what kind of performance levels we can expect from Orochi design in client(desktop) workloads.

Server Vs Desktop performance targets

One "bulldozer" module.Note the shared and dedicated parts.

First thing that comes to mind when someone says "bulldozer performance" is AMD's server division statement of "50% more throughput performance than previous 12C MC products". Looking back in the past(Barcelona) and knowing the difference between server and client workloads,we can say with great certainty that those (server) figures are not representative of desktop performance. Server is all about throughput,where more cores usually scale nicely and where memory BW matters a lot. Interlagos ,a server product, will have 16 "Bulldozer" cores,grouped in pairs and arranged in so called modules(module is AMD's term that means "an optimized dual core" and it is a building block of Orochi design).It will be 2x8C design,a so called Multi Chip Module(different from AMD's "module" term) product,consisting of 2 Orochi dice linked together to create a 16C product.Since both Orochi dice are supporting 2 channel integrated mem. controller,this will give a 16C interlagos a total of 4 memory channels,2 per 8 core die. MCM technique gives AMD an opportunity to better match the cores that have similar real world power/perf. characteristics and cut the costs at the same time(imagine monolithic Interlagos with huge 4 channel IMC and 16cores on a massive 600+mm^2 die,yikes!- now compare it with 2 x ~290mm^2 for MCM Interlagos).


Concept behind one Orochi die.4 modules mean 8 cores.Interlagos will link 2 of these in MCM for a total of 16 cores.

A great picture by Hans De Vries(http://chip-architect.com/). An actual(real) Orochi die shot.4 groups of modules,each of which has 2 cores.Note the die area savings due to "sharing philosophy".Huge L3 cache is partitioned in 4 groups of 2MBs.Each module also have shared L2 cache,2MBs in size.

Back to "50% more throughput" statement.Since this is server statement we can't deduce much about desktop performance from it.We know that even though many server workloads scale nicely with more cores, some server workloads don't scale that well with core count.But we also know that Bulldozer will have very aggressive Turbo Core boost so it will adapt itself to this eventuality: up the clocks by 1Ghz and power/clock gate the idle parts in order to maximize
serial code performance in single or poorly threaded workloads;return from C6 state and clock up to default clock all cores if FPU intensive workloads use up all the cores in a system;clock up by 500Mhz all integer cores if all of them are running integer heavy workloads while FP units are clock gated .

So the "50% more throughput" statement is more of an average of many workloads(both integer and FP and both serial and parallel in nature-mostly parallel though).So with Interlagos we will have 33% more cores(1.33x) ,running at somewhat higher clocks(depending on the nature of workload) and having X% better IPC than Family 10h cores. I say "X% better IPC" because it is unknown by how much will IPC grow and also because we know it will have higher IPC since AMD stated so(it can be even a few % for all we know but it would still be a true statement).

80% throughput performance of CMP approach with much less die area.

This X% better IPC is a variable with Bulldozer,mainly due to 2 reasons.

First is the shared front end for which AMD publicly stated it offers 80% of throughput of conventional dual core
design(a hypothetical conventional Bulldozer dual core done "the old way").


Shared front end in Bulldozer module.

Second is the new integer core design : 2ALU+2AGU with unified integer scheduler and other improvements Vs 3ALU/AGU design with separate math and address schedulers.

First reason (shared front end) will mean that if a Bulldozer(BD) module,which is an optimized dual core,has 100pts on average in a mix of parallel workloads(2 threads),each thread is somewhat penalized .This penalty probably varies a lot and can be as little as 1% or as much as 25%(or even more).AMD listed an average of 80% throughput(25% penalty) but we have to understand that no dual core product out there scales perfectly with more threads.Usually(for non-SMT dual cores) it is around 95% scaling .So essentially BD module is around 19% slower(95/80) due to this penalty but with a much less die area than hypothetical Bulldozer that was to be done "the old way". So each thread on its own (running solo in the module) is up to 19% "stronger" then when both of them run together.
Another thing to note is that sharing is not always bad ;).This is the case of floating point unit,which is shared between 2 integer cores within the module.

BD module's FP unit organization.

When integer cores may have this slight performance penalty ,the FP units that work in SMT mode in BD module may even see the boost from this type of operation. Bulldozer module has a so called FlexFP floating point unit.It consists out of 2 FMAC units that have unified scheduler.Practically we have one FMAC per integer core but note that one integer core can use both if opportunity arises(ie. single threaded SIMD workload).Each FMAC is fused multiply accumulate capable and is 128bits wide. It is estimated that ,performance wise, one 128bit FMAC will be roughly on par with one Family 10h "core" in previous MC products even though FMAC can do either/or ADD,MUL,FMA while one Family 10h core can do one ADD and one MUL (in theory).This is done via core optimizations(new L/S unit,new scheduler,improved reg-reg transfer rate). AMD estimated that 16C Interlagos(~2.5 or 2.6Ghz) will have around 63% better FP throughput performance than 12C 2.5Ghz Magny Cours.How do we know this you may ask?Well following slide is an AMD estimate back from the day when Magny Cours topped at 2.3GHz.

Chart made by HP and AMD in a presentation held back in 2010.All performance figures for Interlagos are estimates.Magny Cours performance based on 2.3Ghz model.

If we correct for the speed bump of 2.3->2.5Ghz that Magny Cours saw in the mean time,the specfp_rate increase that comes with Interlagos(of 1.78x) will be lowered to around 1.63x. To be on the safe side lets say it's around 60% or 1.6x * .So this gets us around ~20% improvement per core with Interlagos(1.6/1.33=~1.2 or 20%). In integer we see AMD estimated 50% improvement versus 12C 2.3Ghz MC ,but after correction for clock speed bump this is down to 38%.On average ,for both integer and fp,according to adjusted projected performance on above chart,Interlagos should give : sqrt(1.38x1.6)=1.485 or close to 50% more throughput than Magny Cours ,as AMD now claims.

*I assumed that Interlagos won't have lower starting clock speed at launch than 12C 45nm MC product(2.5Ghz top model).Interlagos clock speed may end up between 2.4Ghz and 2.6Ghz.

This improvement in fp_rate may be the effect of SMT execution inside the FlexFP.Since both FMACs operate inside the module in SMT fashion,they may see the boost of ~20% ,similar to the boost intel's Nehalem/SB cores see in threaded workloads from intel's own implementation of simultaneous multithreading. Note that with BD this will probably happen in FP heavy workloads that are multithreaded.In single threaded FP heavy workloads,one core can use both FMACs and that is 2x more floating point execution units(both FMACs) in single thread FP usage model.This could lead to very big performance uplifts versus Family 10h.

Thread control/selection in Bulldozer module.Note the SMT organization for FP execution(red boxes,sorry for small image).This helps with hiding pipeline bubbles and may lead to improved FP multithreaded performance.

Putting it all together we have : 50% better throughput performance with 33% more cores(improved cores) and around the same base clock with 500-1000Mhz Turbo on top of this base clock.According to the slide I've linked earlier (that represents AMD's rough performance estimate back in 2010),we have :

-integer throughput
50% higher score than 2.3Ghz MC(90"pts" vs 60"pts"). In order to get to how much will Interlagos score (without the shared penalty) we have to figure out some variables. 1st ,adjust MC results for speed bump : 60x2.5/2.3~=65pts in specint_rate for MC 12C @ 2.5Ghz. Since scores don't scale perfectly with clocks,we have to adjust for ~4.5% (source spec.org and results for 12C MC @ 2.3Ghz and 12C MC @ 2.1Ghz in specint_rate;scaling is roughly equal to 2.2Ghz when we look at the results of 2.3Ghz MC 12C chip so 4.5% correction or 2.3/2.2=1.045). Final adjusted score for 12C MC @ 2.5Ghz : 65/1.045=62.2 pts.
Now we need to estimate the effect of integer Turbo core in Interlagos score. Base is 2.5Ghz(top Interlagos model according to some leaks) ,maximum clock is 3.5Ghz(half cores idle).But for specint_rate we have 500Mhz boost on all integer cores since they are all loaded=> 1.2x or 20% .Again we correct for 4.5% since scores don't scale perfectly with clock speed(1.2/1.045=1.15x or 15% Turbo effect). Sharing penalty is 25% or 1.25x(80% performance of CMP approach) but since we know that usually conventional CMP approach scales less than perfect(~95%),the sharing penalty is around ~19% or 1.19x(95/80). Also of interest is scaling with more cores in spec int rate tests.8C Magny Cours @ 2.3GHz in 4P configuration has 1.4x lower score than 4P 12C Magny Cours @ 2.3Ghz in this test(source: spec.org). This shows us that with 50% more cores we have roughly 40% higher score in specint_rate.With 33% more cores we will therefore have ~24% higher score in specint_rate test,or 1.24x. All summed up ,we get for Interlagos @ 2.5GHz : 90/1.15x1.19/1.24=75.1pts.
Very approximate improvement versus MC per core and per clock in integer workloads: 75.1/62.2=~20%. If we leave 5% for margin of error we get ~14%. If Interlagos launches at 2.6Ghz base clock then the improvement is down to 15% or with error margin at 9% . All very rough approximation of course.

-fp throughput
78% higher score than 2.3Ghz MC(154"pts" vs 86"pts"). In order to get to how much will Interlagos score we have to figure out some variables. 1st ,adjust MC results for speed bump : 86x2.5/2.3~=93.5pts in specfp_rate for MC 12C @ 2.5Ghz. Since scores don't scale perfectly with clocks,we have to adjust for ~4.5% (source spec.org and results for 12C MC @ 2.3Ghz and 12C MC @ 2.1Ghz in specfp_rate;scaling is roughly equal to 2.2Ghz when we look at the results of 2.3Ghz MC 12C chip so 4.5% correction or 2.3/2.2=1.045). Final adjusted score for 12C MC @ 2.5Ghz : 93.5/1.045=89.5 pts.
In FP heavy workloads there won't be any Turbo core available since TDP budget is exhausted . Base is 2.5Ghz(top Interlagos model according to some leaks) ,maximum clock is 3.5Ghz(half cores idle).For specfp_rate we have no Turbo core boost => so 1.0x .
As discussed before,in FP heavy workloads the SMT benefit may come into play. Now we have 8 FlexFP units running 16 threads across 16 FMACs (SMT is done 2way within each module;2 threads run simultaneously on 2 FMACs via unified FP scheduler in FP coprocessor ).So far lets leave this one out and we will return to it later.For final perf. equation SMT benefit is labeled as Y.
Also of interest is scaling with more cores in spec fp rate tests.8C Magny Cours @ 2.3GHz in 4P configuration has 1.27x/1.3x(base) lower score than 4P 12C Magny Cours @ 2.3Ghz in this test(source: spec.org). This shows us that with 50% more cores we have roughly 30% higher score in specfp_rate with Magny Cours.With 33% more cores we will therefore have ~15.3% higher score in specfp_rate test,or 1.15x ,<=this is the effect of 33% more cores in specfp_rate benchmark. All summed up ,with unknown SMT benefit,we get for Interlagos @ 2.5GHz : 154/1.0x/1.15=133pts. To figure out the SMT benefit we divide 133 with the score of MC @ 2.5Ghz which is 89.5 :
133/89.5=1.48 or 48% better per core. Since this may look like a huge jump in performance ,there may be a reason why Interlagos scores so well in FP rate : scaling with more cores is much better than with Magny Cours(which scales not so well in this MT floating point test suite). So if we take the perfect scaling with 33% more cores : 154/1.33=115pts. Now we have 115/89.5=1.28 or 28% better "per core" ,which in turn may be the effect of Simultaneous Multithreading in FLexFP(since each FMAC on its own should be on par with each Magny Cours core,but working in SMT mode we have the boost similar to the boost intel's cores get from their SMT implementation).

Very approximate improvement versus MC per core and per clock in floating point workloads(serial and parallel ): Up to 30% in well threaded(parallel) workloads and more than that(probably >50%) in single threaded(serial) FP workloads. If Interlagos launches at 2.6Ghz base clock then the improvement is down to ~25% "per" core in multithreaded workloads. All very rough approximation of course.

How does all this relate to Desktop performance?

Above I've tried to speculate about how much effect will each aspect of Bulldozer design have on final (server) performance.Since many things are still blurry ,we don't know for sure how high is the core improvement(IPC) relative to Family 10h(K10).It may vary a lot but still it should be higher in the case of Bulldozer. Last March at Cebit event,AMD's John Taylor said in an interview for OCTV that Bulldozer was designed to offer 30-50% more performance within same power envelope as previous design (2:20) (previous design is 125W K10 based 6C Thuban @ 3.3Ghz).Geometric mean of this wide performance range(30-50%) lands at 39.6%. Since I like to use hardware.fr's average chart for performance comparisons, let's see where would Bulldozer land with ~1.38-1.39x better performance than 3.3Ghz Thuban(with Turbo enabled).

Chart looks like this:

38% (average) higher score would put 8C Zambezi at 165.8x1.38=229pts. In the review hardware.fr did when 1090T X6 launched they calculated the effect of 50% more cores in desktop workloads(and effect of Turbo that was really small since in AMD's case it kicks in with workloads that stress no more than 3 cores). So they found out that 1090T X6 @ 3.2Ghz is 24.5% faster than 955BE X4 @ 3.2Ghz. 50% more cores,24.5% higher performance in the chart. Let's see what kind of score we can get if we apply each Zambezi improvement on top of Thuban's base score.

Core count improvement: for Zambezi,this would mean 33% more cores than X6, ~~10.5%~~ 16.7% higher performance in the chart. This would be the "more cores effect" and is as expected because with more cores you get a lot less of performance boost since most desktop applications are not well threaded(they like faster cores,be it IPC or clock or combination).
The Turbo effect in 8C Zambezi is equally hard to estimate. Latest rumors point to following models:

So we supposedly have top 8C model with 3.6GHz base clock and 4.2Ghz Turbo for half active cores(or up to half active cores;if 5th core is activated the max Turbo is lowered to some value below 4.2Ghz). Approximate effect of Turbo in desktop workloads(which are mostly poorly threaded):
geometric mean of 3.6 and 4.2GHz => 3.88GHz or 8% over default clock.This in turn is 14% above Thuban X6 @ 3.4Ghz.I used 3.4 instead 3.3Ghz in order to account for limited Turbo effect Thuban has from its own Turbo Core with 3 active cores. Since Zambezi will usually run above stock and close to the geom. mean value (~3.9Ghz) in most if not all desktop workloads,it's safe to say that 14% or 1.14x is approximate improvement that top Zambezi 8C model will see over Thuban 1100T @ 3.3Ghz .
Next is infamous "IPC" or core improvement.Since I've spent a good deal on this topic in first part of this blog post,I will use the speculated results,although the "more conservative" variants : integer ~10% per core ,FP/SIMD 20% per core.In case of integer,~10% is just an average speculative single core improvement.There is a penalty when both threads run in the module(up to 19%).FP/SIMD benefits from sharing so there is no penalty here,but opposite effect. Geometric average between int and fp is ~14%. I decided to figure in the 0.9x figure as an average penalty factor that is applied to final Zambezi score.
All factors combined: Thubans score x ( 1.167x1.14x1.14x0.9)=165.8x1.364~=226pts in the chart above. Score of ~226 fits quite well with what John Taylor said and that is between 30 and 50% faster than previous AMD design while having the same TDP.If Zambezi really ends up being 38% faster than top Thuban(~229pts) it becomes the fastest desktop chip on the market,posting the same average score as intel's top desktop Westmere 6C product 990x.

My final estimate for 8C Zambezi at 3.6Ghz/4.2Ghz Turbo mode : 36-38% faster than 3.3Ghz 1100T Thuban. As you can see,this is very different from server statement of "50% more throughput than current 12C products",even though the core ratio stays the same between appropriate server and desktop parts and is exactly 33% more cores.Note also that clock speed ratio is even higher in case of desktop Bulldozer models vs Thubans(3.6/4.2 Vs 3.3/3.7) when compared to clock ratio of server BD and Magny Cours parts(more even clock speeds of around 2.5Ghz for both). Still,desktop will see lower increase in performance due to nature of workloads-more serial and less parallel in nature.

In the end,here is a quick estimate for Zambezi 6C and 4C models,assuming same clock speeds for both(3.6Ghz base for top 6C and 4C models):

Top Zambezi 6C 3.6Ghz/4.2GHz with Turbo : ~16.7% slower(effect of 33% more cores) on average than 8C 3.6Ghz/4.2Ghz model(229pts).Approx. chart result : 194-196pts <-faster than 2500K

Top Zambezi 4C 3.8Ghz?/4.4GHz?(based on leaked info above) with Turbo : ~17% slower on average than 6C 3.6Ghz/4.2Ghz model. 17% is a combination of "less cores effect"(/1.24) and more clockspeed effect(x1.05).Approx. chart result : 165-166.5pts <-faster than top end Thuban @ 3.3Ghz

If you have any comments or suggestions,please post them in the comments section.