Deterministic Ethernet & Unified Networking

Deterministic Ethernet for Next-Generation Integrated Architectures for Aerospace Applications (6th and 8th Oct 2015)

2015-09-30T02:08:00.001-07:00

Please join our webcast on deterministic system integration and embedded platform design for next-generation Ethenret-based integrated architectures. We will discuss the following topics:

PART 1: Oct 6th, 2015 - Basic Principles and Standards for Next-Generation Integrated Architectures

Key Mechanisms for Deterministic Performance in Ethernet Networks

hard RT, realtime, soft-time in open and closed systems
deterministic datastreams with QoS and timing guarantees

Deterministic Ethernet Standards for Critical Systems

ARINC664 (AFDX)
SAE AS6802 (Time-Triggered Ethernet)
IEEE TSN (Time-Sensitive Networking / Time-Aware Traffic Shaping)

ARINC664 and TTEthernet (SAE AS6802)

Comparison and Use Cases
Cross-Industry Use Cases - Open and Closed Systems

System architecture design and integrated architectures with deterministic Ethernet networks

IMA (Integrated Modular Avionics) evolution and advanced system integration - Complex IMA vs. Distributed IMA
Cross-Industry applications for Distributed IMA platforms
Models of computation and communication - impact on system architecture design
Embedded virtualization for safety-critical and hard RT systems

How far can we go?: Designing Next-Generation Ethernet-Based Integrated Architectures

PART 2: Oct 8th, 2015 - Embedded Platforms and Design Methodology for Next-Generation Integrated Systems and Distributed IMA

Overview/Introduction - related to Part 1:

What is possible with Deterministic Ethernet standards?
Key Properties of Next-Generation Ethernet-Based Integrated Architectures enabled by Deterministic Ethernet standards

Embedded Platform Design for Integrated Systems and Distributed IMA

SW/HW Integration, Middleware, SW Platforms
Application design methodology
System Complexity Issues and Reduction: Processes and Technology

System design methodology for Integrated Modular Architectures and IMA
Deterministic Network Design and Analysis

Overview network design
Analysis and V&V, network calculus, trajectory methods

Certification aspects for integrated platforms

(your registration is valid for 6th & 8th October 2015 - Part 1&2!)

Deterministic Ethernet (Part 1):
Basic Principles and Standards for Next-Generation Integrated Architectures

Tuesday, Oct 6, 2015
4:00 pm – 5:00 pm (Central European / Berlin-Paris Time - EUROPE)

10:00 am – 11:00 am (Eastern/New York,NY Time - USA)

Deterministic Ethernet (Part 2)

Embedded Platforms and Design Methodology for Next-Generation Integrated Systems and Distributed IMA

Thursday, Oct 8, 2015
4:00 pm – 5:00 pm (Central European / Berlin-Paris Time - EUROPE)

10:00 am – 11:00 am (Eastern/New York,NY Time - USA)

SAE AS-2D Webcast: Deterministic Ethernet, Time-Triggered Systems and Advanced Integrated Architectures

2015-09-21T05:03:00.002-07:00

Join us in our webcast from Seattle SAE AS-2D meeting. Our agenda will discuss the following topics:

Deterministic Ethernet : TTEthernet (SAE AS6802) Capabilities
TTEthernet (SAE AS6802) and ARINC664 Integration and Comparison
System architecture design and integrated architectures with deterministic Ethernet networks
IMA evolution and advanced system integration
Cross-Industry applications for Distributed IMA platforms
Time Triggered Ethernet - Embedded platform design & structure
Models of computation and communication - impact on system architecture design
Embedded virtualization for safety-critical and hard RT systems
System Complexity reduction
System design methodology for IMA-type systems
Overview network design, analysis, V&V, network calculus, trajectory methods
Certification aspects

SAE AS-2D: Deterministic Ethernet, Time-Triggered Systems and Advanced Integrated Architectures

Monday, Sept 21, 2015
1:30 pm – 5:00 pm (Pacific/Seattle,WA Time - USA)

Deterministic Ethernet & Real-Time Design for Critical Applications/IoT

2015-03-20T02:23:00.001-07:00

Cloud computing is a valuable approach for hosting IT applications on a set of shared and interconnected computing resources to optimize costs and utilization of IT resources. Cloud computing does not permit the integration of hard real-time and real-time functions with deterministic performance.

With Internet-of-Things (IoT) in critical and real-time applications, the embedded cloud computing capabilities shall be upgraded to support deterministic operation and robust integration of critical and real-time functions. In parallel, Integrated Modular Architectures and IMA are designed to use less hardware for hosting many integrated real-time functions, sharing common computing and networking resources. In this aspects, the objectives for critical IoT infrastructure, process automation, transportation (aerospace, automotive, railway, ...) and energy systems can converge in the longer term.
This webinar will discuss key technologies, principles and architecture pattens which support the integration of critical functions in larger networked systems, in both closed and open systems, for mixed criticality applications with hard RT functions.

Please join our webinar on "Deterministic Ethernet & Real-Time Design for Critical Applications/IoT" to learn about a framework for design and integration of critical functions in complex integrated systems.

AGENDA:

Embedded Cloud Computing / IoT vs. Cloud Computing
System Architecture Patterns for Embedded Cloud Computing

Models of Computation/Communication (MoCC) and Design Methodology
Networking for Advanced Integrated Systems
Computing for Advanced Integrated Systems
Resource Sharing in Embedded Platform for Safety and Security

Impact on System Architecture Design and Applications

Examples: Integrated Modular Architectures in Transportation (Aerospace, Railway, Automotive), Energy, Industrial IoT ...

Summary: System Architecture Cookbook for Advanced Integrated Systems with Hard RT, Real-Time and Soft-Time Functions
Q&A

AUDIENCE:

System and Software Platform Architects
System Analysts
Embedded Software Team Leads
Advanced Technology Specialist
Advanced Technology VPs
Technical Management - Integrated Systems
Technology Strategists

(NOTE: you will receive webex access links per email a day before webcast!!!)

Deterministic Ethernet & Real-Time Design for Critical Applications/IoT

Wednesday, April 15, 2015
4:00 pm – 5:00 pm (Central Time (Berlin) - EUROPE)

10:00 am – 11:00 pm (Eastern Time (New York) - USA)

Deterministic Ethernet Poll: Wrap-Up

2014-05-13T03:44:00.002-07:00

To be added later ...

Deterministic Ethernet Networking: Why latency and jitter control matter?

2014-05-13T03:39:00.000-07:00

The network determinism can be defined as:
* known end-to-end frame latency
* known end-to-end frame jitter
* known message order

A network which is setup and operated to guarantee max. latency for all logical connections is a "very deterministic" network. In this case only one dimension of communication determinism is covered.

"Very deterministic" networks are sufficent for design of integrated systems based on L-TTA or GALS model of computation/communication (MoCC). Such a network typically can host hard RT traffic for fast control loops only in simple topologies with few logical connections, low bandwidth utilization and flawless (planned) behavior of all network components.

With special precautions and Ethernet swithc mechanisms it is possible to design advanced integrated systems with thousands of deterministic logical links.

a lot of fine-tuning effort and badwdith on modifications.

In comparison, VLANs and priority-based traffic are called "more deterministic" as they do not provide any hard guarantees on traffic performance, but help to increase the probabiulity that highest priority traffic will get through the multi-hop network faster than other traffic. This depends on traffic workload / profile, system topology, and network resource use by different endstations.

, as there are different applications and models of computation/communication (MoCC) which can be covered by those two models.
In critical applications

So one size can fit all applications if it suports

With higher degree of embedded system virtualization with time-critical functions integrated in more or less open systems (e.g IoT).

They represent complementary deterministic capabilities - the communication determinism is defined as:
* known latency
* known jitter
* known message order

A network which is setup and operated to guarantee max. latency for all logical connections is a "very deterministic" network. In this case only one dimension of communication determinism is covered.
This is sufficent for design of integrated systems based on L-TTA or GALS model of computation/communication (MoCC).
Such a network typically can host hard RT traffic for faster control loops only in simpler topologies with few logical connections and a lot of fine-tuning effort on modifications.

In comparison, VLANs and priority-based traffic are called "more deterministic" as they do not provide any hard guarantees on traffic performance, but help to increase the probabiulity that highest priority traffic will get through the multi-hop network faster than other traffic. This depends on traffic workload / profile, system topology, and network resource use by different endstations.

, as there are different applications and models of computation/communication (MoCC) which can be covered by those two models.
In critical applications

Webinar: At a glance – AFDX for Aircraft Data Networks (17th of April 2014)

2014-04-07T23:57:00.005-07:00

In this webinar you will learn about the basics of AFDX (Avionics Full Duplex Switched Ethernet) and its use in modern Aircraft Data Networks.

AGENDA:

basic concepts of deterministic networks
AFDX Introduction: the fundamentals of AFDX networks
benefits of this technology and related aerospace standards
example applications
AFDX Network: Building blocks and services
Q&A led by TTTech's Aerospace Product Manager Ingomar Wenzel

(NOTE: you will receive webex access links per email 3-4 hours before webcast!!!)

At a glance – AFDX for Aircraft Data Networks
Thursday, April 17, 2014
4:00 pm – 5:15 pm (Central Time (Berlin) - EUROPE)

10:00 am – 11:15 pm (Eastern Time (New York) - USA)

Webinar: Deterministic Ethernet Backbone for Asynchronous/Synchronous Networking (15th April 2014)

2014-04-07T01:09:00.000-07:00

Ethernet has a bright future as a deterministic networking technology for time-, safety-, and mission-critical embedded systems and critical infrastructure applications. With right mix of QoS services designers can enhance safety and security of their distributed controls.

Learn more about this webinar here.

(NOTE: you will receive webex access links per email 3-4 hours before webcast!!!)
Deterministic Ethernet Backbone for Asynchronous/Synchronous Networking
Tuesday, April 15, 2014
4:00 pm – 5:00 pm (Central Time (Berlin) - EUROPE)
10:00 am – 11:00 pm (Eastern Time (New York) - USA)

Webinar: Real-Time Platform Design for Advanced Ethernet-Based Integrated Architectures (March 20, 2014)

2014-02-20T04:48:00.000-08:00

The objective of integrated modular architectures is to use less hardware for hosting many integrated real-time functions, sharing common computing and networking resources.
The design of advanced integrated systems requires clean interfacing, layering and partitioning and appropriate system design methodologies.

Please join our webinar on "Real-Time Platform Design for Advanced Ethernet-Based Integrated Architectures" to learn about platform components and general approaches for sustainable design of integrated and modular embedded "cloud" which can host distributed hard real-time and critical functions.

AGENDA:

Generic Platforms for Modular Integrated Architectures
Models of Computation/Communication (MoCC) and Design Methodology
Resource Sharing: Ensuring Hard RT and Real-Time Performance
Resource Sharing: Embedded Platform Safety and Security
Platform Perspective on Complexity and System Integration Capabilities
Integrated Modular Architectures with Ethernet - Design Methodology
Q&A

(NOTE: you will receive webex access links per email 3-4 hours before webcast!!!)

Real-Time Platform Design for Advanced Ethernet-Based Integrated Architectures

Wednesday, March 20, 2014
3:30 pm – 5:00 pm (Central Time (Berlin) - EUROPE)

10:30 am – 12:00 pm (Eastern Time (New York) - USA)

Deterministic Ethernet Networks, Standards and History (12 Feb 2014)

2014-02-12T00:24:00.002-08:00

Ethernet has penetrated different time-, safety-, and mission-critical applications over the last 25 years. We will present on Ethernet evolution, its history in industrial applications and talk about Ethernet standards relevant for design of embedded systems and distributed controls. We will also address differences between mainstream Ethernet and industrial Ethernet variants.

Please join our webinar on "Deterministic Ethernet Networks, Standards and History".

AGENDA:

History: Ethernet in Critical Applications
Overview/Comparison IEEE802.1, industrial RT Ethernet, ARINC664 and SAE AS6802

see Why Deterministic Ethernet?

Capabilities for time-sensitive (rate-constrained) and time-critical (synchronous) communication in Ethernet networks, distributed controls and advanced integrated architecturess
Q&A

(NOTE: you will receive webex access links per email 3-4 hours before webcast!!!)

Deterministic Ethernet Networks, Standards and History
Wednesday, Feb 12, 2014
4:00 pm – 4:30 pm (Central Time (Berlin) - EUROPE)

10:00 am – 11:30 pm (Eastern Time (New York) - USA)

Webinar: Deterministic Ethernet & Highly Available Architectures for Critical Infrastructure Applications, (moved to 31st Jan 2014!!!)

2014-01-03T15:27:00.002-08:00

The development of concepts and key ideas for design of integrated modular architectures for critical infrastructure application has started in early 1980s, with defense and aerospace applications. The objective was to integrate many functions on less hardware and reduce the complexity and system lifecycle costs of critical infrastructure, while ensuring high availability, safety and security for integrated control/protection functions.

Ethernet networks, as a system integration technology of choice, influence the system integration capabilities and system architectures, and enable design of more efficient systems.

Today with IEC61850, integrated systems and Ethernet are becoming a norm for different energy infrastructure applications.

Please join our webinar on "Deterministic Ethernet & Highly Available Architectures for Critical Infrastructure Applications".

AGENDA:

Deterministic Ethernet in Substation Automation

Capabilities for time-sensitive (rate-constrained) and time-critical (synchronous) communication in Ethernet networks

see Why Deterministic Ethernet?

Integrated Architectures: Key Concepts and Evolution

Platform perspective: Complexity and network Capabilities
Impact on system complexity, design, verification and maintenance
IEC61850 Context

Highly Available Architectures Built from Functionally Safe Components

Redundancy vs. Fault-Tolerance vs High-Availability?
Fail-Safe vs Fail-Operational

Embedded Platforms for Deterministic and Highly Available Architectures
Q&A

(NOTE: you will receive webex access links per email 3-4 hours before webcast!!!)

Deterministic Ethernet & Highly Available Architectures for Critical Infrastructure Applications
Friday, Jan 31, 2014
4:00 pm – 5:30 pm (Central Time (Berlin) - EUROPE)

10:00 am – 11:30 pm (Eastern Time (New York) - USA)

History of Real-Time IEEE Ethernet

2013-11-27T14:27:00.001-08:00

Overview

The industry control applications with Ethernet started back in mid-1980s with IEEE802.3 Ethernet bus using CSMA/CD medium access with token passing. Today, switched full-duplex Ethernet dominates the industry Ethernet market, and the networks based on CSMA/CD are phased out. Ethernet-based fieldbuses - the modified and not fully compatible variants of switched full-duplex Ethernet (modified 802.3&802.1) are used in line or ring topologies in high speed control market niches and in low-cost applications which do not require Ethernet switches.

Early Days of Ethernet Bus: 802.3 & CSMA/CD
Ethernet is a set of frame-based network technologies for LAN communications developed since 1980s, but Ethernet has changed significantly over the last 30 years. The advantage of Ethernet standards was always the simplicity and low implementation costs, and broad industry support.

IEEE802 standardization environment has facilitated the process - a "melting pot" environment which enabled selection of promising ideas and disqualification of dead ends.

Ethernet was only one of technologies capable of supporting TCP/IP comunication in LAN networks. There were two "de jure" standards in IEEE802 focusing on LANs:

Token Ring IEEE802.5
Ethernet IEEE802.3

Ethernet, would become the "de facto" standard by mid-1990, and mid-2000, the only IEEE802 standard for LAN networks. IEEE802.4 and IEEE802.5 working groups have been simply disbanded in 2004 and 2008 respectively due to the lack of industry interest.

Ethernet technology has developed gradually from a simple databus technology with a notoriously inneficent half-duplex media access (CSMA/CD), and prevailed over potent (and more deterministic) competitors such as IBM's Token Ring IEEE802.3 by the end of 1990s.

Token Bus Story: 1st Real-Time Industrial Ethernet

Ethernet databus was considered completely unreliable for real-time applications within defined temporal boundaries in 1980s and 1990s.

In order to improve the determinism and reduce congestions, Token Bus IEEE802.4 protocol has been established - it has been supported by General Motors for their industry process control applications. This protocol could imitate some of the positive properties of Token Ring, and minimize shortcomings of Ethernet bus media access CSMA/CD defined in IEEE802.3.

Virtually all real-time Ethernet networks used in process automation from 1990s are based on Token Bus which could operate with Ethernet physical layer and CSMA/CD.

Switched Ethernet: Fast Ethernet and Gigabit Ethernet for Industrial Applications

Rapid change in the networking market can swiftly change the competitive environments in industrial Ethernet. However, significant changes cannot be expected as the IEEE802 Ethernet technology built on IEEE802.3 and IEEE802.1 activities. Ethernet has settled around the following success-drivers and properties which can satisfy the majority of industrial and enterprise networking requirements:

full-duplex Ethernet
star and line topology
100MBit/s

While the star topology minimizes the number of message hops, the store-and-forward buffering in line topology can introduce significant latency for more then 10 hops (approx. 124µs per hop for a full frame). Therefore the industrial automation vendors designed Ethernet-based fieldbuses which can exchange Ethernet frames and use existing physical layer componts.

Ethernet-based Fieldbusses
Ethernet-based fieldbuses improve the real-time performance (communication cycles of min. 12µs) and support the design of switchless automation networks.

Those capabilities are ideal for design of low-cost automation systems with fast real-time performance and without separate switches. A two- or three-port cut-through "switch" is sufficient for every node and can be designed using a simple FPGA or chips provided by TI, Innovasic, Hilscher, IXXAT and others. This portion of industrial market will continue its expansion in industrial automation and motion / drives control, primarily supported by automation companies and PLC OEMs. With growing number of products, this class of modified "Ethernet" networks can speed-up the replacement of traditional fieldbus application domains and creates a "de-facto" standard in selected niches.

Any additional QoS capabilities within IEEE802 can further advance use of Ethenret in hard real-time and integrated applications, however IEEE802 will most probably not be able to make concessions in 802.1 to support summation frames and other changes in MAC for efficent line topologies, as they are not required in high-volume mainstream markets, and do not create business for networking OEMs and semiconductor companies such as Broadcom, Marvell, Cisco, HP, Dell, Huawei and others. This will keep the Ethernet fieldbuses incompatible to switched Ethernet for a foreseable future.

Webinar: Are You Deterministic or Not? Guide for Reducing Complexity in Advanced Integrated Systems (May 13, 2014)

2013-07-26T06:05:00.000-07:00

The objective of integrated modular architectures is to pack many functions on less hardware, and reduce the number of control units, embedded electronics size, weight and power consumption to design of more efficient systems.
Both embedded systems designers and system architects are "wrestling" with increasing complexity of hardware/software integration, and the alignment of different time-, mission-, and safety-critical functions sharing common resources in an integrated system. Additional rework and verification, schedule delays, transient faults in fielded systems / NFF, add costs and risks to many large programs.

Please join our webinar on "Are You Deterministic or Not? Guide for Reducing Complexity in Advanced Integrated Systems" to learn about integrated system complexity reduction approaches.

AGENDA:

Complexity Root-Causes in Integrated Systems
Complexity and (Exponential) Growth of System States:

Time-Driven vs Event-Driven
Synchronous vs. Asynchronous Interfacing
Hard RT vs Real-Time vs Soft-Time vs All-Together
Controlling Key System Interfaces
Controlling Temporal and Logical Behavior

Platform Perspective, Complexity and Network Capabilities
Integrated Modular Architectures with Ethernet
Q&A

(NOTE: you will receive webex access links per email 3-4 hours before webcast!!!)
Are You Deterministic or Not? Guide for Reducing Complexity in Advanced Integrated Systems
Tuesday, May 13, 2014
4:30 pm – 5:45 pm (Central Time (Berlin) - EUROPE)
10:30 am – 11:45 pm (Eastern Time (New York) - USA)

Webinar: Evolution of Integrated Modular Architectures and IMA - The Role of Ethernet Networks (27th August 2014)

2013-07-17T04:34:00.001-07:00

The development of concepts and key ideas for Integrated Modular Architectures and Integrated Modular Avionics (IMA) have started in early 1980s. The objective was to pack many functions on less hardware, and reduce the number of control units, embedded electronics size, weight and power consumption. In aerospace domain this is an essential benefit for design of more efficent aircraft systems.
Hint: Today, very similar concepts emerge today in the field of integrated energy and transportation systems, railway and automotive domain, where many different functions should be integrated using a shared distributed computing infrastructure.

Ethernet networks as a system integration technology of choice influences the system integration capabilities and safety architectures, and enable design of more efficient systems.

Please join our webinar on "Evolution of Integrated Modular Architectures and IMA - The Role of Ethernet Networks"

AGENDA:

Integrated Architectures: Key Concepts and Evolution in Aerospace Domain
Roles and Process in Design of Integrated Systems
Platform Perspective, Complexity and Network Capabilities
Models of Computation and Communication (MoCC) for Integrated Architectures
Capabilities for time-sensitive (rate-constrained) and time-critical (synchronous) communication in Ethernet networks, distributed controls and advanced integrated architectures

see Why Deterministic Ethernet?

Cross-Industry Developments in Domain of Integrated Architectures: Comparing with Aerospace Industry Experiences
Q&A

(NOTE: you will receive webex access links per email 3-4 hours before webcast!!!)
Evolution of Integrated Modular Architectures and IMA - The Role of Ethernet Networks
Wednesday, Aug 27, 2014
4:30 pm – 5:30 pm (Central Time (Berlin) - EUROPE)
10:30 am – 11:30 pm (Eastern Time (New York) - USA)

Webinar: Deterministic Ethernet Backbone for Real-Time Systems (8th April 2015)

2013-06-06T10:55:00.000-07:00

Please join our webinar on "Deterministic Ethernet Backbone for Asynchronous/Synchronous Networking"

AGENDA:

History: Ethenret in Real-Time Applications
Overview/Comparison IEEE 802.1Q, industrial RT-Ethernet, ARINC664 and SAE AS6802 Time-Triggered Ethernet

see Why Deterministic Ethernet?

Capabilities for time-sensitive (rate-constrained) and time-critical (synchronous) communication in Ethernet networks, distributed controls and advanced integrated architectures
Deterministic Ethernet and its influence on system&software architecture
Q&A

(NOTE: you will receive webex access links per email 3-4 hours before webcast!!!)
Deterministic Ethernet Backbone for Real-Time Systems
Wednesday, April 8, 2015
3:30 pm – 4:30 pm (Central Time (Berlin) - EUROPE)
9:30 am – 10:30 am (Eastern Time (New York) - USA)

2012-12-31T09:07:00.000-08:00

Webinar: Deterministic Open Architectures with VPX and Ethernet, 16th Nov 2012

2012-10-12T02:59:00.001-07:00

VPX enables design of rugged modular systems for critical applications. Deterministic Ethernet can be used for VPX backplane and system backbone applications. This enables design of advanced integrated systems and open IMA architectures, which can be developed, integrated, maintained and upgraded at lower costs and in shorter time.

Please join our webinar on "Deterministic Open Architectures with VPX and Ethernet"

AGENDA:

VITA 46 (VPX) Standard and Applications
System Integration and Deterministic Ethernet:
Impact on Embedded Platforms with VPX
Deterministic QoS Layer 2 Services for Backplane and Backbone Ethernet Applications
Use Cases and Impact on System Architectures, Complexity and Application Design

Which application can benefit from technologies and products presented here?

Deterministic Ethernet Backbone
Advanced Integrated Systems - designed for System and SWaP Optimization
Integrated Modular Architectures (IMA) and Vehicle Platforms
Common Core Systems
Payload Integration & Sensor Fusion
High-Speed Distributed Computing
Countermeasures
Mixed Criticality Systems with Fast Hard Real-Time Controls
Complex Cyber-Physical Systems

(NOTE: you will receive webex access links on 15th Nov)
Webinar on "Deterministic Open Architectures with VPX and Ethernet"
Friday, November 16^th, 2012
Time:
07:30 am - 09:00 am, USA Pacific (San Francisco)
10:30 am -12:00 pm, USA Eastern (New York)
04:30 pm - 06:00 pm, Central European (Berlin)

Webinar: Deterministic Ethernet for Safe/Secure Distributed Controls, November 14, 2012

2012-10-08T23:52:00.000-07:00

Please join our webinar on "Deterministic Ethernet for Safe/Secure Distributed Controls"

AGENDA:

Overview/Comparison IEEE 802.1, industrial RT-Ethernet and SAE AS6802 Time-Triggered Ethernet for wire communication

see Why Deterministic Ethernet?

Capabilities for time-sensitive (rate-constrained) and time-critical (synchronous) communication in Ethernet networks & Distributed Controls
Creating Robust Distributed Controls: Safety and security capabilities supported at Network Level
Impact on System Architectures and Application Design

see System Impact: Synchronization and Jitter Control in Ethernet-based Embedded Systems

(NOTE: you will receive webex access links 24 hours before webcast!!!)
Webinar on Deterministic Ethernet for Safe/Secure Distributed Controls
Wednesday, Nov 14, 2012
3:00 pm – 4:00 pm (Central Time (Berlin) - EUROPE)
9:00 am – 10:00 pm (Eastern Time (New York) - USA)

IEEE 802 Plenary Meeting in San Diego, CA

2012-07-18T11:59:00.000-07:00

Discussion on IEEE802.1Qbv Time-Aware Shaper and scheduled (time-driven) traffic ongoing at IEEE802 plenary meeting in San Diego, CA ...

By adding time-driven packets and time-aware shaper, packets with fixed end-to-end latency can be forwarded in multi-hop Ethernet networks.

Right now (18 July 2012) there is an ongoing discussion how scheduled traffic can be integrated and forwarded in the switch, together with best effort and time-sensitive traffic.

Also see Project Authorization Request (PAR)
- http://www.ieee802.org/PARs/2012-03/new-p802-1qbv-draft-par-0112.pdf

... and some background considerations:

- http://www.ieee802.org/3/cfi/0312_4/cfi_0312_4.pdf
- http://www.ieee802.org/1/files/public/docs2012/Qbv-pannell-draft-5C-0112-v03.pdf
- http://www.ieee802.org/1/files/public/docs2012/avb-pannell-gen2-assumptions-0512-v10.pdf

Webinar: Deterministic Ethernet & Advanced System Integration, May 23, 2012

2012-05-16T01:38:00.001-07:00

Ethernet has a bright future as a deterministic networking technology for time-, safety-, and mission-critical embedded systems and critical infrastructure applications.

Please join our webinar on "Deterministic Ethernet & Advanced System Integration"

AGENDA:

Overview/Comparison IEEE 802, avionics Ethernet (AFDX®), industrial RT-Ethernet and SAE AS6802 Time-Triggered Ethernet

see Why Deterministic Ethernet?

Capabilities for time-sensitive (rate-constrained) and time-critical (synchronous) communication in Ethernet networks
Deterministic unified Ethernet: Integration of regular (best-effort), time-critical (synchronous), and time-sensitive (rate-constrained) Ethernet traffic
Impact on System Architectures, Complexity, Embedded Resource Sharing and Application Design

see System Impact: Synchronization and Jitter Control in Ethernet-based Embedded Systems

(NOTE: you will receive webex access links on 22nd May)
Webinar on Deterministic Ethernet & Advanced System Integration
Wednesday, May 23, 2012
5:00 pm – 6:00 pm (Central Time (Berlin) - EUROPE)
11:00 am – 12:00 pm (Eastern Time (New York) - USA)

Webinar: Deterministic Ethernet Backbone & System Integration, 27th April 2012, 09:00am-10:00am Central European Time (Berlin)

2012-04-19T04:36:00.001-07:00

Ethernet has a bright future as a deterministic networking technology for time-, safety-, and mission-critical embedded systems and critical infrastructure applications.

Please join our webinar on "Deterministic Ethernet Backbone & System Integration"

AGENDA:

Overview/Comparison IEEE 802, industrial RT-Ethernet standards and Time-Triggered Ethernet

see Why Deterministic Ethernet?

Capabilities for time-sensitive (rate-constrained) and time-critical (synchronous) communication in Ethernet networks
Deterministic unified Ethernet: Integration of regular (best-effort), time-critical (synchronous), and time-sensitive (rate-constrained) Ethernet traffic
Impact on System Architectures, Complexity, Embedded Resource Sharing and Application Design
Q&A

Webinar on Deterministic Ethernet Backbone & System Integration
Friday, April 27, 2012

WEBEX for Europe/Asia
09:00 am – 10:00 am (Berlin/Vienna - EUROPE)
12:30 pm – 01:30 pm (India)
03:00 pm – 04:00 pm (China)
04:00 pm – 05:00 pm (Japan)

WEBEX for Europe/USA
04:00 pm – 05:00 pm (Berlin/Vienna - EUROPE)
10:00 am – 11:00 am (New York - USA)

Webinar: Deterministic Ethernet & Advanced System Integration, 30th March 2012, 10:00am-11:30am Central European Time (Berlin)

2012-02-24T14:14:00.000-08:00

Ethernet has a bright future as a deterministic networking technology for time-, safety-, and mission-critical embedded systems and critical infrastructure applications.

Please join our webinar on "Deterministic Ethernet & Advanced System Integration"

AGENDA:

Overview/Comparison IEEE 802, avionics Ethernet (AFDX®) and industrial RT-Ethernet standards

see Why Deterministic Ethernet?

Capabilities for time-sensitive (rate-constrained) and time-critical (synchronous) communication in Ethernet networks
Deterministic unified Ethernet: Integration of regular (best-effort), time-critical (synchronous), and time-sensitive (rate-constrained) Ethernet traffic
Impact on System Architectures, Complexity, Embedded Resource Sharing and Application Design
Q&A

Webinar on Deterministic Ethernet & Advanced System Integration
Friday, March 30, 2012
10:00 am – 11:30 am (Central Time - EUROPE)

Zen In The Art Of Ethernet: Time-Critical / Time-Triggered / Scheduled Traffic

2012-02-01T00:08:00.000-08:00

The masters of Zen archery can hit the target from different positions, unaffected by events or body position. When archers shoot correctly, beautiful shooting is realized naturally.

Imagine Ethernet networks delivering messages from A to B with fixed latency and µs-jitter, unaffected by other time-sensitive and best-effort Ethernet traffic. With this capability in every desktop, enterprise and every embedded network switch/bridge/network interface - the point can be reached where Ethernet becomes the Zen artist of deterministic networking.

Expanding Ethernet Capabilities: Low-Jitter Traffic in IEEE802.1

Interesting outcome of discussion on requirements for real-time applications in IEEE802.1 meeting in München, 16-19th January 2012, was the idea of adding time-critical communication capabilities to Ethernet standard. The implementation and design of mechanisms for scheduled time-critical communication, will be discussed in future meetings.

There is a little doubt that future development of IEEE802 will lead to Ethernet networks capable of handling time-sensitive (rate-limited), time-critical (scheduled) and best effort traffic.
Ethernet standard will be able cover all system integration requirements at high-bandwidth, using a shared Ethernet network infrastructure - a deterministic unified Ethernet.

IEEE802 Standards in Critical Applications

In the past, IEEE802 committees were focusing more on audio/video, home and commercial networks, where determinism and robustness were not the primary requirement.
In parallel new QoS Layer 2 services or Ethernet profiles for real-time and safety-critical applications have been developed in other standard organizations such as ARINC or SAE.
Available standards allow handling of time-critical traffic (SAE AS6802), time-sensitive traffic (ARINC664-P7) and best effort traffic in TTEthernet switches designed for deterministic unified Ethernet networking.
With functional integration of real-time functions in different applications, and increasing number of embedded devices and higher robustness requirements, the direction of IEEE802 can abruptly change and provide a standard which would enable convergence of IT and embedded networks, and convergence of standard LAN, low-latency and low-jitter applications.

With pending approval of new Project Authorization Request (PAR) - P802.1Qbv and potential completion of standardization by IEEE in 2015-2016 timeframe, IEEE802 Ethernet could integrate all essential capabilities for design of time-aware queue-draining procedures, managed objects and extensions to existing protocols that enable bridges and end stations to schedule the transmission of frames based on system time. This can further extend the use of Ethernet as a unified network in deterministic systems.

Similar to SAE AS6802 this amendment will provide performance guarantees of latency and delivery variation (jitter!) to enable these applications in an engineered LAN, and also maintain the existing guarantees for the credit-based shaper and best-effort traffic described in IEEE802.1Q.

There is a great opportunity to see mechanisms implemented in SAE AS6802 as a part of IEEE802.1Q, and integrated with time-sensitive and best effort traffic. The key here will be to bring know-how in design of critical networks, communication protocols and robust synchronization. It is about adding a bunch of small things which can make or break the integrated system, in other words support or prevent the spreading of Ethernet in new applications.

Well before this part of Ethernet history is completed, we can only applaud and say "Never Bet Against Ethernet!"

See the presentation on Deterministic Ethernet & Unified Networking!

See the presentation on Robust Clock Synchronization!

IEEE802.1Qbv PAR(Project Authorization Request) References SAE AS6802

7.1 Are there other standards or projects with a similar scope:

Yes, SAE AS6802 (2011-11), Time-Triggered Ethernet

Explain: Time-Triggered Ethernet is a vertical aerospace standard

incorporating material that overlaps parts of 802.1Q, 802.1AS and

this amendment. Unlike AS6802, this amendment integrates scheduled

traffic with the existing credit based shaper and best effort traffic.

We will coordinate our work with the SAE through common membership and

liason.

Zen In The Art Of Ethernet: Time-Critical / Time-Triggered / Scheduled Traffic

2012-01-30T14:36:00.000-08:00

Ethernet: How far can it get?

2012-01-20T13:28:00.000-08:00

The presentation at IEEE802.1 Interim Meeting explains the importance of having Ethernet networking capabilities for robust time-critical services. Scheduled traffic with time-aware buffering enable tight control of jitter in time-critical Ethernet communication. In fact, we emulate circuit switching via packet-switched Ethernet networks and minimize latency. This helps to make Ethernet networks ready for deterministic unified networking.
By covering time-critical, time-sensitive, and best effort traffic, we can integrate critical command and control systems, audio/video, and standard LAN applications. With time-critical QoS Layer 2 services, Ethernet networks can efficiently and natively handle both synchronous and asynchronous communication. Visit "Why Deterministic Ethernet?" for more information.

Therefore Ethernet can cover different applications and can be used as a deterministic networking technology for time-, safety-, and mission-critical embedded systems and critical infrastructure applications. In IT and embedded architectures, time-critical networking services contribute to advances in virtualization of computing and networking resources and influence system lifecycle.

Visit "System Impact: Synchronization and Jitter Control in Ethernet-based Embedded Systems"

As usual, never bet against Ethernet :-) ...

Comparing time-sensitive traffic - IEEE AVB, IEEE DCB and ARINC 664

2011-12-11T15:35:00.000-08:00

There are several rate-constrained QoS standards designed for use in time-sensitive applications. Let's take a closer look on their operation and application domains.

Overview: IEEE AVB, ARINC664, and IEEE DCB
IEEE AVB is a group of amandments to 802.1Q, designed to support audio/video applications over Ethernet. IEEE AVB includes the system synchronization 802.1AS (useful for synchronization and alignment of applications), and 802.1Qat Stream Reservation Protocol, used for setting up AV streams in the network dynamically. Its rate-constrained service is defined in 802.1Qav "Forwarding and Queuing Enhancements for Time-Sensitive Streams".

ARINC 664 has been designed as Avionics Full-Duplex Ethernet, for use in integrated avionics systems, where the determinism and maximum latency must be defined and guaranteed for all virtual links (VL). There is no synchronization capability in ARINC 664. ARINC 664-Part7 focuses on rate-constrained communication. This standard does not allow use of best-effort traffic. ARINC664 is designed for operation in closed redundant networks designed for critical applications.

IEEE DCB is a group of amandments to 802.1Q, designed to support lossless low-latency communication and integration of SAN and LAN networks. It was designed as a first step toward convergence-enhanced Ethernet networks. The communicaton rate in this standard is not based on the temporal control of latency - it balances sender output by signalling switch buffer status for specified traffic class. For high-priority treffic classes this will result in the lowest possible communication latency. In addition, every link has also limited bandwidth, which can be dynamically updated. High-priority IEEE DCB traffic can have exceptional latency performance ocassionaly, but it is not focusing on bounded latency.

Prerequisites for reliable operation of time-sensitive communication with latency bounds
Rate-constrained services rely on statistical multiplexing and there are several considerations which must be fulfilled by network devices in order to model this type of traffic properly, so that the model fits the network's real-life behavior. This is essential for implemetation of Ethernet network devices used in time-sensitive applications, otherwise the temporal properties cannot be guaranteed.

The following considerations should be taken into account when designing switches and network devices:

store-and-forward switches
constant switching (packet forwarding) latency independant of traffic profile and buffer memory use
shaped traffic with maximum allowable bandwidth use and strictly defined periodicity
robust policing and/or shaping to prevent temporal misbehavior
lower-priority (or prohibition!) for any time-insensitive traffic

Traffic shaping or policing?
Traffic shaping is required on sender side in any case, and policing and/or shaping are required on network devices (switches, NICs). Depending on the use case specific properties can be emphasized.

In general policing at incoming ports will ensure that any temporal deviations are detected immediately, while shaping on incoming ports will add some delay before the buffers are overflowed or packets are dropped.
Traffic shaping can "polish"(reduce) the jitter in a message stream, but it increases the total stream latency.
In order to reduce the stream latency, shaping can be used only at traffic source, and the policing can be applied on every switch. In open networks, shaping and policing may be required to guarantee temporal boundaries. In closed networks the traffic shaping can be conducted only at the sender, to simplify design of switching network devices.

More information on traffic policing and shaping can be found here.

Rate-constrained traffic in IEEE AVB
The objective was to have a network which can guarantee max. 2ms delay over 7 hops (switches). This standard allows a portion of bandwidth to be used by best effort traffic, assuming it is not influencing time-sensitive traffic. 802.1Qav introduces new traffic classes which are higher priority than other traffic, and guarantees maximum latency of 125µs (CLASS A) or 250µs (CLASS B) per hop.

While egress (outbound port) traffic shaping adds latency, it also reduces jitter and differences between maximum and minimum latency oscillation.

Rate-constrained traffic in ARINC 664-P7

ARINC664 standard simply assumes that all virtual links are a part of "equal" traffic class, and the standard does not allow lower-priority traffic classes (e.g. best effort traffic). However, it still uses virtual link prioritization (not a traffic class prioritization!), just to ensure correct statistical multiplexing, temporal behavior and packet scheduling of virtual links. Traffic shaping is conducted only once on the packet source (sender).
ARINC664 (AFDX) uses traffic policing on inbound ports for every virtual link separately and drops packets violating the prescribed periodicity. Bandwidth Allocation Gap (BAG) with periods of 1, 2, 4, 8, ... 128ms and maximum defined message size for each period. The policing ensures that all the network traffic (VLs) can arrive to recepients within the given bounded latency, as planned at design time, independant of the virtual link (VL) property violations on the path to the recepient. The policing ensures that the temporal performance for VLs is correct from the source to the target, otherwise the packet is dropped.

Different variations of ARINC664-P7 (AFDX) with improved real-time behavior can be defined by limiting the number of endsystems (nodes) in the system, and by limiting messages size and minimum periodicity to e.g. 500µs and 250µs.

The distinctive feature of this Ethernet standard used in avionics applications is that it requires redundant communication, and takes the first valid message from two redundant virtul links (VLs) passing through redundant paths. This means that higher layers need to take care of message "generations" and adjustments of channels, which leads to slightly different temporal behavior of channels in redundant and non-redundant network operation.

Bandwidth use and Efficency: IEEE AVB, ARINC664, and IEEE DCB
Time-sensitive asynchronous communication can safely reach upto 20% of bandwidth use without violations of guaranteed maximum latencies. With bandwidth use above 25-30%, the latency will start quickly growing above prescribed limits (e.g. 250µs per hop in AVB, in ARINC664-P7 the specified maximum latency for configured virtual links should be increased to avoid packet loss). The side effect in both cases is that the switch (bridge) in this requires large amount of buffer memory to avoid packet losses. The longer the maximum latency and the need to avoid dataloss, the larger packet buffer memory will be required.
So this is a trade-off with different parameters. In real applications, only a fraction of bandwidth will be used to enable updates, system growth, extensions and updates.

In IEEE DCB, this effect will not exist as there is a mechanism for dynamic shaping of source traffic in case the buffer memory is filling to fast. It is clear that the latency of lower priority packet streams will rise, but the packets will not be lost. While there is no time-sensitive component in DCB traffic, there will be some topology and line speed dependancy.