SR latch

noreply@blogger.com (IC Designer) — Wed, 10 Dec 2008 11:07:00 +0000

Latch is one of the storage device because it can hold data. Latch has two stable states, either its output is at high-state or at low-state. Therefore it is categorized as bistable sequence circuit. In analogy, latch can be viewed as a see-saw diagram below. From the diagram, it has only two stable states which are state1 when set is asserted and state2 when reset is asserted.

bistable states

The most basic and fundamental latch is SR latch. SR latch has two types, they are asserted-high SR latch which is formed by NOR gate and asserted low-SR latch which is formed by NAND gate as shown in the diagram below:

NOR type SR Latch

NAND type SR Latch

Both the latches have SET (S) and RESET (R) input pins but the Nand type SR latch has bar lines above the S and R pins, indicating they are low assertion. The Q and Q are latch outputs, which Q or Q' is always in opposite of the output Q. The characteristic table of SR latch is shown as below:

Characteristic table of SR latch

This table is applicable to both Nand type and Nor type SR latches. SR latch has 3 operating modes, they are hold, reset and set mode. The Qn+1 is to represent the next state of SR latch output while Qn is the current state of SR latch output.

When the SR inputs are 00, the latch is in HOLD mode and maintain its next-state output as Qn.
When the SR inputs are 01, the latch is in RESET mode, hence the next-state output is low, 0.
When the SR inputs are 10, the latch is in SET mode, hence the next-state output is high, 1.
When the SR inputs are 11, what will the output to be? (think...).

By refering to the NOR type (NAND type) circuit diagram, the next-state outputs Q and Q becomes low (high). Therefore this circumstance is contradictory to the statement that Q is always in opposite logic of Q. In other words, this condition violates the equation of Q=not(Q) and thereby this state is not allowed!
The other reason is that it is quite unlikely to insert both the inputs at the exact same time. One of the S or R signal will be arrived earlier.

The symbol of the SR latches are given as below:

NOR-type SR latch (generic SR latch)

NAND-type SR latch

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Could you convert SR latch to become gated SR latch or clocked SR latch? How?
Could you distinguish the diferences between latches and flip-flops?

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NOTE:

NAND type SR Latch (the S and R are without bar)

There are some other reference books use different terminology for NAND type SR latch as shown in the figure above. From the figure, the SET (S) and RESET (R) are without bar as compared to the previous figure. Therefore the characteristic table as shown in table below is different from the previous table, which the sequence is inverted. In the other way, you could treat logic low to assert and logic high to deassert the latch. For example, if S=0, R=1, thereby the next-state output is logic 1 or the latch is in set mode.

Characteristic table of NAND type SR latch

3-bit Synchronous down counter with JK flip-flops

noreply@blogger.com (IC Designer) — Mon, 08 Dec 2008 03:23:00 +0000

This tutorial shows how to design a 3-bit synchronous down counter with JK flip-flops.

Step1:
Construst the state table as below:

State Table

It is clearly that the count-down function has 8 states. In other words, the design is a MOD-8 counter.

This state table does not follow the sequence from low (000) to high (111) but it does follow with the description function of count-down function. It might lead to mistakes when constructing Kmap.

Step2:
Construct JK excitation table since JK flip-flops are used in this design:

JK Flip-Flop

In order to do that, the characteristic of JK flip-flop must be completely comprehended. The diagram below shows the JK flip-flop characteristic, which has 4 modes.

JK Flip Flip Characteristic Table

JK flip-flop is in holding mode and toggle mode when the JK inputs are 00 and 11 respectively. If JK inputs are 01, JK flip-flop is in reset mode, while the inputs are 10, JK flip-flop is in set mode. It behaves almost like SR flip-flop but JK flip-flop has toggle mode.

Excitation Table

You must know how to translate JK characteristic table to JK excitatation table as shown in the table above. It is very crucial to start a design with JK flip-flops.

In what condition, the first row of excitation table 0-->0 is met? By refering to JK charateristic table, the condition can be fulfilled by first and second rows of characteristic table, which JK inputs are 00 and 01. Hence, the J input must be "0" and K input must be "d" (don't care) in the excitation table.

Applying the same concept, JK inputs are "1""d" for the transition from 0 to 1 because of row 3 & 4 of JK characteristic table. (row 4=toggling mode)

JK inputs are "d""1" for the transition from 1 to 0 because of row 2 & 4 of JK characteristic table.
JK inputs are "d""0" for the transition from 1 to 1 because of row 1 & 3 of JK characteristic table.

Step3:
Construct the state table with corresponding excitation table:

With the information from JK excitation table, the state table with corresponding excitation table can be constructed as shown in the first diagram.

State Table and Corresponding Excitation Table (d=don't care)

NOTE: state table only states out the transition from present state to next state without corresponding excitation table. In short, it consists of the first and second columns of the above diagram.

Step4:
Build Karnaugh Map or Kmap for each JK inputs:

Kmap

It will be wise if the present state of the state table follows correct sequence from low (000) to high (111) as the diagram below to avoid silly mistakes happen when transfering from state table with corresponding excitation table to the Kmap. Mistakes do happen!!

state table with correct sequence

Step5:
Draw the complete design as below:

3-bit synchronous down counter with JK flip-flop circuit

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Could you design a 4 bit synchronous down counter with JK flip-flop circuit?

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The answer as below:

4-bit synchronous down counter with JK flip-flop

Could you furhter reduce the circuit complexity? how?

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The circuit can be reduced to diagram below:

Reduce the circuit from 3-input AND gate to 2-input AND gate and the routing is much simple.

Simplified 4-bit synchronous down counter with JK flip-flop

What are the advantages and disadvantages for this circuit that has 2-input AND gate as compared to the previous design which has 3-input AND gate?

Tips: The answers can be apparent if you think the counter with large bits, eg: 16 bit synchronous counter.

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Digital System Tutorial

SR latch

3-bit Synchronous down counter with JK flip-flops