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Norton Design of Machinery 4th Edition PDF Free Download

aslam.obf@gmail.com (Unknown) — Wed, 13 Jul 2016 21:32:00 +0500

Norton Design of Machinery

Machine is designed to help human activity by consuming energy into mechanical energy. Machine has its own mechanism system. It is called as machinery that involved kinematics and dynamics in its process in manufacturing or industrial field. To understand about machine, we should know about design of machinery topic. This subject is intended as two semester course.

ABOUT THE AUTHOR

Robert L. Norton earned undergraduate degrees in both mechanical engineering and industrial technology at Northeastern University and an MS in engineering design at Tufts University. He is a registered professional engineer in Massachusetts and New Hampshire. He has extensive industrial experience in engineering design and manufacturing and many years experience teaching mechanical engineering, engineering design, computer science, and related subjects at Northeastern University, Tufts University, and Worcester Polytechnic Institute. At Polaroid Corporation for ten years, he designed cameras, related mechanisms, and high-speed automated machinery. He spent three years at Jet Spray Cooler Inc., Waltham, Mass., designing food-handling machinery and products. For five years he helped develop artificial-heart and noninvasive assisted-circulation (counterpulsation) devices at the Tufts New England Medical Center and Boston City Hospital. Since leaving industry to join academia, he has continued as an independent consultant on engineering projects ranging from disposable medical products to high-speed production machinery. He holds 13 U.S. patents. Norton has been on the faculty of Worcester Polytechnic Institute since 1981 and is currently professor of mechanical engineering and head of the design group in that department. He teaches undergraduate and graduate courses in mechanical engineering with emphasis on design, kinematics, and dynamics of machinery. He is the author of numerous technical papers and journal articles covering kinematics, dynamics of machinery, carn design and manufacturing, computers in education, and engineering education and of the text Machine Design: An Integrated Approach. He is a Fellow of the American Society of Mechanical Engineers and a member of the Society of Automotive Engineers. Rumors about the transplantation of a Pentium microprocessor into his brain are decidedly untrue (though he could use some additional RAM). As for the unobtainium* ring, well, that's another story

Driver Adaptation to Information and Assistance Systems

aslam.obf@gmail.com (Unknown) — Fri, 22 Jan 2016 21:38:00 +0500

Driver Adaptation to Information and Assistance Systems

Probability, Statistics, and Decision for Civil Engineers, PDF Free Download

aslam.obf@gmail.com (Unknown) — Fri, 29 Aug 2014 02:02:00 +0500

Designed as a primary text for civil engineering courses, as a supplementary text for courses in other areas, or for self-study by practicing engineers, this text covers the development of decision theory and the applications of probability within the field.

Preface

This book is designed for use by students, practitioners, teachers, and researchers in civil
engineering. Most books on probability and statistics are intended for readers from many fields, and
therefore the question might be asked, “Why is it necessary to have a book on applied probability and
statistics for civil engineers alone?” Further, within civil engineering itself, we might ask, “Why is it
reasonable to attempt to write to an audience with such widely varying needs?” The need for writing
such a book is a result of the unusual status of probability and statistics in civil engineering.

Although virtually all forward-looking civil engineers see the rationality and utility of probabilistic
models of phenomena of interest to the profession, the number of civil engineers trained in probability theory has been limited. As a result there has not yet been widespread adoption of such models in practice or even in university courses below the advanced graduate level. Indeed, there has not yet been sufficient development of such models to permit a unified probabilistic approach to the many aspects of the strength of materials, soil mechanics, construction planning, water-resource design, and many other subjects where the methods could clearly be useful.

Many departments of civil engineering now require that their students study probability or
statistics. Subsequent undergraduate technical courses, however, usually lack material that draws
upon that study, and this often leaves the student without an appreciation for possible implications of
the theory. Through the use of illustrations and problems taken solely from the civil-engineering field
this book is designed to develop this appreciation for applications. It can serve as a primary text for a
course within a civil-engineering department or as a supplementary text for courses taught in other
departments. The major compromise here was the acceptance of the risk of obscuring or confusing the basic theory in describing the illustrative physical problem. We could have avoided this risk by using only examples dealing with coins, dice, red and black balls, etc., but the desire to develop the ability to construct mathematical models of physical phenomena in civil-engineering applications weighed heavily in favor of professional illustrations.

Students finishing such a professionally oriented probability course may or may not go on to
advanced courses in the theory. This consideration dictated at least an introductory coverage of a
wide variety of material coupled with a thorough treatment of the fundamentals. The kinds of
compromises involved in trying to decide between breadth in subject matter and depth in
fundamentals are obvious. It is unlikely that our many decisions of this kind will be judged optimal by all, or, indeed, by ourselves in time.

8051 Serial communication - Microcontroller Programming and Embedded Systems

aslam.obf@gmail.com (Unknown) — Thu, 11 Apr 2013 15:18:00 +0500

Serial Communication is a form of I/O in which the bits of a byte being transferred appear one after other in a timed sequence on a single wire. Serial Communication uses two methods, asynchronous and synchronous. The Synchronous method transfers a block of data at a time, while the asynchronous method transfers a single byte at a time. In Synchronous Communication the data get transferred based on a common clock signal. But in Asynchronous communication, in addition to the data bit, one start bit and one stop bit is added. These start and stop bits are the parity bits to identify the data present between the start and stop bits.

The 8051 has two pins that are used specifically for transferring and receiving data serially. These two pins are called TXD and RXD and are part of the Port-3 group (Port-3.0 and Port-3.1). Pin 11 of the 8051 is assigned to TXD and pin 10 is designated as RXD. These pins are TTL compatible; therefore they require a line driver to make them RS232 compatible. The line driver chip is MAX232. The MAX232 uses +5v power source, which is same as the source voltage for 8051.

8051 Interrupts Programming - Microcontroller Programming and Embedded Systems

aslam.obf@gmail.com (Unknown) — Thu, 11 Apr 2013 15:03:00 +0500

Interrupt is one of the most important and powerful concepts and features in Microcontroller / processor applications. Almost all the real world and real time systems built around microcontrollers and microprocessors make use of interrupts.

What is Interrupt

The interrupts refer to a notification, communicated to the controller, by a hardware device or software, on receipt of which controller momentarily stops and responds to the interrupt. Whenever an interrupt occurs the controller completes the execution of the current instruction and starts the execution of anInterrupt Service Routine (ISR) or Interrupt Handler. ISR is a piece of code that tells the processor or controller what to do when the interrupt occurs. After the execution of ISR, controller returns back to the instruction it has jumped from (before the interrupt was received). The interrupts can be either hardware interrupts or software interrupts.

Why need interrupts

An application built around microcontrollers generally has the following structure. It takes input from devices like keypad, ADC etc; processes the input using certain algorithm; and generates an output which is either displayed using devices like seven segment, LCD or used further to operate other devices like motors etc. In such designs, controllers interact with the inbuilt devices like timers and other interfaced peripherals like sensors, serial port etc. The programmer needs to monitor their status regularly like whether the sensor is giving output, whether a signal has been received or transmitted, whether timer has finished counting, or if an interfaced device needs service from the controller, and so on. This state of continuous monitoring is known as polling.

In polling, the Microcontroller keeps checking the status of other devices; and while doing so it does no other operation and consumes all its processing time for monitoring. This problem can be addressed by using interrupts. In interrupt method, the controller responds to only when an interruption occurs. Thus in interrupt method, controller is not required to regularly monitor the status (flags, signals etc.) of interfaced and inbuilt devices.

8051 Interfacing to External Memory

aslam.obf@gmail.com (Unknown) — Mon, 14 Jan 2013 00:56:00 +0500

Real-World Interfacing I, LCD, ADC, and SENSORS

aslam.obf@gmail.com (Unknown) — Thu, 27 Dec 2012 03:00:00 +0500

LCD and Keyboard Interfacing

aslam.obf@gmail.com (Unknown) — Mon, 28 May 2012 23:55:00 +0500

8031-51 interfacing with the 8255

aslam.obf@gmail.com (Unknown) — Mon, 28 May 2012 23:30:00 +0500

Real Time Spectrum Analysis

aslam.obf@gmail.com (Unknown) — Sat, 29 Oct 2011 02:11:00 +0500

Fundamentals of Real Time Spectrum Analysis.

A Real Time Analyzer (RTA) is a professional audio device that measures and displays the frequency spectrum of an audio signal; a spectrum analyzer that works in real time. An RTA can range from a small PDA-sized device to a rackmounted hardware unit to software running on a laptop. It works by measuring and displaying sound input, often from an integrated microphone or with a signal from a PA system. Basic RTAs show three measurements per octave at 3 or 6 dB increments; sophisticated software solutions can show 24 or more measurements per octave as well as 0.1 dB resolution.....................

Types

There are generally two types of RTAs:

RTAs employing analog signal processing, and
RTAs employing digital signal processing (DSP).

The main difference between the two types is that the analog RTAs use a series of hardwired, analog bandpass filters to break the signal into frequency bands prior to measuring it. Digital RTAs use digital sampling technology and microprocessor based digital signal processing to perform necessary calculations, such as Fast Fourier Transforms, to perform the measurements and thus do not need analog hardware filters to isolate each frequency band. The digital approach to signal analysis generally yields much higher accuracy and resolution and thus most RTAs currently in production use digital signal processing technology^.Digital signal processing is more cost effective.

Professional Use

RTAs are often used by sound engineers and by acousticians installing audio systems in all kinds of listening spaces: Venues, home theatres, cars etc. The parameters that can be measured are the spectral aspects of sound reproduction caused by effects like resonances and constructive and destructive interference, but not imaging and spatial aspects. In professional audio many systems incorporate an RTA along with a device that also performs equalization. While measuring pink noise or other test tones, such a controller can level out the frequency response by employing a set of adjustments in the appropriate frequency areas according to the system's interaction with the venue's size, shape and construction materials, among other things.

Download | .PDF

Datapath Logic Cells and I/O Cells | Cell Compilers

aslam.obf@gmail.com (Unknown) — Sat, 17 Sep 2011 02:30:00 +0500

Datapath Logic Cells

Suppose we wish to build an n -bit adder (that adds two n -bit numbers) and to exploit the regularity of this function in the layout. We can do so using a datapath structure.

The following two functions, SUM and COUT, implement the sum and carry out for a full adder ( FA ) with two data inputs (A, B) and a carry in, CIN:

SUM = A ⊕ B ⊕ CIN = SUM(A, B, CIN) = PARITY(A, B, CIN) ,	(2.38)

COUT = A · B + A · CIN + B · CIN = MAJ(A, B, CIN).	(2.39)

The sum uses the parity function ('1' if there are an odd numbers of '1's in the inputs). The carry out, COUT, uses the 2-of-3 majority function ('1' if the majority of the inputs are '1'). We can combine these two functions in a single FA logic cell, ADD(A[ i ], B[ i ], CIN, S[ i ], COUT), shown in Figure 2.20(a), where

S[ i ] = SUM (A[ i ], B[ i ], CIN) ,	(2.40)

COUT = MAJ (A[ i ], B[ i ], CIN) .	(2.41)

Now we can build a 4-bit ripple-carry adder ( RCA ) by connecting four of these ADD cells together as shown in Figure 2.20(b). The i th ADD cell is arranged with the following: two bus inputs A[ i ], B[ i ]; one bus output S[ i ]; an input, CIN, that is the carry in from stage ( i – 1) below and is also passed up to the cell above as an output; and an output, COUT, that is the carry out to stage ( i + 1) above. In the 4-bit adder shown in Figure 2.20(b) we connect the carry input, CIN[0], to VSS and use COUT[3] and COUT[2] to indicate arithmetic overflow (in Section 2.6.1 we shall see why we may need both signals). Notice that we build the ADD cell so that COUT[2] is available at the top of the datapath when we need it.

Figure 2.20(c) shows a layout of the ADD cell. The A inputs, B inputs, and S outputs all use m1 interconnect running in the horizontal direction—we call these data signals. Other signals can enter or exit from the top or bottom and run vertically across the datapath in m2—we call these control signals. We can also use m1 for control and m2 for data, but we normally do not mix these approaches in the same structure. Control signals are typically clocks and other signals common to elements. For example, in Figure 2.20(c) the carry signals, CIN and COUT, run vertically in m2 between cells. To build a 4-bit adder we stack four ADD cells creating the array structure shown in Figure 2.20(d). In this case the A and B data bus inputs enter from the left and bus S, the sum, exits at the right, but we can connect A, B, and S to either side if we want.

The layout of buswide logic that operates on data signals in this fashion is called a datapath . The module ADD is a datapath cell or datapath element . Just as we do for standard cells we make all the datapath cells in a library the same height so we can abut other datapath cells on either side of the adder to create a more complex datapath. When people talk about a datapath they always assume that it is oriented so that increasing the size in bits makes the datapath grow in height, upwards in the vertical direction, and adding different datapath elements to increase the function makes the datapath grow in width, in the horizontal direction—but we can rotate and position a completed datapath in any direction we want on a chip.

FIGURE 2.20 A datapath adder. (a) A full-adder (FA) cell with inputs (A and B), a carry in, CIN, sum output, S, and carry out, COUT. (b) A 4-bit adder. (c) The layout, using two-level metal, with data in m1 and control in m2. In this example the wiring is completed outside the cell; it is also possible to design the datapath cells to contain the wiring. Using three levels of metal, it is possible to wire over the top of the datapath cells. (d) The datapath layout.

What is the difference between using a datapath, standard cells, or gate arrays? Cells are placed together in rows on a CBIC or an MGA, but there is no generally no regularity to the arrangement of the cells within the rows—we let software arrange the cells and complete the interconnect. Datapath layout automatically takes care of most of the interconnect between the cells with the following advantages:

Regular layout produces predictable and equal delay for each bit.
Interconnect between cells can be built into each cell.

There are some disadvantages of using a datapath:

The overhead (buffering and routing the control signals, for example) can make a narrow (small number of bits) datapath larger and slower than a standard-cell (or even gate-array) implementation.
Datapath cells have to be predesigned (otherwise we are using full-custom design) for use in a wide range of datapath sizes. Datapath cell design can be harder than designing gate-array macros or standard cells.
Software to assemble a datapath is more complex and not as widely used as software for assembling standard cells or gate arrays.

There are some newer standard-cell and gate-array tools that can take advantage of regularity in a design and position cells carefully. The problem is in finding the regularity if it is not specified. Using a datapath is one way to specify regularity to ASIC design tools.

2.6.1 Datapath Elements

Figure 2.21 shows some typical datapath symbols for an adder (people rarely use the IEEE standards in ASIC datapath libraries). I use heavy lines (they are 1.5 point wide) with a stroke to denote a data bus (that flows in the horizontal direction in a datapath), and regular lines (0.5 point) to denote the control signals (that flow vertically in a datapath). At the risk of adding confusion where there is none, this stroke to indicate a data bus has nothing to do with mixed-logic conventions. For a bus, A[31:0] denotes a 32-bit bus with A[31] as the leftmost or most-significant bit or MSB , and A[0] as the least-significant bit or LSB . Sometimes we shall use A[MSB] or A[LSB] to refer to these bits. Notice that if we have an n -bit bus and LSB = 0, then MSB = n – 1. Also, for example, A[4] is the fifth bit on the bus (from the LSB). We use a ' S ' or 'ADD' inside the symbol to denote an adder instead of '+', so we can attach '–' or '+/–' to the inputs for a subtracter or adder/subtracter.

FIGURE 2.21 Symbols for a datapath adder. (a) A data bus is shown by a heavy line (1.5 point) and a bus symbol. If the bus is n -bits wide then MSB = n – 1. (b) An alternative symbol for an adder. (c) Control signals are shown as lightweight (0.5 point) lines.

Some schematic datapath symbols include only data signals and omit the control signals—but we must not forget them. In Figure 2.21, for example, we may need to explicitly tie CIN[0] to VSS and use COUT[MSB] and COUT[MSB – 1] to detect overflow. Why might we need both of these control signals? Table 2.11 shows the process of simple arithmetic for the different binary number representations, including unsigned, signed magnitude, ones’ complement, and two’s complement.

TABLE 2.11 Binary arithmetic.
Operation	Binary Number Representation
Operation	Unsigned	Signed magnitude	Ones’ complement	Two’s complement
	no change	if positive then MSB = 0 else MSB = 1	if negative then flip bits	if negative then {flip bits; add 1}
3 =	0011	0011	0011	0011
–3 =	NA	1011	1100	1101
zero =	0000	0000 or 1000	1111 or 0000	0000
max. positive =	1111 = 15	0111 = 7	0111 = 7	0111 = 7
max. negative =	0000= 0	1111 = –7	1000 = –7	1000 = –8
addition = S = A + B = addend + augend SG(A) = sign of A	S = A + B	if SG(A) = SG(B) then S = A + B else { if B < A then S = A – B else S = B – A}	S = A + B + COUT[MSB] COUT is carry out	S = A + B
addition result: OV = overflow, OR = out of range	OR = COUT[MSB] COUT is carry out	if SG(A) = SG(B) then OV = COUT[MSB] else OV = 0 (impossible)	OV = XOR(COUT[MSB], COUT[MSB–1])	OV = XOR(COUT[MSB], COUT[MSB – 1])
SG(S) = sign of S S = A + B	NA	if SG(A) = SG(B) then SG(S) = SG(A) else { if B < A then SG(S) = SG(A) else SG(S) = SG(B)}	NA	NA
subtraction = D = A – B = minuend – subtrahend	D = A – B	SG(B) = NOT(SG(B)); D = A + B	Z = –B (negate); D = A + Z	Z = –B (negate); D = A + Z
subtraction result : OV = overflow, OR = out of range	OR = BOUT[MSB] BOUT is borrow out	as in addition	as in addition	as in addition
negation : Z = –A (negate)	NA	Z = A; SG(Z) = NOT(SG(A))	Z = NOT(A)	Z = NOT(A) + 1

2.6.2 Adders

We can view addition in terms of generate , G[ i ], and propagate , P[ i ], signals.

method 1	method 2
G[i] = A[i] · B[i]	G[ i ] = A[ i ] · B[ i ]	(2.42)
P[ i ] = A[ i ] ⊕ B[ i	P[ i ] = A[ i ] + B[ i ]	(2.43)
C[ i ] = G[ i ] + P[ i ] · C[ i –1]	C[ i ] = G[ i ] + P[ i ] · C[ i –1]	(2.44)
S[ i ] = P[ i ] ⊕ C[ i –1]	S[ i ] = A[ i ] ⊕ B[ i ] ⊕ C[ i –1]	(2.45)

where C[ i ] is the carry-out signal from stage i , equal to the carry in of stage ( i + 1). Thus, C[ i ] = COUT[ i ] = CIN[ i + 1]. We need to be careful because C[0] might represent either the carry in or the carry out of the LSB stage. For an adder we set the carry in to the first stage (stage zero), C[–1] or CIN[0], to '0'. Some people use delete (D) or kill (K) in various ways for the complements of G[i] and P[i], but unfortunately others use C for COUT and D for CIN—so I avoid using any of these. Do not confuse the two different methods (both of which are used) in Eqs. 2.42–2.45 when forming the sum, since the propagate signal, P[ i ] , is different for each method.

Figure 2.22(a) shows a conventional RCA. The delay of an n -bit RCA is proportional to n and is limited by the propagation of the carry signal through all of the stages. We can reduce delay by using pairs of “go-faster” bubbles to change AND and OR gates to fast two-input NAND gates as shown in Figure 2.22(a). Alternatively, we can write the equations for the carry signal in two different ways

I/O Cells:

Figure 2.33 shows a three-state bidirectional output buffer (Tri-State^® is a registered trademark of National Semiconductor). When the output enable (OE) signal is high, the circuit functions as a noninverting buffer driving the value of DATAin onto the I/O pad. When OE is low, the output transistors or drivers , M1 and M2, are disconnected. This allows multiple drivers to be connected on a bus. It is up to the designer to make sure that a bus never has two drivers—a problem known as contention .

In order to prevent the problem opposite to contention—a bus floating to an intermediate voltage when there are no bus drivers—we can use a bus keeper or bus-hold cell (TI calls this Bus-Friendly logic). A bus keeper normally acts like two weak (low drive-strength) cross-coupled inverters that act as a latch to retain the last logic state on the bus, but the latch is weak enough that it may be driven easily to the opposite state. Even though bus keepers act like latches, and will simulate like latches, they should not be used as latches, since their drive strength is weak.

Transistors M1 and M2 in Figure 2.33 have to drive large off-chip loads. If we wish to change the voltage on a C = 200 pF load by 5 V in 5 ns (a slew rate of 1 Vns^–1 ) we will require a current in the output transistors of I _DS = C (d V /d t ) = (200 ¥ 10^–12 ) (5/5 ¥ 10^–9 ) = 0.2 A or 200 mA.

Such large currents flowing in the output transistors must also flow in the power supply bus and can cause problems. There is always some inductance in series with the power supply, between the point at which the supply enters the ASIC package and reaches the power bus on the chip. The inductance is due to the bond wire, lead frame, and package pin. If we have a power-supply inductance of 2 nH and a current changing from zero to 1 A (32 I/O cells on a bus switching at 30 mA each) in 5 ns, we will have a voltage spike on the power supply (called power-supply bounce ) of L (d I /d t ) = (2 ¥ 10^–9 )(1/(5 ¥ 10^–9 )) = 0.4 V.

We do several things to alleviate this problem: We can limit the number of simultaneously switching outputs (SSOs), we can limit the number of I/O drivers that can be attached to any one VDD and GND pad, and we can design the output buffer to limit the slew rate of the output (we call these slew-rate limited I/O pads). Quiet-I/O cells also use two separate power supplies and two sets of I/O drivers: an AC supply (clean or quiet supply) with small AC drivers for the I/O circuits that start and stop the output slewing at the beginning and end of a output transition, and a DC supply (noisy or dirty supply) for the transistors that handle large currents as they slew the output.

The three-state buffer allows us to employ the same pad for input and output— bidirectional I/O . When we want to use the pad as an input, we set OE low and take the data from DATAin. Of course, it is not necessary to have all these features on every pad: We can build output-only or input-only pads.

FIGURE 2.32 A three-state bidirectional output buffer. When the output enable, OE, is '1' the output section is enabled and drives the I/O pad. When OE is '0' the output buffer is placed in a high-impedance state.

We can also use many of these output cell features for input cells that have to drive large on-chip loads (a clock pad cell, for example). Some gate arrays simply turn an output buffer around to drive a grid of interconnect that supplies a clock signal internally. With a typical interconnect capacitance of 0.2pFcm^–1 , a grid of 100 cm (consisting of 10 by 10 lines running all the way across a 1 cm chip) presents a load of 20 pF to the clock buffer.

Some libraries include I/O cells that have passive pull-ups or pull-downs (resistors) instead of the transistors, M1 and M2 (the resistors are normally still constructed from transistors with long gate lengths). We can also omit one of the driver transistors, M1 or M2, to form open-drain outputs that require an external pull-up or pull-down. We can design the output driver to produce TTL output levels rather than CMOS logic levels. We may also add input hysteresis (using a Schmitt trigger) to the input buffer, I1 in Figure 2.33, to accept input data signals that contain glitches (from bouncing switch contacts, for example) or that are slow rising. The input buffer can also include a level shifter to accept TTL input levels and shift the input signal to CMOS levels.

The gate oxide in CMOS transistors is extremely thin (100 Å or less). This leaves the gate oxide of the I/O cell input transistors susceptible to breakdown from static electricity ( electrostatic discharge , or ESD ). ESD arises when we or machines handle the package leads (like the shock I sometimes get when I touch a doorknob after walking across the carpet at work). Sometimes this problem is called electrical overstress (EOS) since most ESD-related failures are caused not by gate-oxide breakdown, but by the thermal stress (melting) that occurs when the n -channel transistor in an output driver overheats (melts) due to the large current that can flow in the drain diffusion connected to a pad during an ESD event.

To protect the I/O cells from ESD, the input pads are normally tied to device structures that clamp the input voltage to below the gate breakdown voltage (which can be as low as 10 V with a 100 Å gate oxide). Some I/O cells use transistors with a special ESD implant that increases breakdown voltage and provides protection. I/O driver transistors can also use elongated drain structures (ladder structures) and large drain-to-gate spacing to help limit current, but in a salicide process that lowers the drain resistance this is difficult. One solution is to mask the I/O cells during the salicide step. Another solution is to use pnpn and npnp diffusion structures called silicon-controlled rectifiers (SCRs) to clamp voltages and divert current to protect the I/O circuits from ESD.

There are several ways to model the capability of an I/O cell to withstand EOS. The human-body model ( HBM ) represents ESD by a 100 pF capacitor discharging through a 1.5 k W resistor (this is an International Electrotechnical Committee, IEC, specification). Typical voltages generated by the human body are in the range of 2–4 kV, and we often see an I/O pad cell rated by the voltage it can withstand using the HBM. The machine model ( MM ) represents an ESD event generated by automated machine handlers. Typical MM parameters use a 200 pF capacitor (typically charged to 200 V) discharged through a 25 W resistor, corresponding to a peak initial current of nearly 10 A. The charge-device model ( CDM , also called device charge–discharge) represents the problem when an IC package is charged, in a shipping tube for example, and then grounded. If the maximum charge on a package is 3 nC (a typical measured figure) and the package capacitance to ground is 1.5 pF, we can simulate this event by charging a 1.5 pF capacitor to 2 kV and discharging it through a 1 W resistor.

If the diffusion structures in the I/O cells are not designed with care, it is possible to construct an SCR structure unwittingly, and instead of protecting the transistors the SCR can enter a mode where it is latched on and conducting large enough currents to destroy the chip. This failure mode is called latch-up . Latch-up can occur if the pn -diodes on a chip become forward-biased and inject minority carriers (electrons in p -type material, holes in n -type material) into the substrate. The source–substrate and drain–substrate diodes can become forward-biased due to power-supply bounce or output undershoot (the cell outputs fall below V _SS ) or overshoot (outputs rise to greater than V _DD ) for example. These injected minority carriers can travel fairly large distances and interact with nearby transistors causing latch-up. I/O cells normally surround the I/O transistors with guard rings (a continuous ring of n -diffusion in an n -well connected to VDD, and a ring of p -diffusion in a p -well connected to VSS) to collect these minority carriers. This is a problem that can also occur in the logic core and this is one reason that we normally include substrate and well connections to the power supplies in every cell.

Cell Compilers :

The process of hand crafting circuits and layout for a full-custom IC is a tedious, time-consuming, and error-prone task. There are two types of automated layout assembly tools, often known as a silicon compilers . The first type produces a specific kind of circuit, a RAM compiler or multiplier compiler , for example. The second type of compiler is more flexible, usually providing a programming language that assembles or tiles layout from an input command file, but this is full-custom IC design.

We can build a register file from latches or flip-flops, but, at 4.5–6.5 gates (18–26 transistors) per bit, this is an expensive way to build memory. Dynamic RAM (DRAM) can use a cell with only one transistor, storing charge on a capacitor that has to be periodically refreshed as the charge leaks away. ASIC RAM is invariably static (SRAM), so we do not need to refresh the bits. When we refer to RAM in an ASIC environment we almost always mean SRAM. Most ASIC RAMs use a six-transistor cell (four transistors to form two cross-coupled inverters that form the storage loop, and two more transistors to allow us to read from and write to the cell). RAM compilers are available that produce single-port RAM (a single shared bus for read and write) as well as dual-port RAMs , and multiport RAMs . In a multi-port RAM the compiler may or may not handle the problem of address contention (attempts to read and write to the same RAM address simultaneously). RAM can be asynchronous (the read and write cycles are triggered by control and/or address transitions asynchronous to a clock) or synchronous (using the system clock).

In addition to producing layout we also need a model compiler so that we can verify the circuit at the behavioral level, and we need a netlist from a netlist compiler so that we can simulate the circuit and verify that it works correctly at the structural level. Silicon compilers are thus complex pieces of software. We assume that a silicon compiler will produce working silicon even if every configuration has not been tested. This is still ASIC design, but now we are relying on the fact that the tool works correctly and therefore the compiled blocks are correct by construction .

Types of ASICs

aslam.obf@gmail.com (Unknown) — Sun, 4 Sep 2011 12:54:00 +0500

Types of ASICs

ICs are made on a thin (a few hundred microns thick), circular silicon wafer , with each wafer holding hundreds of die (sometimes people use dies or dice for the plural of die). The transistors and wiring are made from many layers (usually between 10 and 15 distinct layers) built on top of one another. Each successive mask layer has a pattern that is defined using a mask similar to a glass photographic slide. The first half-dozen or so layers define the transistors. The last half-dozen or so layers define the metal wires between the transistors (the interconnect ).

A full-custom IC includes some (possibly all) logic cells that are customized and all mask layers that are customized. A microprocessor is an example of a full-custom IC—designers spend many hours squeezing the most out of every last square micron of microprocessor chip space by hand. Customizing all of the IC features in this way allows designers to include analog circuits, optimized memory cells, or mechanical structures on an IC, for example. Full-custom ICs are the most expensive to manufacture and to design. The manufacturing lead time (the time it takes just to make an IC—not including design time) is typically eight weeks for a full-custom IC. These specialized full-custom ICs are often intended for a specific application, so we might call some of them full-custom ASICs....

We shall discuss full-custom ASICs briefly next, but the members of the IC family that we are more interested in are semicustom ASICs , for which all of the logic cells are predesigned and some (possibly all) of the mask layers are customized. Using predesigned cells from a cell library makes our lives as designers much, much easier. There are two types of semicustom ASICs that we shall cover: standard-cell–based ASICs and gate-array–based ASICs. Following this we shall describe the programmable ASICs , for which all of the logic cells are predesigned and none of the mask layers are customized. There are two types of programmable ASICs: the programmable logic device and, the newest member of the ASIC family, the field-programmable gate array.

1.1.1 Full-Custom ASICs

In a full-custom ASIC an engineer designs some or all of the logic cells, circuits, or layout specifically for one ASIC. This means the designer abandons the approach of using pretested and precharacterized cells for all or part of that design. It makes sense to take this approach only if there are no suitable existing cell libraries available that can be used for the entire design. This might be because existing cell libraries are not fast enough, or the logic cells are not small enough or consume too much power. You may need to use full-custom design if the ASIC technology is new or so specialized that there are no existing cell libraries or because the ASIC is so specialized that some circuits must be custom designed. Fewer and fewer full-custom ICs are being designed because of the problems with these special parts of the ASIC. There is one growing member of this family, though, the mixed analog/digital ASIC, which we shall discuss next.

Bipolar technology has historically been used for precision analog functions. There are some fundamental reasons for this. In all integrated circuits the matching of component characteristics between chips is very poor, while the matching of characteristics between components on the same chip is excellent. Suppose we have transistors T1, T2, and T3 on an analog/digital ASIC. The three transistors are all the same size and are constructed in an identical fashion. Transistors T1 and T2 are located adjacent to each other and have the same orientation. Transistor T3 is the same size as T1 and T2 but is located on the other side of the chip from T1 and T2 and has a different orientation. ICs are made in batches called wafer lots. A wafer lot is a group of silicon wafers that are all processed together. Usually there are between 5 and 30 wafers in a lot. Each wafer can contain tens or hundreds of chips depending on the size of the IC and the wafer.

If we were to make measurements of the characteristics of transistors T1, T2, and T3 we would find the following:

Transistors T1 will have virtually identical characteristics to T2 on the same IC. We say that the transistors match well or the tracking between devices is excellent.
Transistor T3 will match transistors T1 and T2 on the same IC very well, but not as closely as T1 matches T2 on the same IC.
Transistor T1, T2, and T3 will match fairly well with transistors T1, T2, and T3 on a different IC on the same wafer. The matching will depend on how far apart the two ICs are on the wafer.
Transistors on ICs from different wafers in the same wafer lot will not match very well.
Transistors on ICs from different wafer lots will match very poorly.

ASICs Design Flow

aslam.obf@gmail.com (Unknown) — Sun, 4 Sep 2011 12:53:00 +0500

Design Flow

Figure 1.10 shows the sequence of steps to design an ASIC; we call this a design flow . The steps are listed below (numbered to correspond to the labels in Figure 1.10) with a brief description of the function of each step.

FIGURE 1.10 ASIC design flow...

Design entry. Enter the design into an ASIC design system, either using a hardware description language ( HDL ) or schematic entry .
Logic synthesis. Use an HDL (VHDL or Verilog) and a logic synthesis tool to produce a netlist —a description of the logic cells and their connections.
System partitioning. Divide a large system into ASIC-sized pieces.
Prelayout simulation. Check to see if the design functions correctly.
Floorplanning. Arrange the blocks of the netlist on the chip.
Placement. Decide the locations of cells in a block.
Routing. Make the connections between cells and blocks.
Extraction. Determine the resistance and capacitance of the interconnect.
Postlayout simulation. Check to see the design still works with the added loads of the interconnect.

Steps 1–4 are part of logical design , and steps 5–9 are part of physical design . There is some overlap. For example, system partitioning might be considered as either logical or physical design. To put it another way, when we are performing system partitioning we have to consider both logical and physical factors. Chapters 9–14 of this book is largely about logical design and Chapters 15–17 largely about physical design.

Case Study of ASICs

aslam.obf@gmail.com (Unknown) — Sun, 4 Sep 2011 12:50:00 +0500

Case Study

Sun Microsystems released the SPARCstation 1 in April 1989. It is now an old design but a very important example because it was one of the first workstations to make extensive use of ASICs to achieve the following:

Better performance at lower cost
Compact size, reduced power, and quiet operation
Reduced number of parts, easier assembly, and improved reliability

The SPARCstation 1 contains about 50 ICs on the system motherboard—excluding the DRAM used for the system memory (standard parts). The SPARCstation 1 designers partitioned the system into the nine ASlCs shown in Table 1.1 and wrote specifications for each ASIC—this took about three months 1 . LSI Logic and Fujitsu designed the SPARC integer unit (IU) and floating-point unit ( FPU ) to these specifications. The clock ASIC is a fairly straightforward design and, of the six remaining ASICs, the video controller/data buffer, the RAM controller, and the direct memory access ( DMA ) controller are defined by the 32-bit system bus ( SBus ) and the other ASICs that they connect to. The rest of the system is partitioned into three more ASICs: the cache controller , memory-management unit (MMU), and the data buffer. These three ASICs, with the IU and FPU, have the most critical timing paths and determine the system partitioning. The design of ASICs 3–8 in Table 1.1 took five Sun engineers six months after the specifications were complete. During the design process, the Sun engineers simulated the entire SPARCstation 1—including execution of the Sun operating system (SunOS)............

TABLE 1.1 The ASICs in the Sun Microsystems SPARCstation 1.
SPARCstation 1 ASIC		Gates (k-gates)
1	SPARC integer unit (IU)	20
2	SPARC floating-point unit (FPU)	50
3	Cache controller	9
4	Memory-management unit (MMU)	5
5	Data buffer	3
6	Direct memory access (DMA) controller	9
7	Video controller/data buffer	4
8	RAM controller	1
9	Clock generator	1

Table 1.2 shows the software tools used to design the SPARCstation 1, many of which are now obsolete. The important point to notice, though, is that there is a lot more to microelectronic system design than designing the ASICs—less than one-third of the tools listed in Table 1.2 were ASIC design tools.

TABLE 1.2 The CAD tools used in the design of the Sun Microsystems SPARCstation 1.
Design level	Function	Tool 2
ASIC design	ASIC physical design	LSI Logic
	ASIC logic synthesis	Internal tools and UC Berkeley tools
	ASIC simulation	LSI Logic
Board design	Schematic capture	Valid Logic
	PCB layout	Valid Logic Allegro
	Timing verification	Quad Design Motive and internal tools
Mechanical design	Case and enclosure	Autocad
	Thermal analysis	Pacific Numerix
	Structural analysis	Cosmos
Management	Scheduling	Suntrac
	Documentation	Interleaf and FrameMaker

The SPARCstation 1 cost about $9000 in 1989 or, since it has an execution rate of approximately 12 million instructions per second (MIPS), $750/MIPS. Using ASIC technology reduces the motherboard to about the size of a piece of paper—8.5 inches by 11 inches—with a power consumption of about 12 W. The SPARCstation 1 “pizza box” is 16 inches across and 3 inches high—smaller than a typical IBM-compatible personal computer in 1989. This speed, power, and size performance is (there are still SPARCstation 1s in use) made possible by using ASICs. We shall return to the SPARCstation 1, to look more closely at the partitioning step, in Section 15.3, “System Partitioning.”

Economics of ASICs

aslam.obf@gmail.com (Unknown) — Sun, 4 Sep 2011 12:49:00 +0500

Economics of ASICs

In this section we shall discuss the economics of using ASICs in a product and compare the most popular types of ASICs: an FPGA, an MGA, and a CBIC. To make an economic comparison between these alternatives, we consider the ASIC itself as a product and examine the components of product cost: fixed costs and variable costs. Making cost comparisons is dangerous—costs change rapidly and the semiconductor industry is notorious for keeping its costs, prices, and pricing strategy closely guarded secrets. The figures in the following sections are approximate and used to illustrate the different components of cost.

1.4.1 Comparison Between ASIC Technologies

The most obvious economic factor in making a choice between the different ASIC types is the part cost . Part costs vary enormously—you can pay anywhere from a few dollars to several hundreds of dollars for an ASIC. In general, however, FPGAs are more expensive per gate than MGAs, which are, in turn, more expensive than CBICs. For example, a 0.5 m m, 20 k-gate array might cost 0.01–0.02 cents/gate (for more than 10,000 parts) or $2–$4 per part, but an equivalent FPGA might be $20. The price per gate for an FPGA to implement the same function is typically 2–5 times the cost of an MGA or CBIC.

Given that an FPGA is more expensive than an MGA, which is more expensive than a CBIC, when and why does it make sense to choose a more expensive part? Is the increased flexibility of an FPGA worth the extra cost per part? Given that an MGA or CBIC is specially tailored for each customer, there are extra hidden costs associated with this step that we should consider. To make a true comparison between the different ASIC technologies, we shall quantify some of these costs...............

1.4.2 Product Cost

The total cost of any product can be separated into fixed costs and variable costs :

total product cost = fixed product cost + variable product cost ¥ products sold

(1.1)

Fixed costs are independent of sales volume —the number of products sold. However, the fixed costs amortized per product sold (fixed costs divided by products sold) decrease as sales volume increases. Variable costs include the cost of the parts used in the product, assembly costs, and other manufacturing costs.

Let us look more closely at the parts in a product. If we want to buy ASICs to assemble our product, the total part cost is

total part cost = fixed part cost + variable cost per part ¥ volume of parts.

(1.2)

Our fixed cost when we use an FPGA is low—we just have to buy the software and any programming equipment. The fixed part costs for an MGA or CBIC are higher and include the costs of the masks, simulation, and test program development. We shall discuss these extra costs in more detail in Sections 1.4.3 and 1.4.4. Figure 1.11 shows a break-even graph that compares the total part cost for an FPGA, MGA, and a CBIC with the following assumptions:

FPGA fixed cost is $21,800, part cost is $39.
MGA fixed cost is $86,000, part cost is $10.
CBIC fixed cost is $146,000, part cost is $8.

At low volumes, the MGA and the CBIC are more expensive because of their higher fixed costs. The total part costs of two alternative types of ASIC are equal at the break-even volume . In Figure 1.11 the break-even volume for the FPGA and the MGA is about 2000 parts. The break-even volume between the FPGA and the CBIC is about 4000 parts. The break-even volume between the MGA and the CBIC is higher—at about 20,000 parts.

FIGURE 1.11 A break-even analysis for an FPGA, a masked gate array (MGA) and a custom cell-based ASIC (CBIC). The break-even volume between two technologies is the point at which the total cost of parts are equal. These numbers are very approximate.

We shall describe how to calculate the fixed part costs next. Following that we shall discuss how we came up with cost per part of $39, $10, and $8 for the FPGA, MGA, and CBIC.

1.4.3 ASIC Fixed Costs

Figure 1.12 shows a spreadsheet, “Fixed Costs,” that calculates the fixed part costs associated with ASIC design.

FIGURE 1.12 A spreadsheet, “Fixed Costs,” for a field-programmable gate array (FPGA), a masked gate array (MGA), and a cell-based ASIC (CBIC). These costs can vary wildly.

The training cost includes the cost of the time to learn any new electronic design automation ( EDA ) system. For example, a new FPGA design system might require a few days to learn; a new gate-array or cell-based design system might require taking a course. Figure 1.12 assumes that the cost of an engineer (including overhead, benefits, infrastructure, and so on) is between $100,000 and $200,000 per year or $2000 to $4000 per week (in the United States in 1990s dollars).

Next we consider the hardware and software cost for ASIC design. Figure 1.12 shows some typical figures, but you can spend anywhere from $1000 to $1 million (and more) on ASIC design software and the necessary infrastructure.

We try to measure productivity of an ASIC designer in gates (or transistors) per day. This is like trying to predict how long it takes to dig a hole, and the number of gates per day an engineer averages varies wildly. ASIC design productivity must increase as ASIC sizes increase and will depend on experience, design tools, and the ASIC complexity. If we are using similar design methods, design productivity ought to be independent of the type of ASIC, but FPGA design software is usually available as a complete bundle on a PC. This means that it is often easier to learn and use than semicustom ASIC design tools.

Every ASIC has to pass a production test to make sure that it works. With modern test tools the generation of any test circuits on each ASIC that are needed for production testing can be automatic, but it still involves a cost for design for test . An FPGA is tested by the manufacturer before it is sold to you and before you program it. You are still paying for testing an FPGA, but it is a hidden cost folded into the part cost of the FPGA. You do have to pay for any programming costs for an FPGA, but we can include these in the hardware and software cost.

The nonrecurring-engineering ( NRE ) charge includes the cost of work done by the ASIC vendor and the cost of the masks. The production test uses sets of test inputs called test vectors , often many thousands of them. Most ASIC vendors require simulation to generate test vectors and test programs for production testing, and will charge for a test-program development cost . The number of masks required by an ASIC during fabrication can range from three or four (for a gate array) to 15 or more (for a CBIC). Total mask costs can range from $5000 to $50,000 or more. The total NRE charge can range from $10,000 to $300,000 or more and will vary with volume and the size of the ASIC. If you commit to high volumes (above 100,000 parts), the vendor may waive the NRE charge. The NRE charge may also include the costs of software tools, design verification, and prototype samples.

If your design does not work the first time, you have to complete a further design pass ( turn or spin ) that requires additional NRE charges. Normally you sign a contract (sign off a design) with an ASIC vendor that guarantees first-pass success—this means that if you designed your ASIC according to rules specified by the vendor, then the vendor guarantees that the silicon will perform according to the simulation or you get your money back. This is why the difference between semicustom and full-custom design styles is so important—the ASIC vendor will not (and cannot) guarantee your design will work if you use any full-custom design techniques.

Nowadays it is almost routine to have an ASIC work on the first pass. However, if your design does fail, it is little consolation to have a second pass for free if your company goes bankrupt in the meantime. Figure 1.13 shows a profit model that represents the profit flow during the product lifetime . Using this model, we can estimate the lost profit due to any delay.

FIGURE 1.13 A profit model. If a product is introduced on time, the total sales are $60 million (the area of the higher triangle). With a three-month (one fiscal quarter) delay the sales decline to $25 million. The difference is shown as the shaded area between the two triangles and amounts to a lost revenue of $35 million.

Suppose we have the following situation:

The product lifetime is 18 months (6 fiscal quarters).
The product sales increase (linearly) at $10 million per quarter independently of when the product is introduced (we suppose this is because we can increase production and sales only at a fixed rate).
The product reaches its peak sales at a point in time that is independent of when we introduce a product (because of external market factors that we cannot control).
The product declines in sales (linearly) to the end of its life—a point in time that is also independent of when we introduce the product (again due to external market forces).

The simple profit and revenue model of Figure 1.13 shows us that we would lose $35 million in sales in this situation due to a 3-month delay. Despite the obvious problems with such a simple model (how can we introduce the same product twice to compare the performance?), it is widely used in marketing. In the electronics industry product lifetimes continue to shrink. In the PC industry it is not unusual to have a product lifetime of 18 months or less. This means that it is critical to achieve a rapid design time (or high product velocity ) with no delays.

The last fixed cost shown in Figure 1.12 corresponds to an “insurance policy.” When a company buys an ASIC part, it needs to be assured that it will always have a back-up source, or second source , in case something happens to its first or primary source. Established FPGA companies have a second source that produces equivalent parts. With a custom ASIC you may have to do some redesign to transfer your ASIC to the second source. However, for all ASIC types, switching production to a second source will involve some cost. Figure 1.12 assumes a second-source cost of $2000 for all types of ASIC (the amount may be substantially more than this).

1.4.4 ASIC Variable Costs

Figure 1.14 shows a spreadsheet, “Variable Costs,” that calculates some example part costs. This spreadsheet uses the terms and parameters defined below the figure.

FIGURE 1.14 A spreadsheet, “Variable Costs,” to calculate the part cost (that is the variable cost for a product using ASICs) for different ASIC technologies.

The wafer size increases every few years. From 1985 to 1990, 4-inch to 6-inch diameter wafers were common; equipment using 6-inch to 8-inch wafers was introduced between 1990 and 1995; the next step is the 300 cm or 12-inch wafer. The 12-inch wafer will probably take us to 2005.
The wafer cost depends on the equipment costs, process costs, and overhead in the fabrication line. A typical wafer cost is between $1000 and $5000, with $2000 being average; the cost declines slightly during the life of a process and increases only slightly from one process generation to the next.
Moore’s Law (after Gordon Moore of Intel) models the observation that the number of transistors on a chip roughly doubles every 18 months. Not all designs follow this law, but a “large” ASIC design seems to grow by a factor of 10 every 5 years (close to Moore’s Law). In 1990 a large ASIC design size was 10 k-gate, in 1995 a large design was about 100 k-gate, in 2000 it will be 1 M-gate, in 2005 it will be 10 M-gate.
The gate density is the number of gate equivalents per unit area (remember: a gate equivalent, or gate, corresponds to a two-input NAND gate).
The gate utilization is the percentage of gates that are on a die that we can use (on a gate array we waste some gate space for interconnect).
The die size is determined by the design size (in gates), the gate density, and the utilization of the die.
The number of die per wafer depends on the die size and the wafer size (we have to pack rectangular or square die, together with some test chips, on to a circular wafer so some space is wasted).
The defect density is a measure of the quality of the fabrication process. The smaller the defect density the less likely there is to be a flaw on any one die. A single defect on a die is almost always fatal for that die. Defect density usually increases with the number of steps in a process. A defect density of less than 1 cm^–2 is typical and required for a submicron CMOS process.
The yield of a process is the key to a profitable ASIC company. The yield is the fraction of die on a wafer that are good (expressed as a percentage). Yield depends on the complexity and maturity of a process. A process may start out with a yield of close to zero for complex chips, which then climbs to above 50 percent within the first few months of production. Within a year the yield has to be brought to around 80 percent for the average complexity ASIC for the process to be profitable. Yields of 90 percent or more are not uncommon.
The die cost is determined by wafer cost, number of die per wafer, and the yield. Of these parameters, the most variable and the most critical to control is the yield.
The profit margin (what you sell a product for, less what it costs you to make it, divided by the cost) is determined by the ASIC company’s fixed and variable costs. ASIC vendors that make and sell custom ASICs have huge fixed and variable costs associated with building and running fabrication facilities (a fabrication plant is a fab ). FPGA companies are typically fabless —they do not own a fab—they must pass on the costs of the chip manufacture (plus the profit margin of the chip manufacturer) and the development cost of the FPGA structure in the FPGA part cost. The profitability of any company in the ASIC business varies greatly.
The price per gate (usually measured in cents per gate) is determined by die costs and design size. It varies with design size and declines over time.
The part cost is determined by all of the preceding factors. As such it will vary widely with time, process, yield, economic climate, ASIC size and complexity, and many other factors.

As an estimate you can assume that the price per gate for any process technology falls at about 20 % per year during its life (the average life of a CMOS process is 2–4 years, and can vary widely). Beyond the life of a process, prices can increase as demand falls and the fabrication equipment becomes harder to maintain. Figure 1.15 shows the price per gate for the different ASICs and process technologies using the following assumptions:

For any new process technology the price per gate decreases by 40 % in the first year, 30 % in the second year, and then remains constant.
A new process technology is introduced approximately every 2 years, with feature size decreasing by a factor of two every 5 years as follows: 2 m m in 1985, 1.5 m m in 1987, 1 m m in 1989, 0.8–0.6 m m in 1991–1993, 0.5–0.35 m m in 1996–1997, 0.25–0.18 m m in 1998–2000.
CBICs and MGAs are introduced at approximately the same time and price.
The price of a new process technology is initially 10 % above the process that it replaces.
FPGAs are introduced one year after CBICs that use the same process technology.
The initial FPGA price (per gate) is 10 percent higher than the initial price for CBICs or MGAs using the same process technology.

From Figure 1.15 you can see that the successive introduction of new process technologies every 2 years drives the price per gate down at a rate close to 30 percent per year. The cost figures that we have used in this section are very approximate and can vary widely (this means they may be off by a factor of 2 but probably are correct within a factor of 10). ASIC companies do use spreadsheet models like these to calculate their costs.

FIGURE 1.15 Example price per gate figures.

Having decided if, and then which, ASIC technology is appropriate, you need to choose the appropriate cell library. Next we shall discuss the issues surrounding ASIC cell libraries: the different types, their sources, and their contents.

ASIC Cell Libraries

aslam.obf@gmail.com (Unknown) — Sun, 4 Sep 2011 12:46:00 +0500

ASIC Cell Libraries

The cell library is the key part of ASIC design. For a programmable ASIC the FPGA company supplies you with a library of logic cells in the form of a design kit , you normally do not have a choice, and the cost is usually a few thousand dollars. For MGAs and CBICs you have three choices: the ASIC vendor (the company that will build your ASIC) will supply a cell library, or you can buy a cell library from a third-party library vendor , or you can build your own cell library.

The first choice, using an ASIC-vendor library , requires you to use a set of design tools approved by the ASIC vendor to enter and simulate your design. You have to buy the tools, and the cost of the cell library is folded into the NRE. Some ASIC vendors (especially for MGAs) supply tools that they have developed in-house. For some reason the more common model in Japan is to use tools supplied by the ASIC vendor, but in the United States, Europe, and elsewhere designers want to choose their own tools. Perhaps this has to do with the relationship between customer and supplier being a lot closer in Japan than it is elsewhere.

An ASIC vendor library is normally a phantom library —the cells are empty boxes, or phantoms , but contain enough information for layout (for example, you would only see the bounding box or abutment box in a phantom version of the cell in Figure 1.3). After you complete layout you hand off a netlist to the ASIC vendor, who fills in the empty boxes ( phantom instantiation ) before manufacturing your chip.

The second and third choices require you to make a buy-or-build decision . If you complete an ASIC design using a cell library that you bought, you also own the masks (the tooling ) that are used to manufacture your ASIC. This is called customer-owned tooling ( COT , pronounced “see-oh-tee”). A library vendor normally develops a cell library using information about a process supplied by an ASIC foundry . An ASIC foundry (in contrast to an ASIC vendor) only provides manufacturing, with no design help. If the cell library meets the foundry specifications, we call this a qualified cell library . These cell libraries are normally expensive (possibly several hundred thousand dollars), but if a library is qualified at several foundries this allows you to shop around for the most attractive terms. This means that buying an expensive library can be cheaper in the long run than the other solutions for high-volume production.

The third choice is to develop a cell library in-house. Many large computer and electronics companies make this choice. Most of the cell libraries designed today are still developed in-house despite the fact that the process of library development is complex and very expensive.

However created, each cell in an ASIC cell library must contain the following:

A physical layout
A behavioral model
A Verilog/VHDL model
A detailed timing model
A test strategy
A circuit schematic
A cell icon
A wire-load model
A routing model

For MGA and CBIC cell libraries we need to complete cell design and cell layout and shall discuss this in Chapter 2. The ASIC designer may not actually see the layout if it is hidden inside a phantom, but the layout will be needed eventually. In a programmable ASIC the cell layout is part of the programmable ASIC design (see Chapter 4).

The ASIC designer needs a high-level, behavioral model for each cell because simulation at the detailed timing level takes too long for a complete ASIC design. For a NAND gate a behavioral model is simple. A multiport RAM model can be very complex. We shall discuss behavioral models when we describe Verilog and VHDL in Chapter 10 and Chapter 11. The designer may require Verilog and VHDL models in addition to the models for a particular logic simulator.

ASIC designers also need a detailed timing model for each cell to determine the performance of the critical pieces of an ASIC. It is too difficult, too time-consuming, and too expensive to build every cell in silicon and measure the cell delays. Instead library engineers simulate the delay of each cell, a process known as characterization . Characterizing a standard-cell or gate-array library involves circuit extraction from the full-custom cell layout for each cell. The extracted schematic includes all the parasitic resistance and capacitance elements. Then library engineers perform a simulation of each cell including the parasitic elements to determine the switching delays. The simulation models for the transistors are derived from measurements on special chips included on a wafer called process control monitors ( PCMs ) or drop-ins . Library engineers then use the results of the circuit simulation to generate detailed timing models for logic simulation. We shall cover timing models in Chapter 13.

All ASICs need to be production tested (programmable ASICs may be tested by the manufacturer before they are customized, but they still need to be tested). Simple cells in small or medium-size blocks can be tested using automated techniques, but large blocks such as RAM or multipliers need a planned strategy. We shall discuss test in Chapter 14.

The cell schematic (a netlist description) describes each cell so that the cell designer can perform simulation for complex cells. You may not need the detailed cell schematic for all cells, but you need enough information to compare what you think is on the silicon (the schematic) with what is actually on the silicon (the layout)—this is a layout versus schematic ( LVS ) check.

If the ASIC designer uses schematic entry, each cell needs a cell icon together with connector and naming information that can be used by design tools from different vendors. We shall cover ASIC design using schematic entry in Chapter 9. One of the advantages of using logic synthesis (Chapter 12) rather than schematic design entry is eliminating the problems with icons, connectors, and cell names. Logic synthesis also makes moving an ASIC between different cell libraries, or retargeting , much easier.

In order to estimate the parasitic capacitance of wires before we actually complete any routing, we need a statistical estimate of the capacitance for a net in a given size circuit block. This usually takes the form of a look-up table known as a wire-load model . We also need a routing model for each cell. Large cells are too complex for the physical design or layout tools to handle directly and we need a simpler representation—a phantom —of the physical layout that still contains all the necessary information. The phantom may include information that tells the automated routing tool where it can and cannot place wires over the cell, as well as the location and types of the connections to the cell.

A Tutorial | Architecture of FPGAs and CPLDs

aslam.obf@gmail.com (Unknown) — Thu, 18 Aug 2011 05:38:00 +0500

Abstract

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This article provides a tutorial survey of architectures of commercially available high-capacity field-programmable devices (FPDs), and gives a summary of recent research results in the field.In the survey section, we first define the relevant terminology in the field and then describe the recent evolution of FPDs. The three main categories of FPDs are delineated: Simple PLDs (SPLDs), Complex PLDs (CPLDs) and Field-Programmable Gate Arrays (FPGAs). We then give details of the architectures of all of the most important commercially available chips. The second part of the article gives an overview of the most important research results on FPD architecture over the past six years, and provides suggestions as to features that may be included in future architectures.

What is FPGAs Technology | Overview | Benefits of FPGA

aslam.obf@gmail.com (Unknown) — Tue, 7 Jun 2011 21:13:00 +0500

Overview

Field-programmable gate array (FPGA) technology continues to gain momentum, and the worldwide FPGA market is expected to grow from $1.9 billion in 2005 to $2.75 billion by 2010¹. Since its invention by Xilinx in 1984, FPGAs have gone from being simple glue logic chips to actually replacing custom application-specific integrated circuits (ASICs) and processors for signal processing and control applications. Why has this technology been so successful? This article provides an introduction to FPGAs and highlights some of the benefits that make FPGAs unique.

What is an FPGA?

At the highest level, FPGAs are reprogrammable silicon chips. Using prebuilt logic blocks and programmable routing resources, you can configure these chips to implement custom hardware functionality without ever having to pick up a breadboard or soldering iron. You develop digital computing tasks in software and compile them down to a configuration file or bitstream that contains information on how the components should be wired together. In addition, FPGAs are completely reconfigurable and instantly take on a brand new “personality” when you recompile a different configuration of circuitry. In the past, FPGA technology was only available to engineers with a deep understanding of digital hardware design. The rise of high-level design tools, however, is changing the rules of FPGA programming, with new technologies that convert graphical block diagrams or even C code into digital hardware circuitry...................................................

FPGA chip adoption across all industries is driven by the fact that FPGAs combine the best parts of ASICs and processor-based systems. FPGAs provide hardware-timed speed and reliability, but they do not require high volumes to justify the large upfront expense of custom ASIC design. Reprogrammable silicon also has the same flexibility of software running on a processor-based system, but it is not limited by the number of processing cores available. Unlike processors, FPGAs are truly parallel in nature so different processing operations do not have to compete for the same resources. Each independent processing task is assigned to a dedicated section of the chip, and can function autonomously without any influence from other logic blocks. As a result, the performance of one part of the application is not affected when additional processing is added.

Top Benefits of FPGA Technology

Performance
Time to Market
Cost
Reliability
Long-Term Maintenance

Performance – Taking advantage of hardware parallelism, FPGAs exceed the computing power of digital signal processors (DSPs) by breaking the paradigm of sequential execution and accomplishing more per clock cycle. BDTI, a noted analyst and benchmarking firm, released benchmarks showing how FPGAs can deliver many times the processing power per dollar of a DSP solution in some applications.² Controlling inputs and outputs (I/O) at the hardware level provides faster response times and specialized functionality to closely match application requirements.

Time to market – FPGA technology offers flexibility and rapid prototyping capabilities in the face of increased time-to-market concerns. You can test an idea or concept and verify it in hardware without going through the long fabrication process of custom ASIC design.³ You can then implement incremental changes and iterate on an FPGA design within hours instead of weeks. Commercial off-the-shelf (COTS) hardware is also available with different types of I/O already connected to a user-programmable FPGA chip. The growing availability of high-level software tools decrease the learning curve with layers of abstraction and often include valuable IP cores (prebuilt functions) for advanced control and signal processing.

Cost – The nonrecurring engineering (NRE) expense of custom ASIC design far exceeds that of FPGA-based hardware solutions. The large initial investment in ASICs is easy to justify for OEMs shipping thousands of chips per year, but many end users need custom hardware functionality for the tens to hundreds of systems in development. The very nature of programmable silicon means that there is no cost for fabrication or long lead times for assembly. As system requirements often change over time, the cost of making incremental changes to FPGA designs are quite negligible when compared to the large expense of respinning an ASIC.

Reliability – While software tools provide the programming environment, FPGA circuitry is truly a “hard” implementation of program execution. Processor-based systems often involve several layers of abstraction to help schedule tasks and share resources among multiple processes. The driver layer controls hardware resources and the operating system manages memory and processor bandwidth. For any given processor core, only one instruction can execute at a time, and processor-based systems are continually at risk of time-critical tasks pre-empting one another. FPGAs, which do not use operating systems, minimize reliability concerns with true parallel execution and deterministic hardware dedicated to every task.

Long-term maintenance – As mentioned earlier, FPGA chips are field-upgradable and do not require the time and expense involved with ASIC redesign. Digital communication protocols, for example, have specifications that can change over time, and ASIC-based interfaces may cause maintenance and forward compatibility challenges. Being reconfigurable, FPGA chips are able to keep up with future modifications that might be necessary. As a product or system matures, you can make functional enhancements without spending time redesigning hardware or modifying the board layout.

Multiplication in FPGA Design!!

aslam.obf@gmail.com (Unknown) — Sun, 29 May 2011 17:23:00 +0500

Multiplication is basically a shift add operation. There are, however, many variations on how to do it. Some are more suitable for FPGA use than others. This page is a brief tutorial on multiplication hardware. The hyperlinked items in this list are currently in the text. The remaining items will be added in a future release of this page.

Scaling Accumulator Multipliers

	Parallel by serial algorithm
	Iterative shift add routine
	N clock cycles to complete
	Very compact design
	Serial input can be MSB or LSB first depending on direction of shift in accumulator
	Parallel output

A scaling accumulator multiplier performs multiplication using an iterative shift-add routine. One input is presented in bit parallel form while the other is in bit serial form. Each bit in the serial input multiplies the parallel input by either 0 or 1. The parallel input is held constant while each bit of the serial input is presented. Note that the one bit multiplication either passes the parallel input unchanged or substitutes zero. The result from each bit is added to an accumulated sum. That sum is shifted one bit before the result of the next bit multiplication is added to it.

1     1011001
0    0000000
1 1011001
1 +1011001
   10010000101

Serial by Parallel Booth Multipliers

	Bit serial adds eliminate need for carry chain
	Well suited for FPGAs without fast carry logic
	Serial input LSB first
	Serial output
	Routing is all nearest neighbor except serial input which is broadcast
	Latency is one bit time

The simple serial by parallel booth multiplier is particularly well suited for bit serial processors implemented in FPGAs without carry chains because all of its routing is to nearest neighbors with the exception of the input. The serial input must be sign extended to a length equal to the sum of the lengths of the serial input and parallel input to avoid overflow, which means this multiplier takes more clocks to complete than the scaling accumulator version. This is the structure used in the venerable TTL serial by parallel multiplier.

Ripple Carry Array Multipliers

	Row ripple form
	Unrolled shift-add algorithm
	Delay is proportional to N

A ripple carry array multiplier (also called row ripple form) is an unrolled embodiment of the classic shift-add multiplication algorithm. The illustration shows the adder structure used to combine all the bit products in a 4x4 multiplier. The bit products are the logical and of the bits from each input. They are shown in the form x,y in the drawing. The maximum delay is the path from either LSB input to the MSB of the product, and is the same (ignoring routing delays) regardless of the path taken. The delay is approximately 2*n.

This basic structure is simple to implement in FPGAs, but does not make efficient use of the logic in many FPGAs, and is therefore larger and slower than other implementations.

Row Adder Tree Multipliers

	Optimized Row Ripple Form
	Fundamentally same gate count as row ripple form
	Row Adders arranged in tree to reduce delay
	Routing more difficult, but workable in most FPGAs
	Delay proportional to log2(N)

Row Adder tree multipliers rearrange the adders of the row ripple multiplier to equalize the number of adders the results from each partial product must pass through. The result uses the same number of adders, but the worst case path is through log2(n) adders instead of through n adders. In strictly combinatorial multipliers, this reduces the delay. For pipelined multipliers, the clock latency is reduced. The tree structure of the routing means some of the individual wires are longer than the row ripple form. As a result a pipelined row ripple multiplier can have a higher throughput in an FPGA (shorter clock cycle) even though the latency is increased.

Carry Save Array Multipliers

	Column ripple form
	Fundamentally same delay and gate count as row ripple form
	Gate level speed ups available for ASICs
	Ripple adder can be replaced with faster carry tree adder
	Regular routing pattern

Look-Up Table (LUT) Multipliers

	Complete times table of all possible input combinations
	One address bit for each bit in each input
	Table size grows exponentially
	Very limited use
	Fast - result is just a memory access away

Look-Up Table multipliers are simply a block of memory containing a complete multiplication table of all possible input combinations. The large table sizes needed for even modest input widths make these impractical for FPGAs.

The following table is the contents for a 6 input LUT for a 3 bit by 3 bit multiplication table.

	001	010	011	100	101	110	111
000	000000	000000	000000	000000	000000	000000	000000
001	000001	000010	000011	000100	000101	000110	000111
010	000010	000100	000110	001000	001010	001100	001110
011	000011	000110	001001	001100	001111	010010	010101
100	000100	001000	001100	010000	010100	011000	011100
101	000101	001010	001111	010100	011001	011110	100011
110	000110	001100	010010	011000	011110	100100	101010
111	000111	001110	010101	011100	100011	101010	110001

Partial Product LUT Multipliers

	Works like long hand multiplication
	LUT used to obtain products of digits

Partial products combined with adder tree

Partial Products LUT multipliers use partial product techniques similar to those used in longhand multiplication (like you learned in 3rd grade) to extend the usefulness of LUT multiplication. Consider the long hand multiplication:

67
x 54
28
240
350
+3000
3618

By performing the multiplication one digit at a time and then shifting and summing the individual partial products, the size of the memorized times table is greatly reduced. While this example is decimal, the technique works for any radix. The order in which the partial products are obtained or summed is not important. The proper weighting by shifting must be maintained however.

The example below shows how this technique is applied in hardware to obtain a 6x6 multiplier using the 3x3 LUT multiplier shown above. The LUT (which performs multiplication of a pair of octal digits) is duplicated so that all of the partial products are obtained simultaneously. The partial products are then shifted as needed and summed together. An adder tree is used to obtain the sum with minimum delay.

The LUT could be replaced by any other multiplier implementation, since LUT is being used as a multiplier. This gives the insight into how to combine multipliers of an arbitrary size to obtain a larger multiplier.

The LUT multipliers shown have matched radices (both inputs are octal). The partial products can also have mixed radices on the inputs provided care is taken to make sure the partial products are shifted properly before summing. Where the partial products are obtained with small LUTs, the most efficient implementation occurs when LUT is square (ie the input radices are the same). For 8 bit LUTs, such as might be found in an Altera 10K FPGA, this means the LUT radix is hexadecimal. For 4 bit LUTs, found in many FPGA logic cells, the ideal radix is 2 bits (This is really the only option for a 4 LUT: a 1 bit input reduces the LUT to an AND gate, and since each LUT cell has 1 output, it can only use one bit on the other input).

A more compact but slower version is possible by computing the partial products sequentially using one LUT and accumulating the results in a scaling accumulator. Note that in this case, the shifter would need a special control to obtain the proper shift on all the partials

Computed Partial Product Multipliers

	Partial product optimization for FPGAs having small LUTs
	Fewer partial products decrease depth of adder tree
	2 x n bit partial products generated by logic rather than LUT
	Smaller and faster than 4 LUT partial product multipliers

A partial product multiplier constructed from the 4 LUTs found in many FPGAs is not very efficient because of the large number of partial products that need to be summed (and the large number of LUTs required). A more efficient multiplier can be made by recognizing that a 2 bit input to a multiplier produces a product 0,1,2 or 3 times the other input. All four of these products are easily generated in one step using just an adder and shifter. A multiplexer controlled by the 2 bit multiplicand selects the appropriate product as shown below. Unlike the LUT solution, there is no restriction on the width of the A input to the partial product. This structure greatly reduces the number of partial products and the depth of the adder tree. Since the 0,1,2 and 3x inputs to the multiplexers for all the partial products are the same, one adder can be shared by all the partial product generators. This structure works well in coarser grained FPGAs like the Xilinx 4K series.

2 x n bit partial product generated with adder and multiplexer

The Xilinx Virtex device includes an extra gate in the carry chain logic that allows a 4 input LUT plus the carry chain to perform a 2xN partial product, thereby achieving twice the density otherwise attainable. In this case, the adder (consisting of the XOR gates and muxes in the carry chain) adds a pair of 1xN partial products obtained with AND gates. The extra AND gate in the carry logic allows you to put AND gates on both inputs of the adder while maintaining a 4 input function.

2 x n bit computed partial product implemented in Xilinx Virtex using special MULTAND gate in carry chain logic

Constant Coefficient Multipliers

	Multiplies input by a constant
	LUT contains custom times table
	Width of constants do not affect depth of adder tree
	All LUT inputs available for multiplicand
	More efficient than full multiplier
	Size is constant regardless of value of constant (assuming equal constant bit widths)

A full multiplier accepts the full range of inputs for each multiplicand. If one of the multiplicands is a constant, then it is far more efficient to construct a times table that only has the column corresponding to the constant value. These are known as constant (K) Coefficient Multipliers or KCM's. The example below multiplies a 5 bit input (values 0 to 31) by a constant 67. Note that with a constant multiplier, all of the LUT inputs are available for the variable multiplicand. This makes the KCM more efficient than a full multiplier (fewer partial products for a given width).

	5 bit input * 67
input	00	01	10	11
000	0	536	1072	1608
001	67	603	1139	1675
010	134	670	1206	1742
011	201	737	1273	1809
100	268	804	1340	1876
101	335	871	1407	1943
110	402	938	1474	2010
111	469	1005	1541	2077

When the LUT does not offer enough inputs to accommodate the desired variable width, several identical LUTs may be combined using the partial products techniques discussed above. In this case, the constant multiplicand is full width, so the partial products will be m x n where m is the number of LUT inputs and n is the width of the constant.

Limited Set LUT Multipliers

	Multiplies input by one of a small set of constants
	Similar to KCM multiplier
	LUT input bit(s) select which constant to use
	Useful in modulators, other signal processing applications

In signal processing, there are often instances where one multiplicand is taken from of a small set of constant values. In these cases, the KCM multiplier can be extended so that the LUT contains the times tables for each constant. One or more of the LUT inputs select which constant is used, while the remaining inputs are for the variable multiplicand. The example below is a 6 LUT containing times tables for the constants 67 and 85. One bit of the input selects which times table is used. The remaining inputs are the 5 bit variable multiplicand (values from 0 to 31). Again, the input width can be extended using the partial product techniques discussed previously.

	5 bit input * 67				5 bit input * 85
	000	001	010	011	100	101	110	111
000	0	536	1072	1608	0	680	1360	2040
001	67	603	1139	1675	85	765	1445	2125
010	134	670	1206	1742	170	850	1530	2210
011	201	737	1273	1809	255	935	1615	2295
100	268	804	1340	1876	340	1020	1700	2380
101	335	871	1407	1943	425	1105	1785	2465
110	402	938	1474	2010	510	1190	1870	2550
111	469	1005	1541	2077	595	1275	1955	2635

Constant Multipliers from Adders

	Adder for each '1' bit in constant
	Subtractor replaces strings of '1' bits using Booth recoding
	Efficiency, size depend on value of constant
	KCM multipliers are usually more efficient for arbitrary constant values

The shift-add multiply algorithm essentially produces m 1xn partial products and sums them together with appropriate shifting. The partial products corresponding to '0' bits in the 1 bit input are zero, and therefore do not have to be included in the sum. If the number of '1' bits in a constant coefficient multiplier is small, then a constant multiplier may be realized with wired shifts and a few adders as shown in the 'times 10' example below.

0     0000000
1    1011001
0 0000000
1 +1011001
    1101111010

In cases where there are strings of '1' bits in the constant, adders can be eliminated by using Booth recoding methods with subtractors. The 'times 14 example below illustrates this technique. Note that 14 = 8+4+2 can be expressed as 14=16-2, which reduces the number of partial products.

0      0000000
1     1011001
1 1011001
1 +1011001
    10011011110

0       0000000
-1 1110100111
0     0000000
0 0000000
1 +1011001
     10011011110

Combinations of partial products can sometimes also be shifted and added in order to reduce the number of partials, although this may not necessarily reduce the depth of a tree. For example, the 'times 1/3' approximation (85/256=0.332) below uses less adders than would be necessary if all the partial products were summed directly. Note that the shifts are in the opposite direction to obtain the fractional partial products.

Clearly, the complexity of a constant multiplier constructed from adders is dependent upon the constant. For an arbitrary constant, the KCM multiplier discussed above is a better choice. For certain 'quick and dirty' scaling applications, this multiplier works nicely.

Wallace Trees

	Optimized column adder tree
	Combines all partial products into 2 vectors (carry and sum)
	Carry and sum outputs combined using a conventional adder
	Delay is log(n)
	Wallace tree multiplier uses Wallace tree to combine 1 x n partial products
	Irregular routing
	Not optimum in many FPGAs

A Wallace tree is an implementation of an adder tree designed for minimum propagation delay. Rather than completely adding the partial products in pairs like the ripple adder tree does, the Wallace tree sums up all the bits of the same weights in a merged tree. Usually full adders are used, so that 3 equally weighted bits are combined to produce two bits: one (the carry) with weight of n+1 and the other (the sum) with weight n. Each layer of the tree therefore reduces the number of vectors by a factor of 3:2 (Another popular scheme obtains a 4:2 reduction using a different adder style that adds little delay in an ASIC implementation). The tree has as many layers as is necessary to reduce the number of vectors to two (a carry and a sum). A conventional adder is used to combine these to obtain the final product. The structure of the tree is shown below. The red numbers after each full adder in the illustration indicate the bit weights of each signal. For a multiplier, this tree is pruned because the input partial products are shifted by varying amounts.

A section of an 8 input wallace tree. The wallace tree combines the 8 partial product inputs to two output vectors corresponding to a sum and a carry. A conventional adder is used to combine these outputs to obtain the complete product..

If you trace the bits in the tree (the tree in the illustration is color coded to help in this regard), you will find that the Wallace tree is a tree of carry-save adders arranged as shown to the left. A carry save adder consists of full adders like the more familiar ripple adders, but the carry output from each bit is brought out to form second result vector rather being than wired to the next most significant bit. The carry vector is 'saved' to be combined with the sum later, hence the carry-save moniker.

A Wallace tree multiplier is one that uses a Wallace tree to combine the partial products from a field of 1x n multipliers (made of AND gates). It turns out that the number of Carry Save Adders in a Wallace tree multiplier is exactly the same as used in the carry save version of the array multiplier. The Wallace tree rearranges the wiring however, so that the partial product bits with the longest delays are wired closer to the root of the tree. This changes the delay characteristic from o(n+n) to o(n+log(n)) at no gate cost. Unfortunately the nice regular routing of the array multiplier is also replaced with a rats-nest.

A Wallace tree by itself offers no performance advantage over a ripple adder tree

To the casual observer, it may appear the propagation delay though a ripple adder tree is the carry propagation multiplied by the number of levels or o(n*log(n)). In fact, the ripple adder tree delay is really only o(n + log(n)) because the delays through the adder's carry chains overlap. This becomes obvious if you consider that the value of a bit can only affect bits of the same or higher significance further down the tree. The worst case delay is then from the LSB input to the MSB output (and disregarding routing delays is the same no matter which path is taken). The depth of the ripple tree is log(n), which is the about same as the depth of the Wallace tree. This means is that the ripple carry adder tree's delay characteristic is similar to that of a Wallace tree followed by a ripple adder! If an adder with a faster carry tree scheme is used to sum the Wallace tree outputs, the result is faster than a ripple adder tree. The fast carry tree schemes use more gates than the equivalent ripple carry structure, so the Wallace tree normally winds up being faster than a ripple adder tree, and less logic than an adder tree constructed of fast carry tree adders. An ASIC implementation may also benefit from some 'go faster' tricks in carry save adders, so a Wallace tree combined with a fast adder can offer a significant advantage there.

A Wallace tree is often slower than a ripple adder tree in an FPGA

Many FPGAs have a highly optimized ripple carry chain connection. Regular logic connections are several times slower than the optimized carry chain, making it nearly impossible to improve on the performance of the ripple carry adders for reasonable data widths (at least 16 bits). Even in FPGAs without optimized carry chains, the delays caused by the complex routing can overshadow any gains attributed to the Wallace tree structure. For this reason, Wallace trees do not provide any advantage over ripple adder trees in many FPGAs. In fact due to the irregular routing, they may actually be slower and are certainly more difficult to route.

Booth Recoding

Booth recoding is a method of reducing the number of partial products to be summed. Booth observed that when strings of '1' bits occur in the multiplicand the number of partial products can be reduced by using subtraction. For example the multiplication of 89 by 15 shown below has four 1xn partial products that must be summed. This is equivalent to the subtraction shown in the right panel.

1    1011001
1     1011001
1    1011001
1 1011001
0 +0000000
    10100110111

1    -1011001
1     0000000
1    0000000
1 0000000
0 +1011001
    10100110111

Cheap Ultrasonic Range Finder | Microcontroller Project

aslam.obf@gmail.com (Unknown) — Sun, 22 May 2011 13:14:00 +0500

Do you need to add a distance sensor to your embedded project ? Build this simple ultrasonic range finder !
This quick & dirty PIC ultrasonic range finder will find a place in numerous projects : presence detector, robotics, car parking, distance measurement...
With a few cheap components and less than 200 bytes of code, this sensor will work from 30 to 200 cm, around 1 cm accuracy, with underflow and overflow indication.

How does it work & Circuit schematic

Everybody knows the speed of the sound in the dry air is around 340 m/s. Send a short ultrasonic pulse at 40 Khz in the air, and try to listen to the echo. Of course you won't hear anything, but with an ultrasonic sensor the back pulse can be detected. If you know the time of the forth & back travel of the ultrasonic wave, you know the distance, divide the distance by two and you know the range from the ultrasonic sensor to the first obstacle in front of it.
Here we use an ultrasonic piezzo transmitter with its receiver, they are very efficient, easy to find and quite cheap...................................................

First, we have to send the pulse : it is easy to get a 40 Khz pulse from a PIC PWM output. You can drive an ultrasonic transmitter directly from the PIC output, but the sense range will not exceed 50 cm. Using a transistor and a resonator circuit, the ultrasonic transmitter will get around 20 volts and the sense range will be extended up to 200 cm.

Second we have to sense the echo : the piezzo receiver can provide a few dozens of millivolt, this will be enough for a PIC ADC with 4 mV resolution without extra hardware.

C1 is a decoupling capacitor

The PWM pulse from the RC2 pin of the PIC drives the T1 transistor base through R1 resistor

A 330 µH inductor is added in parallel to the piezzo ultrasonic transceiver, to form a LC resonnator, the D1 diode protects T1 from reverse voltage.

The ultrasonic receiver is directly connected to the RA1 pin of the PIC (ADC channel number 1), with R3 in parallel as impedance adaptator.

FOR COMPLETE SOURCE CODE CLICK HERE

The prototype board <- Component side Solder side -> Take care to align as best as possibe the transmitter with the receiver......

INSTRUCTIONS FOR USE

I tested it with an EasyPic4 development board :

Of course, this ranger is very basic and have a few drawbacks :
A little shock to the piezzo receiver cell could lead to a wrong measurement,
Since ultrasonic pulse is not coded, any other ultrasonic source will put the mess :

=> Unwanted underflow or overflow conditions may happen

This is the price of the very simple design of the ranger.

This is what you should see on your scope, if you probe to the ultrasonic receiver pins :

Horizontal : 1 ms/div
Vertical : 5 mV/div
The mechanical echo is removed by a software delay.
The reflected wave is around 40 mV peak to peak, it comes around 9.5 ms after the ultrasonic burst, if we say that sound velocity is 340 m/s it means that the object distance was around 0.0095 / 2 * 340 = 1.615 meters.
Actually, it was the ceiling, it was 172 cm above the circuit, the LCD wrote 170 cm.
I hope this basic project will make a good start for yours !

Microcontroller Project | Memo Game Sound

aslam.obf@gmail.com (Unknown) — Mon, 9 May 2011 14:07:00 +0500

This example will show you how to build a PIC based simple memorization game system. With only a PIC16F84A and a few cheap components, you will train your brain first to understand a few basics about PICs, second to play to a not that easy memory game !
PIC Sleep Mode and Wake-Up from PORTB Change are the keys of the software.

Game rules

You will have to memorize a melody, made of up to 62 steps.
A step is one of the four tones available in the game system.
In order to help you, each tone is associated to a color LED (yellow, green, orange, red) which lights each time the tone is played.
The game system plays the melody, then you have to repeat it correctly by pressing the button of the tone's LED. At the beginning, the melody has only one step.
If you fail, an error melody is played, the melody is played again and you can try again to repeat it.
If you succeed, a new tone is added to the melody.
The longest melody is 62 step long, will you be able to learn it by heart ?
If you get bored with one melody, press the RB4 and RB5 buttons at the same time, the game system will create a new melody.
If you want to modify the melody rythme, press the RB6 and RB7 buttons at the same time, and select a new rythme by pressing a key when the LED is on :..................................

RA0 : very fast
RA1 : fast
RA2 : slow
RA3 : very slow (default)
Circuit Schematic
The game is battery operated, and the circuit is powered with a LP2950CZ-5.0 regulator with some decoupling capacitors. There is no main switch, because the circuit is in sleep mode when nothing happens. A standard 9V battery should work for weeks.
Four switches are connected to the PORTB high nibble to allow wake-up on PORT change of the PIC when the player press a button. There is no pull-up resistors, because internal weak pull-up of the PIC is used.
The RB0 pin of the PIC drives directly a little piezzo speaker.
The PORTA low nibble drives fours LEDs, through current limitation resistors.
A cheap 8Mhz crystal is used to clock the PIC, you could add the two 15pf capacitors from crystal to ground to follow Microchip recommendation, but the PIC works very well without, just do it if you have a lazy PIC that does not start oscillator.
PIC C Source Code
This project is made for a PIC16F84A MCU, but could be changed to any other PIC MCU with only a very few adjustments.
As this project fits within the 2k demo limit of the mikroC compiler, you can use it for free, download it from.

EEPROM Definition :
This project uses the internal PIC EEPROM, you have to add this EEPROM definition to your project :

0x00 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
0x10 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
0x20 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
0x30 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 04

You can download the .HEX file for PIC16F84A 8 Mhz crystal here :
DOWNLOAD.Hex

Prototype
Here is the picture of the prototype I built with VeroBoard :

LED Programming Status | Microcontroller Project

aslam.obf@gmail.com (Unknown) — Thu, 5 May 2011 22:19:00 +0500

Follow this steps, it will take 10 minutes of your time, and after this you will not need to watch your screen anymore when you flash your program into your MCU : just wait for the LED to turn off.

What do you need ?
Here are the parts you need : a resistor and a LED.
I used a 3mm red LED but any will do the job.
The LED will be powered with +5V, select the correct resistor value for your LED (470 ohms for mine) to limit the current.

Where to place it ?
The perfect place would be between USB LINK LED and POWER LED, but there is a track in between, so that I had to shift it up a little bit.
After drilling a 3mm hole, it looked like this :

Component side	Solder side

How to connect it ?
The LED is powered directly by the USB PIC programmer's output that drives the 4053 analog switch, so that the LED will light when the user's PIC is connected to the programming circuit, instead of the development board circuit.
Please do this very carefully because any damage to the programmer's circuitry would mean the end of your board, so be sure of what you do, and do it under your own responsibility.

1/ Insert the LED through the hole, with the cathode pin to the POWER LED side.
This should look like this :

2/ Glue to LED to the board
3/ Solder the LED cathode (left pin on the picture) to the left pin of the POWER LED : it is connected to the ground of the board
3/ Solder the LED anode (right pin on the picture) to the resistor
4/ Solder the other pin of the resistor to the pin 9 of the 4053 analog switch IC : it is the switch command line
5/ Verify that both LED and resistor are firmly in place, and ensure that there is no short circuit with other tracks

Test it now !
Plug the board : everything should be as usual.
Now launch PicFlash2 : the LED lights during programming. Great, it works !

On-board Ethernet Adapter Microcontroller Project

aslam.obf@gmail.com (Unknown) — Sun, 1 May 2011 18:51:00 +0500

Turn your EasyPic2 development board into an ENC28J60 Ethernet Toolkit

You will be surprised to see how simple it is !

The EasyPic2 : A good candidate for this enhancement

This is good old EasyPic2 development board from MikroElektronika. But it is still healthy and does a lot of good job. For those who don't know this board, here is a little review of its main features :

On-board USB fast programmer
DIP8 to DIP40 PIC sockets
32 LEDs and 32 buttons, connected to I/O pins
4 digits 7 segments LED display
Socket for 2x16 LCD text display
2 trimmers for A/D conversion
5 connectors, directly connected to I/O pins with pull-up/pull-down resistor arrays
RS232 adaptor and connector

What do we see bottom right ? Let's have a look closer..

There was space left on the board, so MikroElektronika had the good idea to make a prototype area for users.
210 plated-trough holes, both sides solder mask : until this day I never used this area.

On the back side, we see that the upper row is connected to the +5V power line, and the lower row to the ground line.

Good ! Nature hates empty spaces isn't it ? Me too !

What do we need ?

Almost all that you need is on this picture. The heart of the circuit is the ENC28J60 Microchip Serial Ethernet Adapter, it is now widely available, and its DIP28 package is very convenient for prototyping.
Other important part is the 3.3V voltage regulator (transistor-like 3-pins plastic case on the picture) : the ENC28J60 can't operate directly with the +5V provided by the board.
The 25 Mhz crystal for ENC28J60 clock is easy to find at your usual supplier.
You will have also to find a magnetic for ethernet network (black rectangular box left to the RJ-45 socket), this one comes from an old ethernet hub board, as well as other parts seen on this picture. There are now RJ-45 sockets with integrated LEDs and magnetic, if you want to save more space on your board.

And now, go shopping :

Quantity	Part # or value	Type
1	ENC28J60 (Microchip)	Serial Ethernet Controller
1	LP2950CZ-3.3	+3.3V voltage regulator
1	25 MHz	crystal
1	Green	LED
1	Red	LED
1	10 µF 25V	capacitor
1	47 µF 25V	capacitor
2	10 nF	capacitor
2	15 pF	capacitor
1	100 nF	capacitor
1	1 nF 2KV	capacitor
4	50 Ohm 1%	precision resistor
1	2.7 K 1%	precision resistor
2	470 Ohm	resistor
1	FB2022	TX/RX magnetic filter
1	ferrite bead (value not critical)	inductor
1	DIP 28 pins	IC socket
1	RJ45	female solderable socket
1	2x5 pins connector + 5 jumpers	used as switch

The circuit schematic

The circuit schematic comes from the datasheet of the ENC28J60 :
http://ww1.microchip.com/downloads/en/DeviceDoc/39662a.pdf

As you can see, it is pretty simple :
The ENC controller is connected to the network through a magnetic adapter.
It needs a 25 Mhz crystal for its internal clock, resistors & capacitors for terminations, a 2.7K bias resistor, and a 10 µF capacitor to stabilize its internal 2.5V power supply.
The controller can directly drive two programmable LEDs through current limitation resistors.
It is connected to the PIC through a 5 lines bus : reset line (RESET), chip select line (CS), SPI clock (CLK), SPI data input (SI), SPI data output (S0).
There are also 2 control lines that are not used in this exemple, but you can add them if you want, they are the interrupt line (INT) and the wake up on lan line (WOL). They can be used to trigger PIC interrupts, but in this example we operate using the polling method and we don't need them.
The most frequently asked question about this controler is the voltage level adaptation. The controller operates at 3.3V and the PIC on the board operates at 5.0V.
So, the question is : how to adapt ENC voltage levels to PIC voltage level ?

We must consider both sides :

PIC output voltage for logical 1 is 5V : does ENC accepts 5V on its inputs, whereas it is 3.3V powered ?
The answer is yes, ENC inputs are 5V compliant, so that there is no risk for the controller to apply 5V on its inputs, and they will correspond to logical 1.

ENC output voltage for logical 1 is 3.3V : will the inputs of the PIC turn high or low when 3.3V coming from the ENC outputs is applied ?
The answer is : it depends on the inputs of the PIC. TTL inputs give logical 1 above 2.05V, and will not require voltage level shifting. Schmitt trigger inputs give logical 1 above 3.5V, and will require voltage level shifting.
In fact, we can consider that if we connect ENC outputs to PIC TTL inputs only, the voltage level adapter is... a wire.
Most of PICs have TTL inputs and integrated SPI on PORTC, so we will connect all ENC line to this port.

Assembly

After soldering, you should get something that looks like this :

As you can see, I used a red/green bicolor LED instead of the two LEDs.

The jumper socket is placed just in front of the five lines that are connected to the PIC, so that removing the jumper isolates the ethernet circuit from the PIC, and PORTC can be used for other purposes.

The 3.3V regulator is mounted on a tulip socket : I have only one for now, and it is shared with another test board.

The 25 Mhz crystal is also mounted on a tulip socket, to save place for the two 15 pF capacitors hidden behind.

I'm a little bit ashamed, but I show you the back side anyway. Sorry for the mess ;-)

Take care to respect the receive circuit polarity, because ENC is not able to detect it correctly due to a silicon bug. That's why I used color wires. If you connect it wrong, you may either have receive problem, or no receive at all.

The bus is connected to the PORTC pins of the DIP28 socket.

Note that my cable deserves to be shortened...

Finally, this is what it looks like :

Front side	Back side

And now...

Testing the Ethernet board with a source code example

It's time !
First, check and double-check all connections.
Don't plug the ENC28J60 in its socket, then power the board and verify the 3.3V power supply on each pin of the ENC.
Then turn the board off, put a 40 pins PIC as a PIC16F877A or a PIC18F452 in its socket, and clock it at its maximum speed.
Plug the ENC28J60 in its socket, and set the fiver jumpers to enable bus line between PIC and ENC.

Get complete code

VR Stamp development kit by mikroElektronika

aslam.obf@gmail.com (Unknown) — Sat, 30 Apr 2011 13:35:00 +0500

For those who dream about embedding speech, music & voice recognition in their systems, Sensory Inc. has built a powerful RSC-4128 based stamp.
MikroElektronika released in March 2006 a complete development kit system for this stamp, with a board named Easy-VR Stamp, and a C compiler named RSC-4x mikroC compiler.
As a user of this tools, here is a little review of what you have to know about it.
Later, I will add some VR Stamp C source code examples, just like I do for PICs.

1/ What comes with the MikroElektronika Easy VR-Stamp development system
Unpacking the box, here is what I found :
From top to bottom, and from left to right :

the CD with software. I did not use it, I explain why below
the most important : the board, with a VR Stamp plugged into its socket
a 2 lines x 16 characters LCD display (not included in the base package, sold separately)
the USB cable to connect the on-board programmer to the host computer
a serial cable to connect the VR Stamp to a host computer (RS232 level adapter is on the board)
the board manual with schematic.

As usual with MikroElektronika, the board looks great ! Let's have a closer look.
2/ The Easy-VR Stamp board
Here is a view of the board :

As you can see, it looks funny : it is not usual to have a speaker system on development board, but MikroElektronika dared to include a speaker and a microphone on its board.
You understand immediately that you have nothing to add to start working !
From top to bottom, and from left to right, you can see on the board :

the speaker system : thanks to its big case, the speaker sounds good. An audio out connector is also available if you want to connect your own speaker
the audio amplifier, with a little pot to adjust the volume level. Some jumpers select either DAC or PWM coming from the VR Stamp
the RS232 socket and level adapter (MAX232)
the USB programmer : binary files for VR Stamp are big, and a high-speed programmer is needed, for tests & firmware updates as quick as possible
the power supply : the board may be powered either by USB connection, or by external low voltage AD or DC supply, depending on a jumper state
the real time clock and its battery cell : it is based on the popular PCF8583 I²C chip
the VR Stamp socket, with all pins clearly identified
the microphone, with its associated jumpers to select gain or external microphone
three sets of 2x5 ICD connectors, with all pins marked. They give access to the MCU I/O pins, and to the 3.3V power supply. I/O may either be pull-up or pulled-down (resistor arrays are on board) with jumpers, PORT2 has its own DIP switch
24 leds, to display the MCU I/O pins state
a DIP switch to configure some I/O pins
a 5V <=> 3.3V level adapter for the LCD display, with a contrast pot
the 3.3V regulator
the reset switch
the external microphone connector
24 buttons are connected to the MCU I/O pins, buttons are globally set for pull-up or pull-down with a jumper
the 2x16 LCD area, with plugs
a Compact Flash Memory Card slot : some applications may require external data storage for voice, music, logs...

The board reflects the quality we can expect from MikroElektronika, and users of others of their boards will immediately feel familiar with it.
3/ Pluging the board

The board comes with a ready-programmed VR Stamp. So when you power the board for the first time, the board starts immediately to run a program example. I don't remember which one ! But you immediately hear something from the board. The jumpers are also accorded to this first example.
4/ Installing USB Drivers & Flash software
I usually download software from web sites, instead of using the CDs that come with the packages, just to be sure to have the latest releases.
First, I downloaded the USB Drivers and the VRStamp Flash Software from this page :

VRStamp Flash software and drivers for Windows [1.18MB]
Drivers for VRStamp Flash software [1.51MB]
Easy-VRStamp Manual [1.43MB]
Installing USB drivers [420.79KB]

After installing these softwares, the Easy VR Stamp USB programmer was correctly detected, and the VRStamp Flash programmer software was able to communicate with the board.
5/ Installing RSC-4x mikroC compiler

This step is not difficult but you will have to pay attention to the mikroC manual to do it right.
I did it for you !
The RSC-4x mikroC compiler is based on a third-party assembler and linker : you have to install them properly. Just follow these steps :
First, download the RSC-4x mikroC compiler from this web page :
http://www.mikroe.com/eng/downloads/get/862/rsc4x_mikroc_2_0_0_0.zip

It comes with the complete IDE, a built-in manual, libraries : just follow the instructions and install it on your computer.
The download is free, without registration form.
Without a licence key, the .HEX ouptput is limited to 64K of program words (RSC-4128 small memory model), that is enough to do the first tests.
If you launch the compiler and try to build the example, you will get an error message : of course, there is no assembler nor linker !
Second, you will have to install the development package for Sensory RSC MCU (MCA-SE assembler & MCLINK linker) :
Just follow the instructions given by the built-in help of the RSC4x mikroC compiler when you try to build the example, here is the package to download :
http://www.phyton.com/downloads/project-se.zip.
The package is free, without registration form.
Close the compiler and install the package on your computer.

Then, launch the compiler and don't forget to give the path of the package to the compiler :
Tools-> Options -> Preferences -> Corss Tools -> External assembler & linker path

This done, you will be able to build the mikroC examples : press the build button, it works ! The .HEX output file is generated.
Load it into the VRStamp Flash Software and press the "Write" button : the program will be flashed into the VR Stamp, and then it starts to run.
That's a good step !
Third, The FluentChip library :
Now, open a project in the __Senory_Examples directory and try to build it : you will have a lot of errors, there is still something wrong !
The Sensory's FluentChip library is the missing part, you will need it to use the advanced speech, music & voice recognition features of the chip.

The default paths that come with the compiler are wrong, because a new version of the FluentChip library has been released since the packaging of the mE compiler.

This done, you are ready to work, and you will be able to compile some short Sensory examples, the biggest ones will need a RSC-4x mC licence key.
Anyway, if you don't have a MikroC licence key, all the Sensory examples are ready to be flashed : just select the .HEX file with the programmer, and you will hear the smooth voice of your favorite board !
6/ My opinion
I have been very impressed by the speaker independent speech recognition example (simple math quizz t2simath example in the __Sensory_Examples directory), which works fine in a noisy room.
Exploring all the possibilities of the board (including sound effects, Karaoke, MIDI & DTMF features...) will need a little bit more time, but it is worth the time.
The MikroC for RSC-4x shares the same IDE than the MikroC for PIC, with some interesting extra features.
For example, you can reduce & expand a C block in the editor :

As you can see, the while(1) {} block is reduced and its content is displayed in a pop-up frame when the cursor enters the block.
Just click on the + or - symbols in front of the line to expand or reduce the blocks.

With a few words, I liked very much :

the on-board speaker & microphone : as far as I know, this is a unique feature for a VR Stamp development system
the quality & finition of the board
the fast USB programmer
the comfortable IDE of the compiler

I found no real weakness in this development system, but a little bit more care in the manual to explain the rules and installation of external assembler, linker and libraries would have been helpful.

Automatic LED display dimmer | microcontroller Project

aslam.obf@gmail.com (Unknown) — Fri, 29 Apr 2011 17:15:00 +0500

This example shows how to use a simple LED as light sensor, and to dim a 7-segments LED display with PWM automatically in the dark.
You will use :

the PIC analog input and its ADC
the PIC timer 0
a 4 digits 7 segments LED display
2 buttons
a simple LED diode

Did you ever use 7 segments LED display ? Of course yes.
Then you surely adjusted the brightness of the LED, so that it is clearly readable in the day light.
But what happens in the dark ? Your display is simply too much bright !
How to know if it is bright or dark, without adding an analog extra-circuit ?
How to control the brightness of the display, without adding an analog extra-circuit ?

1. A LED as light sensor ?

This is not big news :
A LED emits light when electricity passes from its anode to its cathode.
This may be an interesting news :
A LED emits electricity when light is applied to its silicon junction. How much electricity ? Not that much, but enough for our purpose, a few tenth of milliVolts at most. This could easily be read by the ADC of a PIC, by connecting its cathode to the ground and its anode to the input pin of the PIC.
But this is the real trick :
We will reverse the connections of the LED : its cathode will be connected to the input pin of the PIC, and its anode to the ground.
Why ? Shall we have to read a negative voltage value ? Will the PIC be destroyed by the negative voltage ? Will the LED fry, because it is reversed ?
Not at all !
Connecting the diode in reverse polarity to the PIC ADC input will have the effect :
In the dark : the silicon junction does not receive any light, and no voltage is present between its pin. In fact, the diode acts like an open circuit. Due to its internal structure (a charged capacitor), the PIC ADC will read in this case a 'phantom' voltage, and its value will be returned by the conversion.
In the light : the silicon junction of the LED is excited and a little voltage appears between its pins. As it is reversed to the 'phantom' voltage, the result voltage will be less than zero, and the PIC ADC will return a null value.
Of course, this reverse voltage is far away from being dangerous for your PIC, and no current drives through the LED to fry it : your circuit is safe !

2. Dimming the display

To dim the display, we have to reduce the amount of current that drives through the LED display.
To reduce the amount of current, the first idea is to reduce the current itself. Of course it is possible, but it would need some extra analog circuitry.
A better idea would be to reduce the period during which the current is supplied to the LEDs. The amount of current received by the display during a time unit will be less, and the display will dim. This can be done with software : 7 segments LED displays are usually time-multiplexed, some adjustments in the software will do the job, and no extra circuitry will be needed.
The software will do a kind of PWM (Pulse Width Modulation) : by adjusting its duty cycle, we control the brightness of the display.
With a 0% duty cycle, the display is switched off (the LEDs receive no current), with a 100% duty cycle, the display is turned on (the LEDs receive all the available current), otherwise the LEDs light proportionally to the duty cycle.
The software PWM for LED display is not that hard to code, because the PWM frequency involved is not very high, and not time-critical too.

3. Build the circuit

All that you have to do, is to insert the LED into the DIP28 socket of your Easypic. This socket has the advantage to have the RA5 pin and the Ground pin side by side, so that we don't need extra circuitry.
Plug the cathode of the diode into the RA5 hole, and the anode into the Ground hole. This should look like this :

Your light sensor is ready to use !

Then set up your EP3 board as follows :

put a pic16f877a in the dip40 socket
put a 8 Mhz crystal in the oscillator socket
enable PORTC LEDs
enable 7 segments LED display
set pull-down to PORTD
set pull-up to keyboard

3. The program

You can download the C source code for PIC 16F877 from this page.
This C source code will allow you to experiment your new light sensor. You can compile it with the MikroC compiler, it fits within the 2k demo limit (in fact less than 300 bytes of ROM), so that you don't need a licence key to build the binary file.
If you don't have already MikroC compiler for PIC on your PC, then download it now for free :
DOWNLOAD.Zip

4. Run the program

Just turn off the light of the room and see the result on the display.
The LED is a very sensitive sensor : the display will dim only if there is no light at all.
The message "HIGH" is printed on the display when the LED sensor receives the light of a lamp, and then the message "DIMM" is printed with a dimmed brightness when the light goes off.
(WMV, 1.2 Mo)

To adjust the brightness of the dimmed display, press the RD0 or RD1 keys : the PWM duty cycle will change and the brightness of the display too.
If you enable PORTC LEDs, the duty cycle is shown as a bar graph.
5. Try other LEDS
Try with all LEDs you have : depending on their diameters and colors, sensitivity may vary.