EDA Blog

Technosoft TML_LIB_X20 Motion Control Library

Ken Cheung — Thu, 09 Jul 2009 17:56:26 +0000

The TML_LIB_X20 Motion Control Library embeds the Technosoft drives’ intelligence into a B&R PLC environment. The library is a collection of high-level functions and blocks enabling the control of the Technosoft intelligent drives from a B&R PLC. It works with B&R’s Automation Studio v3.0 SP3. With TML_LIB functions, designers can control Technosoft drives individually or grouped, by sending commands for simple (TS_MoveAbsolute), complex (TS_SetPVT, TS_PVTPoint, etc.) or synchronized (TS_GearIn) moves. The TML_LIB_X20 is an ideal tool for a quick implementation on a B&R PLC of motion control applications with Technosoft products.

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Designing a Wireless System using CC2500 Transceivers and MSP430 MCUs

Ken Cheung — Thu, 09 Jul 2009 16:03:05 +0000

Avnet and Texas Instruments are offering a one-day wireless technical design seminar. The wireless seminar features live presentations and demonstrations of TI’s CC2500 RF transceivers and MSP430 microcontrollers. The seminar will show users how to build a wireless network using the CC25xx radio. Attendees will learn how to accelerate the development cycles by utilizing the features and benefits of the CC2500 and MSP430 devices and SimpliciTI network protocol software in their designs. Each seminar participant will receive a free TI eZ430-RF2500 MSP430 wireless development tool. The event is free and will take place across North America starting July 14, 2009.

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Strategic Test TX-STAR i.MX25 SOM and Development Kit

Ken Cheung — Wed, 08 Jul 2009 21:18:59 +0000

Strategic Test launched the TX-STAR Freescale i.MX25 processor-based System on Module (SOM) and Development Kit. The TX-STAR features a 400 MHz i.MX25 processor, 64 MB SDRAM, 128 MB NAND flash memory, and a 200-pin SODIMM connector. The TX-STAR offers an operating temperature range from -45 to +85 degrees C, low price, small size, and low power consumption. It measures only 67.6 x 26 x 3.5 mm (2.6″ x 1″ x 0.09″). The TX-STAR is available with both Linux and Microsoft Windows Embedded CE 6.0. The SOM is priced at $79.

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Cluster Migration Workshop

Ken Cheung — Wed, 08 Jul 2009 17:17:35 +0000

EDA and high performance computing (HPC) in the cloud experts will conduct a workshop. The event will provide training and best practices for users of HPC clusters. The free Cluster Migration Workshop will take place July 27th from 12 pm to 2 pm. Experts from Sun Microsystems, eXludus and Univa UD will lead the lunchtime session. The workshop is ideal for design engineers, HPC infrastructure owners, and IT decision makers.

1Team Genesis Reference Flow for Automated SoC Assembly

Ken Cheung — Tue, 07 Jul 2009 17:44:41 +0000

Atrenta, Sonics, and Denali Software are building a reference flow based on Atrenta’s 1Team-Genesis automated chip assembly product. The flow will facilitate a healthy eco-system of semiconductor intellectual property (IP) that is qualified and ready to use in automated system-on-chip (SoC) assembly. The collaboration enables IP suppliers to ensure seamless integration of their IP portfolio into the 1Team-Genesis automated chip assembly and feasibility analysis solution. The result of this collaboration is a reference flow that defines the interfaces to the supplier’s IP generators, pre-qualifies their IP-XACT models and ensures that the generated RTL is SpyGlass clean.

More info: Atrenta

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Mentor Graphics iSolve SATA for Serial-ATA II Verification

Ken Cheung — Tue, 07 Jul 2009 17:09:41 +0000

Mentor Graphics introduced their iSolve SATA hardware-assisted solution for accelerateing the verification of Serial-ATA (SATA) II products — including hard disk drives (HDD) and optical CD/DVD drives. iSolve SATA enables designers to test their system-on-chips (SoCs) that control a HDD or optical drive by providing an accurate, hardware-based model of the real disk drive connected to their SoC. The solution has a “plug-and-play” interface to the Veloce family of hardware-assisted emulators, providing a cost-effective and efficient solution to verify SATA designs.

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Oasys RealTime Designer for 100 Million Gate RTL Synthesis

Ken Cheung — Tue, 07 Jul 2009 04:02:16 +0000

RealTime Designer, from Oasys Design Systems, is a design tool for physical RTL synthesis of 100-million-gate designs. RealTime Designer synthesizes RTL to placed gates in a single pass and in a fraction of the time compared to traditional synthesis. The tool features a RTL placement approach that eliminates unending design closure and iterations between synthesis and layout. RealTime Designer is immediately available and pricing begins at $395,000 for a one-year time-based license.

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Oasys Design Systems Chip Synthesis for 20M+ Gate Designs

Ken Cheung — Tue, 07 Jul 2009 04:01:42 +0000

Oasys Design Systems launched Chip Synthesis. According to Oasys, Chip Synthesis reinvents of RTL synthesis for chips beyond 20-million gates. The Oasys Chip Synthesis technology can synthesize an entire design from RTL to placed gates in a single bite, and do it in a fraction of the time. The Oasys technology has been built from the ground up to overcome some of the very fundamental limitations of traditional RTL and physical synthesis tools. The new platform for RTL design can handle today’s most complex designs. The early consideration of physical information using Oasys’ Place First approach ensures the best quality of results and a convergent flow all the way through layout.

More info: Oasys Design Systems

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Design Automation Conference Tutorials

Ken Cheung — Mon, 06 Jul 2009 23:34:21 +0000

The Design Automation Conference (DAC) will feature six educational, full-day tutorials focused on a variety of design methods. The tutorials will provide CAD professionals, design engineers, managers, and academic researchers with an in-depth look at electronic design. Tutorial attendees will have the opportunity to earn university Continuing Education Credits in the field of VLSI and Design Automation through a partnership with the University of California Santa Cruz (UCSC) Extension and the University of California San Diego (UCSD) Extension.

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Design Automation Conference Workshops

Ken Cheung — Mon, 06 Jul 2009 23:20:02 +0000

The Design Automation Conference (DAC) will feature nine in-depth workshops on a variety of timely and practical topics. The event include workshops on design for manufacturing (DFM), system-level design topics, and the emerging bio-design automation area. A new workshop this year addresses the needs of young faculty and others who are considering a career in academia. The 2009 DAC will take July 26 - 31 at the Moscone Center in San Francisco.

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