electronics designer's gallery

My Experience with "Noise" (Part II)

2009-10-10T23:30:00.000-07:00

Electro Static Discharge (ESD):

I believe most of us have experienced the static electric shock some point of time and are aware about how static electricity is formed. Hence I'm not going to bore you by going into those theories again. Also we know that the generation of static electric voltage is more effective in a dry climatic condition. For your information, the following table shows different means of static electric generation and the respective voltage levels (Source: ESD Association).

====================== ==============================

Means Of Generation--------------V (10-25% RH)-----V (65-90% RH)

====================================================

Walking across carpet------------------35,000-----------------1,500

Walking across vinyl tile---------------12,000-------------------250

Poly bag picked up from bentch------20,000----------------1,200

Getting up from chair with

Urethane foam-----------------------------18,000----------------1,500

====================== ==============================

In the manufacturing environment, ICs are only specified to survive 2KV HBM (Human Body Model: standard intended to simulate a person becoming charged and discharging from a bare finger to ground through the circuit under test), although some have been specified as high as 8KV while others - particularly newer parts in very small geometry processes - can be 500V or less.

The standard IEC 61000-4-2 specifies the test methodologies & measurement techniques to test the electronic products (& systems), which simulates the real industrial environment having possible ESD hazards. Electronic products are required to be tested for ESD immunity (IEC 61000-4-2) to insure their continued reliable operation if subjected to ESD after commissioned in the field. The European Union’s EMC Directive 2004/108/EC (replaced 89/336/EEC) mandates ESD immunity testing for virtually all electrical and/or electronic products as a requirement for obtaining the CE Mark before shipping to a member state of the European Union. As per IEC 61000-6-2: 2005, Electromagnetic Compatibility (EMC): Generic Standard, a device shall be tested as per IEC 61000-4-2 to verify that it passes the following test levels (at minimum):

1. Air Discharge: 8KV

2. Direct (Contact) Discharge: 4KV

The standard for ESD, IEC 61000-4-2 specifies the standard strike waveform. It is worth to study the nature of the waveform before designing the necessary protection in the circuit.

Protection against ESD:

There could be several way we could protect our devices from ESD. Were ever applicable, one could use series blocking resistor, ceramic capacitor, opto-isolation, bare guard trace, dual-rail clamping diodes, zener diodes, MOVs, TVS diodes or a combination of some of these techniques. The articles published in the following links could be useful as references:

- http://www.ce-mag.com/archive/01/Spring/Lee.html

- http://www.ce-mag.com/archive/03/ARG/dunnihoo.html

- http://www.necel.com/discrete/en/products/diode/nncd_index.html

- http://www.semtech.com/circuit-protection/low-capacitance/sr70/

- http://focus.ti.com/lit/ml/sszb130/sszb130.pdf

- http://www.littelfuse.com/data/en/Articles/BoardleveldesignMar2001_ED.pdf

It is not only about selecting a suitable protection device but also important to pay careful attention to the layout design. It is necessary to follow cautious approach in implementing a proper ground system such that the returning current through the protection circuit doesn't interfere with the rest of the circuit in operation. In case of a TVS, the common practice to refer the protection circuit to chassis ground or, in case of systems with non-conductive enclosures, power ground. Mount the TVS closest (as possible) to the entry point, use short and wide traces and used dedicated ground plane if possible, avoid loops and other best practices of high speed design.

Next, we are going to continue our discussion on "Electrical Transient Burst (EFT)' in part III.

My Experience with "Noise"

2009-09-13T00:38:00.000-07:00

For any electronics engineer involved in board design, working with digital circuits running at medium/high speed (clock frequency > ~10Mhz) or SMPS circuit design, "noise" is a nightmare. For any of the new designs, the first question appears in my mind is obviously whether it will work or not. The second question is whether my board will pass the EMC (Electro Magnetic Compliance) tests or not. The first could be more confidently answered than the second. I have most of my experience in digital and mixed circuit design, but I've also seen people struggling for several months to resolve EMC issues on SMPS boards. So far, I've seen SMPS designers having hard time to pass conducted and radiated emission tests, where as digital designers struggle to pass ESD (Electro Static Discharge), EFT (Electrical Fast Trasient) or RF susceptability tests. When I was a novice designer (That doesn't mean that I'm an expert now), I used to ask myself an "open-ended" question before starting a design: What all measures and design practices shall I follow in order to not get stuck due to EMC issues. As I gained experience over time, I've learned that it is better to ask myself a couple of questions:

What are the EMC tests that my product needs to pass?
Can I have the necessary measures and design practices implemented in order to pass those applicable tests?

If I have answered the above two questions satisfactorily, I have experienced a much better success rate.

The generic electromagneic compliance standard IEC 61000-6-2 specify the EMC tests to be conducted and alse specifies the test levels. This is important for an organization to get its products certified by agencies to obtain CE marking on its products. The generic standard IEC 61000-6-2 again calls various standards mentioned below, which are specific to the different EMC tests to be conducted. The following standards documents the detailed testing & measurement techniques for difference EMC tests.

IEC 61000-4-1: Over view of IEC 61000-4 series
IEC 61000-4-2 : Electro Static Discharge (ESD) Test
IEC 61000-4-3: Radio Frequesncy (RF) Immunity Test
IEC 61000-4-4: Electric Fast Transient (EFT) Immunity Test
IEC 61000-4-5 High Voltage Surge Immunity Test
IEC 61000-4-6: Immunity to Conducter Radio Frequency (RF)
IEC 61000-4-8: Power frequency magnetic field immunity test.
IEC 61000-4-10: Damped oscillatory magnetic field immunity test.
IEC 61000-4-11: Voltage dips, short interruptions and voltage variations immunity tests.

There are some more. The tests specified in the above international EMC standards are designed for testing the products in a harsh environment simulating the real world EMI situations. Hence if we approach from understanding the tests specified in those standards and then take necessary precausions in our design in order to pass those tests, it is highly likely that our product will also work in real life environment.

Let us now focus on each of those EMC tests standards by standard. Let's start with ESD: IEC 61000-4-2.

(To Be Continued In Part II...)

Fixing "Task Manager" recovering from virus attack

2009-06-06T10:41:00.000-07:00

In recent past, my personal computer at my home suffered a virus attack in between my previous ani-virus software expired and new ani-virus downloaded. After I installed the Avast anti-virus, it detected several infections. More over I observed that I was no longer able to open task manager. Whenever I used to press "Ctrl+Alt+Del", a message used to pop-up saying similar to "Task manager has been disabled by your administrator". I knew that this damage was caused by the virus attack as I myself is the administrator of my own PC. Also I discovered that the "Run" menu has vanished from the "Start" menu. I was helpless for a moment as I was not able to open "IE" at the same time. All my electronics hobby activities stopped because of this for some time. Some how I had another browser installed, which helped me in access the resources shared by our friends in several websites about the fixes. Thanks to all who have put those information! Finally I could manage to fix it as mentioned below. If you also face a similar issue, execute the following steps.
Step1:
Go to "C:\windows\system32" and click on "gpedit.msc". This will open the group policy editor. Next drill down to "User configuration" --> "Administrative templates" --> "Start Menu and Taskbar".Find "Remove run from start menu". This would be displayed as "Not Configured". Right click on it to display the property. First set “Disable” (followed by clicking on "apply" --> "OK") and next set it back to "Not configured" (followed by clicking on "Apply" --> "OK").
Now you should find run in start menu.
Step2:
Go to "Start" --> "Run", type "gpedit.msc" and press "enter". Drill down to "User Configuration" --> "Administrative Template" --> "System" --> "Ctrl+Alt+Del Options". Right click on "Remove Task Manager" and click on "Properties". The "property" should be set to "Not configured". First set the property to "Disable" (followed by clicking on "apply" --> "OK") and next set it back to "Not configured" (followed by clicking on "Apply" --> "OK").
Now you should be able to invoke the task manager!
Hope you won't need the above tips!!

FLASH memory basics

2009-02-24T08:49:00.000-08:00

FLASH memories are being used widely as non-volatile memory for the purpose of storing large amount of data in a small foot-print. Flash memory was invented by Dr. Fujio Mansuoka while working for Toshiba in 1980. According to Toshiba, the name "flash" was suggested by Dr. Masuoka's colleague, Mr. Shoji Ariizumi, because the erasure process of the memory contents reminded him of a flash of a camera.Flash memory is a form of EEPROM (Electrically Erasable Programmable Read-Only Memory) that allows multiple memory locations to be erased or written in one programming operation. In other terms, it is a form of rewritable memory chip that, unlike a RAM (Random Access Memory) chip, power supply is not required to hold the contents. It is commonly used in memory cards for computers, USB flash drives, MP3 players, digital cameras, mobile phones and many other electronic embedded products. The FLASH memory has certain advantages as compared to the other non-volatile memories such as EEPROM or the hard drives. FLASH memories

offer better (faster) read access time as compared to the EEPROM.
offer better kinetic shock resistance than the hard disks.
when FLASH memory is packaged in a "memory card", it is enormously durable, can withstand harsh environmental conditions

FLASH memories are of two types - "NAND FLASH" and "NOR FLASH". Both types has certain advantages over the other. The following table and the picture depicts a comparison between these two types of FLASH memory.

Useful and Interesting Resources for Electronics Hobbyists

2008-09-09T09:51:00.000-07:00

The collection of the links below can be useful and interesting to an electronics hobbyist.
Web-resources, articles, circuits
http://www.hobbyprojects.com/index.html
www.electronic-circuits-diagrams.com/
www.electronickits.com/kit/complete/complete.htm
http://www.electronics2000.co.uk/
http://www.bgmicro.com/
http://www.hobby-elec.org/e_menu.htm
http://www.uoguelph.ca/~antoon/circ/circuits.htm
http://www.hobby-electronics.info/
http://www.hobby-hour.com/electronics/
http://www.circuithut.com/
Magazines
http://www.elektor.com/
http://www.electronicsforu.com/electronicsforu/default.asp
http://www.epemag.wimborne.co.uk/
http://www.siliconchip.com.au/
http://www.nutsvolts.com/

Picking The Right A/D Converter For Your Design

2007-11-17T21:11:00.000-08:00

The analog to digital converter is a bridge between the analog and digital world, which is used in a wide range of applications where there is a need to convert the analog signal into the digital data. Based on fundamental architectures, there are several A/D converters. They are:

--> Successive Approximation
--> Sigma-Delta
--> Flash
--> Subranging (Pipelined)
--> Bit-per-stage (Ripple)

There are several factors to consider while selecting an A/D converter for your design. The most important parameters to consider are:

--> Resolution
--> Through-put (Speed)
--> Errors (offset, gain & linearity errors)
--> Monotonacity
--> AC Specifications: Such as Signal To Noise And Distortion (SINAD), Effective Number Of Bits (ENOB), Bandwidth

Let's now recapitulate the definitions of some of these factors as we studied during our engineering. Some of the important specifications of ADC are presented below:

Resolution is the smallest analog increment/decrement corresponding to a 1 LSB converter code change. We express resolution in number of bits.

Throughput Rate is the maximum continuous conversion rate of an ADC. This specification indicate the speed of an ADC. This is often expressed in KSPS (Killo samples per second), MSPS (Mega samples per second).

Offset Error is the difference between ideal LSB transition to the actual transition point. This specification is expressed in LSBs.

Gain Error is the difference between the input voltage just causing a transition to positive fullscale and (Vref - 1.5LSB). This specification is expressed in LSBs or % Full Scale.

Differential Non-Linearity (DNL) is the measure of the maximum deviation from the ideal step size of 1 LSB. DNL is commonly measured at the rated clock frequency with a ramp input and expressed in LSBs.

Intigral Non-Linearity (INL) is a measure of the deviation of each individual code from a line drawn from zero scale or negative full scale (1⁄2 LSB below the first code transition) through positive full scale (1⁄2 LSB above the last code transition). The deviation of any given code from this straight line is measured from the center of that code value. The end point test method is used. INL is commonly measured at rated clock frequency with a ramp input and expressed in LSBs.

Related to DNL are two critical figures of merit used in defining ADC operation They are:

Missing Code are those output codes that are skipped or will never appear at the ADC outputs. These codes cannot be reached by any input value.

Monotonicity - An ADC is monotonic if it continually increases conversion result with an increasing voltage (and vice versa). A nonmonotonic ADC may give a lower conversion result for a higher input voltage, which may also mean that the same conversion may result from two separate voltage ranges. Often, the transfer function will completely miss the lower code until after the higher code is converted (on an increasing input voltage).

Now, some of the important AC (dynamic) specifications of ADC are presented below:

Analog Input Bandwidth is a measure of the frequency at which the reconstructed output fundamental drops 3 dB below its low frequency value for a full scale input. The test is performed with fIN equal to 100 kHz plus integer multiples of fCLK. The input frequency at which the output is −3 dB relative to the low frequency input signal is the full power bandwidth.

Signal To Noise Plus Distortion (SINAD) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of all of the other spectral components below half the clock frequency, including harmonics but excluding dc.

Spurious Free Dynamic Range (SFDR) is the difference, expressed in dB, between the rms values of the input signal at the output and the peak spurious signal. where a spurious signal is any signal present in the output spectrum that is not present at the input.

Intermodulation Distortion (IMD) is the creation of additional spectral components as a result of two sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dB.

Keeping the above parameters in mind, we are ready to examine various applications for which ADCs are used and then we can sort out the most important parameters relevant to the application areas. Most of the A/D converter applications can be categorized into the following major application areas:

Audio
Communication (voice band)
Data Acquisition & Control
Precision Measurement (e.g. Oscilloscope)
Image Processing

Now the question arises, how to choose the appropriate A/D converter for a particular application? We can find this out if we can map the ADC parameters relevant to each of the above application areas. The following table shows a relationship between the application areas and the A/D converter parameters important for the respective application areas.

From the Table 1, it can be observed that one parameter of ADC important for one particular application may not be important for other applications. For example, in some of the communication type applications, you're really interested in inter- modulation distortion, whereas in an industrial control loop, that might not factor in as much. You're more interested in the actual linearity or the monotonicity of the converter.

Based on their working principles, each type of ADC has certain advantages, i.e. one ADC category can be superior when compared to their peers based on certain specifications and can be inferior for other parameters. Based on the guidance provided in Table 1 we can concentrate only on the specific parameters important to the respective application area.

On a high level we can classify ADCs according to their suitability for the application categories based only on resolution and sampling rate as depicted in Figure 1. This can serve as a basic guideline for choosing the type of ADC architecture best suitable for the application. Next we can narrow down our choise based on the specifications mentioned in Table 1.

P.S. Kindly post your comments and suggestions for improving the quality of information presented in this article.

Designing With Digital Logic Families: Basics

2007-11-11T01:29:00.000-08:00

The designers of complex digital boards generally deal with multiple supply voltages on their boards. While interfacing the IOs of one device to the other, the designer should make sure that the IO type of the driver is compatible to that of the receiver and the right part is chosen for the right application.

While working with the digital ICs, the first set if parameters we would look at, are the input & output voltage level parameters VOH and VIH. The Figure 1 illustrates the IO voltage levels of some popular logic families. For example, we can directly connect a 5-V CMOS output to a 5-V TTL input, but the vice-versa is not permitted. Again, we can connect a 5-V TTL output to a 3.3-V TTL input, provided the 3.3-V input is 5-V tolerant. Also note that, the families such as AHCT, HCT, ACT, (omitted in Figure 1) can accept 5-V TTL input levels, but drives 5-V CMOS levels. Hence these families can act like bridge between 5-V TTL and 5-V CMOS logic levels. The table 1 below presents a summery of the compatibility chart between the popular logic families.

Please note that '*' mark indicates that the compatibility is possible only if the input stage is tolerant to the maximum voltage output level provided by the driver. The designer also need to calculate the noise margin as below:

Noise Margin Output High = VOH (driver) - VIH (receiver)

Noise Margin Output Low = VIL (receiver) - VOL (driver).

Higher noise margin indicates higher noise immunity. Also note that, negative noise margin indicates a sign of incompatibility.

The next set of important parameters we would like to examine are the "fan-in" and "fan-out". These numbers indicate the sinking and sourcing capabilities of input and output stages. These parameters are calculated as below:

Fan-out Output High = IOH (driver) / IIH (receiver)

Fan-out Output Low = IOL (driver) / IIH (receiver)

As we can see, the above calculations must be made for each of the two logic levels. Naturally, the smaller the resulting numbers determines the actual fan-out. The fan-out calculations can be used not only for the gates of a particular family, but also among different families.

Another important parameter to consider while choosing a logic family is the "propagation delay" or more generically known as speed. This parameter helps in analyzing whether the output timings meet the set-up and hold-up time requirements of the input stage satisfactorily. Again, as the speed increases (i.e. lesser the propagation delay), the power dissipation increases. Hence the "speed-power" product is also important to select the right logic family for the right application.

Some More Things To Remember While Using Digital Logic Families:

Connections between ICs and other devices must be kept as short as possible. As the operating frequency increases, the inductance of the long traces plays an important role to induce distortion on the digital signals. If the frequency is high enough, the long traces between these ICs acts like transmission line. Phenomenons such as reflections and ringing can be controlled by using proper termination resistors.
Proper decoupling capacitors should be used as close to the VCC pin as possible. This is to avoid power supply glitches due to digital switching.
The unused input pins must not be left floating to avoid high current drawn due to oscillation of the floating gates, and possible damage of the IC. Connect the unused inputs to either VCC or ground preferably using resistors in series.
Timing analysis must be done to check if set-up/hold-up parameters are violated or met.

P.S. I would like to request to the readers of this article to share their comments, suggestions or correction about this topic in order to enrich this article.

Latest Version Of Software Tool May Not be The Best!!!

2007-11-06T09:26:00.000-08:00

In the world of programmable logic development tools, the latest may not be the greatest!!!...Do you agree with me? Recently I went through a horrible experience working with Lattice CPLDs & their development tool. A couple of years back, some old CPLD devices were replaced with new CPLDs and the old ABEL codes were re-synthesized using ispLEVER software from Lattice. The re-compiled codes worked fine with the new devices. The designers did not bother to preserve the version of the ispLEVER software tool they used to compile the ABEL codes, since they were only concerned about archiving the source codes and other inout information to the tool.

In the recent past, there was a need to make a minor modification to some of these CPLD codes. By this time, we no more had the version of the ispLEVER software that was used to compile the ABEL codes a couple of years back. I downloaded the latest ispLEVER Classic software from the Lattice website and compiled the same ABEL code with out any changes in it. I downloaded the .jed file to the respective CPLD and to my surprise, the board did not work.

After a lots of hard work, debugging with a logic analyser, I found the root of the problem lied in the new version of the compiler, which mis-interpreted some portion of the ABEL code related to the bi-directional signals. After that, it took a while to fix this by adding some extra pins, board revision etc.

This incident taught me a lesson. When ever I finish a design, I would keep the version of the development tool used for development, archived along with the tool. This would consume more storage space, but would save some time spent in re-work. Again, in a big organization, it may not be always possible to archive each version of tool used for designs. In that case the designer has to be foresighted to be able to write a device architecture independent & synthesis tool independent code using popular HDLs such as VHDL/Verilog or other high level languages such as System C.