http://www.fabtech.org/ Online information source for semiconductor professionals Copyright 2008, Semiconductor Media en-GB info@fabtech.org Mon, 15 Mar 2021 14:17:10 GMT 120 http://www.fabtech.org/ white_papers/_a/lithography_efficiency_a_cost_comparison_model/ By Sven Grünzig, Nemotek Technologie, Rabat, Morocco ABSTRACT The paper presents a calculation model and conclusions with focus on the comparison of low-throughput and high-throughput lithography clusters via an analysis of the lithography Cost of Ownership (COO) and applied data of the Overall Equipment Efficiency (OEE) and Overall Factory Efficiency (OFE). The report will show that the published documents up to today are not sufficient to prove that a higher throughput necessarily leads to an advantage of the manufacturing effectiveness and that it is necessary to calculate and adapt it onto the chip manufacturer’s requirements. It will show metrics and a methodology for fab planners and equipment engineers to calculate the needed cluster throughput and to optimize the lithography efficiency. Furthermore, the calculation model presents a flexible method to identify not only the key drivers to run an efficient production, but also to easily compare different scenarios. Two examples are shown, with models evaluated with real data. This study might also be applicable to other semiconductor processing steps. Thu, 21 Oct 2010 15:48:20 GMT http://www.fabtech.org/ white_papers/_a/preview_edition_39_wafer_edge_yield_engineering_in_leading_edge_dram_manufa/ By Oguz Yavas, Ernst Richter, Christian Kluthe & Markus Sickmoeller, Qimonda AG - ABSTRACT - A recent collection of data on 90nm, 80nm and 75nm technology from state-of-the-art 300mm wafer fabs have been brought together to perform a comprehensive analysis of wafer-edge yield engineering. For this study, a dedicated cross-functional team thoroughly investigated wafer periphery using innovative tools such as yield test chips and advanced process inspection. Critical processes were identified and countermeasures implemented to improve overall yield performance. Best practice sharing within the fabrication cluster resulted in a significant learning speed that supported an aggressive global production ramp. The challenges and the methodology used to address fast wafer-edge yield learning in Dynamic Random Access Memory (DRAM) manufacturing are the focus of this paper. Thu, 12 Mar 2009 17:36:07 GMT http://www.fabtech.org/ white_papers/_a/edition_38_evaluation_of_particle_shedding_and_trace_metal_extraction_from/ By Mark R. Litchy, CT Associates, Inc., Minnesota, USA & Reto Schoeb, Levitronix, LLC, Massachusetts, USA. - ABSTRACT - The production of semiconductor devices continues to be extremely sensitive to particulate and metallic contamination. As feature sizes continue to decrease, the need for purity will continue to increase. Various types of pumps are used in bulk chemical delivery systems, recirculating etch baths, and other high purity process applications. Many of these pumps shed significant quantities of particles that may reduce product yield or impact the performance or lifetime of filters used in the process loop. Furthermore, metallic contamination in process chemicals can cause a variety of yield-related issues. This paper evaluates the levels of trace metal extraction and particle shedding under different operating conditions using two high purity pump types from three manufacturers. Wed, 25 Feb 2009 11:50:45 GMT http://www.fabtech.org/ white_papers/_a/edition_38_300mm_activity_report_may_to_october_2008/ Worsening global economic conditions in the second half of 2008 has started to seriously impact the semiconductor industry. Weakening demand in all major device sectors is causing fab utilization to fall, while more 300mm fab expansions and new fab construction has been put on hold. The six-month review covered in this report highlights the rapidly changing dynamics with regard to fabs on hold and expected tool install schedules, and provides a review of the foundry sector. Mon, 09 Feb 2009 16:01:20 GMT http://www.fabtech.org/ white_papers/_a/preview_edition_39_technology_transfer_and_ramp_in_a_giant_300mm_production/ By Ernst Richter et al - ABSTRACT - This article follows up on a previously published paper that introduced the 110nm technology transfer of Dynamic Random Access Memory (DRAM) for the Inotera Memories joint venture at start-up [1]. In this paper, technology transfer and ramp of the 75nm DRAM technology is outlined for Inotera in full production mode. Again, technology transfer was done from Qimonda (previously Infineon Technologies) at Dresden in Germany where the technology was jointly developed with Nanya Technologies. Inotera at Taoyuan in Taiwan was the first receiving site to repeat the technology qualification. Continuous sales price reduction puts pressure on memory firms for fast introduction of technology shrinks to remain cost competitive [2]. Delays as short as a few days in the production ramp can translate into millions of dollars of missed opportunity in revenue. This paper sets forth the steps taken by the two companies to avoid such setbacks in the technology transfer. Thu, 29 Jan 2009 18:30:39 GMT http://www.fabtech.org/ white_papers/_a/edition_38_the_permeation_resistance_of_polymers/ By Chuck Extrand, Entegris, Chaska, Minnesota, USA - ABSTRACT - Polymers, commonly referred to as plastics, are widely used in the manufacturing of microelectronic devices. In addition to their many desirable properties, such as low cost, light weight, strength, ductility and ease of processing, polymers can be created free of metals and inorganic constituents that may interfere with sensitive clean room fabrication processes in multiple ways. For example, the loose molecular structure of polymers may allow the unwanted permeation of gases and simple liquids in fabrication facilities. This paper will provide a brief introduction to factors that influence permeation through polymers, discussing polymer structure background and its relation to permeation, and the influences of various polymer properties on permeation. Tue, 27 Jan 2009 12:00:49 GMT http://www.fabtech.org/ white_papers/_a/edition_38_2008_semiconductor_manufacturing_survey_results_and_the_fabs_of_/ By David Jimenez & Daren Dance, Wright Williams & Kelly, Inc., Pleasanton, California, U.S. - ABSTRACT - In April of 2007, WWK conducted a survey of semiconductor industry professionals and asked several questions pertinent to the semiconductor manufacturing industry, including the respondents’ expected arrival date of 450mm wafers and the likelihood of direct write patterning being incorporated into more manufacturing processes. A follow-up survey was carried out in 2008, and these combined sets of data are portrayed in a projection of a typical manufacturing facility in 2013. Mon, 26 Jan 2009 18:42:35 GMT http://www.fabtech.org/ white_papers/_a/edition_38_performance_testing_manufacturing_execution_system/ By Brandon Lee & Susanta Dash, CIMAC, San Jose, California, U.S. - ABSTRACT - Performance testing is carried out on an MES system to identify and eliminate bottlenecks that can potentially cause production outages and lost revenue in a semiconductor production fab. In a distributed system, bottlenecks can occur at the client site, within the server or in the  network. The MES system is the heart of the manufacturing operation and interacts with a number of other systems to support the manufacturing line in a fab. As production increases with ramping up of the production volume, the loads on the various systems that support the production also increase. This paper puts forward the potential benefits in applying the MES system for testing and validation of performance and scalability to measure the various key parameters, thus providing good ROI by early detection of potential problems. Mon, 26 Jan 2009 13:08:40 GMT http://www.fabtech.org/ white_papers/_a/chiller_plant_optimization/ By Terrence Morris & Steve Blaine PE, CH2M HILL, Oregon, USA Outside of the process tools themselves, the chilled water plant is typically the single largest consumer of electrical energy in a semiconductor facility. This load includes not just chillers but also cooling tower fans, primary pumps, secondary pumps and condenser pumps. In order to meet the cooling requirements for any particular heat load, many different combinations of this equipment can be run. However, electricity consumption varies considerably depending on the combination of equipment used and the operating levels of the individual components. Selecting the optimal mix of equipment and operating levels presents a substantial challenge for an automatic control system and plant operators. Typically, no method is available to predict the effect of interactions and variations in load demand and outside air. This makes it challenging, if not impossible, to find an equipment mix that achieves optimal energy use. In response to this challenge, we set out to create a model/tool that would allow operators to automatically determine the optimal equipment mix to satisfy cooling requirements and minimize energy use. This paper describes how this model was created and how it works. Wed, 21 Jan 2009 18:43:29 GMT http://www.fabtech.org/ white_papers/_a/38th_edition_cmos_32nm_technology_node_business_as_usual_for_interconnect_d/ By Gerald Beyer et al, IMEC - ABSTRACT - Although immersion-based 193nm lithography has been able to provide significant improvements in resolution, a through-pitch solution for the critical dimensions of the CMOS 32nm technology node is not currently attainable. The commonly used lithography approach is to create all patterns per metal layer in a single exposure. Double patterning is the most likely choice to create damascene features of a half pitch of about 50nm, which will be a typical value for the 1X layers of the CMOS 32nm technology node. The consequences of this patterning choice on the other process steps in the damascene flow are under examination, while the potential of this patterning approach for the creation of structures for the CMOS 22nm node is being stressed. Thu, 15 Jan 2009 17:21:26 GMT http://www.fabtech.org/ white_papers/_a/38th_edition_the_holistic_route_to_high_yields_at_smallest_feature_sizes/ By Bernardo Kastrup, ASML, Veldhoven, The Netherlands - ABSTRACT - Feature shrink is the force that drives the semiconductor industry forward. At each step along the technology roadmap, manufacturers need to be able to produce chips efficiently, cost effectively and with high yield. As feature sizes become ever smaller, the manufacturing challenges increase almost exponentially, putting extremely tight requirements on parameters such as overlay and critical dimension uniformity (CDU). Even the tiniest process variation can have a potentially disastrous effect. In order to remedy these challenges, this paper’s proposal for a holistic manufacturing approach claims to avoid these effects by looking at all of the essential steps and processes together as a whole. Thu, 08 Jan 2009 18:55:45 GMT http://www.fabtech.org/ white_papers/_a/38th_edition_metrology_equipment_for_the_45_32nm_nodes/ For a state-of-the-art fab to achieve profitable production yields, successful in-line metrology is essential. Full functionality and high circuit speed are achieved only through control of defectivity and tight distributions of feature sizes. In-line monitoring of applicable metrics is key to ensuring success. It is also used to fine-tune production processes for improved yield and circuit speed. Metrology has now become an inherent part of missioncritical production processes. This article gives a high-level overview of the findings of the ISMI metrology program to review some of the major manufacturing challenges at future ITRS technology nodes. Thu, 11 Dec 2008 17:32:56 GMT http://www.fabtech.org/ white_papers/_a/sources_of_overlay_error_in_double_patterning_integration_schemes/ David Laidler, Philippe Leray, Koen D’Havé & Shaunee Cheng, IMEC, Leuven, Belgium Sat, 01 Mar 2008 15:52:48 GMT http://www.fabtech.org/ white_papers/_a/193nm_reticle_haze_the_dirty_little_secret_and_its_ultimate_solution/ Oleg Kishkovich, Anatoly Grayfer & Frank V. Belanger, Entegris, Inc., Franklin, MA, USA Sat, 01 Mar 2008 12:34:20 GMT http://www.fabtech.org/ white_papers/_a/emerging_materials_in_semiconductors/ Mark Thirsk & Mike Corbett, Linx Consulting LLC, Massachusetts, USA Sat, 01 Mar 2008 12:13:54 GMT http://www.fabtech.org/ white_papers/_a/special_valve_configurations_and_evolutions_for_new_ald_precursors/ John Baxter, Swagelok Company, Solon, OH, USA Sat, 01 Mar 2008 11:53:28 GMT http://www.fabtech.org/ white_papers/_a/the_effect_of_hcl_permeaton_through_pfa_on_expected_component_life/ Don Grant & Debra Carrieri, CT Associated, Inc., Eden Prairie, Minnesota, USA Sat, 01 Mar 2008 11:33:17 GMT http://www.fabtech.org/ white_papers/_a/advanced_process_control_of_copper_electroplating_thickness_profile/ Sai Boyapati, Kevin Chamness, Frank Smith, Patrick Cowan & John Crowley, Spansion, Inc., Austin, Texas, USA Sat, 01 Mar 2008 11:30:55 GMT http://www.fabtech.org/ white_papers/_a/meeting_the_doping_challenges_the_case_for_plasma_doping/ Jose I. Del Agua, Tze Poon, Pete Porshnev $ Majeed Foad, Applied Materials, Inc., Santa Clara, California; Malgorzata Jurczak, Jean-Luc Everaert & Wilfrid Vandervorst, IMEC, Leuven, Belgium Sat, 01 Mar 2008 11:01:47 GMT http://www.fabtech.org/ white_papers/_a/contamination_control_for_the_32nm_node/ Twan Bearda, Rita Vos, Paul W. Mertens, Gabriela Catana & Cedric Huyghebaert, IMEC, Leuven, Belgium Sat, 01 Mar 2008 10:55:21 GMT