FPGA BLOG

Quartus II Synthesis Error During Compilation

noreply@blogger.com (fpgaforum) — Thu, 6 Jul 2017 10:27:00 -0700

If you are seeing the following error message and wondering what is wrong with your System Verilog syntax, then, you have come to the right place. I believe you are using dual dimensional input and/or output in the module port list like shown in the template below. The truth is there might be nothing wrong with your code, you just need to add the System Verilog file into the Quartus II project.

module SubModule

(
  input clk,
  input reset,
  input[15:0]          input_port[0:3],
  output reg[15:0] output_port[0:3]
);

endmodule

To add this file to your Quartus II project, simply go to Project menu and choose “Add/Remove Files in Project…”. The rest of the steps should be quite straight forward for you. Just choose the file and add it in the project. Then, recompile your Quartus II project. After that, this synthesis error will disappear. Before doing this step, if you right-click on the error message and choose Help, it will show you the Quartus II help like the shown in the link below but to me this help content doesn’t help at all.

http://quartushelp.altera.com/17.0/index.htm#msgs/msgs/evrfx_sv_aggregate_port_connection_requires_module.htm

I need to write this down to keep reminding myself not to fall into the same trap again. Sometimes, it could just take hours to realize about this. As far as I know, this happens to the latest Quartus II version 17.0 (latest as of today) and also earlier Quartus II versions.

Here is the synthesis error message displayed in the Quartus II message window.

ID:10703 SystemVerilog error at <location>: can't resolve aggregate expression in connection to port <number> on instance "<string>" because the instance has no module binding

Hope this helps you.

Any Replacement For Altera EPCQ Devices?

noreply@blogger.com (fpgaforum) — Tue, 16 Jun 2015 08:09:00 -0700

I previously wrote an article “Any Replacement For Altera EPCS Devices?” in year 2006. I hope it has helped a lot of engineers out there. This article serves the same purpose. I just want to raise the same awareness here especially if this is your very first time using Altera FPGAs. You can confidently replace the expensive EPCQ devices with N25Q serial flash from Micron. The price difference is really huge! Look at price table below. I don’t even need to elaborate more. Prices are quotated from Digikey or Newark website as of today.

Density	Altera Part Number	Price (USD$)	Micron Part Number	Price (USD$)
32Mb	EPCQ32SI8N	11.00	N25Q032A13ESC40G	1.08
64Mb	EPCQ64SI16N	18.00	N25Q064A13ESE40E	1.64
128Mb	EPCQ128SI16N	30.00	N25Q128A13ESE40E	1.88
256Mb	EPCQ256SI16N	50.00	N25Q256A13ESF40G	3.06

Besides the cost difference, there is a huge advantage by using N25Q128 or N25Q064. Their packages are both SOIC-8 whereas EPCQ64 and EPCQ128 are only available in SOIC-16 packages as of today. This could save you some board space!

I personally had tested N25Q128A13ESE40E and N25Q256A13EF840E on hardware to configure Altera FPGAs in both Active Serial x4 and Active Serial x1 modes. It works fine. No issue for the Quartus II software programmer to program the POF files into these N25Q devices, too.

Function '__builtin_stwio' could not be resolved

noreply@blogger.com (fpgaforum) — Fri, 28 Feb 2014 08:57:00 -0800

If you are using Eclipse IDE for Altera NIOS II C++ firmware development, you will probably be annoyed by the following two reported semantic error messages when you are using IOWR() and IORD() macros from the io.h:

Function '__builtin_stwio' could not be resolved for IOWR() functions in the C++ code.

Function '__builtin_ldwio' could not be resolved for IORD() function in the C++ code.

Anyway, you will still be able to load and run the firmware program in the hardware successfully and everything is working as expected.

These two error messages (builtin stwio could not be resolved and builtin ldwio could not be resolved) are however do not appear if you convert your C++ code to C code.

But you want to write your code in C++. The question is how to remove the two reported semantic error messages above because they are very annoying and they keep distracting you from the actual error messages?

Simple. Go to the Windows in main menu bar. Select Preferences. On the left-hand column, expand C/C++. Select Code Analysis. Scroll down a bit on the right-hand column. Look for the option Function cannot be resolved. Then, it is up to you to change this setting. You can uncheck the option for Function cannot be resolved. Or, you can just change it to Info or Warning from the drop-down list.

Important reminder, after applying the change of the setting, don’t forget to close the Eclipse IDE and reopen it. I noticed that without restarting the Eclipse IDE, the new setting is not effective. After restarting the Eclipse IDE, you will notice that the two semantic error messages above are no longer reported as error.

Cyclone V needs Windows 64-bit

noreply@blogger.com (fpgaforum) — Mon, 21 Oct 2013 08:30:00 -0700

Seeing Cyclone V architecture is almost like a dream comes true, at least for me. If you told me that this will be the Cyclone V architecture ten years ago, I would laugh at you right away, “Are you sure you are not talking about Stratix?”

By the way, your fear is true, Quartus II compilation for Cyclone V FPGA device requires Windows 64-bit OS. I had tried to compile a few designs targeting Cyclone V FPGA using a 32-bit Windows 7 Professional laptop with 4Gbytes memory, it all ended with failure due to out of memory. In fact, one of the designs was a relatively small design with around 1800 logic elements using the smallest Cyclone V GX device 5CGXFC3BF7F23C8.

Anyway, this is not a nightmare. You just need to plan ahead by preparing yourself a PC with Windows 64-bit OS if you are serious in using any Cyclone V device in your new design.

Well, compiling a simple 32-bit counter won’t crash, though.

Quartus II 9.1 and NIOS II 9.1 on Windows 7

noreply@blogger.com (fpgaforum) — Wed, 14 Apr 2010 11:48:00 -0700

I am sharing my personal experience here. I have been using Quartus II 9.1 and NIOS II IDE 9.1 on Windows 7 since they were released. Now, I am using Quartus II 9.1 SP2 and NIOS II IDE 9.1 SP2.

A lot of users were asking questions the compatibility of these softwares on Windows 7.
Quartus II 9.1 and its SOPC builder seem to work fine on Windows 7 since the first day they are installed.

It is the NIOS II IDE 9.1 that really bothered me. Most of the time when you build a project, it will report error messages like two examples below. The success rate is only 20%.

Example 1:
make -s all includes
3 [main] ? (3732) c:\altera\91\quartus\bin\cygwin\bin\make.exe: *** fatal error - couldn't allocate heap, Win32 error 487, base 0x9E0000, top 0xB30000, reserve_size 1372160, allocsize 1376256, page_const 4096
2 [main] make 7588 fork: child -1 - died waiting for longjmp before initialization, retry 0, exit code 0x100, errno 11
make: vfork: Resource temporarily unavailable

Example 2:
make -s all includes
3 [main] ? (4980) c:\altera\91\quartus\bin\cygwin\bin\make.exe: *** fatal error - couldn't allocate heap, Win32 error 487, base 0x970000, top 0xA40000, reserve_size 847872, allocsize 851968, page_const 4096
2 [main] make 1972 fork: child -1 - died waiting for longjmp before initialization, retry 0, exit code 0x100, errno 11
make[1]: /cygdrive/c/altera/91/nios2eds/components/altera_hal/build/common.mk:54: fork: Resource temporarily unavailable
3 [main] ? (6092) c:\altera\91\quartus\bin\cygwin\bin\make.exe: *** fatal error - couldn't allocate heap, Win32 error 487, base 0x970000, top 0xA60000, reserve_size 978944, allocsize 983040, page_const 4096
8408744 [main] make 1972 fork: child -1 - died waiting for longjmp before initialization, retry 0, exit code 0x100, errno 11
make[1]: /cygdrive/c/altera/91/nios2eds/components/altera_hal/build/chac_rules.mk:147: fork: Resource temporarily unavailable
make[1]: *** No rule to make target `/bin/gtf/generated_all.mk.gtf', needed by `system_description/../obj/generated_all.mk-t'. Stop.
make: *** [system_project] Error 2
Build completed in 40.947 seconds

Some says it is related to the Norton Antivirus software. Yes, my PC is installed with Norton Antivirus software. But I observed that it happened to Windows 7 PC which is not installed with Norton Antivirus software, as well. Turning off the Norton Antivirus software does slightly help to increase the probability that the project is successfully built, from 20% to about 40%.

Anyway, I found some tricks which can make your life easier if you are using Nios II IDE 9.1 on Windows7.

Under your Quartus II folder, go to bin->cygwin->bin folder, select the following files in the list below and then right-click and choose Properties. Under the Compatibility tab, check “Run this program in compatibility mode for:” and choose “Windows XP (Service Pack 2)”. Check “Run this program as an administrator”, as well.
Here is the list of files that you can select to change their compatibility mode under the Quartus II->bin->cygwin->bin folder:
1. Make.exe
2. Sh.exe
3. Echo.exe
4. Cygstart.exe
5. MakeInfo.exe
6. Perl.exe
7. Collect2.exe (under nios2eds\bin\nios2-gnutools\ H-i686-pc-cygwin\libexec\gcc\nios2-elf\3.4.6)
8. Nios2-elf-g++.exe (under nios2eds\bin\nios2-gnutools\ H-i686-pc-cygwin\bin)

By doing the steps mentioned above, the success rate of building a project in NIOS II IDE 9.1 will be increased to above 90%.

When your Altera USB-Blaster is not working ...

noreply@blogger.com (fpgaforum) — Fri, 3 Oct 2008 14:46:00 -0700

When your USB-Blaster is not working and you have verified that it is neither USB Driver issue nor PCs issue nor USB cables issue, there is no need to feel disappointed, frustrated and throw away the USB Blaster which worth USD$300 market value yet.

There is still hope to salvage your USB Blaster. You can try to replace both the MAXIM low-voltage level translator parts (part number: MAX3378E) on the small USB-Blaster board. Usually, I found that both the MAXIM parts need to be replaced when I came across a bad USB-Blaster. Their reference designators on the small USB-Blaster board are labeled U2 and U5, respectively.

Alternatively, if you can’t find the MAXIM parts, you can use Texas Instruments 4-bit bidirectional voltage-level translator with part number TXS0104EPWRG4. It works equally fine and slightly cheaper, too.

Thick Film Resistor vs Thin Film Resistor

noreply@blogger.com (fpgaforum) — Thu, 6 Sep 2007 15:21:00 -0700

If you are a system designer, you probably always find that there are two kinds of chip resistor, which are thick film resistor and thin film resistor. The question is, what is the difference between thick film resistor and thin film resistor?

Found this site that explains the difference.

Cyclone series continues ...

noreply@blogger.com (fpgaforum) — Sat, 31 Mar 2007 09:03:00 -0700

Finally, Altera launched Cyclone III, after a couple of months lauching Stratix III. Of course, success stories should be continued... That's why we still see Cyclone III and Stratix III today.

To be honest, I anticipated improvement on the Cyclone III logic elements architecture compared with Cyclone II, such as implementing a 5-input LUT in a logic element. Nonetheless, other improved features are pretty interesting, too. I am particularly excited with M9K, PLL reconfiguration and improved I/O element.

The cost is an important factor when you are evaluating a new device. However, the cost factor is never mentioned in the data sheet or handbook. I am referring to Digikey for cost comparison among all the Cyclone series families. EP3C25 is chosen as benchmark as it is the only Cyclone III FPGA available now. The Cyclone II and Cyclone FPGAs that come closest to this density are EP2C20 and EP1C20, respectively. No doubt, from the table below, Cyclone III is certainly worth considered if you have a new design to start with a low-cost FPGA. At a slightly lower price, you can get a higher performance, same density and twice internal memory size for Cyclone III FPGA, compared with Cyclone II and Cyclone I.

Cyclone series	EP3C25F256C8NES	EP2C20F256C8	EP1C20F324C8
Price	$44.80	$42.70	$60.00

Low power consumption seems to be the highlight for Cyclone III in the Altera marketing slides. Unfortunately, that doesn’t interest me too much as I am not working very much on the portable designs. Anyway, I still hope to use 65-nm Cyclone III and Stratix III parts for my new coming designs.

Can PLL self-locked without "External" input?

noreply@blogger.com (fpgaforum) — Sat, 14 Oct 2006 04:50:00 -0700

I was busy working on something and suddenly a crazy idea came up.

Can a PLL lock itself if I connect a PLL output clock to the PLL input clock on a PCB and both the PLL multiplication and division value is set to 1? I expected the answer is no, of course. But the curiosity kills sometimes. So, I went ahead and did the simple test.

I was using a Cyclone II device. Surprisingly, I saw the PLL locked output signal went high. However, the output signal frequency wasn't the expected frequency (10MHz). I probed at the PLL output clock (which was also connected to the PLL input clock signal), it showed about 420kHz.

So, what is the conclusion of this story? Nothing.

Lattice Now Blogs!

noreply@blogger.com (fpgaforum) — Sat, 2 Sep 2006 19:32:00 -0700

Insteresting! Lattice now blogs! A lots of non-confidential-but-technical information out there!
It is always nice to see a FPGA vendor takes initiative to provide a platform for their knowledgable engineers to share their experience and knowledge. The good thing is that the knowledge shared is not only limited to Lattice products but all the vendors FPGA.
I know it is not easy for the writers as they now have one more repeatitive task in their long to-do list besides their daily jobs. Anyway, I hope they continue doing this! Bravo to all the writers!

Embed Tclet in Your HTML

noreply@blogger.com (fpgaforum) — Tue, 1 Aug 2006 09:18:00 -0700

Since started this blog, I found out that I need to study a minimum amount of HTML to display my writing correctly. Besides, I can have more control writing in "HTML mode" compared with "Compose mode". For an example, you can't just type the symbol "<" in your blog message, instead, you need to type "<" to display "<" in your blog. Don't get me wrong, I am not trying to show off my HTML skills. In fact, I only have very basic and minimum knowledge about HTML.

Anyway, if I am not wrong (considering myself not a webmaster), it seems like HTML alone doesn't have the ability to let you do real-time programming stuff on your web browser, such as Mozilla Firefox or Internet Explorer. However, it can be done using a plugin.

There are many different types of plugins out there, but I choose to use Tcl applet or Tclet since I did some study on this language before. (If you've never heard of the Tcl/Tk language before, you can visit here.) I don't know how to embed a Tclet properly in blogspot. However, I manage to do it on another free site. This Tclet in this free site is to display all the gray code counter results in sequence after you have entered the number of bits your gray code counter is. I don't know how useful it is to you, but it is useful to me because I always forget how the gray code counter increments. Bear in mind that if you are a first-time user or viewer, you need to download and install the Tcl Web Browser Plugin for free. And, of course, it is SAFE to be installed in your PC. If you haven't installed it yet, you will see a blank square instead of the picture on the left side here.

It will be a bit long for me to describe how to embed Tclet in your HTML code here. The best source is the reference book that I show in here. Of course, you can look at the HTML code in the example above. Plenty of funky Tclet examples can also be easily found on web if you are interested to see others. Hope you like it.

Save More Power In Handheld Devices

noreply@blogger.com (fpgaforum) — Thu, 13 Jul 2006 09:26:00 -0700

How to save more power when your CPLD device is in idle mode?
Use a very slow clock to reduce toggle rate? Partially disabling the logic inside the device? Well, why not powering off the device?
I came across this interesting article by accident and found it a simple yet smart idea to prolong the battery life of a portable handheld devices. In future, if I have the chance to design a portable product with interactive user interface, this idea will surely be the first one to cross my mind.
If for whatever reason, you have to use a FPGA in a battery-operated product, this article will sure help you more.

OP-AMP Configurations Recall

noreply@blogger.com (fpgaforum) — Sun, 2 Jul 2006 08:58:00 -0700

It has been a while since I last dealed with op-amp. So, it is good to recall some of the most fundamental op-amp configurations, especially when I am dealing with them recently.
In my opinion, op-amp is like logic gates in analog world. You need op-amps to transfer your analog inputs into your desired analog outputs.
The following are some important notes for me, not for you, of course, :)!

Common Names	Op-Amp Circuits	Transfer Functions
Voltage Follower Amplifier		Vout = Vin
Inverting Amplifier		Vout = -(Rf/Rs)Vin
Noninverting Amplifier		Vout = (1+R2/R1)Vin
Difference Amplifier		If R1/R2 = R3/R4, Vout = (V_in+ - V_in-)(R2/R1) + V_shift
Summing Amplifier		Vout = (R2/R1)* (V1+V2-V3-V4)

Embedded Logic Analyzer inside FPGA

noreply@blogger.com (fpgaforum) — Sun, 4 Jun 2006 02:57:00 -0700

There is no reason to doubt that most of the FPGA users like you and me have gone through some painful experiences wanting to know what is happening inside an FPGA. It is even more painful when you strongly believe your code is working fine and you don’t have any clue which part of the design is causing you sleepless nights. You keep on routing all the suspected internal signals to the very limited unused I/O pins of your FPGA and then probe and trigger them on your oscilloscope that usually has only four channels or LESS! Sad to say, the oscilloscope couldn’t help much in situation like this unless it is related to the signal integrity issue.

If you are lucky, you can have a logic analyzer instrument to sample a lot of signals for your analysis and verification. Well, if you are not, good news for you, you can insert an embedded logic analyzer inside your FPGA and it is totally licensed-free, at least for Altera FPGA users! The Altera Embedded Logic Analyzer tool named SignalTap II is FREE for use even you don’t purchase any software license from Altera. That means you can use your SignalTap II inside Quartus II Web Edition software for FREE provided that you install and enable the TalkBack Feature of Quartus II software.

The SignalTap II works almost like a logic analyzer equipment but at a very much smaller scale as it has very limited on-chip memory to store the sampled data. Other logic analyzer’s features such as Rising-Edge triggering, Falling-Edge triggering, Either-Edge triggering, Boolean triggering, Multi-Level triggering and others are also available in the SignalTap II tool. In fact, you can also instantiate up to 127 SignalTap II instances in your design, as long as it can fit in your chosen FPGA device. You can imagine each instance of SignalTap II is a small scale of logic analyzer equipment which also has an external trigger-in and trigger-out. And, the input of the trigger-in can come from other instances trigger-out or I/O pins or any internal logic signal. I think this is an advantage to the SignalTap II because a logic analyzer equipment trigger-in must come from one of your device I/O pins, isn’t it? Anyway, I rarely make use of the trigger-in, trigger-out and the multiple analyzer features because I prefer to monitor all my signals in just one analyzer. Why bother creating so many instances of analyzer where it doesn’t help saving you any logic and memory resource at all? One of the reasons is you need to have different acquisition clocks for the signals that you are interested to tap. It could also be you have different sample depth requirement for your acquiring signals and etc.

The purpose of this post is not to teach you using SignalTap II, but to make you aware of the availability of this tool if you haven’t come across or heard of this tool. My life as a FPGA user would have been a lot easier if I learnt to use this tool immediately after learning Quartus II. Instead, I only had the chance to pick up this tool after about one year being an Altera user. It is worth every moment to learn and pick up this tool as it makes your debugging process simpler and a lot faster. Unlike Xilinx’s ChipScope Pro, you don’t need to install the SignalTap II tool separately. It comes together with Quartus II and it is available after the Quartus II installation is done.

Last but not least, thanks to Altera that the SignalTap II is FREE!!

USB-Blaster vs Platform Cable USB

noreply@blogger.com (fpgaforum) — Fri, 19 May 2006 11:48:00 -0700

Both USB-Blaster and Platform Cable USB are the USB download cables provided by Altera and Xilinx, respectively. Most of time, the download cable is a necessity while developing and debugging your design in the FPGA. You need them to download the FPGA configuration bitstream through JTAG or Passive/Slave serial mode, to program the CPLD, to program the configuration device, to download your firmware into the soft processor and to tap the signals inside the FPGA through the FPGA embedded logic analyzer. Both of them are able to achieve all the above-mentioned purposes. But what is the main difference between them? The SELLING PRICE!!! The USB-Blaster costs USD$300 while the Platform Cable USB only costs half the price of the USB-Blaster, which is USD$149. This is really killing me because sometimes I need to use more than one download cable at the same time when dealing with multi-FPGA environment. Why can’t the Altera USB-Blaster at least cost the same like the Xilinx Platform Cable USB? In fact, Xilinx Platform Cable USB has even more features than USB-Blaster such as programming the configuration clock frequency. The USB-Blaster operates at USB full speed, which is 12Mbps, while the Platform Cable USB can operate at USB high speed!

Frankly speaking, the download cable should cost as cheap as possible by the FPGA vendors because they should be making money from selling their FPGA and CPLD devices, not from selling the download cables. Similar to the Quartus II and ISE web edition software tool, the download cable should just be a marketing tool to help promote the usage of FPGA or CPLD solutions! Imagine if I am a newbie who want to learn to use FPGA or CPLD on my own, it doesn’t make sense for me to buy a tool that is much much more expensive than a single low-cost FPGA/CPLD device.

Anyway, just for your reference, I also compare the cost of download cables that use the PC parallel port interface which are Altera ByteBlaster II, USD$150 and Xilinx Parallel Cable IV, USD$95. Once again, Xilinx is the winner when it comes to the price war. Is this the reason Xilinx being the market leader? Well, you know better.

/////////////////////////////////////////////////////////////////////////////////
// Disclaimer: All the price stated above are extracted from Altera Buy On-Line and Xilinx Online Store websites at the posting time and may change from time to time in future.

Convert Floating Point to String

noreply@blogger.com (fpgaforum) — Fri, 5 May 2006 03:27:00 -0700

A few months ago, I found out that there is no built-in function for converting a floating point data type variable to a string although there are functions that do the following:

1. Convert a string to floating point (atof)
2. Convert an integer to string (itoa)
3. Convert a string to an integer (atoi)

All the above functions come in very handy when you want to write your data to a text file. It is quite intriguing because itoa(), atoi() and atof() are provided but ftoa() are not. Unfortunately, many data are floating points in nature. Also, data that are larger than a 32-bit integer are usually represented as floating point data type. Anyway, many programming experts have already provided ftoa() solution on their websites. I believe it is not difficult to find one out there but I would like to have my very own one, too, as it is no harm trying. The C/C++ code is as shown below. I have tested it in the Microsoft Visual C++ compiler but I do not cover all the possible cases. So, use it on your own risk. It is not the best solution available for ftoa() but it certainly enough to meet my purposes. If you need one, I hope that it helps you, as well. If not, you can always write one for yourself.

////////////////////////////////////////////////////////////////
// my_ftoa.cpp
// date created: May 5, 2006
// author: http://fpgaforum.blogspot.com/
////////////////////////////////////////////////////////////////

#include <iostream>
#include <cmath>
using namespace std;
#define PRECISION_POINT 4 //Change this to display more or less precision point

void ftoa(float f, char* a, int point); //function prototype

void main()
{
  float f = -1.23456;
  char result[32];
  ftoa(f,result, PRECISION_POINT);
  cout << result;
}

void ftoa(float f, char* a, int point)
{
  char buf_int [2]; //temporary buffer
  char buf_d [16]; //to store the integral part, e.g. "-123" for "-123.456"
  char buf_f [16]; //to store all the fraction part, e.g. "000123" for "1.000123"
  char buf_nz [16]; //to store the non-zero fraction part, e.g. "123" for "1.000123"
  int d= (int)(f); //integral part

  float fp = (f<0) ? (d-f) : (f-d); //fractional part

  int fp2int = fp*(pow(10,point));
  int fpplus1 = fp*(pow(10,point+1));

  if((fpplus1%10)>=5)
    fp2int++;

  strcpy(buf_int,"");
  strcpy(buf_d,""); //clear the buffer, just to be safe
  strcpy(buf_f,""); //clear the buffer, just to be safe
  strcpy(buf_nz,""); //clear the buffer, just to be safe

  if((d == 0) && (f<0) && (f>-1))
  {
    strcat(buf_d,"-");
    itoa(d,buf_int,10);
    strcat(buf_d,buf_int);
  }
  else
  {
    itoa(d,buf_d,10);
  }
  strcat(buf_d,".");
  //looking for the leading zeros at the fractional part
  if(fp2int == 0)
  {
    for(int i = 0; i < point-1; i++)
      strcat(buf_f,"0");
  }
  else if(fp2int < (pow(10,point-1)))
  {
    for(int i = 0; i < point; i++)
    {
      int j = pow(10,(point-1-i));
      if(fp2int < j)
        strcat(buf_f,"0");
      else break;
    }
  }

  itoa(fp2int,buf_nz,10);
  strcat(buf_f,buf_nz);
  strcat(buf_d,buf_f);
  strcpy(a,buf_d);
}

// The end
////////////////////////////////////////////////////////////////

Tcl Script to Automate Quartus II Compilation

noreply@blogger.com (fpgaforum) — Fri, 21 Apr 2006 09:41:00 -0700

Below is a sample Tcl script that I use to automate the compilation of my Quartus II projects overnight or over the weekend. You can easily find more information about the usage by just typing "tcl" on the Altera search column in www.altera.com and you can easily get some examples over there. The most relevant reading material for Quartus II tool specific scripts would be the Tcl Scripting chapter of the Quartus II Handbook.

############################################
## auto_compile.tcl
## date created : April 9, 2006
## author : http://fpgaforum.blogspot.com
############################################

###Assume that the objective of this script is to compile
###a similar project twice, one with a minimum current strength
###and the other with a maximum current strength.
###(Sometimes you need to do some characterization of the current
###strength on your hardware!)
###The final product is two sof files, one for the minimum
###current strength and the other one for the maximum
###current strength. This means that this script will also rename
###the sof file for after every compilation to avoid being overwritten
###on the next compilation cycle

###go to project folder in command prompt
### Then type quartus_sh -s
### Verify the Quartus II Version number is as targeted, if you have multiple
### versions of Quartus II on your PC
### After verified, type the following command:
### source (This filename.tcl)
### OR
### Open the Quartus II project, then open up the Quartus II Tcl Console by
### go to View->Utility Windows->Tcl Console
### In the Quartus II Tcl Console, type the following command if the tcl script
### is placed in the project folder:
### source (This filename.tcl)

########## TCL script starts #################

####### Auto Compilation TCL Script ############
#change the following line according to your Quartus II project folder##
##assume the 1st project that I want to compile is in the following folder
cd D:/data/project1

##This is to set the minimum current strength
set project_name project1
set revision_name project1
project_open -revision $revision_name $project_name;
set_global_assignment -name Family StratixII
set_global_assignment -name DEVICE EP2S60F1020C3ES

#some assignments to the pins. Of course, I am not going to list all
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to data_bus[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to data_bus[1]

load_package flow
execute_flow -compile
project_close

set sof [pwd]/project1.sof
if [file exists $sof] {
file rename $sof project1_MIN.sof
} else {
puts "ERROR! RENAME $sof to project1_MIN.sof"
}

###======================================

##This is to set the maximum current strength
set project_name project1
set revision_name project1
project_open -revision $revision_name $project_name;
set_global_assignment -name Family StratixII
set_global_assignment -name DEVICE EP2S60F1020C3ES

#some assignments to the pins. Of course, I am not going to list all
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to data_bus[0]
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to data_bus[1]

load_package flow
execute_flow -compile
project_close

set sof [pwd]/project1.sof
if [file exists $sof] {
file rename $sof project1_MAX.sof
} else {
puts "ERROR! RENAME $sof to project1_MAX.sof"
}

###======================================
########## TCL script ends #################

The Secret of NIOS II Success

noreply@blogger.com (fpgaforum) — Wed, 19 Apr 2006 09:50:00 -0700

Altera NIOS II soft processor has been known as the world’s most versatile embedded processors. What is the reason behind since in my opinion the CPU architecture is more or less the same compared with other processors? In my opinion, the unsung hero that contributes to the success of the NIOS II processor is the Avalon Switch Fabric. I find it a bit weird that Altera or distributors does not put very much effort in directly marketing the Avalon Interface Specification introduced by Altera years ago. I strongly believe that the user-friendly Avalon Interface is one of the main reasons engineers choosing NIOS II processor over their main rival’s Xilinx MicroBlaze processor. It doesn’t matter whether you are designing a master or slave peripheral, as long as your own-designed peripheral supports Avalon Interface, your peripheral can communicate with others peripheral, including NIOS II processor flawlessly as the Avalon Switch Fabric will handle the communication for you.

The Avalon Switch Fabric is generated by Altera SOPC Builder that comes together with Quartus II software tool. That means after installing Quartus II, you do not need to worry about installing the SOPC Builder as it is part of Quartus II software. I like this because I don’t like to open a few application softwares at the same time doing one job. Another good point to mention about the SOPC Builder is the evaluation is free and valid for unlimited period. You just have to re-apply a new Quartus II web edition license about every three months through internet and the license will be sent to your email in split seconds. Too bad that the newly-announced NIOS II C-to-Hardware Acceleration (C2H) Compiler is not available for evaluation to the public without going through the Altera distributors. I am very curious with the improvement achieved using the C2H compiler.

Although many free peripherals that support Avalon interface are available, such as SDRAM controller, DDR SDRAM controller, interval timer, DMA module, UART, etc, it is still very critical to be able to connect your custom IP to the Avalon Switch Fabric. You will find yourself in a situation at times where you need to complete a lot of intensive calculation work within a very short period of time in FPGA. Some good examples are carrying out blemish test for a camera module and CRC checking for a large amount of data. Most of the time, the intensive calculation part takes too much time in C and therefore you can design your own IP in HDL to achieve the performance needed. The purpose of the new C2H compiler is to help the software designers who are not familiar with HDL to accelerate the software functions in their systems. I don’t know how good they are yet without evaluation but I truly believe that if you know HDL, you are still the best person to do the parallel processing in hardware for yourself.

The Avalon Interface uses very easy-to-understand signal types, such as chipselect, read, write, address, clock, reset, readdata, writedata, etc and you can expect yourself to get comfortable with this standard within a day or two. The latest feature that was added to Altera Avalon Interface Specification is Burst Transfer, which is very useful when maximum throughput is required. Burst Transfer guarantees that arbitration between the Avalon Master-Slave pair locked throughout a burst until the burst completes.

Many engineers misunderstand that Avalon Switch Fabric is meant for FPGA devices. Guess what, the CPLD device such as MAX II also supports Avalon Interface. For an example, you can design your custom IP, say a SDRAM master that reads and writes to a SDRAM device that connects to your MAX II device. The setup in the SOPC Builder is as shown in the figure beside. Anyway, NIOS II processor is not supported in MAX or MAX II device as I believe the NIOS II architecture requires on-chip memory.

Recently, due to some reasons, I was required to migrate a NIOS II design to a MicroBlaze design. Unfortunately, there are so many different interface buses involved when I look at the MicroBlaze data sheet, such as On-Chip Peripheral (OPB) bus, Local Memory Bus (LMB) and Fast Simple Link (FSL) bus, just to name a few. I believe it is going to take me quite some times to go through all these new bus standards. No wonder Altera claims that the NIOS II soft processor is the world’s most versatile embedded processor. Well, I think they are right.

Essential Guide to RF and Wireless

noreply@blogger.com (fpgaforum) — Sat, 8 Apr 2006 00:09:00 -0700

If you find yourself in of the following categories, then, BINGO, you can consider looking for this book.

1. You are an engineer but haven’t got in touch with the RF circuitries and terminologies since graduation. Yet, you want to, or perhaps you have to recall the basic knowledge about this subject, either for interest or job requirement.
2. You are a sales and marketing person for RF stuff but have no or little background in RF industry. You need to pick up the fastest learning curve in this area in order to speak about your product features.
3. You are a science enthusiast but you don’t bother about the mathematics such as Maxwell’s equation, Gauss’s Law, etc.
4. You are an engineering undergraduate and you are on the edge of giving up when you are studying the RF subject due to the complicated multi-dimensional RF equations
5. You just want to know about the wireless and RF stuff
6. You are curious to read the content of this book after reading this post.

I read this book quite sometime ago and I did achieve what I wanted from this book. If I remember correctly, you couldn’t find any mathematics equation in this book. So, don’t worry bringing along your scientific calculator and note pad to do calculation while reading. Many jokes are there to make you feel interested and keep on looking for the next one coming. Anyway, you can easily look out for some of the content inside this book such as preface from the internet before buying this book. Well, don’t just listen to me. Find out what others’ opinion about this book, too, for your own judgement!

Accessing EPCS from NIOS II

noreply@blogger.com (fpgaforum) — Sat, 1 Apr 2006 21:11:00 -0800

If you are wondering how to access the EPCS from the NIOS II directly, you have come to the right place. I believe you might have tried to read the NIOS II handbook that covers almost 600 pages to find out the answer. Nevertheless, it seems like there is no straight answer to the question in the NIOS II handbook. You might have even tried to look into the Software Files mentioned in the chapter named EPCS Device Controller Core with Avalon Interface, which are altera_avalon_epcs_controller_flash.c, altera_avalon_epcs_controller_flash.h, epcs_commands.c and epcs_commands.h. However, still, none of these files give you much clue how to access the EPCS from the NIOS II processor.

In fact, the handler that gives you the access to the EPCS device is not alt_flash_epcs_dev (as you see in altera_avalon_epcs_controller_flash.h), but alt_flash_fd, which is the exact same handler that you use to access the common flash device like Spansion and Intel flash device. To my surprise, the NIOS II handbook does not mention about this. Perhaps this is a common sense to everybody else that the Spansion/Intel flash and the SPI Serial Flash should have a same handler, but NOT to a dummy user like me! After asking around, I believe I am not the only one who thinks like this! Therefore, I still see that there is some room for improvement in the next version of NIOS II handbook. Not every NIOS II user is a hardware designer. Not every NIOS II user is a software developer, either. Some NIOS II users like me have to do co-hardware/software design and development at the same time. Sometimes I just feel that the handbook couldn’t link me very well between the hardware and software. For an example, my earlier frustration could have been resolved if there is a small piece of C code like the following included in the Chapter 3 of the Quartus II Handbook Volume 5 (a.k.a. NIOS II Handbook Volume 3).

////////////////////////////////////////////
// hello_epcs.cpp
// date created: March 30, 2006
// author: http://fpgaforum.blogspot.com
////////////////////////////////////////////
#include <iostream>
#include "system.h"
#include "sys/alt_flash.h"
#include "sys/alt_flash_dev.h"
using namespace std;

int main()
{
  alt_flash_fd* my_epcs;
  char my_data[256];

  //check your (EPCS_CONTROLLER_NAME) from system.h
  my_epcs = alt_flash_open_dev(EPCS_CONTROLLER_NAME);

  if(my_epcs)
  {
    cout << "EPCS opened successfully!" << endl;

    //example application, read general data from epcs address 0x70000
    int ret_code =     alt_read_flash(my_epcs, 0x70000, my_data, 256);
    if(!ret_code)
    {
      cout << my_data << endl;
      return 0;
    }
    else
      return -1;
  }
  else
  {
    cout << "Error! EPCS not opened!" << endl;
    return -2;
  }
}
// The end
/////////////////////////////////////////////////////////

Anyway, I just found out that if you are lucky, you might still be able to find out the code very similar like above from the software example called memtest.c in the <NIOS II Path>\examples\software\memtest folder. By the way, you can only view the code after installing the NIOS II software tool.

Any Replacement for Altera EPCS Devices?

noreply@blogger.com (fpgaforum) — Sun, 19 Mar 2006 06:12:00 -0800

I know there are already many websites which claim that Altera Serial Configuration Devices, a.k.a. EPCS devices, can be replaced by some lower cost devices. This post is just to give you more confidence on the availability of other cheaper configuration solution for Cyclone series and Stratix II FPGAs.

Altera introduced EPCS devices at the same time the Cyclone device is announced. Traditionally, the cost of the configuration devices (EPC family) for the Altera FPGAs are quite expensive, compared with the cost of the FPGAs. Most of the FPGA users want almost zero cost for the FPGA configuration solution since the configuration device is mostly a combination of a simple controller and a non-volatile memory that stores the configuration bitstream. Therefore, when the so-called "cheapest FPGA family", Cyclone FPGA was launched by Altera, Altera also took the initiative to provide a cost efficient configuration solution for the Cyclone FPGA. The traditional configuration solution for Altera FPGAs prior to Cyclone FPGA requires a simple controller to load the configuration bitstream from a non-volatile memory and write to the FPGAs during configuration. This kind of configuration methodolgy is called passive configuration. The passive configuration can be either in serial form or parallel form, depending on the available configuration modes of the selected FPGAs. Active Serial configuration was first available in Altera Cyclone FPGA family. During the active serial configuration, the FPGA will write out the Read Bytes instruction to the EPCS device and then continuously read the data out from the serial flash from the address 0x000000 until the FPGA is configured. The smart approach greatly reduces the configuration cost by putting the simple controller in the FPGA itself. That means, the configuration cost is only left with the non-volatile memory only. As a result, the SPI serial flash is chosen to store the configuration bitstream as it is low cost, low pin count and easy to control from the FPGA.

Nonetheless, engineers are usually very calculative people. The EPCS price list, if you check from the Digikey website, looks attractive at the first glance due to the sudden price drop on the configuration solution for an Altera FPGA. As time goes by, engineers realize that the EPCS device is none but a very standard serial flash. And, a standard serial flash should cost much lower than an EPCS device with the same memory capacity. I grab some data from the Digikey website. For an example, an EPCS1 device costs USD$3.50 but a ST’s M25P10-A serial flash from ST costs as low as USD$1.10, which is a huge difference! Imagine if you are just targeting the Altera smallest Cyclone device with slowest speed grade, EP1C3T100C8 (costs USD$10.70 quoted by Digikey), you will be paying too much for the configuration solution with EPCS1. Don’t you agree? M25P10 can equally do the job well at lower cost. Why not? Don’t bother whether they are exactly the same die or not. Both devices commands and timing specifications meet the active configuration controller (embedded inside Cyclone FPGA) requirement. Even the Quartus II programmer tool recognizes ST’s M25P10-A, M25P40, M25P16 and M25P64, as EPCS1, EPCS4, EPCS16 and EPCS64, accordingly. Perhaps there are still other cheaper alternative than ST’s M25P family.

In fact, the serial flash can do even more other than the configuration solution. You can use it to store the general-purpose data! You will always find out that the serial flash always has more than enough to store the configuration bitstream, especially if you turn on the configuration bitstream compression in the Quartus II software tool. So, don’t waste the rest of the memory in the serial flash, furthermore, they are non-volatile memory, which is often useful to keep some serial numbers, identification numbers, calibration data, tracking numbers, etc. And, the microprocessor program data! For an example, you can save the NIOS II ELF file in the serial flash and boot from the serial flash after power-up. For that reason, you may need to choose a serial flash with a bigger density, to store not only the configuration data, as well as the microprocessor program data. That way, you don’t need to source another flash device to store the microprocessor data. How big the serial flash required is determined by the code size of your program. Sometimes, instead of using an EPCS4 device just to store the configuration bitstream, I will choose an EPCS16 replacement (USD$ 16.25 from Digikey), ST’s M25P16 (USD$ 4.56 from Digikey) to be my Cyclone, Cyclone II or Straitx II FPGA configuration solution as well as the storage for my NIOS II ELF file, not to mention some general-purpose user data.

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
Disclaimer: The information on this post is for informational purpose only. The author reserves the right not to be responsible for the topicality, correctness, completeness or quality of the information provided. Liability claims regarding damage caused by the use of any information provided, including any kind of information which is incomplete or incorrect, will therefore be rejected.

What is Bandwidth?

noreply@blogger.com (fpgaforum) — Sat, 4 Mar 2006 00:11:00 -0800

Introduction to Bandwidth
According to Meriam-Webster Dictionary, the definition of bandwidth is
1: a range within a band of wavelengths, frequencies, or energies; especially : a range of radio frequencies which is occupied by a modulated carrier wave, which is assigned to a service, or over which a device can operate
2: the capacity for data transfer of an electronic communications system (graphics consume more bandwidth than text does); especially : the maximum data transfer rate of such a system

Anyway, the engineers always do not take the definition from the dictionary as a simple answer. So, what is bandwidth anyway? Engineers always mention about “bandwidth” when dealing with oscilloscope, probe, trace, connectors, etc. Sometimes, due to budget limitation, engineers complain about not enough bandwidth or limited bandwidth. So what is all this fuss about bandwidth?

Ever think about why the sampling oscilloscope with 50GS/s (GS/s: sampling per second) costs so much higher than the digital phosphor oscilloscope with just 1GS/s? The reason is very simple: the scope with 50GS/s has much higher bandwidth than the scope with 1GS/s. The bandwidth of the scope with 1GS/s is about 100MHz whereas the bandwidth of the scope with 50GS/s is 50GHz. May be examples can give you a better idea about bandwidth.

Below is a scope shot of a 50MHz square wave (generated by a FPGA device) captured on a sampling oscilloscope with 50GS/s.

Below is a scope shot of the 50MHz square wave from the similar source as above, captured on a digital phosphor oscilloscope with 1GS/s.

As you can see, it doesn't seem to have much difference from both the captured scope shots of a 50MHz square wave, but sometimes looks can be deceiving. Let's check out the rising time of this 50MHz square wave. Again, both scope shots (zoomed in from the previous shots) are shown here for your reference.
Square wave rising-edge captured on a 50GS/s scope:

Square wave rising-edge captured on a 1GS/s scope:

So, as you can see, the rising-edge of the 50MHz square wave actually is within ps (pico-second)range, but the 1GS/s scope tells you that the rising-edge takes almost 1ns (nano-second). Anyway, this is still acceptable for 50MHz square wave.

Let's now measure 250MHz square wave (also generated by FPGA) on both the 50GS/s scope and 1GS/S scope.
This is measured on the 50GS/s scope:

This is measured on the 1GS/s scope:

Needless to say, the 250MHz square wave looks more like a trapezoidal wave on the 1GS/s scope.

How does 500MHz square wave look like on both scope? Here are the scope shots.
500MHz square wave measured on 50GS/s scope:

500MHz square wave measured on 1GS/s scope and it no longer looks like square wave:

Finally, this is how the 1GHz square wave looks like on the 50GS/s and 1GS/s scope, respectively. As you can see, the 1GHz not only looks more like a sinusoidal wave from the 1GS/s scope, its amplitude is also much smaller.

I believe all the above scope shots can prove to you the importance of bandwidth of a oscilloscope. Not only that, the bandwidth of a probe can also affect the results seen on the oscilloscope. The scope shot below is captured using a 4GHz FET probe and a SMA cable on a 7GHz storage scope. The signal measured is a 3.125Gbps signal generated by a Stratix GX FPGA device.

So, in conclusion, what are the considerations for the bandwidth? There are several rules of thumb when considering the bandwidth of an instrument.
1. Minimum bandwidth should be at least 5 times of the expected measured highest frequency.
2. If you are interested to measure the rise time, the minimum bandwidth should be 0.45/(rise time). Otherwise, the rise time that you have measured is inaccurate. For an example, look at the rise time of the 50MHz square wave captured above from different scopes.
3. Or, the minimum bandwidth is up to the 9th harmonic of the highest frequency, of course, higher the better. If you are not sure of what is 9th harmonic, then you can read my previous posts, History and Beauty of Sine Function and Building Square Wave from Fourier Series. That is the reason I said that the Fourier Series plays an important role in today's world and this is just one of the thousands examples or applications that have a close relationship with Fourier.

Building Square Wave from Fourier Series

noreply@blogger.com (fpgaforum) — Tue, 21 Feb 2006 08:07:00 -0800

As promised in my previous post, I would like to show how a square waveform can be built from the Fourier Series. I am using Tcl/Tk script to generate a periodic square wave from Fourier Series. The reason I am using Tcl/Tk language for this is because I have never practically done this before although I know it can be done. In case you haven’t heard about Tcl/Tk language before up to this point, you can read the previous post in this blog, The Interesting Tcl Language.

As you have known from my previous post, the periodic signals can be constructed using Fourier Series, which consists of summation of sine and cosine functions at frequencies which are harmonically related. The square wave function F(t) derived from Fourier Series is as follows:

F(t) = sin(t) + sin(3t)/3 + sin(5t)/5 + sin(7t)/7 + sin(9t)/9 + …
= ∑sin(nt)/n (n odd, 0< n <∞) (1.1)

It is too long to describe how the above function is derived. If you are interested to know how it is derived, it is not to difficult this information from the reference books or internet.

Since the square wave is luckily just constructed from summation of sine functions at different harmonic frequency, let’s display a simple sine wave using Tk first.

The Tcl/Tk source code for the above diagram is as follows. As you may agree, it doesn’t take many lines of complicated code to display a sine wave on your computer screen using Tcl/Tk script.

############################################
## sinewave.tcl
## date created : February 21, 2006
## author : http://fpgaforum.blogspot.com
############################################

wm focusmodel . passive
wm geometry . 460x360; update
wm resizable . 1 1
wm deiconify .
wm title . "Sine Wave Generator by FPGA FORUM"

label .msg1 -wraplength 4i -justify center -text "This generates a simple sine wave."
label .msg2 -wraplength 4i -justify center -text "http://fpgaforum.blogspot.com"
pack .msg1 -side top
pack .msg2 -side top

canvas .sinewave -bg black -width 450 -height 300
pack .sinewave

set coordList {}

#2*pi*f0 = w0 = 1/25
#fundamental frequency, f0 = 1/(25*2*pi)

for {set x 0} {$x<=450} {incr x} {
lappend coordList $x [expr sin($x/25.0) * 50 + 150]
}

eval .sinewave create line 0 150 450 150 -fill white -activefill blue
eval .sinewave create line $coordList -fill green -activefill red

##The end of sinewave.tcl
################################################

I purposely multiply the sine function result by a factor of 50 to amplify the sine wave. Otherwise, the sine wave would be too small.

The square wave, if constructed by the first 5 harmonics of sine functions looks like below. Of course, if you complain that this is not a square wave, then you are absolutely right. A perfect square wave is constructed when you have summed all the harmonics of sine functions according to the Equation 1.1.

The Tcl/Tk source code for generating the above square wave is as follows, and once again, the script doesn’t look much different from the one that generates a sine wave.

############################################
## squarewave.tcl
## date created : February 21, 2006
## author : http://fpgaforum.blogspot.com
############################################

wm focusmodel . passive
wm geometry . 460x360; update
wm resizable . 1 1
wm deiconify .
wm title . "Square Wave Generator by FPGA FORUM"

label .msg1 -wraplength 4i -justify center -text "This generates a square wave from the Fourier Series."
label .msg2 -wraplength 4i -justify center -text "http://fpgaforum.blogspot.com"
pack .msg1 -side top
pack .msg2 -side top

canvas .squarewave -bg black -width 450 -height 300
pack .squarewave

set coordList {}

#2*pi*f0 = w0 = 1/25
#fundamental frequency, f0 = 1/(25*2*pi)

for {set x 0} {$x<=450} {incr x} {
set y 0
set z 0
for {set N 1} {$N<=5} {set N [expr {$N + 2}]} {
set z [expr sin($x*$N/25.0) /$N* 50]
set y [expr $y + $z]

}
lappend coordList $x [expr $y+150]
}

eval .squarewave create line 0 150 450 150 -fill white -activefill blue
eval .squarewave create line $coordList -fill green -activefill red

##The end of squarewave.tcl
#####################################################

If the N is 101, then you can see that an almost perfect square waveform is displayed using the squarewave.tcl script. And, it is not too difficult for you to imagine that a perfect square wave will be generated if you keep on increasing the value of N, which is also the Nth harmonic sine wave from the fundamental sine wave frequency.

You may now feel curious about the real applications of the Fourier Series after reading this post. In my next post, I will tell you one real application that has the connection with what I have brought out in this post.

History and Beauty of Sine Function

noreply@blogger.com (fpgaforum) — Sun, 19 Feb 2006 07:01:00 -0800

Still remember when was the first time you learn about sine function? Still remember how the sine function was derived when you were in the secondary school? I first learnt about the sine function from the trigonometry chapter at 14 years old if I remember correctly. 10 years later, I almost forgot that the sine function introduction was from a right-angled triangle. Sine function of the angle A (not the right angle) in a right angular triangle is the length of the side opposite to the angle A divided by the length of hypotenuse, which is the longest side of a right-angle triangular. Cosine function of the angle A, on the other hand, is defined as the length of the adjacent side of the angle A divided by the length of hypotenuse. From the above explanation, it is not too difficult to think that cosine function is an extension from the sine function. Perhaps this is the reason why cosine function is named as co-sine function.

Everything looks so simple when I was beginning to learn the sine and cosine functions. Never could I have thought that these simple functions have so much influence on today’s mankind history. No kidding! What would happen if there was no sine function nowadays? The influence of the sine function is too much way beyond anyone imagination.

An example of the importance of Sine function is shown obviously in Fourier Series. Fourier Series was discovered by a French mathematician, Jean Baptiste Joseph Fourier (1768-1830, one of the French Revolution contributors) when he was studying and analyzing the heat flow in a metal rod. Therefore, the Fourier Series was named in honor of him. According to the Fourier Series, a periodic function can be represented by an infinite sum of sine or cosine functions that are harmonically related. For an instance, a square wave, which doesn’t seems to be any sinusoidal at all, can be represented by a Fourier Series. (If I have the time, I would like to prove it to you in graphics next time.) If you think that this is an easy statement, then you are totally wrong. Fourier Series as well as Fourier Transform which bears his name, are considered among the greatest discoveries in scientific and engineering discipline.

There are too many periodic motions or waveforms around us all the time. To name a few, signals transmitted by the cell phone base-station, television and radio stations are sinusoidal and periodic. The alternating current (a.c.) power sources generate voltages and currents are in sinusoidal form. Function or Signal Generators generate different kind of periodic waveforms in your laboratories. The generation and analyzing of the periodic motions or waveforms are made possible through Fourier Series. Anyway, the Fourier Series will not be possible if there was no Sine function before Joseph Fourier.

Isn’t it amazing? Why sinusoidal shape matters? Why not square, triangular, or circle? This is really intriguing.

The Interesting Tcl Language

noreply@blogger.com (fpgaforum) — Mon, 6 Feb 2006 05:12:00 -0800

People pronounce Tcl as "Tickel". Tcl means Tool Command Language. Usually, you see Tcl paired with its young brother, Tk. Tk is the Tcl toolkit for building graphical user interfaces.
I was first introduced by this cool Tcl language about 3 years ago when I tried to find a solution to automate the compilation of Quartus II overnight and during the weekend. Basically, I had about twenty different Quartus II projects to compile and each of them took a few hours to complete due to the large logic usage and strict timing requirement inside the designs. If I didn't automate this process, I would be wasting my time to do the manual push-button compilation after every one or two hours of compilation, which was kind of stupid. So, that was my first purpose of using the Tcl language.

However, soon after that, I found out that the Tcl language is not merely a scripting language that is limited for automation process. It can do much more than that, such as file processing, easy interface with the PC serial port without any external DLL, easy construction of GUI, interface with a DLL written by you or others, etc. Besides that, I also found out that most of the FPGA tools like Quartus II, ISE and famous third-party simulation tool, ModelSim, provide the API and platform for you to command them in Tcl language.

One of the reasons people use Tcl language is that the script written in Tcl language works regardless of the operating system used. It saves the hassle of providing the software in different versions just to support different OS.
If you never heard about the Tcl and are interested with this Tcl language, you can go to ActiveState to download the ActiveTcl software, and it is freely distributed. There are many Tcl application examples that you can easily download from the website for reference. If you would like to know even more details about this cool language, you can read the Practical Programming in Tcl and Tk written by Brent B. Welch, Ken Jones with Jeffrey Hobbs. This Tcl/Tk bestseller comes with a CD-ROM that includes all the examples used in the book and also the ActiveTcl software which may have been outdated. This book (fourth edition) has been my Tcl/Tk bible since I start using Tcl and Tk and it still is.