FPGA Journal http://www.fpgajournal.com/ The World's Premier Programmable Logic Publication Technology Tech News en Copyright 2008 Tue, 30 Jun 2009 17:27:47 GMT Tue, 30 Jun 2009 17:27:47 GMT RSS DreamFeeder v 2.2.0 46th DAC Announces Power-Scavenging Topic Wins First-Ever Community-Selected Panel Vote BusinessWire June 30, 2009 06:00 AM Pacific Daylight Time <br/> <a href="http://www.businesswire.com" target="_blank">BusinessWire</a><br/> June 30, 2009 06:00 AM Pacific Daylight Time http://www.fpgajournal.com/news_2009/06/20090630_01.htm Tue, 30 Jun 2009 20:23:00 GMT http://www.fpgajournal.com/news_2009/06/20090630_01.htm.1246382865125.4 eInfochips Announces VMM-Enabled MIPI® CSI-2, DSI & HSI and SDIO Verification IP for the Synopsys® DesignWare(R) Verification IP Alliance Program Source: PRNewswire Jun 30, 2009 09:00 ET <br/> Source: PRNewswire<br/> Jun 30, 2009 09:00 ET http://www.fpgajournal.com/news_2009/06/20090630_02.htm Tue, 30 Jun 2009 20:23:00 GMT http://www.fpgajournal.com/news_2009/06/20090630_02.htm.1246382865125.3 Curtiss-Wright Controls Announces Successful Environmental Testing of CHAMP-FX2 VPX and XMC-442 FPGA-based Application Accelerator Modules Source: Curtiss-Wright Controls June 30, 2009 <br/> Source: Curtiss-Wright Controls<br/> June 30, 2009 http://www.fpgajournal.com/news_2009/06/20090630_03.htm Tue, 30 Jun 2009 20:23:00 GMT http://www.fpgajournal.com/news_2009/06/20090630_03.htm.1246382865125.2 Broadcast Video Test Equipment Leader PHABRIX Selects National Semiconductor's 3-Gbps SDI Family Source: PRNewswire Jun 30, 2009 08:00 ET <br/> Source: PRNewswire<br/> Jun 30, 2009 08:00 ET http://www.fpgajournal.com/news_2009/06/20090630_04.htm Tue, 30 Jun 2009 20:23:00 GMT http://www.fpgajournal.com/news_2009/06/20090630_04.htm.1246382865125.1 New Package Option For Lattice MachXO PLD Family Reduces Cost And Board Area Source: Lattice Semiconductor June 29, 2009 <br/> Source: Lattice Semiconductor<br/> June 29, 2009 http://www.fpgajournal.com/news_2009/06/20090629_04.htm Mon, 29 Jun 2009 19:55:00 GMT http://www.fpgajournal.com/news_2009/06/20090629_04.htm.1246294668687.5 Mentor Graphics Extends Catapult C with Support for Control Logic to Enable Full-Chip High-Level Synthesis BusinessWire June 29, 2009 06:00 AM Pacific Daylight Time <br/> <a href="http://www.businesswire.com" target="_blank">BusinessWire</a><br/> June 29, 2009 06:00 AM Pacific Daylight Time http://www.fpgajournal.com/news_2009/06/20090629_03.htm Mon, 29 Jun 2009 19:55:00 GMT http://www.fpgajournal.com/news_2009/06/20090629_03.htm.1246294668687.4 SMSC Introduces Low-Cost, High-Performance I/O Port Expander and DTCP Co-Processor for MOST® Networks BusinessWire June 29, 2009 08:39 AM Pacific Daylight Time <br/> <a href="http://www.businesswire.com" target="_blank">BusinessWire</a><br/> June 29, 2009 08:39 AM Pacific Daylight Time http://www.fpgajournal.com/news_2009/06/20090629_02.htm Mon, 29 Jun 2009 19:55:00 GMT http://www.fpgajournal.com/news_2009/06/20090629_02.htm.1246294668687.3 Aquantia deploys Synopsys IC Validator and IC Compiler for 40nm quad 10GBASE-T design Source: Synopsys June 29,2009 <br/> Source: Synopsys<br/> June 29,2009 http://www.fpgajournal.com/news_2009/06/20090629_01.htm Mon, 29 Jun 2009 19:55:00 GMT http://www.fpgajournal.com/news_2009/06/20090629_01.htm.1246294668687.2 Altera Announces New Cyclone III LS FPGAs Source: Altera June 29, 2009 <br/> Source: Altera<br/> June 29, 2009 http://www.fpgajournal.com/news_2009/06/20090629_05.htm Mon, 29 Jun 2009 19:55:00 GMT http://www.fpgajournal.com/news_2009/06/20090629_05.htm.1246294668687.1 LinuxLink from Timesys Simplifies Development of Linux Products Using Xilinx Virtex-4 and Virtex-5 FPGAs Comprehensive solution from Timesys includes LinuxLink build environment as well as new FPGA design service PITTSBURGH, June 26 -- Timesys Corporation (http://www.timesys.com), provider of LinuxLink, the first commercial software development framework for building custom embedded Linux based products, today announced LinuxLink 3.0 support for Xilinx Virtex-4 and Virtex-5 FPGAs. Complementing this new Virtex support within LinuxLink, Timesys also announced an FPGA design service. Customers who want to focus on developing value-adding applications for their product can rely on Timesys to provide both a well-optimized hardware design and accompanying Linux platform support. With support for Xilinx's reference boards, LinuxLink customers can easily leverage the flexibility of Xilinx's FPGAs to develop custom hardware with comprehensive embedded Linux support. LinuxLink provides full support for a wide variety of peripherals including Ethernet, Serial and System ACE, enabling developers to achieve fast product design cycle. The combination of the LinuxLink framework from Timesys and the EDK development tools from Xilinx results in smooth hardware-software integration. The Xilinx EDK tools accelerate the design cycle by allowing a hardware design team to choose and customize from several IP blocks. Similarly, the Timesys LinuxLink framework accelerates software development by enabling the design, customization and integration of a custom Linux image matching the hardware platform. The combination of these development tools allows companies to create a complete custom Linux based product using the latest open source code at a very reasonable cost. "Timesys assists customers throughout the entire development process of an FPGA-based Linux platform," said Charlie Ashton, Vice President of Business Development at Timesys. "Providing LinuxLink support for Virtex FPGAs along with FPGA design services allows us to deliver an end-to-end platform design approach that is well aligned with FPGAs from Xilinx." For a limited time, developers can obtain free LinuxLink access to quickly configure, build and evaluate embedded Linux on PowerPC-based Virtex processors by registering at https://linuxlink.timesys.com/register/factory. Developers should enter promotion code PRV4V5 when completing the online free trial registration form. Additional information about LinuxLink subscriptions for Xilinx processors can be found at http://www.timesys.com/xilinx. About Timesys Source: Timesys June 25, 2009 <br/> Source: Timesys <br/> June 25, 2009 http://www.fpgajournal.com/news_2009/06/20090626_01.htm Fri, 26 Jun 2009 20:16:00 GMT http://www.fpgajournal.com/news_2009/06/20090626_01.htm.1246036633562.1 The Latest Report on the Opportunities for ARM in Embedded Processing is Available Today BusinessWire June 25, 2009 02:44 AM Pacific Daylight Time <br/> <a href="http://www.businesswire.com" target="_blank">BusinessWire</a><br/> June 25, 2009 02:44 AM Pacific Daylight Time http://www.fpgajournal.com/news_2009/06/20090625_04.htm Thu, 25 Jun 2009 22:04:00 GMT http://www.fpgajournal.com/news_2009/06/20090625_04.htm.1245957169203.1 Curtiss-Wright Controls Announces New Board Level Products Supporting Xilinx Virtex-6 FPGAs Source: Curtiss-Wright Controls June 25, 2009 <br/> Source: Curtiss-Wright Controls<br/> June 25, 2009 http://www.fpgajournal.com/news_2009/06/20090625_02.htm Thu, 25 Jun 2009 22:03:00 GMT http://www.fpgajournal.com/news_2009/06/20090625_02.htm.1245957169203.3 Achilles Test Systems Founders Present at DAC Conference Source: PRNewswire Jun 25, 2009 07:45 ET <br/> Source: PRNewswire <br/> Jun 25, 2009 07:45 ET http://www.fpgajournal.com/news_2009/06/20090625_03.htm Thu, 25 Jun 2009 22:03:00 GMT http://www.fpgajournal.com/news_2009/06/20090625_03.htm.1245957169203.2 Designers to Share Real-World Experiences at the 46th Design Automation Conference User Track BusinessWire June 25, 2009 06:00 AM Pacific Daylight Time <br/> <a href="http://www.businesswire.com" target="_blank">BusinessWire</a><br/> June 25, 2009 06:00 AM Pacific Daylight Time http://www.fpgajournal.com/news_2009/06/20090625_01.htm Thu, 25 Jun 2009 22:03:00 GMT http://www.fpgajournal.com/news_2009/06/20090625_01.htm.1245957169203.4 Verific Design Automation Tools Deliver Industry-Leading RTL Language Support for Xilinx ISE Design Suite BusinessWire June 24, 2009 08:00 AM Pacific Daylight Time <br/> <a href="http://www.businesswire.com" target="_blank">BusinessWire</a><br/> June 24, 2009 08:00 AM Pacific Daylight Time http://www.fpgajournal.com/news_2009/06/20090624_01.htm Wed, 24 Jun 2009 20:15:00 GMT http://www.fpgajournal.com/news_2009/06/20090624_01.htm.1245864967968.5 IAR Embedded Workbench drives up to 30% additional power savings for Atmel’s new picoPower AVR32 family Source: IAR Systems June 24, 2009 <br/> Source: IAR Systems<br/> June 24, 2009 http://www.fpgajournal.com/news_2009/06/20090624_02.htm Wed, 24 Jun 2009 20:15:00 GMT http://www.fpgajournal.com/news_2009/06/20090624_02.htm.1245864967968.4 Mentor Graphics Announces Logic and Physical Synthesis Support for Xilinx Virtex-6 and Spartan-6 FPGAs BusinessWire June 24, 2009 04:30 AM Pacific Daylight Time <br/> <a href="http://www.businesswire.com" target="_blank">BusinessWire</a><br/> June 24, 2009 04:30 AM Pacific Daylight Time http://www.fpgajournal.com/news_2009/06/20090624_03.htm Wed, 24 Jun 2009 20:15:00 GMT http://www.fpgajournal.com/news_2009/06/20090624_03.htm.1245864967968.3 Achronix selects Synopsys as its leading EDA partner Source: Synopsys June 24, 2009 <br/> Source: Synopsys<br/> June 24, 2009 http://www.fpgajournal.com/news_2009/06/20090624_04.htm Wed, 24 Jun 2009 20:15:00 GMT http://www.fpgajournal.com/news_2009/06/20090624_04.htm.1245864967968.2 Xilinx Accelerates Development of Next-Generation Systems with Industry’s First Deployment of Targeted Design Platforms Source: Xilinx June 25, 2009 <br/> Source: Xilinx<br/> June 25, 2009 http://www.fpgajournal.com/news_2009/06/20090624_05.htm Wed, 24 Jun 2009 20:15:00 GMT http://www.fpgajournal.com/news_2009/06/20090624_05.htm.1245864967968.1 Synopsys and TSMC Deliver Accurate Lithography Verification for 28nm Designs Source: Synopsys Jun 23, 2009 09:00 ET <br/> Source: Synopsys<br/> Jun 23, 2009 09:00 ET http://www.fpgajournal.com/news_2009/06/20090623_04.htm Tue, 23 Jun 2009 20:19:00 GMT http://www.fpgajournal.com/news_2009/06/20090623_04.htm.1245777663968.1 Cryptography Research Announces Integration of SASEBO-G into DPA Workstation™ BusinessWire June 23, 2009 05:00 AM Pacific Daylight Time <br/> <a href="http://www.businesswire.com" target="_blank">BusinessWire</a><br/> June 23, 2009 05:00 AM Pacific Daylight Time http://www.fpgajournal.com/news_2009/06/20090623_01.htm Tue, 23 Jun 2009 20:19:00 GMT http://www.fpgajournal.com/news_2009/06/20090623_01.htm.1245777663968.4