In applications engineering we are often asked, “Why is my simple FPGA design not routing?” or “Why does my CPLD design have such a large timing score?” Sometimes we’ll also hear “PAR is taking forever, and then it fails!” In many cases, the solution is embarrassingly simple: “Create a timing constraint!”

For those familiar with designing using ispLEVER tools, making the upgrade to Diamond is easy; in fact,  you will find a number of the backend engines like MAP, PAR, and TRACE are based on those found in ispLEVER 8.1. The modern GUI features direct task navigation, centralized reports and summary, extensive cross-probing, and integrated NCD Editor and Programmer. The Diamond tool continues to bundle the popular third party tools Synopsys Synplify Pro and Aldec ActiveHDL.

Some of the new advanced features found in Diamond include Implementations and Strategies, integrated HDL checking, Run Manager, expanded TCL support, and expanded OS support. One of my favorite new features is the new Timing Analysis tool, which is much easier and faster to use. The new Timing Analysis view offers an easy to use graphical environment for navigating timing information. Click on a constraint and see the timing paths, detailed paths, and path Floorplan/Physical views instantly. Easy visual cues, such as coloring constraints that fail in red, provide instant feedback on your design. A key new benefit in Timing Analysis view is rapidly updated analysis when timing constraints are changed. You no longer have to re-implement your design to re-run a TRACE report. Instead, change a timing constraint, click update in Timing Analysis and your analysis report is run directly.

Videos of the new Timing Analysis in action can be found at:
http://www.latticesemi.com/products/designsoftware/diamond/videos/index.cfm

One of the most common questions that programmable logic designers face today is how to connect unique, disparate modules in their system.  That is to say, “Block A needs to talk to block B and vice versa. What bus should I choose?”  There are a plethora of choices that the designer can choose from, but what most designers really need is a proven, simple-to-connect bus interface without the overhead of many proprietary bus interfaces.  Enter WISHBONE.

In case you’ve not heard of WISHBONE, it’s a popular, open source hardware interface that is promoted by the OpenCores project (http://www.opencores.org).  Being open source offers several advantages for programmable logic designs:

Open source designs:  The OpenCores project is the web’s main proponent of the WISHBONE architecture.  In addition to its role as WISHBONE advocacy, the OpenCores website offers many grass-roots built RTL modules that are available for users in both Verilog and VHDL, many of which are of course, WISHBONE ready.  This means that a designer can attach their own WISHBONE design to one or several of these OpenCores designs, saving development time on both core functionality and bus connectivity.

Flexibility: Perhaps the most subtle advantage of WISHBONE is its flexibility.  Unlike most bus system, WISHBONE can be implemented as any one major bus types including hierarchical, point-to-point, or many-to-many.  In addition, a WISHBONE bus can be multi-master or single master and can be 8, 16, 32, or 64 bits wide.  The net effect of this flexibility is that WISHBONE is appropriate for programmable logic designs of almost any complexity.

Proven:  The WISHBONE interface is a well-defined standard, has been around for more than six years and has been implemented in hundreds, if not thousands of systems.  If you want a flexible, but low-risk bus architecture, WISHBONE fits the bill.

The Price: As stated on the Opencores website: “The WISHBONE standard is not copyrighted, and is in the public domain. It may be freely copied and distributed by any means. Furthermore, it may be used for the design and production of integrated circuit components without royalties or other financial obligations.”

Lattice and WISHBONE:

Lattice believes in the WISHBONE credo and has several resources for Lattice users:

LatticeMico32:  This is Lattice’s own 32-bit “soft” microprocessor.  It has a native WISHBONE interface and is free with an open IP core licensing agreement.  The power of the LatticeMico32 lies not only in the flexibility of the core itself (it’s synthesizable), but also that it can be connected to any WISHBONE peripherals including open source cores or your own, custom logic.

Reference Designs: Lattice offers several freely downloadable WISHBONE reference designs as a starting point for user designs.  These reference designs come complete with documentation, RTL, and testbenches.  WISHBONE modules include an I2C bus master, a SPI controller, and a LatticeMico8 WISHBONE adapter.  Again, since they are WISHBONE, these reference designs can be combined with OpenCores designs or a LatticeMico32.

System Examples:  Our successful MachXO Mini Evaluation Board comes with a native demo (“Mini SoC Demo”) that illustrates the WISHBONE bus in a working system. This demo includes our 8 bit LatticeMico8 soft processor, a UART, an I2C master, and a SPI memory controller, all connected on a WISHBONE bus.  A Lattice user can examine the WISHBONE bus connectivity by downloading the RTL and documentation for this demo at our MachXO Mini Development Kit website. At this website, find the “Demo Applications” button under “MachXO Mini Development Kit Resources” at the bottom of the page.  You can also view a video of the demo or experiment with it yourself by purchasing the board from the MachXO Mini Development Kit website.

Rather than taking a traditional approach to assessing the tradeoffs, I’d suggest that we need to carefully consider the two most critical definitions:  What does “integration” mean and what does “risk” mean?

In board development discussions, integration usually means reducing the number of components on your board by bringing as much function as possible into as few components as possible.   Likewise, risk is commonly associated with the complexity of the board that you are bringing to market.

I propose that the most accurate definitions of risk and integration imply both a physical aspect and a process aspect.  That is to say, risk can be quantified not only from the physical complexity of a board, but also with the complexity of the process that brings the board to market.  In the same way, integration can mean not only a reduced BOM (bill of materials) but also a simplified development process.

Whether risk and integration complement each other or not depends on how they are combined.  Higher levels of power management integration can bring more risk if the new solution is unproven.  On the other hand, higher levels of integration can actually reduce risk if new parts actually simplify the processes that are required to bring the board to market. The right balance is achieved when we can find new power management solutions that not only increases integration, but also reduce the risk.

The mission of the ProcessorPM POWR605 is to do just this.  That is, to reduce complexity and risk not only in terms of the physical board itself, but also in the process that brings it to market.   The ProcessorPM reduces the physical complexity of a processor power solution by bringing voltage monitoring, processor reset and watchdog timer functionality all under one roof.  Higher integration and a reduced BOM translate into lower risk.

The ProcessorPM comes with a tested and pre-programmed, factory configuration. The factory configuration integrates voltage monitoring for 5V, 3.3V, 2.5V and 1.8V supply monitoring with a CPU reset and watchdog timer interrupt output generation.  Although the user can change the programming, there is no need to do so if the default functionality suits their needs.  All they need to do is include ProcessorPM into their schematics and select the appropriate strap values to set watchdog delays and reset pulse stretching.   This simplifies the development flow and reduces risk by eliminating the need to develop and test a new configuration.

Integration and risk will continue to be factors in the ever advancing pace of microprocessor based systems.  The savvy engineer will continue to look for ways to optimize both for their system power management.