VLSI DESIGN

2013-06-07T04:17:00.002-07:00

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2011-10-12T02:17:00.005-07:00

Verilog Code For 8:3 Priority Encoder using "casex" | Verilog Example Codes

Priority encoder is a special type of encoder in which multiple bits at the input can be asserted. The response at the output is however defined by the priority rule, defined previously. Priority encoders have vast application in different client-server systems. In client-server systems decision is made to grant a service based on the priority of any specific client.

Here is a verilog code for an 8:3 priority encoder. It grants the highest priority to the "most left sided bit in the input word". For example in data word "00010101" the highest priority is carried by the most left sided one, appearing at the fourth (counting from left side). So all the other bits that come next to it will be discarded or in other words will not be taken into account. Verilog implementation has been done using "casex" statement.

module priority_encoder (code, valid_data, data);
output [2:0] code;
output       valid data;
input [7:0] data;
reg    [2:0] code;

assign valid_data= |data; // Use of "reduction or" operator
always @ (data)
begin
casex (data)
8'b1xxxxxxx : code=7;
8'b01xxxxxx : code=6;
8'b001xxxxx : code=5
8'b0001xxxx : code=4;
8'b00001xxx : code=3;
8'b000001xx : code=2;
8'b0000001x : code=1;
8'b00000001 : code=0;
dafault     : code=3'bx;

endcase
endmodule

Clock Gating

2011-08-30T22:40:00.000-07:00

Clock tree consume more than 50 % of dynamic power. The components of this power are:

1) Power consumed by combinatorial logic whose values are changing on each clock edge
2) Power consumed by flip-flops and
3) The power consumed by the clock buffer tree in the design.

It is good design idea to turn off the clock when it is not needed. Automatic clock gating is supported by modern EDA tools. They identify the circuits where clock gating can be inserted.

RTL clock gating works by identifying groups of flip-flops which share a common enable control signal. Traditional methodologies use this enable term to control the select on a multiplexer connected to the D port of the flip-flop or to control the clock enable pin on a flip-flop with clock enable capabilities. RTL clock gating uses this enable signal to control a clock gating circuit which is connected to the clock ports of all of the flip-flops with the common enable term. Therefore, if a bank of flip-flops which share a common enable term have RTL clock gating implemented, the flip-flops will consume zero dynamic power as long as this enable signal is false.

There are two types of clock gating styles available. They are:

1) Latch-based clock gating
2) Latch-free clock gating.

Latch free clock gating

The latch-free clock gating style uses a simple AND or OR gate (depending on the edge on which flip-flops are triggered). Here if enable signal goes inactive in between the clock pulse or if it multiple times then gated clock output either can terminate prematurely or generate multiple clock pulses. This restriction makes the latch-free clock gating style inappropriate for our single-clock flip-flop based design.

Latch free clock gating

Latch based clock gating

The latch-based clock gating style adds a level-sensitive latch to the design to hold the enable signal from the active edge of the clock until the inactive edge of the clock. Since the latch captures the state of the enable signal and holds it until the complete clock pulse has been generated, the enable signal need only be stable around the rising edge of the clock, just as in the traditional ungated design style.

Latch based clock gating

Specific clock gating cells are required in library to be utilized by the synthesis tools. Availability of clock gating cells and automatic insertion by the EDA tools makes it simpler method of low power technique. Advantage of this method is that clock gating does not require modifications to RTL description.

Backend (Physical Design) Interview Questions and Answers

2011-08-30T22:35:00.001-07:00

Below are the sequence of questions asked for a physical design engineer.

In which field are you interested?

Answer to this question depends on your interest, expertise and to the requirement for which you have been interviewed.

Well..the candidate gave answer: Low power design

Can you talk about low power techniques?
How low power and latest 90nm/65nm technologies are related?

Refer here and browse for different low power techniques.

Do you know about input vector controlled method of leakage reduction?

Leakage current of a gate is dependant on its inputs also. Hence find the set of inputs which gives least leakage. By applyig this minimum leakage vector to a circuit it is possible to decrease the leakage current of the circuit when it is in the standby mode. This method is known as input vector controlled method of leakage reduction.

How can you reduce dynamic power?

-Reduce switching activity by designing good RTL
-Clock gating
-Architectural improvements
-Reduce supply voltage
-Use multiple voltage domains-Multi vdd

What are the vectors of dynamic power?

Voltage and Current

How will you do power planning?

Refer here for power planning.

If you have both IR drop and congestion how will you fix it?

-Spread macros
-Spread standard cells
-Increase strap width
-Increase number of straps
-Use proper blockage

Is increasing power line width and providing more number of straps are the only solution to IR drop?

-Spread macros
-Spread standard cells
-Use proper blockage

In a reg to reg path if you have setup problem where will you insert buffer-near to launching flop or capture flop? Why?

(buffers are inserted for fixing fanout voilations and hence they reduce setup voilation; otherwise we try to fix setup voilation with the sizing of cells; now just assume that you must insert buffer !)

Near to capture path.

Because there may be other paths passing through or originating from the flop nearer to lauch flop. Hence buffer insertion may affect other paths also. It may improve all those paths or degarde. If all those paths have voilation then you may insert buffer nearer to launch flop provided it improves slack.

How will you decide best floorplan?

Refer here for floor planning.

What is the most challenging task you handled?
What is the most challenging job in P&R flow?

-It may be power planning- because you found more IR drop
-It may be low power target-because you had more dynamic and leakage power
-It may be macro placement-because it had more connection with standard cells or macros
-It may be CTS-because you needed to handle multiple clocks and clock domain crossings
-It may be timing-because sizing cells in ECO flow is not meeting timing
-It may be library preparation-because you found some inconsistancy in libraries.
-It may be DRC-because you faced thousands of voilations

How will you synthesize clock tree?

-Single clock-normal synthesis and optimization
-Multiple clocks-Synthesis each clock seperately
-Multiple clocks with domain crossing-Synthesis each clock seperately and balance the skew

How many clocks were there in this project?

-It is specific to your project
-More the clocks more challenging !

How did you handle all those clocks?

-Multiple clocks-->synthesize seperately-->balance the skew-->optimize the clock tree

Are they come from seperate external resources or PLL?

-If it is from seperate clock sources (i.e.asynchronous; from different pads or pins) then balancing skew between these clock sources becomes challenging.

-If it is from PLL (i.e.synchronous) then skew balancing is comparatively easy.

Why buffers are used in clock tree?

To balance skew (i.e. flop to flop delay)

What is cross talk?

Switching of the signal in one net can interfere neigbouring net due to cross coupling capacitance.This affect is known as cros talk. Cross talk may lead setup or hold voilation.

How can you avoid cross talk?

-Double spacing=>more spacing=>less capacitance=>less cross talk
-Multiple vias=>less resistance=>less RC delay
-Shielding=> constant cross coupling capacitance =>known value of crosstalk
-Buffer insertion=>boost the victim strength

How shielding avoids crosstalk problem? What exactly happens there?

-High frequency noise (or glitch)is coupled to VSS (or VDD) since shilded layers are connected to either VDD or VSS.

Coupling capacitance remains constant with VDD or VSS.

How spacing helps in reducing crosstalk noise?

width is more=>more spacing between two conductors=>cross coupling capacitance is less=>less cross talk

Why double spacing and multiple vias are used related to clock?

Why clock?-- because it is the one signal which chages it state regularly and more compared to any other signal. If any other signal switches fast then also we can use double space.

Double spacing=>width is more=>capacitance is less=>less cross talk

Multiple vias=>resistance in parellel=>less resistance=>less RC delay

How buffer can be used in victim to avoid crosstalk?

Buffer increase victims signal strength; buffers break the net length=>victims are more tolerant to coupled signal from aggressor.

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16 February 2008

Physical Design Questions and Answers

I am getting several emails requesting answers to the questions posted in this blog. But it is very difficult to provide detailed answer to all questions in my available spare time. Hence i decided to give "short and sweet" one line answers to the questions so that readers can immediately benefited. Detailed answers will be posted in later stage.I have given answers to some of the physical design questions here. Enjoy !

What parameters (or aspects) differentiate Chip Design and Block level design?

Chip design has I/O pads; block design has pins.

Chip design uses all metal layes available; block design may not use all metal layers.

Chip is generally rectangular in shape; blocks can be rectangular, rectilinear.

Chip design requires several packaging; block design ends in a macro.

How do you place macros in a full chip design?

First check flylines i.e. check net connections from macro to macro and macro to standard cells.

If there is more connection from macro to macro place those macros nearer to each other preferably nearer to core boundaries.

If input pin is connected to macro better to place nearer to that pin or pad.

If macro has more connection to standard cells spread the macros inside core.

Avoid criscross placement of macros.

Use soft or hard blockages to guide placement engine.

Differentiate between a Hierarchical Design and flat design?

Hierarchial design has blocks, subblocks in an hierarchy; Flattened design has no subblocks and it has only leaf cells.

Hierarchical design takes more run time; Flattened design takes less run time.

Which is more complicated when u have a 48 MHz and 500 MHz clock design?

500 MHz; because it is more constrained (i.e.lesser clock period) than 48 MHz design.

Name few tools which you used for physical verification?

Herculis from Synopsys, Caliber from Mentor Graphics.

What are the input files will you give for primetime correlation?

Netlist, Technology library, Constraints, SPEF or SDF file.

If the routing congestion exists between two macros, then what will you do?

Provide soft or hard blockage

How will you decide the die size?

By checking the total area of the design you can decide die size.

If lengthy metal layer is connected to diffusion and poly, then which one will affect by antenna problem?

Poly

If the full chip design is routed by 7 layer metal, why macros are designed using 5LM instead of using 7LM?

Because top two metal layers are required for global routing in chip design. If top metal layers are also used in block level it will create routing blockage.

In your project what is die size, number of metal layers, technology, foundry, number of clocks?

Die size: tell in mm eg. 1mm x 1mm ; remeber 1mm=1000micron which is a big size !!

Metal layers: See your tech file. generally for 90nm it is 7 to 9.

Technology: Again look into tech files.

Foundry:Again look into tech files; eg. TSMC, IBM, ARTISAN etc

Clocks: Look into your design and SDC file !

How many macros in your design?

You know it well as you have designed it ! A SoC (System On Chip) design may have 100 macros also !!!!

What is each macro size and number of standard cell count?

Depends on your design.

What are the input needs for your design?

For synthesis: RTL, Technology library, Standard cell library, Constraints

For Physical design: Netlist, Technology library, Constraints, Standard cell library

What is SDC constraint file contains?

Clock definitions

Timing exception-multicycle path, false path

Input and Output delays

How did you do power planning? How to calculate core ring width, macro ring width and strap or trunk width? How to find number of power pad and IO power pads? How the width of metal and number of straps calculated for power and ground?

Get the total core power consumption; get the metal layer current density value from the tech file; Divide total power by number sides of the chip; Divide the obtained value from the current density to get core power ring width. Then calculate number of straps using some more equations. Will be explained in detail later.

How to find total chip power?

Total chip power=standard cell power consumption,Macro power consumption pad power consumption.

What are the problems faced related to timing?

Prelayout: Setup, Max transition, max capacitance

Post layout: Hold

How did you resolve the setup and hold problem?

Setup: upsize the cells

Hold: insert buffers

In which layer do you prefer for clock routing and why?

Next lower layer to the top two metal layers(global routing layers). Because it has less resistance hence less RC delay.

If in your design has reset pin, then it’ll affect input pin or output pin or both?

Output pin.

During power analysis, if you are facing IR drop problem, then how did you avoid?

Increase power metal layer width.

Go for higher metal layer.

Spread macros or standard cells.

Provide more straps.

Define antenna problem and how did you resolve these problem?

Increased net length can accumulate more charges while manufacturing of the device due to ionisation process. If this net is connected to gate of the MOSFET it can damage dielectric property of the gate and gate may conduct causing damage to the MOSFET. This is antenna problem.

Decrease the length of the net by providing more vias and layer jumping.

Insert antenna diode.

How delays vary with different PVT conditions? Show the graph.

P increase->dealy increase

P decrease->delay decrease

V increase->delay decrease

V decrease->delay increase

T increase->delay increase

T decrease->delay decrease

Explain the flow of physical design and inputs and outputs for each step in flow.

Click here to see the flow diagram

What is cell delay and net delay?

Gate delay

Transistors within a gate take a finite time to switch. This means that a change on the input of a gate takes a finite time to cause a change on the output.[Magma]

Gate delay =function of(i/p transition time, Cnet+Cpin).

Cell delay is also same as Gate delay.

Cell delay

For any gate it is measured between 50% of input transition to the corresponding 50% of output transition.

Intrinsic delay

Intrinsic delay is the delay internal to the gate. Input pin of the cell to output pin of the cell.

It is defined as the delay between an input and output pair of a cell, when a near zero slew is applied to the input pin and the output does not see any load condition.It is predominantly caused by the internal capacitance associated with its transistor.

This delay is largely independent of the size of the transistors forming the gate because increasing size of transistors increase internal capacitors.

Net Delay (or wire delay)

The difference between the time a signal is first applied to the net and the time it reaches other devices connected to that net.

It is due to the finite resistance and capacitance of the net.It is also known as wire delay.

Wire delay =fn(Rnet , Cnet+Cpin)

What are delay models and what is the difference between them?

Linear Delay Model (LDM)

Non Linear Delay Model (NLDM)

What is wire load model?

Wire load model is NLDM which has estimated R and C of the net.

Why higher metal layers are preferred for Vdd and Vss?

Because it has less resistance and hence leads to less IR drop.

What is logic optimization and give some methods of logic optimization.

Upsizing

Downsizing

Buffer insertion

Buffer relocation

Dummy buffer placement

What is the significance of negative slack?

negative slack==> there is setup voilation==> deisgn can fail

What is signal integrity? How it affects Timing?

IR drop, Electro Migration (EM), Crosstalk, Ground bounce are signal integrity issues.

If Idrop is more==>delay increases.

crosstalk==>there can be setup as well as hold voilation.

What is IR drop? How to avoid? How it affects timing?

There is a resistance associated with each metal layer. This resistance consumes power causing voltage drop i.e.IR drop.

If IR drop is more==>delay increases.

What is EM and it effects?

Due to high current flow in the metal atoms of the metal can displaced from its origial place. When it happens in larger amount the metal can open or bulging of metal layer can happen. This effect is known as Electro Migration.

Affects: Either short or open of the signal line or power line.

What are types of routing?

Global Routing

Track Assignment

Detail Routing

What is latency? Give the types?

Source Latency

It is known as source latency also. It is defined as "the delay from the clock origin point to the clock definition point in the design".

Delay from clock source to beginning of clock tree (i.e. clock definition point).

The time a clock signal takes to propagate from its ideal waveform origin point to the clock definition point in the design.

Network latency

It is also known as Insertion delay or Network latency. It is defined as "the delay from the clock definition point to the clock pin of the register".

The time clock signal (rise or fall) takes to propagate from the clock definition point to a register clock pin.

What is track assignment?

Second stage of the routing wherein particular metal tracks (or layers) are assigned to the signal nets.

What is congestion?

If the number of routing tracks available for routing is less than the required tracks then it is known as congestion.

Whether congestion is related to placement or routing?

Routing

What are clock trees?

Distribution of clock from the clock source to the sync pin of the registers.

What are clock tree types?

H tree, Balanced tree, X tree, Clustering tree, Fish bone

What is cloning and buffering?

Cloning is a method of optimization that decreases the load of a heavily loaded cell by replicating the cell.

Buffering is a method of optimization that is used to insert beffers in high fanout nets to decrease the dealy.

Companywise ASIC/VLSI Interview Questions

2011-08-30T22:34:00.001-07:00

Below interview questions are contributed by ASIC_diehard (Thanks a lot !). Below questions are asked for senior position in Physical Design domain. The questions are also related to Static Timing Analysis and Synthesis. Answers to some questions are given as link. Remaining questions will be answered in coming blogs.

Common introductory questions every interviewer asks are:

Discuss about the projects worked in the previous company.
What are physical design flows, various activities you are involved?
Design complexity, capacity, frequency, process technologies, block size you handled.

Intel

Why power stripes routed in the top metal layers?

The resistivity of top metal layers are less and hence less IR drop is seen in power distribution network. If power stripes are routed in lower metal layers this will use good amount of lower routing resources and therefore it can create routing congestion.

Why do you use alternate routing approach HVH/VHV (Horizontal-Vertical-Horizontal/ Vertical-Horizontal-Vertical)?

Answer:

This approach allows routability of the design and better usage of routing resources.

What are several factors to improve propagation delay of standard cell?

Answer:

Improve the input transition to the cell under consideration by up sizing the driver.

Reduce the load seen by the cell under consideration, either by placement refinement or buffering.

If allowed increase the drive strength or replace with LVT (low threshold voltage) cell.

How do you compute net delay (interconnect delay) / decode RC values present in tech file?
What are various ways of timing optimization in synthesis tools?

Answer:

Logic optimization: buffer sizing, cell sizing, level adjustment, dummy buffering etc.

Less number of logics between Flip Flops speedup the design.

Optimize drive strength of the cell , so it is capable of driving more load and hence reducing the cell delay.

Better selection of design ware component (select timing optimized design ware components).

Use LVT (Low threshold voltage) and SVT (standard threshold voltage) cells if allowed.

What would you do in order to not use certain cells from the library?

Answer:

Set don’t use attribute on those library cells.

How delays are characterized using WLM (Wire Load Model)?

Answer:

For a given wireload model the delay are estimated based on the number of fanout of the cell driving the net.

Fanout vs net length is tabulated in WLMs.

Values of unit resistance R and unit capacitance C are given in technology file.

Net length varies based on the fanout number.

Once the net length is known delay can be calculated; Sometimes it is again tabulated.

What are various techniques to resolve congestion/noise?

Answer:

Routing and placement congestion all depend upon the connectivity in the netlist , a better floor plan can reduce the congestion.

Noise can be reduced by optimizing the overlap of nets in the design.

Let’s say there enough routing resources available, timing is fine, can you increase clock buffers in clock network? If so will there be any impact on other parameters?

Answer:

No. You should not increase clock buffers in the clock network. Increase in clock buffers cause more area , more power. When everything is fine why you want to touch clock tree??

How do you optimize skew/insertion delays in CTS (Clock Tree Synthesis)?

Answer:

Better skew targets and insertion delay values provided while building the clocks.

Choose appropriate tree structure – either based on clock buffers or clock inverters or mix of clock buffers or clock inverters.

For multi clock domain, group the clocks while building the clock tree so that skew is balanced across the clocks. (Inter clock skew analysis).

What are pros/cons of latch/FF (Flip Flop)?

Answer: Pros and cons of latch and flip flop

How you go about fixing timing violations for latch- latch paths?
As an engineer, let’s say your manager comes to you and asks for next project die size estimation/projection, giving data on RTL size, performance requirements. How do you go about the figuring out and come up with die size considering physical aspects?
How will you design inserting voltage island scheme between macro pins crossing core and are at different power wells? What is the optimal resource solution?
What are various formal verification issues you faced and how did you resolve?
How do you calculate maximum frequency given setup, hold, clock and clock skew?
What are effects of metastability?

Answer: Metastability

Consider a timing path crossing from fast clock domain to slow clock domain. How do you design synchronizer circuit without knowing the source clock frequency?
How to solve cross clock timing path?
How to determine the depth of FIFO/ size of the FIFO?

Answer: FIFO Depth

STmicroelectronics

What are the challenges you faced in place and route, FV (Formal Verification), ECO (Engineering Change Order) areas?
How long the design cycle for your designs?
What part are your areas of interest in physical design?
Explain ECO (Engineering Change Order) methodology.
Explain CTS (Clock Tree Synthesis) flow.

Answer: Clock Tree Synthesis

What kind of routing issues you faced?
How does STA (Static Timing Analysis) in OCV (On Chip Variation) conditions done? How do you set OCV (On Chip Variation) in IC compiler? How is timing correlation done before and after place and route?

Answer: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis (STA)

If there are too many pins of the logic cells in one place within core, what kind of issues would you face and how will you resolve?
Define hash/ @array in perl.
Using TCL (Tool Command Language, Tickle) how do you set variables?
What is ICC (IC Compiler) command for setting derate factor/ command to perform physical synthesis?
What are nanoroute options for search and repair?
What were your design skew/insertion delay targets?
How is IR drop analysis done? What are various statistics available in reports?
Explain pin density/ cell density issues, hotspots?
How will you relate routing grid with manufacturing grid and judge if the routing grid is set correctly?
What is the command for setting multi cycle path?
If hold violation exists in design, is it OK to sign off design? If not, why?

Texas Instruments (TI)

How are timing constraints developed?
Explain timing closure flow/methodology/issues/fixes.
Explain SDF (Standard Delay Format) back annotation/ SPEF (Standard Parasitic Exchange Format) timing correlation flow.
Given a timing path in multi-mode multi-corner, how is STA (Static Timing Analysis) performed in order to meet timing in both modes and corners, how are PVT (Process-Voltage-Temperature)/derate factors decided and set in the Primetime flow?
With respect to clock gate, what are various issues you faced at various stages in the physical design flow?
What are synthesis strategies to optimize timing?
Explain ECO (Engineering Change Order) implementation flow. Given post routed database and functional fixes, how will you take it to implement ECO (Engineering Change Order) and what physical and functional checks you need to perform?

Qualcomm

In building the timing constraints, do you need to constrain all IO (Input-Output) ports?
Can a single port have multi-clocked? How do you set delays for such ports?
How is scan DEF (Design Exchange Format) generated?
What is purpose of lockup latch in scan chain?
Explain short circuit current.

Answer: Short Circuit Power

What are pros/cons of using low Vt, high Vt cells?

Answer:

Multi Threshold Voltage Technique

Issues With Multi Height Cell Placement in Multi Vt Flow

How do you set inter clock uncertainty?

Answer:

set_clock_uncertainty –from clock1 -to clock2

In DC (Design Compiler), how do you constrain clocks, IO (Input-Output) ports, maxcap, max tran?
What are differences in clock constraints from pre CTS (Clock Tree Synthesis) to post CTS (Clock Tree Synthesis)?

Answer:

Difference in clock uncertainty values; Clocks are propagated in post CTS.

In post CTS clock latency constraint is modified to model clock jitter.

How is clock gating done?

Answer: Clock Gating

What constraints you add in CTS (Clock Tree Synthesis) for clock gates?

Answer:

Make the clock gating cells as through pins.

What is trade off between dynamic power (current) and leakage power (current)?

Answer:

Leakage Power Trends

Dynamic Power

How do you reduce standby (leakage) power?

Answer: Low Power Design Techniques

Explain top level pin placement flow? What are parameters to decide?
Given block level netlists, timing constraints, libraries, macro LEFs (Layout Exchange Format/Library Exchange Format), how will you start floor planning?
With net length of 1000um how will you compute RC values, using equations/tech file info?
What do noise reports represent?
What does glitch reports contain?
What are CTS (Clock Tree Synthesis) steps in IC compiler?
What do clock constraints file contain?
How to analyze clock tree reports?
What do IR drop Voltagestorm reports represent?
Where /when do you use DCAP (Decoupling Capacitor) cells?
What are various power reduction techniques?

Answer: Low Power Design Techniques

Hughes Networks

What is setup/hold? What are setup and hold time impacts on timing? How will you fix setup and hold violations?
Explain function of Muxed FF (Multiplexed Flip Flop) /scan FF (Scal Flip Flop).
What are tested in DFT (Design for Testability)?
In equivalence checking, how do you handle scanen signal?
In terms of CMOS (Complimentary Metal Oxide Semiconductor), explain physical parameters that affect the propagation delay?
What are power dissipation components? How do you reduce them?

Answer:

Short Circuit Power

Leakage Power Trends

Dynamic Power
Low Power Design Techniques

How delay affected by PVT (Process-Voltage-Temperature)?

Answer: Process-Voltage-Temperature (PVT) Variations and Static Timing Analysis (STA)

Why is power signal routed in top metal layers?

Avago Technologies (former HP group)

How do you minimize clock skew/ balance clock tree?
Given 11 minterms and asked to derive the logic function.
Given C1= 10pf, C2=1pf connected in series with a switch in between, at t=0 switch is open and one end having 5v and other end zero voltage; compute the voltage across C2 when the switch is closed?
Explain the modes of operation of CMOS (Complimentary Metal Oxide Semiconductor) inverter? Show IO (Input-Output) characteristics curve.
Implement a ring oscillator.
How to slow down ring oscillator?

Hynix Semiconductor

How do you optimize power at various stages in the physical design flow?
What timing optimization strategies you employ in pre-layout /post-layout stages?
What are process technology challenges in physical design?
Design divide by 2, divide by 3, and divide by 1.5 counters. Draw timing diagrams.
What are multi-cycle paths, false paths? How to resolve multi-cycle and false paths?
Given a flop to flop path with combo delay in between and output of the second flop fed back to combo logic. Which path is fastest path to have hold violation and how will you resolve?
What are RTL (Register Transfer Level) coding styles to adapt to yield optimal backend design?
Draw timing diagrams to represent the propagation delay, set up, hold, recovery, removal, minimum pulse width.

About Contributor

ASIC_diehard has more than 5 years of experience in physical design, timing, netlist to GDS flows of Integrated Circuit development. ASIC_diehard's fields of interest are backend design, place and route, timing closure, process technologies.

Readers are encouraged to discuss answers to these questions. Just click on the 'post a comment' option below and put your comments there. Alternatively you can send your answers/discussions to my mail id: shavakmm@gmail.com

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17 April 2008

Issues with Multi Height Cell Placement in Multi Vt Flow

Creating the reference libraries

There are two reference libraries required. One is low Vt cell library and another is high Vt cell library. These libraries have two different height cells. Reference libraries are created as per the standard synopsys flow. Library creation flow is given in Figure 1. Read_lib command is used for this purpose. As TF and LEF files are available TF+LEF option is chosen for library creation. After the completion of the physical library preparation steps, logical libraries are prepared.

Figure 1 Library preparation command window

Different Unit Tile Creation

The unit tile height of lvt cells is 2.52 µ and hvt cells are 1.96 µ. Hence two separate unit tiles have to be created and should be added in the technology file. Hvt reference library is created with the unit tile name “unit” and lvt reference library is created with unit tile name “lvt_unit”. By default “unit” tile is defined in technology file and the other unit tile “lvt_unit” is also added to the technology file.

Figure 2. Tile height specifications in library preparation

Floor Planning

70% of the core utilization is provided. Aspect ratio is kept at 1. Rows are flipped, double backed and made channel less. No Top Design Format (TDF) file is selected as default placement of the IO pins are considered. Since we have multi height cells in the reference library separate placement rows have to be provided for two different unit tiles. The core area is divided into two separate unit tile section providing larger area for Hvt unit tile as shown in the Figure 3.

Figure 3. Different unit tile placement

First as per the default floor planning flow rows are constructed with unit tile. Later rows are deleted from the part of the core area and new rows are inserted with the tile “lvt_unit”. Improper allotment of area can give rise to congestion. Some iteration of trial and error experiments were conducted to find best suitable area for two different unit tiles. The “unit” tile covers 44.36% of core area while “lvt_unit” 65.53% of the core area. PR summary report of the design after the floor planning stage is provided below.

PR Summary:

Number of Module Cells: 70449

Number of Pins: 368936

Number of IO Pins: 298

Number of Nets: 70858

Average Pins Per Net (Signal): 3.20281

Chip Utilization:

Total Standard Cell Area: 559367.77

Core Size: width 949.76, height 947.80; area 900182.53

Chip Size: width 999.76, height 998.64; area 998400.33

Cell/Core Ratio: 62.1394%

Cell/Chip Ratio: 56.0264%

Number of Cell Rows: 392

Placement Issues with Different Tile Rows

Legal placement of the standard cells is automatically taken care by Astro tool as two separate placement area is defined for multi heighten cells. Corresponding tile utilization summary is provided below.

PR Summary:

[Tile Utilization]

============================================================

unit 257792 114353 44.36%

lvt_unit 1071872 702425 65.53%

============================================================

But this method of placement generates unacceptable congestion around the junction area of two separate unit tile sections. The congestion map is shown in Figure 4.

Figure 4. Congestion

There are two congestion maps. One is related to the floor planning with aspect ratio 1 and core utilization of 70%. This shows horizontal congestion over the limited value of one all over the core area meaning that design can’t be routed at all. Hence core area has to be increased by specifying height and width. The other congestion map is generated with the floor plan wherein core area is set to 950 µm. Here we can observe although congestion has reduced over the core area it is still a concern over the area wherein two different unit tiles merge as marked by the circle. But design can be routable and can be carried to next stages of place and route flow provided timing is met in subsequent implementation steps.

Tighter timing constraints and more interrelated connections of standard cells around the junction area of different unit tiles have lead to more congestion. It is observed that increasing the area isn't a solution to congestion. In addition to congestion, situation verses with the timing optimization effort by the tool. Timing target is not able to meet. Optimization process inserts several buffers around the junction area and some of them are placed illegally due to the lack of placement area.

Corresponding timing summary is provided below:

Timing/Optimization Information:

[TIMING]

Setup Hold Num Num

Type Slack Num Total Target Slack Num Trans MaxCap Time

========================================================

A.PRE -3.491 3293 -3353.9 0.100 10000.000 0 8461 426 00:02:26

A.IPO -0.487 928 -271.5 0.100 10000.000 0 1301 29 00:01:02

A.IPO -0.454 1383 -312.8 0.100 10000.000 0 1765 36 00:01:57

A.PPO -1.405 1607 -590.9 0.100 10000.000 0 2325 32 00:00:58

A.SETUP -1.405 1517 -466.4 0.100 -0.168 6550 2221 31 00:04:10

========================================================

Since the timing is not possible to meet design has to be abandoned from subsequent steps. Hence in a multi vt design flow cell library with multi heights are not preferred.

References

[1] Astro, User Guide, Version X-2005.09, September 2005

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08 April 2008

Physical Design Objective Type of Questions and Answers

1) Chip utilization depends on ___.

a. Only on standard cells
b. Standard cells and macros
c. Only on macros
d. Standard cells macros and IO pads

2) In Soft blockages ____ cells are placed.

a. Only sequential cells
b. No cells
c. Only Buffers and Inverters
d. Any cells

3) Why we have to remove scan chains before placement?

a. Because scan chains are group of flip flop
b. It does not have timing critical path
c. It is series of flip flop connected in FIFO
d. None

4) Delay between shortest path and longest path in the clock is called ____.

a. Useful skew
b. Local skew
c. Global skew
d. Slack

5) Cross talk can be avoided by ___.

a. Decreasing the spacing between the metal layers
b. Shielding the nets
c. Using lower metal layers
d. Using long nets

6) Prerouting means routing of _____.

a. Clock nets
b. Signal nets
c. IO nets
d. PG nets

7) Which of the following metal layer has Maximum resistance?

a. Metal1
b. Metal2
c. Metal3
d. Metal4

8) What is the goal of CTS?

a. Minimum IR Drop
b. Minimum EM
c. Minimum Skew
d. Minimum Slack

9) Usually Hold is fixed ___.

a. Before Placement
b. After Placement
c. Before CTS
d. After CTS

10) To achieve better timing ____ cells are placed in the critical path.

a. HVT
b. LVT
c. RVT
d. SVT

11) Leakage power is inversely proportional to ___.

a. Frequency
b. Load Capacitance
c. Supply voltage
d. Threshold Voltage

12) Filler cells are added ___.

a. Before Placement of std cells
b. After Placement of Std Cells
c. Before Floor planning
d. Before Detail Routing

13) Search and Repair is used for ___.

a. Reducing IR Drop
b. Reducing DRC
c. Reducing EM violations
d. None

14) Maximum current density of a metal is available in ___.

a. .lib
b. .v
c. .tf
d. .sdc

15) More IR drop is due to ___.

a. Increase in metal width
b. Increase in metal length
c. Decrease in metal length
d. Lot of metal layers

16) The minimum height and width a cell can occupy in the design is called as ___.

a. Unit Tile cell
b. Multi heighten cell
c. LVT cell
d. HVT cell

17) CRPR stands for ___.

a. Cell Convergence Pessimism Removal
b. Cell Convergence Preset Removal
c. Clock Convergence Pessimism Removal
d. Clock Convergence Preset Removal

18) In OCV timing check, for setup time, ___.

a. Max delay is used for launch path and Min delay for capture path
b. Min delay is used for launch path and Max delay for capture path
c. Both Max delay is used for launch and Capture path
d. Both Min delay is used for both Capture and Launch paths

19) "Total metal area and(or) perimeter of conducting layer / gate to gate area" is called ___.

a. Utilization
b. Aspect Ratio
c. OCV
d. Antenna Ratio

20) The Solution for Antenna effect is ___.

a. Diode insertion
b. Shielding
c. Buffer insertion
d. Double spacing

21) To avoid cross talk, the shielded net is usually connected to ___.

a. VDD
b. VSS
c. Both VDD and VSS
d. Clock

22) If the data is faster than the clock in Reg to Reg path ___ violation may come.

a. Setup
b. Hold
c. Both
d. None

23) Hold violations are preferred to fix ___.

a. Before placement
b. After placement
c. Before CTS
d. After CTS

24) Which of the following is not present in SDC ___?

a. Max tran
b. Max cap
c. Max fanout
d. Max current density

25) Timing sanity check means (with respect to PD)___.

a. Checking timing of routed design with out net delays
b. Checking Timing of placed design with net delays
c. Checking Timing of unplaced design without net delays
d. Checking Timing of routed design with net delays

26) Which of the following is having highest priority at final stage (post routed) of the design ___?

a. Setup violation
b. Hold violation
c. Skew
d. None

27) Which of the following is best suited for CTS?

a. CLKBUF
b. BUF
c. INV
d. CLKINV

28) Max voltage drop will be there at(with out macros) ___.

a. Left and Right sides
b. Bottom and Top sides
c. Middle
d. None

29) Which of the following is preferred while placing macros ___?

a. Macros placed center of the die
b. Macros placed left and right side of die
c. Macros placed bottom and top sides of die
d. Macros placed based on connectivity of the I/O

30) Routing congestion can be avoided by ___.

a. placing cells closer
b. Placing cells at corners
c. Distributing cells
d. None

31) Pitch of the wire is ___.

a. Min width
b. Min spacing
c. Min width - min spacing
d. Min width + min spacing

32) In Physical Design following step is not there ___.

a. Floorplaning
b. Placement
c. Design Synthesis
d. CTS

33) In technology file if 7 metals are there then which metals you will use for power?

a. Metal1 and metal2
b. Metal3 and metal4
c. Metal5 and metal6
d. Metal6 and metal7

34) If metal6 and metal7 are used for the power in 7 metal layer process design then which metals you will use for clock ?

a. Metal1 and metal2
b. Metal3 and metal4
c. Metal4 and metal5
d. Metal6 and metal7

35) In a reg to reg timing path Tclocktoq delay is 0.5ns and TCombo delay is 5ns and Tsetup is 0.5ns then the clock period should be ___.

a. 1ns
b. 3ns
c. 5ns
d. 6ns

36) Difference between Clock buff/inverters and normal buff/inverters is __.

a. Clock buff/inverters are faster than normal buff/inverters
b. Clock buff/inverters are slower than normal buff/inverters
c. Clock buff/inverters are having equal rise and fall times with high drive strengths compare to normal buff/inverters
d. Normal buff/inverters are having equal rise and fall times with high drive strengths compare to Clock buff/inverters.

37) Which configuration is more preferred during floorplaning ?

a. Double back with flipped rows
b. Double back with non flipped rows
c. With channel spacing between rows and no double back
d. With channel spacing between rows and double back

38) What is the effect of high drive strength buffer when added in long net ?

a. Delay on the net increases
b. Capacitance on the net increases
c. Delay on the net decreases
d. Resistance on the net increases.

39) Delay of a cell depends on which factors ?

a. Output transition and input load
b. Input transition and Output load
c. Input transition and Output transition
d. Input load and Output Load.

40) After the final routing the violations in the design ___.

a. There can be no setup, no hold violations
b. There can be only setup violation but no hold
c. There can be only hold violation not Setup violation
d. There can be both violations.

41) Utilisation of the chip after placement optimisation will be ___.

a. Constant
b. Decrease
c. Increase
d. None of the above

42) What is routing congestion in the design?

a. Ratio of required routing tracks to available routing tracks
b. Ratio of available routing tracks to required routing tracks
c. Depends on the routing layers available
d. None of the above

43) What are preroutes in your design?

a. Power routing
b. Signal routing
c. Power and Signal routing
d. None of the above.

44) Clock tree doesn't contain following cell ___.

a. Clock buffer
b. Clock Inverter
c. AOI cell
d. None of the above

Answers:

1)b
2)c
3)b
4)c
5)b
6)d
7)a
8)c
9)d
10)b
11)d
12)d
13)b
14)c
15)b
16)a
17)c
18)a
19)d
20)a
21)b
22)b
23)d
24)d
25)c
26)b
27)a
28)c
29)d
30)c
31)d
32)c
33)d
34)c
35)d
36)c
37)a
38)c
39)b
40)d
41)c
42)a
43)a
44)c

Delay - Timing path Delay" : Static Timing Analysis (STA)

2011-08-29T06:38:00.000-07:00

Now in a circuit there are 2 major type of Delay.

CELL DELAY

Timing Delay between an input pin and an output pin of a cell.
Cell delay information is contained in the library of the cell. e.g- .lef file

NET DELAY.

Interconnect delay between a driver pin and a load pin.
To calculate the NET delay generally you require 3 most important information.

Characteristics of the Driver cell (which is driving the particular net)
Load characteristic of the receiver cell. (which is driven by the net)
RC (resistance capacitance) value of the net. (It depends on several factor- which we will discuss later)

Both the delay can be calculated by multiple ways. It depends at what stage you require this information with in the design. e.g During pre layout or Post layout or during Signoff timing. As per the stage you are using this, you can use different ways to calculate these Delay. Sometime you require accurate numbers and sometime approximate numbers are also sufficient.

Now lets discuss this with previous background and then we will discuss few new concepts.

Now in the above fig- If I will ask you to calculate the delay of the circuit, then the delay will be

Delay=0.5+0.04+0.62+0.21+0.83+0.15+1.01+0.12+0.57=4.05ns (if all the delay in ns)

Now lets add few more value in this. As we know that every gate and net has max and min value, so in that case we can find out the max delay and min delay. (on what basis these max delay and min delay we are calculating .. we will discuss after that)

So in the above example, first value is max value and 2nd value is min value. So

Delay(max)= 0.5+0.04+0.62+0.21+0.83+0.15+1.01+0.12+0.57=4.05ns

Delay(min)= 0.4+0.03+0.6+0.18+0.8+0.1+0.8+0.1+0.5=3.51ns

Till now every one know the concept. Now lets see what's the meaning of min and max delay.

The delay of a cell or net depends on various parameters. Few of them are listed below.

Library setup time
Library delay model
External delay
Cell load characteristic
Cell drive characteristic
Operating condition (PVT)
Wire load model
Effective Cell output load
Input skew
Back annotated Delay

If any of these parameter vary , the delay vary accordingly. Few of them are mutually exclusive. and In that case we have to consider the effect of only one parameter at a time. If that's the case , then for STA, we calculated the delay in both the condition and then categorize them in worst (max delay) condition or the best condition (min delay). E.g- if a cell has different delay for rise edge and fall edge. Then we are sure that in delay calculation we have to use only one value. So as per their value , we can categorize fall and rise delay of all the cell in the max and min bucket. And finally we come up with max Delay and min delay.

Information used in Cell and net delay calculation (Picture Source - Synopsys)

The way delay is calculated also depends which tool are you using for STA or delay calculation. Cadence may have different algorithm from Synopsys and same is the case of other vendor tools like mentor,magma and all. But in general the basic or say concepts always remain same.

I will explain about all these parameter in detail in next of few blogs, but right now just one example which can help you to understand the situation when you have a lot of information about the circuit and you want to calculate the delay.

In the above diagram, you have 2 paths between UFF1 and UFF3. So when ever you are doing setup and hold analysis, these path will be the part of launch path (arrival time). So lets assume you want to calculate the max and min value of delay between UFF1 and UFF2.

Information1:

	UOR4	UNAND6	UNAND0	UBUF2	UOR2
DELAY(ns)	5	6	6	2	5

Calculation:

Delay in Path1 : 5+6=11ns,

Delay in Path2: 6+2+5+6=19ns,

Max Delay = 19ns - Path2 - Longest Path - Worst Path

Min Delay = 11ns - Path1 - Smallest Path - Best Path

Information2:

	UOR4	UNAND6	UNAND0	UBUF2	UOR2
Rise Delay (ns)	5	6	4	1	1
Fall Delay (ns)	6	7	3	1	1

Calculation:

Delay in Path1 : Rise Delay : 5+6=11ns, Fall Delay: 6+7=13ns

Delay in Path2: Rise Delay : 4+1+1+6=12ns, Fall Delay: 3+1+1+7=12ns

Max Delay = 13ns -Path1 (Fall Delay)

Min Delay = 11ns - Path1 (Rise Delay)

Note: here there are lot of more concepts which can impact the delay calculation sequence, like unate. We are not considering all those right now. I will explain later.

Information3:

Library	Delay	UOR4	UNAND6	UNAND0	UBUF2	UOR2
Min	Rise Delay (ns)	5	6	4	1	1
Min	Fall Delay (ns)	6	7	3	1	1
Max	Rise Delay (ns)	5.5	6.5	4.5	1.5	1.5
Max	Fall Delay (ns)	5.5	6.5	2.5	0.5	0.5

Calculation:
For Min Library:

Delay in Path1 : Rise Delay : 5+6=11ns, Fall Delay: 6+7=13ns

Delay in Path2: Rise Delay : 4+1+1+6=12ns, Fall Delay: 3+1+1+7=12ns

For Max Library:

Delay in Path1 : Rise Delay : 5.5+6.5=12ns, Fall Delay: 5.5+6.5=14ns

Delay in Path2: Rise Delay : 4.5+1.5+1.5+6.5=14ns, Fall Delay: 2.5+0.5+0.5+6.5=10ns

Max Delay = 14ns- Path1(Fall Delay)/Path2(Rise Delay)

Min Delay = 10ns - Path2(Fall Delay)

As we have calculated above, STA tool also uses similar approach for finding the Max delay and Min Delay. Once Max and Min delay is calculated then during setup and hold calculation, we use corresponding value.

Once again I am mentioning that all these values are picked randomly. So it may be possible that practically the type/amount of variation in value is not possible.

In next part we will discuss these parameter in detail one by one.

"Setup and Hold Time Violation" : Static Timing Analysis (STA)caluculation

2011-08-29T06:34:00.000-07:00

Here we will discuss how to calculate the Setup and Hold Violation for a design.

Till now we have discussed setup and hold violation with respect to the single flipflop, now lets extend this to 2 flip flop. In the following fig there are 2 flipflops (FF1 and FF2).

Single-Cycle Setup and Hold For Flip-Flops

Few important things to note down here-

Data is launching from FF1/D to FF1/Q at the positive clock edge at FF1/C.
At FF2/D , input data is coming from FF1/Q through a combinational logic.
Data is capturing at FF2/D, at the positive clock edge at FF2/C.
So I can say that Launching Flip-Flop is FF1 and Capturing Flip-Flop is FF2.
So Data path is FF1/C --> FF1/Q --> FF2/D
For a single cycle circuit- Signal has to be propagate through Data path in one clock cycle. Means if data is launched at time=0ns from FF1 then it should be captured at time=10ns by FF2.

So for Setup analysis at FF2, Data should be stable "Ts" time before the positive edge at FF2/C. Where "Ts" is the Setup time of FF2.

If Ts=0ns, then , data launched from FF1 at time=0ns should arrive at D of FF2 before or at time=10ns. If data takes too long ( greater then 10ns) to arrive (means it is not stable before clock edge at FF2) , it is reported as Setup Violation.
If Ts=1ns, then, data launched from FF1 at time=0ns should arrive at D of FF2 before or at time=(10ns-1ns)=9ns. If data takes too long (greater then 9ns) to arrive (means it is not stable before 1ns of clock edge at FF2), it is reported as Setup Violation.

For Hold Analysis at FF2, Data should be stable "Th" time after the positive edge at FF2/C. Where "Th" is the Hold time of FF2. Means there should not be any change in the Input data at FF2/D between positive edge of clock at FF2 at Time=10ns and Time=10ns+Th.

To satisfy the Hold Condition at FF2 for the Data launched by FF1 at 0ns, the data launched by FF1 at 10ns should not reach at FF2/D before 10ns+Th time.
If Th=0.5ns, then we can say that the data launched from FF1 at time 10ns does not get propagated so soon that it reaches at FF2 before time (10+0.5)=10.5ns ( Or say it should reach from FF1 to FF2 with in 0.5ns). If data arrive so soon (means with in 0.5ns from FF1 to FF2, data can't be stable at FF2 for time=0.5ns after the clock edge at FF2), its reported Hold violation.

With the above explanation I can say 2 important points:

Setup is checked at next clock edge.
Hold is checked at same clock edge.

Setup Check timing can be more clear for the above Flip-flop combination with the help of following explanation.

Setup Check Timing

In the above fig you can see that the data launched by FF1/D ( at launch edge) reaches at FF2/D after a specific delay ( CLK-to-Q delay + Conminational Logic Delay) well before the setup time requirement of Flip-Flop FF2, so there is no setup violation.

From the Fig its clear that if Slack= Required Time - Arrival time < 0 (-ive) , then there is a Setup violation at FF2.

Hold Check timing can be more clear with the help of following circuit and explanation.

Hold Check Timing

In the above fig you can see that there is a delay in the CLK and CLKB because of the delay introduced by the series of buffer in the clock path. Now Flip-flop FF2 has a hold requirement and as per that data should be constant after the capture edge of CLKB at Flip-flop FF2.
You can see that desired data which suppose to capture by CLKB at FF2.D should be at Zero (0) logic state and be constant long enough after the CLKB capture edge to meet hold requirement but because of very short logic delay between FF1/Q and FF1/D, the change in the FF1/Q propagates very soon. As a result of that there occurs a Hold violation.

This type of violation (Hold Violation) can be fixed by shortening the delay in the clock line or by increasing the delay in the data path.

Setup and Hold violation calculation for the single clock cycle path is very easy to understand. But the complexity increases in case of multi-cycle path ,Gated clock, Flip-flop using different clocks, Latches in place of Flip-Flop. We will discuss all these later sometime.

"Setup and Hold Time" : Static Timing Analysis (STA)

2011-08-29T06:32:00.001-07:00

The way we will discuss this concept in the following manner

What is SetUp and Hold time?
Definition of Setup and Hold.
Setup and Hold Violation.
How to calculate the Setup and Hold violation in a design?

I saw that lots of people are confused with respect to this concept. And the reason of this are

They know the definition but don't know the origin or say concept behind Setup and Hold timing.
They know the formula for calculating setup and hold violation but don't know how this formula come in picture.
They become confuse by few of the terminology like capture path delay, launch path delay, previous clock cycle, current clock cycle, data path delay, slew, setup slew, hold slew, min and max concept, slowest path and fastest path, min and max corner, best and worst case etc during the explanation of Setup and Hold Timings/Violation.

I hope I can clarify your confusion. Let me explain this and if you face any problem let me know.

What is Setup and Hold time?

To understand the origin of the Setup and Hold time concepts first understand it with respect to a System as shown in the fig. An Input DIN and external clock CLK are buffered and passes through combinational logic before they reach a synchronous input and a clock input of a D flipflop (positive edge triggered). Now to capture the data correctly at D flip flop, data should be present at the time of positive edge of clock signal at the C pin ( to know the detail just read basis of D flipflop).

Note: here we are assuming D flip flop is ideal so Zero hold and setup time for this.

SetUp and Hold Time of a System

There may be only 2 condition.

Tpd DIN > Tpd Clk

For capture the data at the same time when Clock signal (positive clock edge) reaches at pin C, you have to apply the input Data at pin DIN "Ts(in)=(Tpd DIN) - (Tpd Clk)" time before the positive clock edge at pin CLK.
In other word, at DIN pin, Data should be stable "Ts(in)" time before the positive clock edge at CLK pin.
This Time "Ts(in)" is know as Setup time of the System.

Tpd DIN < Tpd Clk

For capture the data at the same time when clock signal (positive clock edge) reaches at pin C, input Data at pin DIN should not change before "Th(in)= (Tpd Clk) - (Tpd DIN)" time. If it will change, positive clock edge at pin C will capture the next data.
In other word, at DIN pin, Data should be stable "Th(in)" time after the positive clock edge at CLK pin.
This time "Th(in)" is know as Hold Time of the System.

From the above condition it looks like that both the condition can't exist at the same time and you are right. But we have to consider few more things in this.

Worst case and best case (Max delay and min delay)

Because of environment condition or because of PVT, we can do this analysis for the worst case ( max delay) and best case ( min delay) also.

Shortest Path or Longest path ( Min Delay and Max delay)

If combinational logic has multiple paths, the we have to do this analysis for the shortest path ( min delay) and longest path ( max delay) also.

So we can say that above condition can be like this.

Tpd DIN (max) > Tpd Clk (min)

SetUp time == Tpd DIN (max) - Tpd Clk (min)

Tpd DIN (min) < Tpd Clk (max)

Hold time == Tpd Clk (max) - Tpd DIN (min)

For example for combinational logic delays are

Data path (max, min) = (5ns, 4 ns)

Clock path (max, min) = (4.5ns, 4.1ns)

Then Setup time= 5-4.1=0.9ns

Hold time is = 4.5-4=0.5ns

Now similar type of explanation we can give for a D flip flop. There is a combinational logic between C and Q , between D and Q of the Flipflop. There are different delays in those conbinational logic and based on there max and min value , a flipflop has Setup and Hold time. One circuitry of the positive edge triggered D flip is shown below.

Positive Edge Triggered D flip-flop

There are different ways for making the D flip flop. Like by JK flipflop, master slave flipflop, Using 2 D type latches etc. Since the internal circuitry is different for each type of Flipflop, the Setup and Hold time is different for every Flipflop.

Definition:

Setup Time:

Setup time is the minimum amount of time the data signal should be held steady before the clock event so that the data are reliably sampled by the clock. This applies to synchronous circuits such as the flip-flop.
Or In short I can say that the amount of time the Synchronous input (D) must be stable before the active edge of the Clock.
The Time when input data is available and stable before the clock pulse is applied is called Setup time.

Hold time:

Hold time is the minimum amount of time the data signal should be held steady after the clock event so that the data are reliably sampled. This applies to synchronous circuits such as the flip-flop.
Or in short I can say that the amount of time the synchronous input (D) must be stable after the active edge of clock.
The Time after clock pulse where data input is held stable is called hold time.

Setup and Hold Violation:

In simple language-

If Setup time is Ts for a flip-flop and if data is not stable before Ts time from active edge of the clock, there is a Setup violation at that flipflop. So if data is changing in the non-shaded area ( in the above figure) before active clock edge, then it's a Setup violation.

And If hold time is Th for a flip flop and if data is not stable after Th time from active edge of the clock , there is a hold violation at that flipflop. So if data is changing in the non-shaded area ( in the above figure) after active clock edge, then it's a Hold violation.

"Time Borrowing" : Static Timing Analysis

2011-08-29T06:29:00.001-07:00

In a ASIC there are majorly two types of component. Flip-flop and other is Latches. Basically Here we will discuss about Latched based timing analysis.

Before this we should understand the basic differences between the latch based design and flip-flop based design.

Edge-triggered flip-flops change states at the clock edges, whereas latches change states as long as the clock pin is enabled.
The delay of a combinational logic path of a design using edge-triggered flip-flops cannot be longer than the clock period except for those specified as false paths and multiple-cycle paths. So the performance of a circuit is limited by the longest path of a design.
In latch based design longer combinational path can be compensated by shorter path delays in the sebsequent logic stages.So for higher performance circuits deisgner are turning to latched based design.

Its true that in the latched based design its difficult to control the timing because of multi-phase clockes used and the lack of "hard" clock edges at which events must occur.

The technique of borrowing time from the shorter paths of the subsequent logic stages to the longer path is called time borrowing or cycle stealing.

Lets talk about this. Please See the following figure.

Example of Latched based design.

There are 4 latches (positive level sensitive). L1 and L3 are controlled by PH1 and L2 and L4 are controlled by PH2. G1, G2, G3 and G4 are combinational logic paths. For now assume a library setup time is zero for the latches and zero delay in latch data-path in the transparent mode.

Now if assume that if designs using edge-triggered flip-flops, the clock period has to be at least 8 ns because the longest path in G1 is 8 ns. Now as the clock pulse is 5ns , there is a voilation at L2. On the other hand, if the design uses latches , L2 latch is transparent for another 5ns and since the eighth (8th) ns is within the enabled period of L2, the signal along path1 can pass through L2 and continue on path2. Since the delay along path2 is 2 ns, which is short enough to compensate for the overdue delay of path1, this design will work properly. In other word we can say that path1 can borrow sometime (3ns) from the path2. Since the sum of path1 and path2 is 10ns, which is the required time of L3, there will be no voilation in either of the Latches.

For the same reason, path3 can borrow some time (1ns) from path4 without any timing violation.

Note: A latch-based design completes the execution of the four logic stages in 20 ns, whereas an edge-triggered based design needs 32 ns.

Lets see this in a more complex design. Its self explanatory.

Example Of Timing Borrowing

Just wanted to convey here that this Timing borrowing can be multistage. Means we can easily say that for a latched based design, each executing path must start at a time when its driving latch is enabled, and end at a time when its driven latch is enabled.

Few Important things:

Time borrowing occur with in the same cycle. Means launching and capturing latches be using the same phase of the same clock. when the clocks of the launching and capturing latches are out of phase, time borrowing is not to happen. Usually it was disabled by EDA tools.
Time borrowing typically only affects setup slack calculation since time borrowing slows data arrival times. Since hold time slack calculation uses fastest data, time-borrowing typically does not affect hold slack calculation.

Few Important terminology:

Maximum Borrow time:

Maximum Borrow time is the clock pulse width minus the library setup time of the latch. Usually to calculate the maximum allowable borrow time, start with clock pulse width and then substract clock latency , clock reconvergence pessimism removal , library setup time of the endpoint latch.

Negative Borrow time:

If the arrival time minus the clock edge is a negative number, the amount of time borrowing is negative ( in other way you can say that no borrowing). This amount is know as Negative Borrow time.

Power Gating

2011-08-29T06:16:00.001-07:00

Power Gating is effective for reducing leakage power [3]. Power gating is the technique wherein circuit blocks that are not in use are temporarily turned off to reduce the overall leakage power of the chip. This temporary shutdown time can also call as "low power mode" or "inactive mode". When circuit blocks are required for operation once again they are activated to "active mode". These two modes are switched at the appropriate time and in the suitable manner to maximize power performance while minimizing impact to performance. Thus goal of power gating is to minimize leakage power by temporarily cutting power off to selective blocks that are not required in that mode.

Power gating affects design architecture more compared to the clock gating. It increases time delays as power gated modes have to be safely entered and exited. The possible amount of leakage power saving in such low power mode and the energy dissipation to enter and exit such mode introduces some architectural trade-offs. Shutting down the blocks can be accomplished either by software or hardware. Driver software can schedule the power down operations. Hardware timers can be utilized. A dedicated power management controller is the other option.

An externally switched power supply is very basic form of power gating to achieve long term leakage power reduction. To shutoff the block for small interval of time internal power gating is suitable. CMOS switches that provide power to the circuitry are controlled by power gating controllers. Output of the power gated block discharge slowly. Hence output voltage levels spend more time in threshold voltage level. This can lead to larger short circuit current.

Power gating uses low-leakage PMOS transistors as header switches to shut off power supplies to parts of a design in standby or sleep mode. NMOS footer switches can also be used as sleep transistors. Inserting the sleep transistors splits the chip's power network into a permanent power network connected to the power supply and a virtual power network that drives the cells and can be turned off.

The quality of this complex power network is critical to the success of a power-gating design. Two of the most critical parameters are the IR-drop and the penalties in silicon area and routing resources. Power gating can be implemented using cell- or cluster-based (or fine grain) approaches or a distributed coarse-grained approach.

Power-gating parameters

Power gating implementation has additional considerations than the normal timing closure implementation. The following parameters need to be considered and their values carefully chosen for a successful implementation of this methodology [1] [2].

Power gate size: The power gate size must be selected to handle the amount of switching current at any given time. The gate must be bigger such that there is no measurable voltage (IR) drop due to the gate. Generally we use 3X the switching capacitance for the gate size as a rule of thumb. Designers can also choose between header (P-MOS) or footer (N-MOS) gate. Usually footer gates tend to be smaller in area for the same switching current. Dynamic power analysis tools can accurately measure the switching current and also predict the size for the power gate.

Gate control slew rate: In power gating, this is an important parameter that determines the power gating efficiency. When the slew rate is large, it takes more time to switch off and switch-on the circuit and hence can affect the power gating efficiency. Slew rate is controlled through buffering the gate control signal.

Simultaneous switching capacitance: This important constraint refers to the amount of circuit that can be switched simultaneously without affecting the power network integrity. If a large amount of the circuit is switched simultaneously, the resulting "rush current" can compromise the power network integrity. The circuit needs to be switched in stages in order to prevent this.

Power gate leakage: Since power gates are made of active transistors, leakage is an important consideration to maximize power savings.

Fine-grain power gating

Adding a sleep transistor to every cell that is to be turned off imposes a large area penalty, and individually gating the power of every cluster of cells creates timing issues introduced by inter-cluster voltage variation that are difficult to resolve. Fine-grain power gating encapsulates the switching transistor as a part of the standard cell logic. Switching transistors are designed by either library IP vendor or standard cell designer. Usually these cell designs conform to the normal standard cell rules and can easily be handled by EDA tools for implementation.

The size of the gate control is designed with the worst case consideration that this circuit will switch during every clock cycle resulting in a huge area impact. Some of the recent designs implement the fine-grain power gating selectively, but only for the low Vt cells. If the technology allows multiple Vt libraries, the use of low Vt devices is minimum in the design (20%), so that the area impact can be reduced. When using power gates on the low Vt cells the output must be isolated if the next stage is a high Vt cell. Otherwise it can cause the neighboring high Vt cell to have leakage when output goes to an unknown state due to power gating.

Gate control slew rate constraint is achieved by having a buffer distribution tree for the control signals. The buffers must be chosen from a set of always on buffers (buffers without the gate control signal) designed with high Vt cells. The inherent difference between when a cell switches off with respect to another, minimizes the rush current during switch-on and switch-off.

Usually the gating transistor is designed as a high vt device. Coarse-grain power gating offers further flexibility by optimizing the power gating cells where there is low switching activity. Leakage optimization has to be done at the coarse grain level, swapping the low leakage cell for the high leakage one. Fine-grain power gating is an elegant methodology resulting in up to 10X leakage reduction. This type of power reduction makes it an appealing technique if the power reduction requirement is not satisfied by multiple Vt optimization alone.

Coarse-grain power gating

The coarse-grained approach implements the grid style sleep transistors which drives cells locally through shared virtual power networks. This approach is less sensitive to PVT variation, introduces less IR-drop variation, and imposes a smaller area overhead than the cell- or cluster-based implementations. In coarse-grain power gating, the power-gating transistor is a part of the power distribution network rather than the standard cell.

There are two ways of implementing a coarse-grain structure:

1) Ring-based

2) column-based

Ring-based methodology: The power gates are placed around the perimeter of the module that is being switched-off as a ring. Special corner cells are used to turn the power signals around the corners.

Column-based methodology: The power gates are inserted within the module with the cells abutted to each other in the form of columns. The global power is the higher layers of metal, while the switched power is in the lower layers.

Gate sizing depends on the overall switching current of the module at any given time. Since only a fraction of circuits switch at any point of time, power gate sizes are smaller as compared to the fine-grain switches. Dynamic power simulation using worst case vectors can determine the worst case switching for the module and hence the size. IR drop can also be factored into the analysis. Simultaneous switching capacitance is a major consideration in coarse-grain power gating implementation. In order to limit simultaneous switching daisy chaining the gate control buffers, special counters are used to selectively turn on blocks of switches.

Isolation Cells

Isolation cells are used to prevent short circuit current. As the name indicates these cells isolate power gated block from the normally on block. Isolation cells are specially designed for low short circuit current when input is at threshold voltage level. Isolation control signals are provided by power gating controller. Isolation of the signals of a switchable module is essential to preserve design integrity. Usually a simple OR or AND logic can function as an output isolation device. Multiple state retention schemes are available in practice to preserve the state before a module shuts down. The simplest technique is to scan out the register values into a memory before shutting down a module. When the module wakes up, the values are scanned back from the memory.

Retention Registers

When power gating is used, the system needs some form of state retention, such as scanning out data to a RAM, then scanning it back in when the system is reawakened. For critical applications, the memory states must be maintained within the cell, a condition that requires a retention flop to store bits in a table. That makes it possible to restore the bits very quickly during wakeup. Retention registers are special low leakage flip-flops used to hold the data of main register of the power gated block. Thus internal state of the block during power down mode can be retained and loaded back to it when the block is reactivated. Retention registers are always powered up. The retention strategy is design dependent. During the power gating data can be retained and transferred back to block when power gating is withdrawn. Power gating controller controls the retention mechanism such as when to save the current contents of the power gating block and when to restore it back.

References

[1] Practical Power Network Synthesis For Power-Gating Designs, http://www.eetimes.com/news/design/showArticle.jhtml?articleID=199903073&pgno=1, 11/01/2008

[2] Anand Iyer, “Demystify power gating and stop leakage cold”, Cadence Design Systems, Inc. http://www.powermanagementdesignline.com/howto/181500691;jsessionid=NNNDVN1KQOFCUQSNDLPCKHSCJUNN2JVN?pgno=1, 11/01/2008

[3] De-Shiuan Chiou, Shih-Hsin Chen, Chingwei Yeh, "Timing driven power gating", Proceedings of the 43rd annual conference on Design automation,ACM Special Interest Group on Design Automation, pp.121 - 124, 2006

Basic of Timing Analysis in Physical Design

2011-08-22T00:58:00.000-07:00

What is Timing Analysis??

Before we start anything at least we should know what exactly we mean by Timing Analysis. Why these days it’s so important?

There are a couple of reasons for performing timing analysis.

We want to verify whether our circuit meet all of its timing requirements (Timing Constraints)

There are 3 types of design constraints- timing, power, area. During designing there is a trade-offs between speed, area, power, and runtime according to the constraints set by the designer. However, a chip must meet the timing constraints in order to operate at the intended clock rate, so timing is the most important design constraint.

We want to make sure that circuit is properly designed and can work properly for all combinations of components over the entire specified operating environment. "Every Time".
Timing analysis can also help with component selection.

An example is when you are trying to determine what memory device speed, you should use with a microprocessor. Using a memory device that is too slow may not work in the circuit (or would degrade performance by introducing wait states), and using one that is too fast will likely cost more than it needs to.

So I can say Timing analysis is the methodical analysis of a digital circuit to determine if the timing constraints imposed by components or interfaces are met. Typically, this means that you are trying to prove that all set-up, hold, and pulse-width times are being met.

Note: Timing analysis is integral part of ASIC/VLSI design flow. Anything else can be compromised but not timing!

Types of Timing Analysis:

There are 2 type of Timing Analysis-

Static Timing Analysis:

Checks static delay requirements of the circuit without any input or output vectors.

Dynamic Timing Analysis.

verifies functionality of the design by applying input vectors and checking for correct output vectors

Basic Of Timing Analysis:

The basis of all timing analysis is the clock and the sequential component (here we will discuss with the help of Flip-flop) . Following are few of the things related to clock and flip-flop which we usually wants to take care during Timing analysis.

Clock related:

It must be well understood parametrically and glitch-free.
Timing analysis must ensure that any clocks that are generated by the logic are clean, are of bounded period and duty cycle, and of a known phase relationship to other clock signals of interest.
The clock must, for both high and low phases, meet the minimum pulse width requirements.
Certain circuits, such as PLLs, may have other requirements such as maximum jitter. As the clock speeds increase, jitter becomes an increasingly important parameter.
When "passing" data from one clock edge to the other, ensure that the worst-case duty cycle is used for the calculation. A frequent source of error is the analyst assuming that every clock will have a 50% duty cycle.

Flip-Flop related:

All of the flip-flops parameters are always met. The only exception to this is when synchronizers are used to synchronize asynchronous signals
For asynchronous presets and clears, there are two basic parameters that must be met.
All setup and hold times are met for the earliest/latest arrival times for the clock.
Setup times are generally calculated by designers and suitable margins can be demonstrated under test. Hold times, however, are frequently not calculated by designers.
When passing data from one clock domain to another, ensure that there is either known phase relationships which will guarantee meeting setup and hold times or that the circuits are properly synchronized

Now Lets talk about Each type of Timing analysis One by one in the next few blogs.

Tuesday, February 22, 2011

Clock Reconvergence Pessimism (CRP) basic

Full Form :

CRP : Clock Reconvergence Pessimism.

What is CRP (Clock Reconvergence Pessimism)?

As the "convergence" means (dictionary) "the occurrence of two or more things coming together". So we can assume that its also related to 2 clock path coming together. (Please refer the another blog for understanding the Clock path- Static Timing Analysis Basic: Part1 "Timing Paths")

Now lets assume 2 flip-flop circuit as shown in the figure.

Clock Reconvergence Pessimism

As you can see that flop share a common clock but are placed physically at the different places in the same die. Or in other way you can say that Launch clock path and capture clock path (Please refer Static Timing Analysis Basic: Part1 "Timing Paths" for defination of Launch and Capture Clock path) share a common segment in the clock tree till the point know as "common point" (in above fig you can see that "common point" is written as "The clock path common to both flops till this point"). The 2 clock path diverse from that point.

As we know that every cell has two type of delay as a part of its specification, "Max Delay" and "Min delay". There are several scenario in the design where we use either max delay or min delay of a particular cell. Such as best case analysis (BC), worst case (WC) analysis, OCV (on chip variation) analysis during timing analysis.

Lets consider that max delay and min delay of the common segment is as
Max delay=1.2ns
Min Delay=1.0ns.

Now, if during timing analysis a condition arise where you have to use max delay for one timing path and min delay for another timing path (such as during OCV analysis), you have to use 2 different values for a common path. But practically same set of cells can't be behave different for different clock path.

For example, for a setup check, it uses the maximum delay for the launch clock path (1.2ns + delay because of rest of the circuit in the launch path) and the minimum delay for the capture clock path (1.0ns + delay because of rest of the circuit in the launch path.

In a physical design, however, the cells along the common portion of the clock tree cannot simultaneously achieve their maximum and minimum delay values. Thus there will be a single value of delay to the common point that will be propagated to both the launching and capturing clock paths. This conflicts with our timing analysis method described above since we utilise two sets of delay values at the common point.

Therefore our timing report contains artificially introduced pessimism that is derived from our usage of max and min delay for the launching and capturing paths along this common portion of the clock network. The value of this pessimism, is the difference between max and min delay at the common point in the clock network.

The amount of pessimism due to this effect (in this example, 0.2 ns) is called "clock reconvergence pessimism".

Clock reconvergence pessimism = (maximum clock delay) - (minimum clock delay)

Note: Above situation is identical for hold checks also.

Similar type of situation can arise in different type of circuit also. Lets discuss one of that. Please see the following fig.

Schematic of a reconvergent clock

The two clock paths that feed into the multiplexer cannot be active at the same time, but an analysis could consider both the shorter and longer paths for one setup or hold check. This results in different launch and capture clock path delays and the consequent pessimism.

How to remove CRP ?

Automated correction of this inaccuracy is called clock reconvergence pessimism removal (CRPR). By default , most of the tools (EDA tools for timing calculation) disable this feature (automated correction). By you can enable this feature by setting one/more variables during timing analysis. Different Tools have different variable for this. For that please refer the USER GUIDE or MANUAL of corresponding tool.

Saturday, February 19, 2011

Different File Formats (file extensions)

There are different type of the files generated during a design cycle or data received by the library vendor/foundry. Few of them having specific extension. Just to know the extension, you can easily identity the type of content in that file.

I am listing down of the file extension. Please let me know if you find any extension is missing. I will add those later on.

File Extensions:

*.v - Verilog source file. Normally it’s a source file your write. Design Compiler, and IC Compiler can use this format for the gate-level netlist.
*.vg, .g.v - Verilog gate-level netlist file. Sometimes people use these file extension to differentiate source files and gate-level netlists.
*.svf - Automated setup file. This file helps Formality process design changes caused by other tools used in the design flow. Formality uses this file to assist the compare point matching and verification process. This information facilitates alignment of compare points in the designs that you are verifying. For each automated setup file that you load, Formality processes the content and stores the information for use during the name-based compare point matching period.
*.ddc - Synopsys internal database format. This format is recommended by Synopsys to hand gate-level netlists.
*.vcd - Value Change Dump format. This format is used to save signal transition trace information. This format is in text format, therefore, the trace file in this format can get very large quickly. There are tools like vcd2vpd, vpd2vcd, and vcd2saif switch back and forth between different formats.
*.vpd - VCD Plus. This is a proprietary compressed binary trace format from Synopsys. This file format is used to save signal transition trace information as well.
*.saif - Switching Activity Interchange Format. It’s another format to save signal transition trace information. SAIF files support signals and ports for monitoring as well as constructs such as generates, enumerated types, records, array of arrays, and integers.
*.tcl - Tool Command Language (Tcl) scripts. Tcl is used to drive Synopsys tools.
*.sdc - Synopsys Design Constraints. SDC is a Tcl-based format. All commands in an SDC file conform to the Tcl syntax rules. You use an SDC file to communicate the design intent, including timing and area requirements between EDA tools. An SDC file contains the following information: SDC version, SDC units, design constraints, and comments.
*.lib - Technology Library source file. Technology libraries contain information about the characteristics and functions of each cell provided in a semiconductor vendor’s library. Semiconductor vendors maintain and distribute the technology libraries. In our case the vendor is Synopsys. Cell characteristics include information such as cell names, pin names, area, delay arcs, and pin loading. The technology library also defines the conditions that must be met for a functional design (for example, the maximum transition time for nets). These conditions are called design rule constraints. In addition to cell information and design rule constraints, technology libraries specify the operating conditions and wire load models specific to that technology.
*.db - Technology Library. This is a compiled version of *.lib in Synopsys database format.
*.plib - Physical Library source file. Physical libraries contain process information, and physical layout information of the cells. This information is required for floor planning, RC estimation and extraction, placement, and routing.
*.pdb - Physical Library. This is a compiled version of *.plib in Synopsys database format.
*.slib - Symbol Library source file. Symbol libraries contain definitions of the graphic symbols that represent library cells in the design schematics. Semiconductor vendors maintain and distribute the symbol libraries. Design Compiler uses symbol libraries to generate the design schematic. You must use Design Vision to view the design schematic. When you generate the design schematic, Design Compiler performs a one-to-one mapping of cells in the netlist to cells in the symbol library.
*.sdb - Symbol Library. This is a compiled version of *.slib in Synopsys database format.
*.sldb - DesignWare Library. This file contains information about DesignWare libraries.
*.def - Design Exchange Format. This format is often used in Cadence tools to represent physical layout. Synopsys tools normally use Milkyway format to save designs.
*.lef - Library Exchange Format. Standard cells are often saved in this format. Cadence tools also often use this format. Synopsys tools normally use Milkyway format for standard cells.
*.rpt - Reports. This is not a proprietary format, it’s just a text format which saves generated reports by the tools when you use the automated makefiles and scripts.
*.tf - Vendor Technology File. This file contains technology-specific information such as the names, characteristics (physical and electrical) for each metal layer, and design rules. These information are required to route a design.
*.itf - Interconnect Technology File. This file contains a description of the process crosssection and connectivity section. It also describes the thicknesses and physical attributes of the conductor and dielectric layers.
*.map - Mapping file. This file aligns names in the vendor technology file with the names in the process *.itf file.
*.tluplus - TLU+ file. These files are generated from the *.itf files. TLUPlus models are a set of models containing advanced process effects that can be used by the parasitic extractors in Synopsys place-and-route tools for modeling.
*.spef - Standard Parasitic Exchange Format. File format to save parasitic information extracted by the place and route tool.
*.sbpf - Synopsys Binary Parasitic Format. A Synopsys proprietary compressed binary format of the *.spef. Size of the file shrinks quite a bit using this format.
*.mw( Milkyway database) The Milkyway database consists of libraries that contain information about your design. Libraries contain information about design cells, standard cells, macro cells, and so on. They contain physical descriptions, such as metal, diffusion, and polygon geometries. Libraries also contain logical information (functionality and timing characteristics) for every cell in the library. Finally, libraries contain technology information required for design and fabrication. Milkyway provides two types of libraries that you can use: reference libraries and design libraries. Reference libraries contain standard cells and hard or soft macro cells, which are typically created by vendors. Reference libraries contain physical information necessary for design implementation. Physical information includes the routing directions and the placement unit tile dimensions, which is the width and height of the smallest instance that can be placed. A design library contains a design cell. The design cell might contain references to multiple reference libraries (standard cells and macro cells). Also, a design library can be a reference library for another design library. The Milkyway library is stored as a UNIX directory with subdirectories, and every library is managed by the Milkyway Environment. The top-level directory name corresponds to the name of the Milkyway library. Library subdirectories are classified into different views containing the appropriate information relevant to the library cells or the designs. In a Milkyway library there are different views for each cell, for example, NOR1.CEL and NOR1.FRAM. This is unlike a .db formatted library where all the cells are in a single binary file. With a .db library, the entire library has to be read into memory. In the Milkyway Environment, the Synopsys tool loads the library data relevant to the design as needed, reducing memory usage. The most commonly used Milkyway views are CEL and FRAM. CEL is the full layout view, and FRAM is the abstract view for place and route operations.
simv - Compiled simulator. This is the output of vcs. In order to simulate, run the simulator by ./simv at the command line.
alib-52 - characterized target technology library. A pseudo library which has mappings from Boolean functional circuits to actual gates from the target library. This library provides Design Compiler with greater flexibility and a larger solution space to explore tradeoffs between area and delay during optimization.

Process Variation - Effects On Design, Different Types and Modelling

The Scaling down of Process technologies has increased the Process variations. Because of this delay variation increases and impact the frequency performance of the design. These things also impacted the TAT (Turn Around Time) and timing yields (The ration of chips that achieve the target Frequency).

As a design specification its important to Target a particular frequency and Yield. Means how many chip can perform with in the target frequency after fabrication). Designer have done a lot of things to achieve this and one of the way is "adding sufficient margin" for delay variation.

In Process node above 90nm , the margins for the delay variations are small enough and their impact on the design can be eliminated but below 90nm increased Delay variation (because of Process variation) enlarge the margins in the circuit design. Because of this we have to overestimate delay in the design and which makes design work difficult (Increased the TAT of the design).

So its very important to understand that what are the delay variations?

Delay Variations are due to various type of process variations.

Type Of Process variation:

Random Variation

Occurs without regards to the location and patterns of the transistors with in the chip.
E.g

variation in transistor threshold voltage caused by density variations of impurities in the transistor material.

Systematic variation

Related to the location and patterns
E.g

Exposure pattern variation that occurred in lithography process.
silicon surface flatness variations caused by layout pattern density variation during the CMP (Chemical Mechanical Planarization)

Intra-die Or Within-die variation

Variations between the elements in the same chip

Inter-die Or Die-to-die variation.

Variations between chips in the same wafer or in different wafers.

Part(a) is a type of Random variation. Part(b) for Systematic variation and Part(c) for Die-to-die and within-die variations.

There are few more classification for the Process variations

Front-end Variation

Mainly refer to the variations present at the transistor level.
The primary components of the front end variations

transistor gate length
gate width,
gate oxide thickness,
doping related variations.

These physical variations cause changes in the electrical characteristics of the transistors which eventually lead to the variability in the circuit performance

Back-end Variation.

Refer to the variations on various levels of interconnecting metal and dielectric layers used to connect numerous devices to form the required logic gates

Now at least we have a rough idea about the type of Variations. Now next question is what is the solution of these variations. If these variations are there then how can we take care about this. So regarding this Foundries and EDA companies had done a lot of experiments and they always come with better solutions.

One best way is To MODEL these variation (mathematically) and implement it during the designing cycle.

Lets Talk about these one by one.

Systematic Variation's Modeling:

Controlled not like Random variation modeling where every thing is distributed.
Generally Geometry-dependent or layout-dependent.
Modeling is based on practical models. These models are implemented mathematically using different Tables(matrix), equations and simulators.
Few of the area/causes on the basis of which modeling methods are decided

ETCH modelling.

Conductor's Width and Spacing Dependent ETCH.
Device Specific

Conductor Thickness variation.

Density dependent
Width and spacing dependent.
Dielectric coefficient dependent.

Dielectric thickness variation.
Trapezoidal Line Shape and width enlargement (Trap tangent modelling)
Damage Modelling.
The intra-die variations, or variations within the same chip, are modeled using a deterministic process and are well controlled.

Random Variation's Modelling.

Distributed , across different dies or even wafers
Random and independent in nature.
Manimum and minimun variation for a given parameter is usually know, along with the type of distribution the parameter exhibits. Usually this information is provided by the foundry.
Commonly, we use "Normal Gaussian Distribution" based on "Central Limit Theorem" for modelling random variation.

Based on Probability of occurance of a particular variation.
Assumption: Variation of a paramenter is independent of rest of the factors and none of them playing dominant role.

Random variations are modelled through process corners, where max and min variations represented by +3sigma and -3sigma.
Following parameters are modelled as Random variations

Thickness of

Conductor
Dielectric

Width of Conductor.
Dielectric Constant.

Inter-die variations, or the process variation from die to die or wafer to wafer, are assumed to be random, and therefore are generally modeled using a normal and/or uniform distribution.

NOTE: There are lots of systematic variation, which are part of Random variation for lower technology node. Because as the chip size is decreases, Its very difficult to come-up a well defined equations/tables for few of the parameters. e.g thickness variation due to chemical mechanical polishing (CMP) or line width variation because of optical inaccuracies.

Note: Please refer the Corresponding Blog for the detail of specific variation/model types.

ETM (Extracted Timing Models) - More detail

Lets Talk about ETM models little more: Check the ETM(Extracted Timing Models)-Basic blog for basic idea.

Advantage of Extracted Timing models:

Much smaller than the original netlist.
significantly reduce the time needed to analyze a large design.
Using a model in place of a netlist prevents a user from seeing the contents of the block.

Extraction Requirement:

To generate these models you should have

Block netlist.
Technology Library
Timing details of the block.

As I have mentioned previously in one of my blog that Extracted timing models creates a timing arc for each path (port to port or port to register or register to port) in the original design (block). As we know that delay in a design is accurate for a range of operating condition , but in the ETM models delay data does not depend on any specific parameter's value (like input transition times, output capacitive loads, input arrival times, output required times etc) and that's the reason these models are know as "context independent" models(condition applied ## [:)]). But when you are using these models in your design for timing analysis, then delay value depends on these parameters. So in other word I can say that these models are functions of different parameters and not limited to a specific set of parameter's values.

Timing information of different parts of the design in the Extracted models:

Nets:

Boundary nets: Preserves the boundary nets of the design. Since these are the nets which will interact with the outside world (when you are going to instantiate this in the other design), so proper/correct and original information is necessary to avoid any mismatching.
Internal Nets: Delay values are extracted in the models as per the information provided during the extraction. Means if you provide the "wire load models" then it will contain the information as per that or if you will provide detailed parasitics (of these internal nets), it will contain that information.

Paths:

Input to register: Extracted into equivalent setup arc and hold arc between these 2.

Setup arc = delay of the longest path + setup time of the register library cell.
Hold arc = delay of the shortest path + hold times of the register library cell.
Note:

calculation between the shortest and longest path is between a particular input to all registers clocked by the same clock
These values are function of transition time of input signal and clock, so if you are using this block in some other clock frequency (different then the value you have used during generation of these models), then you can do it easily.

Register to Input: Same as above.
Input to output path: Extracted into 2 equivalent arc (one is for shortest path and other for longest path).
Register to register: Not extracted
Clock path: Delays and transition times of clock networks are reflected in the extracted model.

Noise Analysis using These models:

By default these is no noise information is included in extracted models. If you want then you can use special command for including noise characteristics in the extracted models.

Other Information:

There are lot of other information present in the extracted timing models. For that you can refer PrimeTime User Guide.

## "Context independent" doesn't mean that you can operate these models for any set of conditions. Before a timing model is created, the internal logic of the block is checked for timing violations, subject to external conditions such as input delay and output delay. Once verified, the internal timing of the model is guaranteed to have no violations as long as the external conditions are within the ranges specified when the internal logic was checked.

## SO before using these blocks you should know the range of these blocks (know as scope of the block). You can generate the scope file containing all these information also and check that one before using this in your design.

## Information stored in the ETM is in the form of delay table (A 2x2 Matrix). These matrix specifies the arc delay value as a function of the input transition time and the output load capacitance. Interpolation and extrapolation are performed for calculating the values other then specified in the table. These models are accurate for the range of values specified in the table.

ETM (Extracted Timing Models) basics

Introduction:
In a design Once a block has met its timing constraints at the gate level, the detailed internal timing of the block is not needed for chip-level timing analysis. For that we can create/write a timing model for that block.

Timing Model of the block

Should completely model the full input/output timing characteristics without requiring the complete netlist of the block.
Do not model every path in the block. Internal registerto register paths are generally discarded, as these paths can be analyzed at the block level using the complete gate-level netlist.

Synopsys has a tool named as PrimeTime and its most trusted and advanced timing sign-off solution for gate-level STA tool. Its accuracy is within 5% of SPICE.

Prime Time Provides following types of advance timing models.

Interface Logic Models (ILM) for hierarchical static timing analysis and sign-off
Extracted Timing Models (ETM) in .lib format for cell-based reusable IP and physical design flows
Quick Timing Models (QTM) for top-down design

In this Blog we will discuss only about the ETM models basic. For More detail please refer "ETM (Extracted Timing Models) - More detail" blog.

ETM (Extracted Timing Models):-

Block based model (.lib)
Contents of block are hidden
Original netlist replaced by model containing timing arcs for block interfaces.
NLDM lookup tables are extracted for each of the timing arcs.
These arcs whose delay are a function of input transition and output load. This makes ETM usable with different input transition times and different output loads.
Multiple modes per model
Single PVT per model
Used for implementation (not sign-off) of IP models. Here the content are protected because the model contains abstracted timing information, without any netlist information.

ETM model Illustration:

Types Of ETMs:

There are 2 types of ETM avaliable-

NetList
Liberty library cell (.lib)

Note: Most frequent usages is the .lib cells.

Developing of ETM Models:

Developing an ETM model in Primetime consists of three high level steps:

Preparing for the ETM
Creation of the ETM
Verification of the ETM

ETM scripts example:

As such the flow of the script vary from design to design and company to company, but following example just give a rough idea about the commands for generating the ETM. I will suggest you to check the PrimeTime user-guide for more details.

ETM creation :

############################################

# Template for ETM extract when using spef #
############################################
 
set BLOCK "blockname"
set NETLIST "blockname.v"
set SPEF "blockname.spef"
set SDC "blockname.sdc"
 
# Preserve unconnected nets
set svr_keep_unconnected_nets true
 
# set search_path and link_library
 
# Read and link netlist
read_verilog $NETLIST
current_design ${BLOCK}
link
#  for nets not annotated
set_wire_load_model -name B0.1X0.1
# Read spef
read_parasitics $SPEF
# Read constraints
read_sdc $SDC
set_propagated_clock [all_clocks]
 
 
# Define operating conditions
set_operating_conditions -library g65xp lsiW_090V_125C \
  -analysis_type on_chip_variation 
 
# Set extract_model variables
# Note: These should be considered example settings. Final variable
# settings ultimately depend on the specific design usage.
set extract_model_data_transition_limit 0.75
set extract_model_clock_transition_limit 0.75
set extract_model_capacitance_limit 1.0
set extract_model_num_clock_transition_points 7
set extract_model_num_data_transition_points 7
set extract_model_num_capacitance_points 7
set extract_model_use_conservative_current_slew true
set extract_model_enable_report_delay_calculation true
 
# to create an ETM model with propagated clocks:
set extract_model_with_clock_latency_arcs true
extract_model -output ${BLOCK} -format {db lib} \
 -library_cell -test_design
 
quit

############################################

ETM verification:

############################################
# Template for ETM verification            #
############################################
 
set BLOCK "blockname"
set NETLIST "blockname.v"
set SDC "blockname.sdc"
set ETM_MODEL "${BLOCK}_lib.db"
set ETM_TEST  "${BLOCK}_test.db"
set ETM_CONST "${BLOCK}_constr.pt"
 
# Compute the interface timing of the netlist.
 
# Read in reference netlist design
read_verilog $NETLIST
current_design ${BLOCK}
link
set_wire_load_model -name B0.1X0.1
read_parasitics $SPEF
read_sdc ${SDC}
set_propagated_clock [all_clocks]
set_operating_conditions -library g65xp lsiW_090V_125C \
  -analysis_type on_chip_variation
write_interface_timing netlist_report.txt
 
 
# Compute the interface timing of the ETM model.
 
# Remove reference netlist and read in ETM model
remove_design -all
lappend link_path ${ETM_MODEL}
read_db ${ETM_TEST}
current_design ${BLOCK}_test
link
# set wire_load that has 0.0 cap loading
set_wire_load_model -name TSMC_CLN90G_WLM_0.0
## alternatively, use
#set_load -wire_load 0 *
read_sdc ${SDC}
set_propagated_clock [all_clocks]
source ${ETM_CONST}
write_interface_timing model_report.txt
 
# Compare the interface timing for the netlist vs ETM model.
 
compare_interface_timing -absolute_tolerance 0.1 \
 netlist_report.txt model_report.txt -output cmp.rpt
 
quit

#######################################################

Synopsys Design Constraints (SDC) Basics

Full form of SDC: - Synopsys Design Constraints.

What is SDC: - SDC is a format used to specify the design intent, including the timing, power and area constraints for a design. SDC is tcl based.

Tool used this format: - DC (Design compiler, ICC (IC compiler), Prime Time (PT).

Information In the SDC: - There are mainly 4 type of the information.

1. The SDC version (optional)

2. The SDC units (optional)

3. The Design Constraints

4. Comments (Optional)

1. SDC version:

Variable name: sdc_version

E.g:- set sdc_version

Default Version: 1.9

2. SDC units:

Command name: set_units

Description: using above command you can specify the units for capacitance, resistance, time, voltage, current, and power

E.g:

set_units -capacitance cap_unit -resistance res_unit \

-time time_unit -voltage voltage_unit \

-current current_unit -power power_unit

3. Design Constraints:

You can specify design constraints using Synopsys constraints commands.

Type of information	Commands
Operating conditions	set_operating_conditions
Wire load models	set_wire_load_min_block_size set_wire_load_mode set_wire_load_model set_wire_load_selection_group
System interface	set_drive set_driving_cell set_fanout_load set_input_transition set_load set_port_fanout_number
Design rule constraints	set_max_capacitance set_max_fanout set_max_transition set_min_capacitance
Timing constraints	create_clock create_generated_clock group_path set_clock_gating_check set_clock_groups set_clock_latency set_clock_sense set_clock_transition set_clock_uncertainty set_data_check set_disable_timing set_ideal_latency set_ideal_network set_ideal_transition set_input_delay set_max_time_borrow set_output_delay set_propagated_clock set_resistance set_timing_derate
Timing exceptions	set_false_path set_max_delay set_min_delay set_multicycle_path
Area constraints	set_max_area
Multivoltage and power optimization constraints	create_voltage_area set_level_shifter_strategy set_level_shifter_threshold set_max_dynamic_power set_max_leakage_power
Logic assignments	set_case_analysis set_logic_dc set_logic_one set_logic_zero

Most of the constraint commands require a design object as a command argument.

Design Objects:

Design object	Access command	Description
design	current_design	A container for cells. A block.
clock1	get_clocks all_clocks	A clock in a design. All clocks in a design.
port	get_ports all_inputs all_outputs	An entry point to or exit point from a design. All entry points to a design. All exit points from a design.
cell	get_cells.	An instance of a design or library cell
pin	get_pins	An instance of a design port or library cell pin.
net	get_nets	A connection between cell pins and design ports
library	get_libs	A container for library cells
lib_cell	get_lib_cells	A primitive logic element.
lib_pin	get_lib_pins	An entry point to or exit point from a lib_cell.
register	all_registers	A sequential logic cell.

4. Comments:

You can add comments to an SDC file either as complete lines or as fragments after a command. To identify a line as a comment, start the line with a pound sign (#).

E.g : # This is an SDC comment line.

To add a comment after a command, end the command using a semicolon, then precede the comment with a pound sign (#).

E.g: create_clock -period 10 [get_ports CLK]; # comment fragment

How to generate The SDC file Automatically:

Using Synopsys Tool like DC, ICC or PrimeTime you can generate the SDC. There may be slight variation between the generated SDC across the different tool.

Command for generation: - write_sdc

Validation of manually generated SDC files:-

Command file: read_sdc -syntax_only

Clock Reconvergence Pessimism (CRP) basic

2011-08-21T08:21:00.000-07:00

Clock Reconvergence Pessimism (CRP) basic

Clock Reconvergence Pessimism

Schematic of a reconvergent clock

Basic of Timing analysis

2011-08-21T07:48:00.001-07:00

Static Timing Analysis
Dynamic Timing Analysis.

Note: There is one more type of Timing analysis: "Manual Analysis". But now a days nothing is 100% Manual. Evey thing is more automated and less manual. So that we are not discussing right now.

In this Blog (and few next as a part of this) we will discuss about the Static Timing Analysis. We will discuss Dynamic Timing Analysis later on.

Static Timing analysis is divided into several parts:

Part1 -> Timing Paths
Part2 -> Time Borrowing
Part3a -> Basic Concept Of Setup and Hold
Part3b -> Basic Concept of Setup and Hold Violation
Part3c -> Practical Examples for Setup and Hold Time / Violation
Part4 -> Delay

Note: Part 4, 5 and 6 are still under development.

Static Timing Analysis:

Static timing analysis is a method of validating the timing performance of a design by checking all possible paths for timing violations under worst-case conditions. It considers the worst possible delay through each logic element, but not the logical operation of the circuit.

In comparison to circuit simulation, static timing analysis is

Faster - It is faster because it does not need to simulate multiple test vectors.
More Thorough - It is more thorough because it checks the worst-case timing for all possible logic conditions, not just those sensitized by a particular set of test vectors.

Once again Note this thing : Static timing analysis checks the design only for proper timing, not for correct logical functionality.

Static timing analysis seeks to answer the question, “Will the correct data be present at the data input of each synchronous device when the clock edge arrives, under all possible conditions?”

In static timing analysis, the word static alludes to the fact that this timing analysis is carried out in an input-independent manner. It locates the worst-case delay of the circuit over all possible input combinations. There are huge numbers of logic paths inside a chip of complex design. The advantage of STA is that it performs timing analysis on all possible paths (whether they are real or potential false paths).
However, it is worth noting that STA is not suitable for all design styles. It has proven efficient only for fully synchronous designs. Since the majority of chip design is synchronous, it has become a mainstay of chip design over the last few decades.

The Way STA is performed on a given Circuit:
To check a design for violations or say to perform STA there are 3 main steps:

Design is broken down into sets of timing paths,
Calculates the signal propagation delay along each path
And checks for violations of timing constraints inside the design and at the input/output interface.

The STA tool analyzes ALL paths from each and every startpoint to each and every endpoint and compares it against the constraint that (should) exist for that path. All paths should be constrained, most paths are constrained by the definition of the period of the clock, and the timing characteristics of the primary inputs and outputs of the circuit.

Before we start all this we should know few key concepts in STA method: timing path, arrive time, required time, slack and critical path.
Let's Talk about these one by one in detail. In this Blog we will mainly Focus over Different Types of Timing Paths.

Timing Paths:

Timing paths can be divided as per the type of signals (e.g clock signal, data signal etc).

Types of Paths for Timing analysis:

Data Path
Clock Path
Clock Gating Path
Asynchronous Path

Each Timing path has a "Start Point" and an "End Point". Definition of Start Point and End Point vary as per the type of the timing path. E.g for the Data path- The startpoint is a place in the design where data is launched by a clock edge. The data is propagated through combinational logic in the path and then captured at the endpoint by another clock edge.

Start Point and End Point are different for each type of paths. It's very important to understand this clearly to understand and analysing the Timing analysis report and fixing the timing violation.

Data path

Start Point

Input port of the design (because the input data can be launched from some external source).
Clock pin of the flip-flop/latch/memory (sequential cell)

End Point

Data input pin of the flip-flop/latch/memory (sequential cell)
Output port of the design (because the output data can be captured by some external sink)

Clock Path

Start Point

Clock input port

End Point

Clock pin of the flip-flop/latch/memory (sequential cell)

Clock Gating Path

Start Point

Input port of the design

End Point

Input port of clock-gating element.

Asynchronous path

Start Point

Input Port of the design

End Point

Set/Reset/Clear pin of the flip-flop/latch/memory (sequential cell)

Data Paths:

If we use all the combination of 2 types of Starting Point and 2 types of End Point, we can say that there are 4 types of Timing Paths on the basis of Start and End point.

Input pin/port to Register(flip-flop).
Input pin/port to Output pin/port.
Register (flip-flop) to Register (flip-flop)
Register (flip-flop) to Output pin/port

Please see the following fig:

Timing Path- 4 types of Data Path

PATH1- starts at an input port and ends at the data input of a sequential element. (Input port to Register)
PATH2- starts at the clock pin of a sequential element and ends at the data input of a sequential element. (Register to Register)
PATH3- starts at the clock pin of a sequential element and ends at an output port.(Register to Output port).
PATH4- starts at an input port and ends at an output port. (Input port to Output port)

Clock Path:

Please check the following figure

Timing Paths- Clock Paths

In the above fig its very clear that for clock path the starts from the input port/pin of the design which is specific for the Clock input and the end point is the clock pin of a sequential element. In between the Start point and the end point there may be lots of Buffers/Inverters/clock divider.

Clock Gating Path:

Clock path may be passed trough a “gated element” to achieve additional advantages. In this case, characteristics and definitions of the clock change accordingly. We call this type of clock path as “gated clock path”.

As in the following fig you can see that

Timing Path- Clock Gating path.

LD pin is not a part of any clock but it is using for gating the original CLK signal. Such type of paths are neither a part of Clock path nor of Data Path because as per the Start Point and End Point definition of these paths, its different. So such type of paths are part of Clock gating path.

Asynchronous path:

A path from an input port to an asynchronous set or clear pin of a sequential element.

See the following fig for understanding clearly.

Timing Path- Asynchronous Path

As you know that the functionality of set/reset pin is independent from the clock edge. Its level triggered pins and can start functioning at any time of data. So in other way we can say that this path is not in synchronous with the rest of the circuit and that's the reason we are saying such type of path an Asynchronous path.

Other types of Paths:

There are few more types of path which we usually use during timing analysis reports. Those are subset of above mention paths with some specific characteristics. Since we are discussing about the timing paths, so it will be good if we will discuss those here also.

Few names are

Critical path
False Path
Multi-cycle path
Single Cycle path
Launch Path
Capture Path
Longest Path ( also know as Worst Path , Late Path , Max Path , Maximum Delay Path )
Shortest Path ( Also Know as Best Path , Early Path , Min Path, Minimum Delay Path)

Critical Path:

In short, I can say that the path which creates Longest delay is the critical path.

Critical paths are timing-sensitive functional paths. because of the timing of these paths is critical, no additional gates are allowed to be added to the path, to prevent increasing the delay of the critical path.
Timing critical path are those path that do not meet your timing. What normally happens is that after synthesis the tool will give you a number of path which have a negative slag. The first thing you would do is to make sure those path are not false or multicycle since it that case you can just ignore them.

Taking a typical example (in a very simpler way), the STA tool will add the delay contributed from all the logic connecting the Q output of one flop to the D input of the next (including the CLK->Q of the first flop), and then compare it against the defined clock period of the CLK pins (assuming both flops are on the same clock, and taking into account the setup time of the second flop and the clock skew). This should be strictly less than the clock period defined for that clock. If the delay is less than the clock period, then the "path meets timing". If it is greater, than the "path fails timing". The "critical path" is the path out of all the possible paths that either exceeds its constraint by the largest amount, or, if all paths pass, then the one that comes closest to failing.

False Path:

Physically exist in the design but those are logically/functionally incorrect path. Means no data is transferred from Start Point to End Point. There may be several reasons of such path present in the design.
Some time we have to explicitly define/create few false path with in the design. E.g for setting a relationship between 2 Asynchronous Clocks.
The goal in static timing analysis is to do timing analysis on all “true” timing paths, these paths are excluded from timing analysis.
Since false path are not exercised during normal circuit operation, they typically don't meet timing specification,considering false path during timing closure can result into timing violations and the procedure to fix would introduce unnecessary complexities in the design.
There may be few paths in your design which are not critical for timing or masking other paths which are important for timing optimization, or never occur with in normal situation. In such case , to increase the run time and improving the timing result , sometime we have to declare such path as a False path , so that Timing analysis tool ignore these paths and so the proper analysis with respect to other paths. Or During optimization don't concentrate over such paths. One example of this. e.g A path between two multiplexed blocks that are never enabled at the same time. You can see the following picture for this.

False Path

Here you can see that False path 1 and False Path 2 can not occur at the same time but during optimization it can effect the timing of another path. So in such scenario, we have to define one of the path as false path.

Same thing I can explain in another way (Note- Took snapshot from one of the forum). As we know that, not all paths that exist in a circuit are "real" timing paths. For example, let us assume that one of the primary inputs to the chip is a configuration input; on the board it must be tied either to VCC or to GND. Since this pin can never change, there are never any timing events on that signal. As a result, all STA paths that start at this particular startpoint are false. The STA tool (and the synthesis tool) cannot know that this pin is going to be tied off, so it needs to be told that these STA paths are false, which the designer can do by telling the tool using a "false_path" directive. When told that the paths are false, the STA tool will not analyze it (and hence will not compare it to a constraint, so this path can not fail), nor will a synthesis tool do any optimizations on that particular path to make it faster; synthesis tools try and improve paths until they "meet timing" - since the path is false, the synthesis tool has no work to do on this path.
Thus, a path should be declared false if the designer KNOWS that the path in question is not a real timing path, even though it looks like one to the STA tool. One must be very careful with declaring a path false. If you declare a path false, and there is ANY situation where it is actually a real path, then you have created the potential for a circuit to fail, and for the most part, you will not catch the error until the chip is on a board, and (not) working. Typically, false paths exists

from configuration inputs like the one described above
from "test" inputs; inputs that are only used in the testing of the chip,and are tied off in normal mode (however, there may still be some static timing constraints for the test mode of the chip)
from asynchronous inputs to the chip (and you must have some form of synchronizing circuit on this input) (this is not an exhaustive list, but covers the majority of legitimate false paths).

So we can say that false paths should NOT be derived from running the STA tool (or synthesis tool); they should be known by the designer as part of the definition of the circuit, and constrained accordingly at the time of initial synthesis.

MultiCycle Path:

A multicycle path is a timing path that is designed to take more than one clock cycle for the data to propagate from the startpoint to the endpoint.

A multi-cycle path is a path that is allowed multiple clock cycles for propagation. Again, it is a path that starts at a timing startpoint and ends at a timing endpoint. However, for a multi-cycle path, the normal constraint on this path is overridden to allow for the propagation to take multiple clocks.

In the simplest example, the startpoint and endpoint are flops clocked by the same clock. The normal constraint is therefore applied by the definition of the clock; the sum of all delays from the CLK arrival at the first flop to the arrival at the D of the second clock should take no more than 1 clock period minus the setup time of the second flop and adjusted for clock skew.
By defining the path as a multicycle path you can tell the synthesis or STA tool that the path has N clock cycles to propagate; so the timing check becomes "the propagation must be less than N x clock_period, minus the setup time and clock skew". N can be any number greater than 1.

Few examples are

When you are doing clock crossing from two closely related clocks; ie. from a 30MHz clock to a 60MHz clock,

Assuming the two clocks are from the same clock source (i.e. one is the divided clock of the other), and the two clocks are in phase.
The normal constraint in this case is from the rising edge of the 30MHz clock to the nearest edge of the 60MHz clock, which is 16ns later. However, if you have a signal in the 60MHz domain that indicates the phase of the 30MHz clock, you can design a circuit that allows for the full 33ns for the clock crossing, then the path from flop30 -> to flop60 is a MCP (again with N=2).
The generation of the signal 30MHZ_is_low is not trivial, since it must come from a flop which is clocked by the 60MHz clock, but show the phase of the 30MHz clock.

Another place would be when you have different parts of the design that run at different, but related frequencies. Again, consider a circuit that has some stuff running at 60MHz and some running on a divided clock at 30MHz.

Instead of actually defining 2 clocks, you can use only the faster clock, and have a clock enable that prevents the clocks in the slower domain from updating every other clock,
Then all the paths from the "30MHz" flops to the "30MHz" flops can be MCP.
This is often done since it is usually a good idea to keep the number of different clock domains to a minimum.

Single Cycle Path:

A Single-cycle path is a timing path that is designed to take only one clock cycle for the data to propagate from the startpoint to the endpoint.

Launch Path and Capture Path:

Both are inter-related so I am describing both in one place. When a flip flop to filp-flop path such as UFF1 to UFF3 is considered, one of the flip-flop launches the data and other captures the data. So here UFF1 is referred to "launch Flip-flop" and UFF3 referred to "capture flip-flop".

These Launch and Capture terminology are always referred to a flip-flop to flip-flop path. Means for this particular path (UFF1->UFF3), UFF1 is launch flip-flop and UFF3 is capture flip-flop. Now if there is any other path starting from UFF3 and ends to some other flip-flop (lets assume UFF4), then for that path UFF3 become launch flip-flop and UFF4 be as capture flip-flop.

The Name "Launch path" referred to a part of clock path. Launch path is launch clock path which is responsible for launching the data at launch flip flop.
And Similarly Capture path is also a part of clock path. Capture path is capture clock path which is responsible for capturing the data at capture flip flop.
This is can be clearly understood by following fig.

Launch Clock Path (Launch Path) and Capture Clock Path (Capture path)

Here UFF0 is referred to launch flip-flop and UFF1 as capture flip-flop for "Data path" between UFF0 to UFF1.So Start point for this data path is UFF0/CK and end point is UFF1/D.

One thing I want to add here (which I will describe later in my next blog- but its easy to understand here)-

Launch path and data path together constitute arrival time of data at the input of capture flip-flop.
Capture clock period and its path delay together constitute required time of data at the input of capture register.

Note: Its very clear that capture and launch paths are correspond to Data path. Means same clock path can be a launch path for one data path and be a capture path for another datapath. Its will be clear by the following fig (source of Fig is From Synopsys).

Same clock path behave like Capture and Launch path for different Data path.

Here you can see that for Data path1 the clock path through BUF cell is a capture path but for Data path2 its a Launch Path.

Longest and Shortest Path:

Between any 2 points, there can be many paths.
Longest path is the one that takes longest time, this is also called worst path or late path or a max path.
The shortest path is the one that takes the shortest time; this is also called the best path or early path or a min path.

In the above fig, The longest path between the 2 flip-flop is through the cells UBUF1,UNOR2 and UNAND3. The shortest path between the 2 flip-flops is through the cell UNAND3.

I have tried my best to capture all the important points related to the Timing Paths. Please Let me know If anything is missing here.

"Examples Of Setup and Hold time" : Static Timing Analysis (STA) basic (Part 3c)

2011-08-21T07:39:00.003-07:00

Static Timing analysis is divided into several parts:

Part1 -> Timing Paths
Part2 -> Time Borrowing
Part3a -> Basic Concept Of Setup and Hold
Part3b -> Basic Concept of Setup and Hold Violation
Part3c -> Practical Examples for Setup and Hold Time / Violation
Part4 -> Delay

Note: Part 4, 5 and 6 are still under development.

Till now we have discussed a lot of theory about setup and hold time (with and without Example). Now it’s time to discuss the practical implementation of that. Means in a circuit

How will you calculate the setup and hold values?
How will you analyse setup and hold violation in a circuit?
If you have to improve timing of a circuit then what can you do?

There are few formulas to calculate different parameter ( Theory of those I already explained in my previous blogs). I am not going to explain those right now. First we will solve few examples which will give you an basic idea about these formulas, then in the last I will summarize all those in one place.

I saw a lot of confusion with respect to setup and hold timing calculation. Actually there are two things.

Timing Specification of a Block/Circuit/Library:

You have a block with input A and output Y. Some combinational logic is there between A and Y. Now you have to calculate following parameters for that block

Setup Time Value at input A
Hold Time value at input A.
Maximum operating Clock Frequency or Time Period for that block.
Clock To Y delay value
Input A to Output Y delay value.

Timing Violation of a circuit:

You have to operate a circuit at a particular clock frequency and now you have to find out whether this circuit has any setup or Hold Violation.

So in second case all the parameters are given and you have to find out whether this circuit has any violation or not and In first case you have to find out all the parameters keeping in mind that there should not be any violation.

Lets Discuss in the reverse order.

**********************************************************************************

Problem1: In the following Circuit, Find out whether there is any Setup Or Hold Violation?

Solution:

Hold Analysis:

When a hold check is performed, we have to consider two things-

Minimum Delay along the data path.
Maximum Delay along the clock path.

If the difference between the data path and the clock path is negative, then a timing violation has occurred. ( Note: there are few Exceptions for this- We will discuss that some other time)

Data path is: CLK->FF1/CLK ->FF1/Q ->Inverter ->FF2/D

Delay in Data path

= min(wire delay to the clock input of FF1) + min(Clk-to-Q delay of FF1) +min(cell delay of inverter) + min(2 wire delay- "Qof FF1-to-inverter" and "inverter-to-D of FF2")

=Td = 1+9+6+(1+1)=18ns

Clock path is: CLK-> buffer -> FF2/CLK

Clock path Delay

= max(wire delay from CLK to Buffer input) + max(cell delay of Buffer) + max(wire delay from Buffer output to FF2/CLK pin) + (hold time of FF2)

=Tclk = 3+9+3+2 = 17 ns

Hold Slack = Td - Tclk = 18ns -17ns = 1ns

Since Hold Slack is positive-> No hold Violation.

Note: If the hold time had been 4 ns instead of 2 ns, then there would have been a hold violation.

Td=18ns and Tclk = 3+9+3+4=19ns

So Hold Slack=Td - Tclk = 18ns - 19ns = -1ns (Violation)

Setup Analysis:

When a setup check is performed, we have to consider two things-

Maximum Delay along the data path.
Minimum Delay along the clock path.

If the difference between the clock path and the data path is negative, then a timing violation has occurred. ( Note: there are few Exceptions for this- We will discuss that some other time)

Data path is: CLK->FF1/CLK ->FF1/Q ->Inverter ->FF2/D

Delay in Data path

= max(wire delay to the clock input of FF1) + max(Clk-to-Q delay of FF1) +max(cell delay of inverter) + max(2 wire delay- "Qof FF1-to-inverter" and "inverter-to-D of FF2")

=Td = 2+11+9+(2+2) = 26ns

Note: The first part of the clock path delay (during setup calculation) is the clock period, which has been set to 15 ns. Hope You remember in last blog, I have mentioned very clearly that Setup is checked at the next clock cycle. That's the reason for clock path delay we have to include clock period also.

Clock path is: CLK-> buffer -> FF2/CLK

Clock path Delay

= (Clock period) + min(wire delay from CLK to Buffer input) + min(cell delay of Buffer) + min(wire delay from Buffer output to FF2/CLK pin) - (Setup time of FF2)

=Tclk = 15+2+5+2-4=20ns

Setup Slack = Tclk - Td = 20ns - 26ns = -6ns.

Since Setup Slack is negative -> Setup violation.

Note: A bigger clock period or a less maximum delay of the inverter solve this setup violations in the circuit.

E.g

If Clock period is 22ns then

Tclk = 22+2+5+2-4=31-4=27ns AND Td = 26ns

Setup Slack = Tclk - Td = 27-26=1ns (No Violation)

**********************************************************************************

Problem2: In order to work correctly, what should be the Setup and Hold time at Input A in the following Circuit. Also find out the maximum operating frequency for this circuit. (Note: Ignore Wire delay). Where Tsu- Setup time; Thd-Hold Time; Tc2q- Clock-to-Q delay

Solution:

Step1: Find out the maximum Register to register Delay.

Max Register to Register Delay

= (clk-to-Q delay of U2) + (cell delay of U3) + (all wire delay) + (setup time of U1)

= 5 + 8 + 3 = 16 ns.

Note:

There are 2 register to register paths

U2 -> U3 ->U1 (Delay=5+8+3=16ns)
U1 -> U4 -> U2 ( Delay=5+7+3=15ns)

We have to pick maximum one.

Step2: Find Out Setup Time:

A setup time = Setup time of Flipflop + Max (Data path Delay) - min(Clock path Delay)

= (Setup time of Flipflop + A2D max delay) - (Clk path min delay)

= Tsu + (Tpd U7 + Tpd U3 + wire delay) - Tpd U8

= 3 + (1+8 ) - 2 = 10 ns

Note:

Here we are not using the Clock period. Because we are not suppose to calculate the Setup violation. We are calculating Setup time. Please refer the part3a for the referance.
All the wire dealy is neglected. If Wire delay present, we have to consider those one.
There are 2 Data path

A -> U7 -> U4 -> D of U2 (Data path Delay = 1+7 =8ns )
A -> U7 -> U3 -> D of U1 ( Data path Delay = 1+8 =9ns )

Since for Setup calculation we need maximum Data path delay, we have choosen 2nd for our calculation.

Step3: Find Out Hold Time:

A hold time = Hold time of Flipflop + max(Clock path Delay) - min( Data path delay)

=( Hold time of Flipflop + Clk path max delay) - (A2D max delay)

= Thd + Tpd U8 - (Tpd U7 + Tpd U4+wire delay)

= 4 + 2 - (1+7 ) = -2 ns

Note: Same explanation as for Setup time. For hold time we need minimum data path , so we have picked first Data path.

Step4: Find out Clock to Out Time:

Clock to Out

= Cell delay of U8 + Clk-to-Q delay of FlipFlop+ Cell delay of U5+ Cell delay of U6+ (all wire delay)

= Tpd U8+ U2 Tc2q + U5 Tpd + U6 Tpd

= 2 + 5 + 9 + 6 = 22 ns

Note:

There are 2 Clock to Out path- one from Flip flop U1 and other from U2.
Since in this case the Clk-to-Q path for both Flipflop is same, we can consider any path. But in some other Circuit where the delay is different for both the paths, we should consider Max delay path.

Step5: Find Pin to Pine Combinational Delay (A to Y delay)

Pin to Pin Combinational Delay (A to Y)

= U7 Tpd + U5 Tpd + U6 Tpd

= 1 + 9 + 6 = 16 ns

Step5: Find Out Max Clock Frequency:

Max Clock Freq = 1/ Max (Reg2reg, Clk2Out, Pin2Pin)

= 1/ Max (16, 22, 16)

= 45.5 Mhz

So summery is:

Parameter	Description	Min	Max	Units
Tclk	Clock Period	22		ns
Fclk	Clock Frequency		45.5	Mhz
Atsu	A setup time	10		ns
Athd	A hold time	-2		ns
A2Y	A to Y Tpd		16	ns
Ck2Y	Clock to Y tpd		22	ns

Note: Negative hold times are typically specified as 0 ns.

**********************************************************************************

Problem3: In the above Circuit, Try to improve the timing by adding any "buffer" or "Register".

Solution:

Best way of doing this is “Register all Input and Output”. We are adding DFF so same specification (as U2 and U1).

Now follow all those 5 Steps onn by one.

Step1:

Max Register to Register Delay

U2 Tc2q + U5 Tpd + U9 Tsu = 5 + 9 + 3 = 17 ns

Note:

A lot of Register to Register path

U8 -> U5 -> U9 (Delay = 5+9+3=17ns)
U8 -> U4 -> U2 (Delay = 5+7+3=15ns)
U8 -> U3 -> U1 (Delay = 5+8+3=16ns)
U1 -> U4 -> U2 (Delay= 5+7+3=15ns)
U1 -> U5 -> U9 (Delay= 5+9+3=17ns)
U2 -> U5 -> U9 (Delay = 5+9+3=17ns)
U2 -> U3 -> U1 (Delay = 5+8+3=16ns)

Maximum delay is 17ns, Just picked anyone.

Step2:

A setup time = Tsu + A2D Tpd max - Clk Tpd min

= Tsu + (Tpd U7) - Tpd U8

= 3 + (1) - 2 = 2 ns

Note: Only One path between A and D of FF(i.e U8)

Step3:

A hold time = Thd + Clk Tpd max - A2D Tpd min

= Thd + Tpd U8 - (Tpd U7)

= 4 + 2 - ( 1) = 5 ns

Note: Only One path between A and D of FF(i.e U8)

Step4:

Clock to out:

=Tpd U8+ U9 Tc2q + U6 Tpd

=2+5+6 = 13 ns

Step5:

No direct link between A and Y. So Not Applicable.

Step6:

Max Clock Freq = 1/ Max (Reg2reg, Clk2Out, Pin2Pin)

= 1/ Max (17, 13)

=58.8 Mhz

Parameter	Description	Min	Max	Units
Tclk	Clock Period	17		ns
Fclk	Clock Frequency		58.8	Mhz
Atsu	A setup time	2		ns
Athd	A hold time	5		ns

Ck2Y	Clock to Y tpd		13	ns

**********************************************************************************

**********************************************************************************

I hope This much will help you. Now its the time to summarize all the important things and formulas.

Points to remember:

Setup is checked at next clock edge.
Hold is checked at same clock edge.
For Hold Check ( Checking of hold Violation)

Minimum Delay along the data path.
Maximum Delay along the clock path.

For SetUp Check ( Checking of Setup Violation)

Maximum Delay along the data path.
Minimum Delay along the clock path.

Basic 2 FlipFlop circuit.

Calculation of Setup Violation Check: Consider above circuit of 2 FF connected to each other.

Setup Slack = Required time - Arrival time (since we want data to arrive before it is required)

Where:

Arrival time (max) = clock delay FF1 (max) +clock-to-Q delay FF1 (max) + comb. Delay( max)

Required time = clock adjust + clock delay FF2 (min) - set up time FF2

Clock adjust = clock period (since setup is analyzed at next edge)

Calculation of Hold Violation Check: Consider above circuit of 2 FF connected to each other.

Hold Slack = Arrival Time - Required time (since we want data to arrive after it is required)

Where:

Arrival time (min) = clock delay FF1 (min) +clock-to-Q delay FF1 (min) + comb. Delay( min)

Required time = clock adjust + clock delay FF2 (max) + hold time FF2

Clock adjust = 0 (since hold is analyzed at same edge)

Calculation of Maximum Clock Frequency:

Max Clock Freq = 1/ Max (Reg2reg delay, Clk2Out delay, Pin2Pin delay)

Where:
         Reg2Reg Delay = Clk-to-Q delay of first FF (max) + conb delay (max) + setup time of 2nd FF.
         Clk2Out Delay = Clock delay w.r.t FF (max) + clock-to-Q delay of FF1 (max) + comb. delay (max)
         Pin2Pin delay = Comb delay between input pin to output pin (max)

Multi Voltage Designs: Power Planning Issues

2011-08-19T04:22:00.003-07:00

Efficient power planning is one of the key concerns of modern SoC
designs. In multi voltage designs providing power to the different
power domains is challenging. Every power domain requires independent
local power supply and grid structure and some designs may even have a
separate power pad. Separate power pad is possible in flip-chip
designs and power pad can be taken out near from the power domain.
Other chips have to take out the power pads from the periphery which
can put limit to the number of power domains.
Local on chip voltage regulation is good idea to provide multiple
voltages to different circuits. Unfortunately most of the digital CMOS
technologies are not suitable for the implementation of either
switched mode of operation or linear voltage regulations.

Separate power rail structure is required for each power domain. These
additional power rails introduce different levels of IR drop putting
limit to the achievable power efficiency.

Related Articles
Multiple Voltage ASIC/SoC Designs: Classification

Multiple Voltage Design Challenges
Multiple Voltage Designs: Timing Issues

Fixing Transition Violation

2011-08-19T03:47:00.001-07:00

Transition violations can be fixed by different methods based on the design situations.

They include:

Up sizing the driver cell
Decreasing the net length by moving cells nearer or reducing long routed net
By adding buffers
By using existing spare cells as buffers
By splitting loads through buffers to reduce the fan out number (number of driven cells)

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2011-08-18T06:00:00.001-07:00