Each year, around this time, the electronic design industry and academia meticulously prepare to showcase the latest research and technologies at the Design Automation Conference. For the casual attendee, after a few years the difference between the conferences of years past begins to dim. If you are one of them, allow me to dispel this notion and invite you to look at what is different this year.

For starters, we will be in the beautiful city of San Francisco from July 26-31. The DAC 2009 program, as in previous years, has been thoughtfully composed from using two approaches. The bottom up approach selects technical papers from a pool of submissions using a rigorous review process. This ensures that only the best technical submissions are accepted. For 2009, we see an increasing focus on research towards system level design, low power design and analysis, and physical design and manufacturability. This year, a special emphasis for the design community has been added to the program, with a User Track that runs throughout the conference. The new track, which focuses on the use of EDA tools, attracted 117 submissions reviewed by a committee made up of experienced tool users from the industry. The User Track features front end and back end sessions and a poster session that allows a perfect opportunity to interact with presenters and other DAC attendees. In addition to the traditional EDA professionals, we invite all practitioners in the design community – design tool users, hardware and software designers, application engineers, consultants, and flow/methodology developers, to come join us.

This first approach is complemented by a careful top-down selection of themes and topics in the form of panels, special sessions, keynote sessions, and management day events. The popular CEO panel returns to DAC this year as a keynote panel. The captains of the EDA industry, Aart deGeus (Synopsys), Lip-Bu Tan (Cadence) and Walden Rhines (Mentor) will explore what the future holds for EDA. The keynote on Tuesday by Fu-Chieh Hsu (TSMC), will discuss alignment of business and technology models to overcome design complexity. William Dally (Nvidia and Stanford) will present the challenges and opportunities that throughput computing provides to the EDA world in his keynote on Wednesday. Eight panels on relevant areas are spread across the conference. One panel explores whether the emphasis on Design for Manufacturing is a differentiator or a distraction. Other panels focus on a variety of themes such as confronting hardware-dependent software design, analog and mixed signal verification challenges, and various system prototyping approaches. The financial viability of Moore’s law is explored in a panel, while another panel explores the role of statistical analysis in several fields, including EDA. Lastly, we have a panel exploring the implications of recent changes in the EDA industry from an engineer’s perspective.

Special technical sessions will deal with a wide variety of themes such as preparing for design at 22nm, designing circuits in the face of uncertainty, verification of large systems on chip, bug-tracking in complex designs, novel computation models and multi-core computing. Leading researchers and industry experts will present their views on each of these topics.

Management day includes topics that tackle challenges and decision making in a complex technology and business environment. The current “green” trend is reflected in a slate of events during the afternoon of Thursday July 30th. We start with a special plenary that explores green technology and its impact on system design, public policy and our industry. A special panel investigates the system level power design challenge and finally a special session considers technologies for data centers.

Rather than considering it a hindrance to attendance, the prolonged economic malaise this year should provide a fundamental reason to participate at DAC. As a participant in the technical program, DAC offers an opportunity to share your research and win peer acclaim. As an exhibitor, it is an ideal environment to demonstrate your technology and advance your business agenda. As an attendee, you cannot afford to miss the event where “electronic design meets”. DAC provides an unparalleled chance to network and learn about advances in electronic design for everyone. Won’t you join us at the Moscone Center at the end of the month?

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This year’s DAC will be held July 26-31 at the Moscone Center in San Francisco. Register today at www.dac.com. Note also that there are 600 free DAC passes being offered courtesy of the DAC Fan Club (Atrenta, Denali, Springsoft) for those who have no other means to attend.

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Several years ago, I was driving home from a family vacation when I accidentally speed dialed my boss on the cell phone. His voice mail picked up just as I was singing in the car to my daughter. I had no idea what had occurred until a month later at a staff meeting when he got up in from of my team and my colleagues and played this audio track.

Now you know why I am not trying to become the next EDA Idol at this year’s Design Automation Conference!

Fortunately, there is another tongue-in-cheek contest that I am honored to be part of, EDA’s Next Top Blogger.

In case you can’t make DAC this year, I’d like to introduce you to the fellow nominees because they are all great writers and experts in their domains. I encourage you to read these blogs and subscribe to the ones that you find valuable. And look beyond this list because there are many more out there.

Colin Warwick is a Product Marketing Manager at Agilent EEsof EDA group. Colin’s Signal Integrity blog is about signal integrity tips, tricks, and tutorial for multigigabit/s chip-to-chip data links. It includes videos (technical and humorous), tutorial articles, interactive calculators and polls, reviews, and product and event information.

John Busco is a Design Implementation Manager at NVidia. Blogging since 2005, John’s Semi-Blog shares high quality news and opinion about semiconductors and EDA. John is hands-on working in the trenches on the bleeding edge designs, so you can trust what he tells you.

Paul McLellan  has been an executive in EDA and Semiconductors with companies like VLSI Technologies, Compass, Ambit, Cadence,and on and on. His EDA Graffiti blog covers EDA and semiconductor, looking back to some history, analyzing the industry and looking where things are likely to end up. I always walk away from Paul’s blog posts with something to think about.

Daniel Nenni is also an EDA industry veteran with similarly impressive credentials. Although his Silicon Valley Blog is fairly new, Daniel writes like a verteran blogger, sharing his 25+ years of experience in semiconductor design and manufacture in an entertaining manner. He manages to share some of his personal life observations as well.

Karen Bartleson is Director of Community Marketing at Synopsys. Since November 2007, she has presented news, insights, and opinions on the topic of EDA standards in her ever popular The Standards Game blog. Karen is also spearheading Synopsys’ Conversation Central at DAC where you can exchange ideas with many of these same top bloggers (and many more) about how social media is changing the media landscape.

Frank Schirrmeister is Director of Product Marketing and System-Level Solutions at Synopsys. His A View From The Top blog is dedicated to System-Level Design and Embedded Software and deals with the technology and business aspects to get us to ESL and the next abstraction level eventually!

JL Gray is a hands-on verification consultant at Verilab. In his Cool Verification blog, which set the standard for independent blogging in EDA, JL shares this thoughts on hardware verification, the EDA industry, and related topics. JL spearheaded the EDA Blogger Birds-of-a-Feather session at DAC last year and sits on the ever popular Accellera Verification IP Technical Subcommittee.

I have 2 favors to ask. First, please check out some these wonderful bloggers (and some of the others you can find on David Lin’s EDA Blog Roll) who devote their evenings and weekends writing for free (well, about half of us) to bring you valuable information you can’t get anywhere else. Then, show your support by voting for your favorite blog and telling a friend or a co-worker about all this great content out there. Please vote for whoever you want, but remember, if I lose, I might have to sing next year. And you don’t want that!

(Note: The Denali site requires you to enter a Captcha phrase and also your valid email address in order to ensure that people only vote once. The email address WILL NOT be used for any other purpose, so please do not be dissuaded from voting because of this).

harry the ASIC guy

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An interesting question.

About a week ago, Forbes released a study entitled “The Rise of the Digital C-Suite - How Executives Locate and Filter Business Information” for which they surveyed 354 executives at US companies with annual sales > $1B. The results were both surprising and not surprising.

First, what was not surprising. The younger the executive, the more likely he was to use and count on the internet and social media as a resource for business related research. Whereas 56% of executives under 40 say they use Twitter daily or several times a week, only 17% of those over 50 use Twitter at all. The statistics are similarly skewed towards younger executive as regards usage of blogs, RSS feeds, social networks, and so on.

Also not surprising, the more mature social media technologies had the highest adoption rates. Irregardless of age, almost 100% of executives turn to the internet via search engines to do research before enlisting the help of their staff. The top areas of research are competitor analysis, trend analysis (customer, technology, societal, marketing, political), and corporate developments and news about mergers, acquisitions, and joint ventures. Meanwhile, 95% found links from websites, blogs, and other online content to be valuable and 82% found guidance from contacts in online communities to be valuable.

So, what was surprising? Among executives under 40, 72% maintain a work related blog, with almost two-thirds updating it at least weekly. Twitter and RSS usage was very similar. Who knew that these busy executives could find time to keep up a blog or to “waste time” on Twitter? This trend will only increase as more of Generation Netscape and Generation Youtube find their way into the executive suite.

With similar goals, UberCEO.com scoured the Internet to determine how many of the Fortune 100 CEOs were using Facebook, Twitter, LinkedIn, Wikipedia, or had a blog. In stark contrast to the Forbes study, the results of their research indicated that of the 100 CEOs, only 19 had personal Facebook pages, 2 had Twitter accounts, 13 had LinkedIn accounts, 75 had Wikipedia pages, and none had a blog. What could account for this difference between the two studies?

Some of the difference is due to the demographics of the two studies. Whereas UberCEO considered only Fortune 100 CEOs, Forbes looked at executives of all ranks (only 18% were CEOs) and included much smaller companies with sales > $1B. (In fact, the Fortune 100th company had sales over $20B, 20x the limit for the Forbes survey). There seems to be a greater tendency for lower-level executives and those in smaller companies to use social media. Also, the CEOs in the larger Fortune 100 companies are more likely in that 50+ range which makes them less likely to participate in social media. I also think that the UberCEO survey undercounted since they did not contact anyone directly and missed many who may just listen in on blogs and Twitter and other social media and not yet participate as content producers.

A third more in-depth datapoint was provided by Ron Ploof in his recently released eBook on How Johnson and Johnson (Fortune #47) Does New Media. Despite being in a highly regulated industry where they had every excuse not to risk adopting social media, nonetheless JnJ has been very bold and successful with 2 blogs, a Youtube channel, a Twitter account, and now a Facebook page. Apparently, many of JnJ’s executives have adopted social media.

So, back to my colleague’s original question, “do executives really read blogs,” here’s what I think. Considering that we are in a high-tech industry with technology savvy execs, who tend to be younger than the average, with companies smaller than the typical Fortune 100 … Yes, the executives that you are likely trying to reach probably do read blogs. And maybe even use Twitter (see this list of business leaders and executives on Twitter) and have a Facebook page.

But that’s just me. What do you think? I’d especially be interested to hear from any executives out there as to what tools you use, why you find them useful, and how you use them.

harry the ASIC guy

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Get up.  Wake the kids.

Check email.  Ask the kids to stop jumping on the couch.

Check Twitter. Tell the kids again to stop jumping on the couch.

Check my Google Reader. Glare at the kids with that “I’ve asked you for the last time” look.

You get the idea.

This Wednesday morning, somewhere in between conversations with my kids, walking the dog, and getting ready for work, I came across the following comment on a friend’s blog:

Ron, we are listening.

http://www.mentor.com/blogs

Ron Fuller
Web Manager, Mentor Graphics

For background, Ron Ploof is the guy who got the crazy idea almost 3 years ago that Synopsys should be doing something in this new world called social media. (Actually, I don’t think the term “social media” had even been coined back then). He evangelized this belief to the VP of Marketing at Synopsys and created for himself a job as Synopsys’ “New Media Evangelist” (actual title on his business card). He launched Synopsys’ first foray into social media, including podcasts, videos, and most prominently, blogs.

Synopsys’ success motivated Cadence to follow suit (something confided to me by Cadence’s former community manager). And it seems, according to the comment on Ron’s blog, it also motivated Mentor’s move into social media.

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I wanted to find out more about the Mentor blogs and I was able to set up some time to talk over lunch with Sonia Harrison at Mentor (see her sing at the Denali DAC party) . Sonia had helped me set up my previous interview with Paul Hofstadler and had extended me an invitation to attend the Mentor User2User conference (which, unfortunately, I could not attend). As it turns out, Sonia was the absolutely right person to talk to.

Even though I had only now become aware of Mentor blogs, Mentor had evidently coordinated their launch with the launch of their new website several months ago. Sonia was quite humble, but it seems that she was the driving force behind the blogs and Mentor’s presence in other social media like Twitter. She had been watching what was going on for some time, hesitant to jump in without a good plan, and now was the time.

According to Sonia, Mentor’s motivation for doing the blogs was to extend into a new media their “thought leadership” in the industry, to draw customers in to their website, and to exchange information with customers. Interestingly, Mentor did not hire an outside social media consultant or community manager like Cadence had. Rather, the project was homegrown. Sonia recruited various technical experts and others as bloggers. She developed “common sense” social media guidelines to make sure bloggers were informed of and played by social media rules (e.g. no sensitive or proprietary information, be polite, respect copyrights, give attribution).

According to Sonia, “one of the more difficult things was to get people to commit to blogging regularly. Writing takes time, it’s almost a full time job.” Despite this additional work burden, Mentor has no plans to bring in professional journalists as bloggers like Richard Goering at Cadence. And it doesn’t seem they need to. Simon Favre received a blog of the week award from System Level Design a few weeks ago, so they are doing quite well on their own.

Sonia does not have any specific measurable goals (page views, subscribers, etc.), which I think is a mistake, especially when her upper management comes asking for evidence that these efforts are paying off. My friend Ron likes to tell me that social media is the most measurable media ever and it’s a shame not to use the data.

I started playing with the site later in the afternoon and noticed a few things. First, when I added a comment to one of the blogs without registering, it did not show up right away, nor did I get a message that the comment was being moderated. It did show up later in the day, but it would be nice to at least be told that it was “awaiting moderation”. Still better, why moderate or require registration at all? The likelihood of getting inappropriate comments from engineering professionals is very low, and they can always be removed if need be. Moderation of comments will also kill a hot topic in its tracks. I’ve personally had the experience of publishing a new blog post late at night and waking up to several comments, some addressing other comments. Had I moderated the blog, none of those comments would have even showed up until later in the day.

Second, there was no way to enter a URL or blog address when leaving a comment. It is pretty standard practice to have this feature to allow readers to “check out” the person leaving the comment. Hopefully thay can add this.

On the positive side, the most important feature of a blog is the content and the content looks very good, especially the PCB blogs. Also, there is apparently no internal review or censorship of blog posts, so bloggers have the freedom to write whatever they want, within the social media guidelines of course.

 __________

It’s been almost 3 years since Ron made his first pitch to his manager. Who would have thought that the Big 3 and many others would have adopted social media in such a short time. Meanwhile, my kids are still jumping on the couch.

GTG

harry the ASIC guy

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Observation #1 - FPGA people put their pants on one leg at a time, just like me. (Actually, I sometimes do both legs at the same time, but that’s another story). I had been led to believe that there was some sort of secret cabal of FPGA people that all knew the magic language of FPGAs that nobody else knew. Not the case. Although there is certainly a unique set of terminology and acronyms in the FPGA arena (LUTs, DCM, Block RAM) they are all fairly straightforward once you know them.

Observation #2 - I thought that behavioral synthesis had died, but apparently it was just hibernating. There is behavioral synthesis capability in some of the higher-level FPGA tools. I’ve never used it, so I can’t say one way or the other. But it sure was a blast from the past (circa 2000). Memories of SPW, Behavioral Compiler, Cossap, Monet, Matisse.

Observation #3 - Physical design of FPGAs is getting like ASICs. There are floorplanning tools, tools that back-annotate placement back into synthesis, tools that perform synthesis and placement together, tools for doing pre-route and post-route timing analysis. Made me think of Floorplan Manager, Physical Compiler, and IC Compiler.

Observation #4 - Verification of FPGAs is getting like ASICs. It can take a day to resynthesize and route a large FPGA to get back in the lab debugging. That’s an unacceptable turnaround time for debugging an FPGA with lots of bugs. Assertions (SVA, PSL), high-level verification languages (System-Verilog / OVM / VMM) and cross domain checkers are methods being stolen from the ASIC design world to address large FPGA verification. The trick is deciding when there has been enough simulation to start debug in the lab.

After this session, I think this ASIC guy is going to feel right at home in the FPGA world of the future.

harry the ASIC guy

(Read Part II of this series here)

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__________

Chris Schalick is VP of Engineering, CTO, and Founder of GateRocket, Inc. After working in the ASIC and FPGA industry for more than 15 years, Chris founded the company to solve one of the fundamental problems with FPGA design, the ability to simulate hardware FPGA behavior within the design verification environment. GateRocket partners with the three major Electronic Design Automation (EDA) providers, Mentor Graphics, Cadence, and Synopsys, to be able to “plug-in” their hardware to the software simulation environment.

Alvin Cheung is currently a CAD Manager in the aerospace industry. Previously, Alvin worked at TI, Artisan Components and other companies doing ASIC and library development.

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Alvin: Hi Chris. I want to start off by asking a couple of questions that are not necessarily related to FPGA technology but more towards a start-up company. I see that you founded the company in Oct. 2004. You were working for someone else before you decided to found your company. What made you want to start you own business?

Chris: Well, it is something that I always wanted to do as a kid. I love to build things. In the 15 years that I was an ASIC designer, I saw that when I went from ASIC to FPGA there were a lot of problems with debugging the FPGA. The parts that would work in simulation perfectly ended up not working in the lab at all. A lot of ASIC designers have the same issues going from ASIC to FPGA and there were not any tools out there to address this problem. I thought to myself, “There has to be a better way to do the debugging on the FPGAs.” That’s how I came up with the idea. I tested the idea with a couple of colleagues and founded the company. Our RocketDrive builds on the idea of using a logic analyzer in the lab and puts it at the finger tips of the designers doing functional verification with a simulator. You don’t have to reprogram the FPGA over and over again, troubleshoot, and recode your design.

Alvin: Did you find that you needed to adapt from your engineering skills to marketing or sales skills? Did you find that a challenge and a difficult transition?

Chris: In a small company you have to do a lot of things. In the beginning, I had to do everything from calling the customers, talking to the vendors, talking to partners and talking to investors. You’re right in that most engineers don’t have a lot of skills in those areas. I had to learn a lot by trial and error.

Alvin: Do you see a change in lifestyle since you started the company? Is it worthwhile?

Chris: I worked at several start-ups before starting GateRocket. I’m used to working long hours and with a small group of people. Over time, working focused hours with a small group can be more productive than larger groups with more resources. Our company has had its up and downs; keeping a positive attitude and going back to do the right thing is the most important thing.

Alvin: I see that you’ve secured your funding from venture and angel investors. Was it difficult to secure the Series A funding? Did the VC require you to change your plans? Were there a lot of obstacles?

Chris: Raising money is trial and error. The process is always lengthy but not necessarily an obstacle. There are always people who will say “No” and want you to address “one more” thing, but addressing it does not necessary mean that they’ll invest or that you will succeed. All you really need is the one “Yes” from the right guys and you can’t be concerned about the “No’s”. As far as the obstacles, they always want more data, analysis, financial projections and references. Those things are not unreasonable and you do your best to provide them with the information. When I put my own money on the line, I ask for the same things.

Alvin: How long did it take you to develop the “RocketDrive? Is it your first product?

Chris: Yes, the “RocketDrive” is our first product and our only product. It took me 18 months for the first prototype and since our first prototype we have dramatically enhanced the hardware. It took us 2 ½ years to ship our 1st production unit and we worked closely with our customers and partners to develop the product. We are in our 5th year and shipping units. We are constantly improving the product and continue development of RocketDrive as a platform and new software products that run on it. Stay tuned!

Alvin: What would you say are the top three skills needed to be a successful entrepreneur?

Chris: Hmm… I would say the ability to maintain focus. Things don’t always go the way you want. Many things that you don’t expect to happen will happen. You have to maintain focus and go back and look at problems from another angle. The second would be the ability to stay positive. You just keep your chin up and tell yourself you can do it. The third would be imagination. Sometimes the right answer is not obvious. There’s a saying that, “You have to think outside the box.” You really do to succeed. You need to see things from many different angles and sometimes the right answer is not the obvious one. Our first prototype was nothing like what we currently ship.

Alvin: What is your favorite aspect of being an entrepreneur?

Chris: You know the saying that, “You have to play big to win big.”? Well that’s true. From the creative aspect, I’ve always liked to build things and starting a company provides a unique chance to build things that you might not otherwise be able to. Of course money is also a big factor. Although there’s no guarantee of financial success, it certainly is a motivator. I would say it is the combination of the two.

Alvin: Was there a lot of trial and error with your product? Do you find yourself in situations where there is already a competitor out there that has similar technology? If yes, how did you differentiate them from your product?

Chris: There was a huge amount of trial and error. Success is always a trial. Sometimes the answers are not obvious. You have to be persistent and look outside the box. You keep looking for the solution until your find the answers. Our current model looks nothing like our original prototype on the inside. On the outside with the simulator, it looks the same. But on the inside, everything has changed. We believe we are the first product in the market that does logic simulation directly with the FPGA. So, no, there is no direct competition. There are alternatives to develop FPGAs – build a prototype, program the FPGA, take it to the lab, connect it to the logic analyzer and hope everything works according to what you simulate with your RTL and testbench. What we are doing is changing the design flow and people’s concept of verifying the design. You can debug your design on actual silicon before you take it to the lab.

Alvin: How is your company adjusting to the current economic downturn? Did you have to downsize or change your priorities to adjust?

Chris: The environment looks bad on the surface, but people are still working on FPGAs. Some people have fewer dollars to spend, but we are still getting positive feedback with our product and we are selling more of them. We certainly have lots of activity lately with our product due to the growing size and number of FPGA designs.

Alvin: Actually in the current economic climate, would people choose FPGA over ASIC?

Chris: Yes, you are right. With the cost of the ASIC process, more and more people are looking to see how they can fit their designs in FPGAs instead of ASICs. With FPGAs getting larger and design technology getting smaller, more and more designers are choosing FPGA for their designs.

Alvin: I’m going to ask my last question of the interview and don’t want to take too much of your time. So I’m going to end with asking, what is your next step? Where do you see the company going from here?

Chris: Though our company is still growing, we are looking for ways to become the household name when it comes to FPGA development. We are demo’ing to customers and showing them the actual behavior of the simulator on silicon. We are working to craft the message and to expand our presence in the market. We are developing our online presence. We are going to DVCon, FPGA summit, and DAC, and really our best marketing is from “word of mouth”. We want our customers to be successful and in turn we can become successful.

Alvin: Do you think you would IPO or get the company to be on a merger/acquisition deal anytime soon?

Chris: In this environment, I don’t think it is the right time for an IPO. We are focusing on our customers, enhancing the product and expanding our market presence.

Alvin: Ok. Well, thank you for letting me take a big chunk of your time from your busy schedule. Thank you so much for the interview.

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Or the finale of American Idol in which Kris Allen came back to defeat the heavily favored Adam Lambert. Great show!!!

What did I do last night? I listened to the Q2 2009 Synopsys earnings call. Great conference call!!!

(OK … I’ll admit it wasn’t as exciting and nail biting as either of the other viewing options. Just think of it like this: I took on the work of listening to the call and summarizing it for you, in order to free you up to watch the game or idol. You can thank me later )

Here’s the summary. (You can read the full transcript here if you like).

Financials

On the up side, Synopsys had a good Q2, beating their revenue and earnings per share guidance slightly. On the down side, Synopsys lowered its revenue and cash flow guidance slightly for the rest of the year, allowing for potential customer bankruptcies, late payments, and reduced bookings. Customers are approaching Synopsys to “help them right now through this downturn”, i.e. to reduce their cost of software. It looks like the recession is finally catching up to them.

As I finish off this post on Thursday morning, it looks like the analysts agree. Synopsys shares are down 10%, so it seems they are getting punished for revising their forecast. 

Still, Synopsys is in very good financial health, with $877M in cash and short term investments. Their cash flow is going to go down the rest of the year, so they will eat into this fund, but they will still have plenty to selectively acquire strong technology that might add to their portfolio, as they did with the MIPs Analog Business Group.

Themes

There were 2 themes or phrases that kept recurring in the call that I am sure were points of emphasis for Aart.

First, the word “momentum” was used 6 times (by my count) during the call. Technology momentum. Customer momentum. Momentum in the company. Clearly, Synopsys is trying to portray an image of the company building up steam while the rest of the industry wallows in the recession.

Second, customers are “de-risking their supplier relationships”, i.e. looking to consolidate with an EDA vendor with strong financials who’ll still be there when the recession ends. Again, Synopsys is trying to portray itself as the safe choice for customers, hoping to woo customers away from less financially secure competitors like Cadence and Magma. This ties in with the flurry of “primary EDA vendor” relationships that Synopsys has announced recently.

The opportunity for Synopsys (and danger for the competition) is to pick up market share during this downturn and it looks like that may be happening as companies “de-risk” by going with the company with the “momentum” and a “extraordinarily strong position”. Or at least that’s the message that Synopsys is sending.

Technology

Aart did rattle off the usual laundry list of technology that he wanted to highlight, including some introduced last year (e.g. Z-route). Of note were the following:

• Multi-core technology in VCS with 2x speedup (is 2x a lot?)
• Custom Designer, which Aart called “a viable alternative to the incumbent” (ya know marketing didn’t pick the word “viable”)
• Analog IP via the MIPS Analog Business Group acquisition, especially highlighting how that complements the Custom Designer product (do I see “design kits” in the future?)
• The Lynx Design System (see my 5-part series)
• IC-Validator (smells like DRC fixing in IC Compiler - Webinar today, I’ll find out more)

__________

In summary, Synopsys had a good quarter, but they have finally acknowledged that they are not immune to the downturn and they expect to get impacted the next few quarters.

harry the ASIC guy

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At some point, the discussion got around to Aart DeGeus and his leadership qualities. My friend, who plays bass guitar with Aart on occasion, shared with me his observations of Synopsys’ CEO outside of work. “He’s a born leader, even when he’s playing music,” my friend said as he related one story of how Aart lead the band in an improvisational session with the same infectious enthusiasm he brings to Synopsys. Here’s a look.

While driving back from lunch, I recalled a field conference from the mid 1990s where Aart introduced the notion of “Synopsys 2″. Synopsys 2 was to be a new company (figuratively, not literally) that would obsolete Synopsys 1 and take a new leadership role in a transforming industry. At that time, Synopsys 1 was the original “synthesis company” along with some test and simulation tools. The industry challenge driving Synopsys 2 was the need for increased designer productivity to keep up with chip sizes increasing due to the inexorable and ubiquitous Moore’s Law.

Aart’s vision for this new EDA order was twofold. First, behavioral synthesis would allow designers to design at a higher, more efficient, and more productive level of abstraction, thereby increasing their productivity. In fact, your’s truly helped develop and deliver the very first DAC floor demo of Behavioral Compiler. I also developed a very simple but elegant presentation of the power of behavioral synthesis that was used throughout Synopsys, garnered the praise of Aart himself, and sits in my desk as a memento of my time at Synopsys. Unfortunately, behavioral synthesis never really caught on at the time. Oh well. So much for that.

The second part of Aart’s productivity vision was design reuse. Needless to say, that vision has come true in spades. I don’t have reliable numbers at my finger tips, but I would guess that there is hardly a chip designed without some sort of implementation or verification IP reuse. Some chips are almost entirely reusable IP, with the only custom logic stitching it all together. I can’t imagine designing 100M gate chips without design reuse.

Design teams looking for digital IP were faced with a straightforward make vs. buy decision. On the one hand, most design teams could design the IP themselves given enough time and money. They could even prototype and verify the IP via FPGA protoytype to make sure it would work. But could they do it faster and cheaper than buying the IP and could they do it with a higher level of quality? The design team that decided they could do a better, faster, cheaper job themselves, did so. The others bought the IP.

But analog and mixed signal IP is very different. Whereas most design teams have the skills and ability to design digital IP, they usually do not have the expertise to design complex analog and mixed signal IP. Not only are analog designers more scarce, but the problem keeps getting harder at smaller geometries. Ask any analog designer you know how hard it is to design a PLL at 65 nm or 45 nm. What were 4 corner simulations at 90nm become 16 corner or even monte-carlo simulations at 45 nm and below. Not only is analog design difficult, but it often requires access to foundry specific information only available to close partners of the foundries. And even if you can get the info and design the IP, there is no quick FPGA prototype to prove it out. You need to fab a test chip (which is several months), complete with digital noise sources to stress the IP in its eventual environs. The test chip can cost several million dollars (much more than an FPGA protoype for digital IP) and you’d better count on at least one respin to get it right.

That is why Synopsys’ acquisition of the MIPS ABG IP is such a good move. The “value proposition” for analog IP is so much greater than for digital IP. It’s not a matter of whether the customer can design the IP faster, better, cheaper, it’s whether he can design it at all. By expanding its analog IP portfolio, at a bargain price, Synopsys is well positioned to provide much of the analog and mixed signal IP at 65 nm and below. In addition, this acquisition gives Synopsys a real analog design team with which they can perform design services, something they have coveted but lacked for some time.

Once again, it looks like Aart is taking the leadership role. Look for other companies to follow the leader.

harry the ASIC guy

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• Part 1 - Synopsys Lynx Design System Debuts at SNUG
• Part 2 - Lynx Design System? - It’s The Flow, Stupid!
• Part 3 - Strongest Lynx
• Part 4 - The Weakest Lynx
• Part 5 - The Mising Lynx - The ASIC Cloud

One key feature, the inclusion of pre-qualified technology and node specific libraries in the flow, was something I had pushed for when I was previously involved with Lynx (then called Pilot). These libraries would have made Lynx into a complete out-of-the-box foundry and node specific design kit … no technology specific worries. Indeed, everyone thought that it was a good idea and would have happened had it not been for resistance from the foundries that were approached. Alas!

In the months before the announcement of Lynx, I heard that Synopsys had finally cracked that nut and that foundry libraries would be part of Lynx after all. Whilst speaking to Synopsys about Lynx in preparation for my posts, I asked whether this was the case. Given my expectations, I was rather surprised when I was told that no foundry libraries would be included as part of Lynx or as an option.

The explanation was that it proved too difficult to handle the many options that customers used. High Vt and low Vt. Regular and low power process. IO and RAM libraries from multiple vendors like ARM and Virage. Indeed, this was a very reasonable explanation to me since my experience was that all chips used some special libraries along the way. How could one QA a set of libraries for all the combinations? So, I left it at that. Besides, Synopsys offered a script that would build the Lynx node from the DesignWare TSMC Foundry Libraries.

Two weeks ago, at the TSMC Technology Symposium in San Jose, TSMC announced their own Integrated Sign-off Flow that competes with the Lynx flow, this one including their libraries. Now it seems to make sense. TSMC may  have backed out of providing libraries to Synopsys to use with Lynx since they were cooking up a flow offering of their own. I don’t know this to be a fact, but I think it’s a reasonable explanation.

So, besides the libraries, how does the TSMC flow compare to the Synopsys Lynx flow? I’m glad you asked. Here are the salient details of the TSMC offering:

• Complete RTL to GDSII flow much like Lynx
• Node and process specific optimizations
• Uses multiple EDA vendors’ tools  (Synopsys mostly, but also Cadence, Mentor, and Azuro)
• Available only for TSMC 65nm process node (at this time)
• No cost (at least to early adopters … the press release is unclear whether TSMC will charge in the future)
• And of course, libraries are included.

In comparison to Synopsys’ Lynx Design System, there were some notable features missing from the announcement:

• No mention of anything like a Management Cockpit or Runtime Manager
• No mention of how this was going to be supported
• No mention of any chips or customers that have been through the flow

To be fair, just because these were not mentioned, does not mean that they are really missing, I have not seen a demo of the flow or spoken to TSMC (you know how to reach me) and that would help a lot in evaluating how this compares to Lynx. Still, from what I know, I’d like to give you my initial assessment of the strength of these offerings.

TSMC Integrated Signoff Flow

• The flow includes EDA tools from multiple vendors. There is an assumption that TSMC has created a best-of-breed flow by picking the tool that performed each step in the flow the best and making all the tools work together. Synopsys will claim that their tools are all best-of-breed and that other tools can be easily integrated. But, TSMC’s flow comes that way with no additional work required. (Of course, you still need to go buy those other tools).
• Integrated libraries, as I’ve described above. Unfortunately if you are using any 3rd party libraries, you’ll need to integrate them yourself it seems.
• Node and process specific optimizations should provide an extra boost in quality of results.
• Free (at least for now)

Synopsys Lynx Design System

• You can use the flow with any foundry or technology node. A big advantage unless you are set on TSMC 65nm (which a lot of people are).
• Other libraries and tools are easier to integrate into the flow I would think. It’s not clear whether TSMC even supports hacking the flow for other nodes.
• Support from the Synopsys field and support center. Recall, this is now a full fledged product. Presumably, the price customers pay for Lynx will fund the support costs. If there is no cost for the TSMC flow, how will they fund supporting it? Perhaps they will take on the cost to get the silicon business, but that’s a business decision I am not privy to. And don’t underestimate the support effort. This is much like a flow that ASIC vendors (TI, Motorola/Freescale, LSI Logic), not foundries, would have offered. They had whole teams developing and QA’ing their flows. And then they would be tied to a specific set of tool releases and frozen.
• Runtime Manager and Management Cockpit. Nice to have features.
• Been used to create real chips before. As I’d said, the core flow in Lynx dates back almost 10 years and has been updated continuously. It’s not clear what is the genesis of the new TSMC flow. Is it a derivative of the TSMC reference flows? Is it something that has been used to create chips? Again, I don’t know, but I’ve got to give Synopsys the nod in terms of “production proven”.

So, what do I recommend. Well, if you are not going to TSMC 65 nm with TSMC standard cell libraries, then there is not much reason to look at the TSMC flow. However, if you are using the technology that TSMC currently supports, the appeal of a turnkey, optimized, and FREE flow is pretty strong. I’d at least do my due diligence and look at the TSMC flow. It might help you get better pricing from TSMC.

If anyone out there has actually seen or touched the TSMC flow, please add a comment below. Everyone would love to know what you think first hand.
harry the ASIC guy

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