IDF 2008 Event Feed

Vic Lortz on Amplifying your Mobile Experience

2008-03-27T23:33:31Z

Intel is in the enabling game. As a building block supplier, our business is based on the premise that when our customers win, we win, too. We are also in an industry that is constantly pursuing the next big thing to drive new waves of growth and business opportunities. The Mobile Internet Device (MID) category is a candidate for the “next big thing” in mobile computing, although some skeptics question its appeal.

By its very name, it is obvious that a MID will connect to the Internet and consume Internet content and services. However, the “Mobile” part of the name suggests that the resulting experience may have the user interface limitations typical of small devices. A MID may have a bigger screen than a typical mobile phone, but it can’t be dramatically bigger without becoming the equivalent of a notebook or tablet PC.

So, will the MID end up being too small (or too large) to be the next big thing? Maybe, maybe not. I think part of the answer lies in thinking outside of the MID box and recognizing the potential of connecting MIDs to other devices around it. For example, digital TVs have big screens capable of delivering a compelling visual experience. Imagine if digital TVs included a wireless display feature (either integrated or through an external adapter) so that a MID could easily use that large display instead of or in addition to the integrated screen of the MID. It is not much of a stretch to see the possibilities around this combination of technologies.

However, as Edison said, genius is 1% inspiration and 99% perspiration. It is going to take a lot of collective industry perspiration to enable broad deployment of technologies such as wireless remote displays and compatible mobile devices in such a way that the non-geniuses of the world will be able to make it all work.

Intel is working on this and other similar problems together with fellow-travelers in the industry. As we identify the necessary set of technologies and standards to support, we will integrate them into our next-generation mobile devices (both laptops and MIDs). If we succeed, the MID may confound its detractors and become the next big thing after all. Then the OEMs who use Intel’s mobile platforms will have great opportunities to pursue that next wave of growth, and we will grow along with them. After all, Intel is in the enabling game.

Vic Lortz is a Research Scientist and senior architect at Intel’s Communications Technology Lab in Hillsboro, Oregon. He holds a B.A. degree in Physics and a M.S. and Ph.D. in Computer science. In his Ph.D. research at the University of Michigan, he developed methods for time-bounded resource sharing on multiprocessors for hard real-time applications such as machine control and robotics. Since joining Intel in 1994, Vic has focused primarily on technologies related to home networking and wireless network security. He has participated in numerous standards activities, including serving as chair of UPnP Security in 2003 and lead architect and co-editor of Wi-Fi Protected Setup in 2006.

Keotag - tag search multiple engines, tag generator and social bookmark links generator [del.icio.us]

2008-04-23T14:47:02-05:00

This is really useful

Propaganda Posters [Flickr]

2008-04-06T15:50:17-05:00

Hugger Industries posted a photo:

In the bookstore

Green lighting [Flickr]

2008-04-06T15:50:12-05:00

Hugger Industries posted a photo:

Shanghai Greening [Flickr]

2008-04-06T15:50:08-05:00

Hugger Industries posted a photo:

We called this ego-ganda, but did see new parks, air quality stations, and air monitors checking buses. Shanghai was far more breathable than Beijing, which is like sticking your face in a tail pipe of a Suburban.

Eco Shanghai [Flickr]

2008-04-06T15:50:03-05:00

Hugger Industries posted a photo:

Rain Coats [Flickr]

2008-04-06T15:49:58-05:00

Hugger Industries posted a photo:

DailyTech - Intel's "Nehalem" Flirts With 3.2 GHz at IDF 2008 [del.icio.us]

2008-04-03T14:45:09-05:00

Intel shows off working 3.2GHz Nehalem processors at IDF - Engadget [del.icio.us]

2008-04-03T14:44:18-05:00

AnandTech: Intel's Atom Architecture: The Journey Begins [del.icio.us]

2008-04-02T16:48:48-05:00

Intel's Atom processor unveiled - The Tech Report - Page 1 [del.icio.us]

2008-04-02T16:47:43-05:00

Intel's Ultra-Portable Atom: Unveiled - HotHardware [del.icio.us]

2008-04-02T16:47:15-05:00

Intel reveals June launch date for first Atom processor - Engadget [del.icio.us]

2008-04-02T16:46:45-05:00

Intel Fires Up New Atom Processors | Tom's Hardware [del.icio.us]

2008-04-02T16:46:14-05:00

The Mother Board :: View topic - IDF Sprig 2008 Day 0 @ t-break [del.icio.us]

2008-04-02T16:45:43-05:00

PC Perspective - Comments [del.icio.us]

2008-04-02T16:45:20-05:00

Does low power always mean a performance sacrifice?

2008-03-27T00:41:29Z

Not according to the latest SPECpower benchmark results. But first, no doubt you all saw the excellent press coverage the new low voltage Xeon announcement garnered. But what does it mean in practical terms?

Well, let me remind you of our low power line up: We have several new 45nm high-k metal gate quad-core Intel Xeon processors, two of which have a TDP (Thermal Design Power) of 50W and one that has a TDP of only 40W (mainly for use in embedded applications). These chips are up to 25% faster than their 65nm predecessors. It is worth noting that we also have a range of quad-core desktop chips, including versions that come in 65W flavours ideal for small desktop form factors.

And power is an important consideration in the datacentre, where according to IDC every Watt represents an energy and cooling spend of $2 per year. Previously, measuring power efficient performance was a difficult task with many methodologies. Do you measure TDP’s? Add them together to make an arbitrary number? Or use idle power? or create some kind of average power half-way house? None of these solutions was satisfactory. Was just low power important? Or did you also need to measure performance?

So the industry has come together to create a benchmark to measure power efficiency, and the new Intel low voltage chips have raced to the top of the ladder to claim the top prize. (At the time of writing) SPECpower is the first and so far only industry standard energy efficiency benchmark.

The new chips also boast a very low idle power of only 16 Watts - this is just 4 Watts PER CORE!!! How does Intel do this? Well, smart design and the wonders of Intel’s magic 45nm high-k metal gate silicon process technology. This make the processors ideal for use in blades and other high density form factors.

Now that you are going to rush out and purchase large numbers of these new chips - what else can you do to make sure your system is as energy efficient as possible? Try these helpful tips:

Use fewer, larger memory DIMMS. The more memory sticks you have, the more power you will consume overall.
Use a power efficient power supply. Look for the 80Plus sticker or click here.
Switch on all Power Management options such as ‘Demand Based Switching, C1E, etc…

Happy shopping!

A Sneak Peek into Intel's Future

2008-03-19T20:27:44Z

The Intel Developer Forum has been one of the most tech inspiring gatherings I’ve participated in since joining Intel in 2000. The latest incremental advancements, demonstrations that show visionaries are not creating pie in the sky, and the roadmap updates. Yes, the roadmap updates. What gets me zooming is the swirl of the people who come from around the world. Thousands of top hardware and software engineers upgrading their multicore skills and teaming up to build the next new thing — from supercomputers to tiny Mobile Internet Devices to the ever better performing wired and wireless world connecting us to the Internet. The technology is awesome, but the people attending IDF make it meaningful.

I’m remaining at headquarters as IDF 2008 kicks off in Shanghai April 2-3, but there are plenty of ways to get first-hand experiences live from the event by checking into this blog and its siblings, Research@Intel and Mobility@Intel. If you’re a software developer, check in with Josh Bancroft and friends at the Intel Software community. IT pros will be sharing war stories on Open Port. And for those fortunate enough to read simplified Chinese, the real action from the event is being shared here.

If it’s videos you like, we’ll help our bloggers post videos on channelintel. If you prefer the Facebook experience, please join our group or event page. Follow IDF on Twitter and we’ll follow you back. There’s also the one-stop Tumblr stream of online activity. As the event kicks off, fresh photos, videos, news and other materials can be found at the Intel Pressroom.

Business and tech press, and tech reviewers and bloggers who follow Intel just got a sneak peek at some of the technologies Intel is working on for IDF Shanghai. It’s interesting to get their take on how things are progressing, what’s working, what challenges are ahead.

I asked a few friends from various groups inside Intel what they were interested in, and here’s what they shared:

Nehalem — Intel’s code name for its next entirely new chip design
Dunnington — code name for six-core processors for servers and workstations
Itanium — Intel’s family of processors for big servers
Virtualization — a new learning track at IDF this year
Montevina MIDs — Mobile Internet Devices built on Intel Atom and Intel Centrino Atom processor technologies
WiFi/WiMAX wireless switching — see video I shot at IDF 2007 in San Francisco Multi-threading
High Performance Computing
Computerized digital camera (research)
The social media crowd might enjoy MashMaker — see a video I shot at IDF 2007 in San Francisco

Is there something on the list you’re most interested in? Is there something you’d like to add to the list? What do you think will be the most important technologies demonstrated at the show?

Hope you can make it to Shanghai (register here) or join our team online as we share the IDF experience.

Introducing two “Universal Parallel Computing Research Centers”

2008-03-19T17:00:00Z

Today, it’s a pleasure for me to report that Intel and Microsoft are joining forces to accelerate the mainstream adoption of highly parallel computing technology. Together, the two companies are pioneering the concept of industry-funded “Universal Parallel Computing Research Centers” (UPCRCs) at both the University of California at Berkeley and the University of Illinois at Urbana-Champaign. The two schools were selected in an open competition judged by experts at both companies.

It should be no surprise that Intel and Microsoft share the common goal of energizing the academic community in what the president of Stanford University, Professor John Hennessey, called the greatest challenge to computer science in 25 years. These two centers are expected to create long term, high-impact breakthroughs in parallel programming languages, tools, and supporting architectural features that will enable entirely new classes of consumer and enterprise applications. Each center will receive $20 million over five years from Intel and Microsoft. An additional $8 million will come from UIUC, and UC Berkeley has applied for $7 million in funds from a state-supported program to match industry grants. That is serious money by anyone’s measure.

Speaking for Intel, I am tremendously excited by this new approach to funding academic research. We can no longer rely on the government to support the long-term research we need in the universities. Not only do we need them generating the new ideas, we need to eventually hire the students who know the technology and can bring it to life in our products. The transition to mainstream parallel computing will be a historic one for information technology. With the help of these two centers, it will enable new opportunities in entertainment, social interaction and collaboration.

One example that has captured much of my interest the last six months is the shift from a 2D to a 3D Internet. We believe that today’s nascent virtual worlds from Club Penguin to Second Life will soon evolve to become an essential new medium for human interaction and collaboration. The computational requirements, however, to make the 3D Internet truly immersive and personal are beyond anything we can do today. Innovations such as those from these UPCRCs will augment our own efforts towards realizing these future information environments and provide a ready market for our high performance products.

Parallel computing has been in Intel’s blood for more than two decades. In 1985 we shipped the first microprocessor-based parallel supercomputer to Yale University with 128 Intel 80286/80287 processors. If memory serves me, the peak floating point performance of Yale’s machine was about five million floating point operations per second or five megaFLOPS – the equivalent of a typical desktop computer circa 1995. On December 4, 1996, the dream of a parallel computing machine capable of a trillion floating point operations per second (teraFLOPS) speed was realized by the ASCI Red system, built by Intel for the DoE’s Sandia National Laboratory.

In 2004 we decided to that it was time to explore TeraFLOPS capability at the single chip level by integrating many IA-compatible cores on one die. Within our Corporate Technology Group, we committed a substantial percentage of our resources to launch our Tera-scale Computing Research Program, which we announced publicly in 2006. Tera-scale was a holistic HW/SW program to enable mainstream many-core microprocessors and systems. With an 80-core Teraflops Research Processor up and running in the lab, and our first highly parallel product architecture (Larrabee) on track for first silicon later this year, we are well on our way to delivering tera-scale hardware. However, we must do more to make sure average programmers can make full use of Larrabee’s amazing capabilities. That’s why the UPCRC funding activity is essential: helping ordinary programmers write efficient parallel programs for Larrabee and our mainstream multi-core processors.

Our experience as a long-time developer and supporter of current parallel programming standards, such as OpenMP, and as a leading provider of parallel software development tools, such as our Threading Building Blocks, helps us to understand how much work there is to be done. Despite years of work in the high performance computing community, developing parallel software still requires PhD level programming know-how. While we are making good progress in the lab with software technologies such as transactional memory, and our data parallel Ct API, we realized we needed to harness innovation across industry and academia to break parallel computing to the masses. And that’s why the investment in the centers made so much sense.

Berkeley has a 20-year tradition of doing genuinely integrated system projects with many faculty members tackling a common goal. Each faculty member on this project will be a recognized expert in his or her discipline of interest. The UPCRC research at Berkeley will be led by David Patterson. David is known for his ability to identify critical questions for the computer science community and gather interdisciplinary groups of faculty and graduate students to answer them. He currently heads Berkley’s Par-lab, focused on parallel computing. [Ed. Note: See Cheryl’s blog for a video David and team]

Likewise, the University of Illinois has been a leading institution in parallel computing research for more than four decades and has helped define the landscape of parallel processing multiprocessors. The UPCRC efforts here will be led by Profs. Marc Snir and Wen-Mei Hwu. Marc is the director of the Illinois Informatics Institute. Previous to his work at UIUC, he initiated and led the IBM Blue Gene project. Wen-Mei’s team created the first HP-PD compiler, which was used by Intel in the early Itanium design process.

Intel and Microsoft will work together with David, Marc, and Wen-Mei to direct two five-year research efforts under the banner of the UPCRC. Intel views these close academic collaborations as critical components in enabling a shift to desktops and laptops based on many-core chips. We’ve already launched a variety of multi-core software products and, just last week, the Intel Academic Community. We have created a sizable research program in Tera-scale computing and funded numerous individual parallel computing researches. These UPCRCs dramatically increase our investment in academic research.

Making parallel computing pervasive will one day be seen as one of the greatest accomplishments of the 21st century. But enough speculation — let’s get to work.

Stefano Pellerano on 60 GHz Radios

2008-03-13T07:01:00Z

Wireless is cool. But nobody wants a slow wireless connection. However, fast wireless means large bandwidth and in today’s crowded spectrum bandwidth is a scarce resource. Recently, 60GHz radio (often referred to as mm-wave radio) has attracted the attention of the wireless communications community for very wide-band application opportunities. Why 60GHz? First, there is a huge amount of unlicensed spectrum available around there. Second, if we think of the bandwidth as a fixed percentage of the carrier frequency, 10% of 60GHz would give 6GHz, compared to 250MHz at 2.5GHz. With channels larger than 2GHz, applications with data rates over 5Gb/s over relatively short distances (i.e. 10m) are possible. Wireless Personal Area Networks (WPAN), wireless HDMI, synch & go and wireless docking station are just a few examples of what could make mm-wave technology attractive for the high-volume consumer market. Moreover, low-cost technologies like CMOS are already proving to deliver the performance required to build a reliable millimeter-wave wireless link.

Having the radio operate at 60GHz is not free. One of the biggest challenges is to generate a stable mm-wave carrier signal to be used to tune to the right channel in reception or modulate the information up into the right channel for transmission. Mm-wave voltage-controlled oscillators (VCO) in CMOS technology have been demonstrated. However, a simple oscillator is not able to provide the stability and spectrum pureness required for the radio. These oscillators need to be controlled by a feedback loop (i.e. Phase-Locked Loop, PLL) that uses a high-purity crystal oscillator as a reference. Unfortunately, these precise reference oscillators are typically available at lower frequencies of few tens of megahertz. Therefore, before comparing to the reference frequency, the signal at the output of the oscillator has to be divided down to the same frequency of the crystal oscillator. Realizing a mm-wave frequency divider that can perform this function is very challenging even in today’s sub-100nm CMOS technologies.

Figure 1. The concept of an injection-locked frequency divider (ILFD). The ILFD is essentially an oscillator with a free running frequency f_free (top figure). If a signal around f_free or its harmonics is injected onto the divider as shown in the bottom figure, the divider tries to synchronize to the injected signal, i.e. “locks” to it, and the output tracks the injected signal rather than oscillate at its free-running frequency.

At ISSCC 2008 my colleagues at Intel, Texas Instruments and Georgia Institute of Technology, Rajarshi Mukhopadhyay, Ashoke Ravi, Joy Laskar, Yorgos Palaskas and I announced a 39.1-to-41.6GHz ΔΣ Fractional-N Frequency Synthesizer in 90nm CMOS. The proposed mm-wave PLL uses a particular breed of frequency dividers called injection-locking frequency dividers (ILFD) to divide down the VCO signal to lower frequencies where conventional dividers can then be used. An ILFD can operate at very high speed with a reasonable amount of power, but over a limited range of frequencies. To overcome this limitation, a digital-calibration technique has been implemented. How do these dividers work? An injection-locking divider is very similar to an oscillator. When it is not disturbed by any external signal, it oscillates at its own free-running frequency. Due to non-linear effects, some nodes in the circuit experience signals at integer multiples (harmonics) of the output free-running frequency. If an external signal at a frequency close to one of those harmonics is injected in the node, the whole divider will try to synchronize to it, aka “locks” to the injected signal. For example, assume that the free-running frequency of the divider in figure 1(a) is f_free and one of its internal nodes has some 4th harmonic content, i.e. 4f_free. If now an external signal at a frequency f_inj ~ 4f_free is injected on that node, the divider will lock to it and therefore the output signal of the locked divider becomes f_inj/4. This implements a division by 4. However, if the injected frequency is too far from the harmonic of f_free, the divider cannot lock anymore.

Figure 2: The technique used to calibrate the injection locked divider. With a fixed VCO frequency f_VCO, the output of the divider should be constant (f_VCO/4) if the divider is locked. This observation can be used to see if the divider is “tuned” right.

We can extend the frequency range over which the divider locks by making sure that its free-running frequency is always close to one fourth of the injected frequency. Assume that we can control the free-running frequency of the divider by an external voltage V_ilfd and that we want to use the divider to divide the VCO frequency by 4 (Figure 2). The free-running frequency of the divider can be calibrated so that it is close to f_VCO/4. However, since the PLL is not locked yet (we still need to calibrate the divider that is used by the PLL to achieve lock), the VCO frequency is not known. How can we calibrate the divider? The idea is shown in figure 2. The signal from the VCO is injected in the divider. The frequency is unknown, but it is kept fixed. Then the voltage that controls the ILFD free-running frequency is swept while the frequency of the signal at the output of the ILFD is monitored (f_ilfd). When the divider is not locked, its output frequency is equal to the free-running frequency and so it will change by changing V_ilfd. However, when the divider locks onto the VCO signal, f_ilfd becomes one fourth of the VCO frequency and stays constant over the locking range, no matter what the V_ilfd control is. After that, the divider unlocks again, and its output frequency again tracks V_ilfd. By simply looking at the plateau in the plot in figure 2, we can recognize the range of V_ilfd over which the divider is locked (shaded area in figure 2). To center this range around the VCO input frequency we just have to select the center of such range as the calibrated V_ilfd.

The proposed PLL is the first ever fractional-N CMOS mm-wave synthesizer and uses an injection-locking divider-by-4 after the VCO. One division by 4 instead of two successive division by 2 can cut the power consumption by half. However, the locking range of a divider-by-4 is typically smaller compared to a divider-by-2. The calibration technique explained above enables the use of such low-power divider over the required frequency range. The fractional-N synthesizer is able to generate frequencies with a very fine resolution, few kilohertz in our case. This capability can be used to adjust for variation of the reference oscillator, so that a cheaper crystal, with less accuracy in the absolute oscillation frequency, can be used. This further reduces the overall cost of the radio.

Stefano Pellerano was born in Bari, Italy. He received the Laurea Degree and the Ph.D. degree in electronics engineering from the Politecnico di Milano, Milan, Italy, in 2000 and in 2004, respectively. During his Ph.D., his activity was focused on the design of fully integrated frequency synthesizers for wireless LAN applications. In 2003 he has been a consultant with Agere Systems (former Bell Labs) in Allentown, PA. He is now with the Communications Technology Lab of Intel, Hillsboro, OR. His recent research interests include fully-integrated MIMO transceivers, mmWave radios and digital-style phase-locked loops for WiFi/WiMax applications in CMOS technology.

Hasnain Lakdawala on a spectrum sensing, reconfigurable ADC

2008-03-12T07:01:00Z

One of the consequences of widespread use of wireless is that the spectrum is getting crowded. Radio standards must be designed to operate under this rather hostile environment with the presence of a lot of blocking signals in the channels adjacent to the one your radio is working in. It turns out that the standards account for the worst possible scenario, and all radios are designed to meet that specification all the time whether blockers are present or not. This means that a receiver design consumes power whether a blocker is present or not. This is rather wasteful and an obvious way to fix it would be to have a way to reduce power of the receiver if we can determine that there are no blockers present.

A typical radio is designed to handle the worst case blocker. The dynamic range requirement (hence power) can be dramatically reduced if that blocker were not present.

Another challenge a radio designer faces is that with transistor scaling the analog voltage reduces and analog design gets more challenging. This is compounded by the fact radios have to support multiple standards with different bandwidths and data rates. The trend in the industry is to make the radio more digital by pushing most of the analog filtering to the digital domain. This means that we need to have an Analog-to-Digital Converter (ADC) that has a very high dynamic range that is a significant design challenge and takes more power.

At ISSCC 2008, colleagues at Intel, Cornell University and Georgia Institute of Technology Pukar Mala, Kevin Kornegay, K. Soumyanath and I presented an ADC that allows us to tackle both these challenges simultaneously. The sigma-delta ADC is designed for a radio that has minimal filtering in the analog domain, just a programmable one pole and a fixed anti-alias filter. A sigma delta ADC exploits the speed of the modern CMOS process to improve the resolution.

The block diagram of the baseband section of the receiver is shown below:

The block diagram of the ADC in a WiFi/WiMAX receiver. The Simple spectrum analyzer (SSA) uses the low resolution high frequency measurement in the ADC to determine the dynamic range required in the ADC according to the interference scenario.

The core of the sigma-delta has been designed to attain a 12 bit dynamic range in the worst case situation. However it takes most power in this mode. If we can figure out that there is no significant blocker present we can dial down the power of the ADC and possibly other components of the radio. This would allow us to operate in the most optimal power mode while allowing us to survive large blockers.

Sensing the interference environment of the ADC can be performed for free using existing hardware. A sigma-delta ADC can convert the input signal over a large bandwidth with very low resolution. However if we just care about the power of the channels near the signal, the low resolution is sufficient to allow power measurement. We use the unshaped high speed output of the ADC to determine if/where the blockers are present and their power. With this information about the surrounding spectrum we can determine how much dynamic range is required in the ADC and appropriately adjust the power dissipation.

The proposed ADC is the most power efficient ever published for this type of ADC. It takes only 0.27pJ/bit of data converted. The power of the ADC can be reduced from 28mW all the way down to 12mW if reduced dynamic range is allowed when minimal blockers are present. This power reduction is achieved by shutting down portions of the ADC. This small power dissipation is achieved by using scaling friendly architecture that pushes the operation speed of the ADC as high as possible. The ADC uses digital arithmetic to replace the traditional analog summing allowing lower power and scalability.

Another feature of the sigma-delta ADC is the ability to trade off dynamic range for conversion bandwidth. The dynamic range is increased if the conversion bandwidth is reduced. This feature is exploited for WiMAX channels that are 2.5MHz to 20MHz wide to reduce power consumption in these modes. The reduced power consumption is achieved by shutting portions of the ADC rather than reducing the sampling frequency. The sampling frequency of the converter is kept constant for all bandwidths of operation. This ensures that the anti-aliasing requirement of the ADC does not change. Very minimal change in the analog filtering is required in the WiFi/WiMAX modes as the channel select filtering is primarily done in the digital domain.

The ability of the ADC to measure large bandwidths allows us to be aware of the surrounding spectrum of the radio. This information can be used in many ways. We could select the optimal channel to communicate based on this information. This would enable the lowest power operation of the radio to extend battery life. Future standards will fully exploit this technology. This work provides the first circuit implementation of this scheme.

Hasnain Lakdawala received his PhD degree in Electrical and Computer Engineering from the Carnegie Mellon University, Pittsburgh PA in 2002. From 2002 to 2004, he was Product Architect at IC Mechanics Inc, Pittsburgh PA. He has been a Research Scientist at Intel Corporation, Hillsboro, OR since 2004. His research interests include RF and mixed signal circuits for WLAN transceivers.

Intel showboats in Shanghai: IDF approaches | News | TechRadar.com [del.icio.us]

2008-04-01T15:36:33-05:00

Undoubtedly, it's the most significant architectural overhaul of Intel's X86 family since the original Conroe-vintage Core 2 processor blew us all away at the Fall IDF

IDF Shanghai preview: from Atom to Bloomfield to SSD [del.icio.us]

2008-04-01T15:33:20-05:00

An excellent overview of what's big at IDF 2008

MacMod.com - Your Mac Modification HQ - IDF is peep into Apple's future? [del.icio.us]

2008-04-01T15:16:30-05:00

If Apple sticks with Intel for the next few years, we have a good chance of seeing more and more mobile computing products. One chance to see what we might have in store is to watch Intel at the IDF (Intel Developers Forum in China this week.

Intel Developer Forum will give us a peek into the future » Eee PC - Blog [del.icio.us]

2008-04-01T15:14:15-05:00

Intel’s Developer Forum will discuss and showcase a number of technologies they’re currently researching, including a multi-band, power-efficient, CMOS Transceiver. They’ll tackle topics ranging from Energy Efficiency to Biosensors to Gaming.

Intel IDF kit bag includes 2 new MIDs. - UMPC News - News - UMPCPortal.com [del.icio.us]

2008-04-01T15:12:17-05:00

There are two in there that I haven't seen before. "...concepts with GPS..." The BenQ MID has also been re-designed and has a new user interface apparently. Will it be the 'shake me' design based on a new Midinux UI? We'll learn more about all the new dev

Intel unveils vision for mobile connectivity - INQUIRER.net [del.icio.us]

2008-04-01T15:10:19-05:00

Intel is focusing its efforts particularly in four areas: smaller form factor and improved power efficiency; more aware devices that leverage on surrounding technology; greater user personalization; and establishing standards among manufacturers.

ITWeb :Low-cost PCs a reality [del.icio.us]

2008-04-01T14:43:43-05:00

Maloney says in consequence he sees the PC market segmenting the same way the cellphone market has done.

Intel's 'Bloomfield' spied ahead of IDF public demo | Register Hardware [del.icio.us]

2008-04-01T14:06:13-05:00

Intel's next-generation 45nm processor architecture, 'Nehalem', made an appearance at the as-yet-unopened Intel Developer Forum (IDF) event today. A number of machines sported four-core versions of the chip.

Intel breaks ground with first Atom-based ultra-portables in the wild [del.icio.us]

2008-04-01T13:58:30-05:00

There you have it, the first laptop we've seen running Intel's long awaited Atom processors. We're pretty sure that's MSI's Wind PC on display in Shanghai for Intel's Developer Forum.

Intel's Cliffside turns one Wi-Fi adapter into two [del.icio.us]

2008-04-01T13:56:31-05:00

Users can maintain two simultaneous network connections with Cliffside. One connection can link the laptop to a wireless Internet connection and the other to a personal area network (PAN) of Wi-Fi devices.