Most cloud computing services encrypt data in transit and at rest. But that data still needs to be decrypted before cloud servers or virtual machines can perform any kind of computation on it. This risks exposing data—especially sensitive information such as financial transactions or medical records—during processing. This is where The Fog comes in.

Launched in early April by chip startup Niobium, The Fog is an encrypted cloud platform. It follows a client-server architecture, where a person or organization (the client) can encrypt data or workloads locally using their own private keys and deploy the encrypted data or workloads to The Fog (the server) without sharing their keys. These private keys remain with data owners, and only they can decrypt any results from the platform.

Much like actual fog obscures everything it envelops, so does the encrypted cloud platform named after it. Yet unlike physical fog that eventually lifts, The Fog keeps data opaque at all times—even as computation happens.

“The data in our cloud will never be exposed—it’s always encrypted,” says John Barrus, vice president of product at Niobium. “It’s a new category of cloud.”

Fully Homomorphic Encryption keeps The Fog secure

Beneath The Fog lies a cryptographic technique known as fully homomorphic encryption, or FHE, which allows for computing on encrypted data without the need to decrypt it. But FHE is often slow and requires a lot of computing power and memory.

Niobium aims to address these bottlenecks using mistic, its FPGA (field-programmable gate array) chip, which can be reconfigured for FHE after manufacturing. For some applications the company is testing, its accelerator hardware runs FHE about twice as fast as today’s GPUs, Barrus says.

To demonstrate the usability of its encrypted cloud platform, Niobium has developed a handful of template applications “that solve typical problems where you might want to hide the data or keep it encrypted, so people can start there and just try it out,” says Barrus. One such template application involves encrypted semantic search, which queries databases or datasets and returns relevant results based on the context or meaning of the search terms rather than keywords that match them. Both the query and the data source are encrypted, helping ensure data privacy.

“Let’s say you’re a legal firm, and you have sensitive case documents. You encrypt all those documents and store them encrypted in the cloud,” Barrus says. In this scenario, you can ask questions about the documents using encrypted semantic search “and get pointers to those documents back, and then just download and decrypt the documents you need.”

Niobium takes FHE from theory to practice

Kurt Rohloff, cofounder and chief technology officer (CTO) at Duality Technologies, is excited about the prospect of running his company’s privacy-enhancing software products on The Fog. Duality provides software that uses FHE, including an LLM inference framework. Without a platform like The Fog, users may need to purchase dedicated FHE acceleration hardware, he says. But “the Niobium encrypted cloud platform allows users to rapidly scale their use of FHE-protected computing [and] get much more value from their data,” he says.

Echoing the sentiment is Rashmi Agrawal, cofounder and CTO at CipherSonic Labs, a company building FHE-powered encrypted AI infrastructure. “Platforms like Niobium are important because they help move FHE from theory into deployable infrastructure,” she says. “An encrypted cloud platform built on FHE fundamentally changes the trust model of cloud computing. This significantly reduces exposure to data leakage, insider threats, and compliance risks while enabling organizations to safely process highly sensitive data in the cloud.”

However, Agrawal points out that despite FHE’s rapid progress, there are still practical challenges. These include performance overheads for complex tasks or workloads that need to be completed with low latency, as well as filling in skills gaps for software developers who have no FHE knowledge or experience. “Building FHE-compatible applications often requires rethinking traditional approaches. The ecosystem is still maturing as tooling, standards, and interoperability continue to evolve,” she adds.

Barrus acknowledges these hurdles. “I think the real challenge is large language models with a lot of matrix and vector multiplications. We have to be fast enough that you’re not waiting minutes for every token but seconds or so. That’s going to be much harder to solve,” he says.

In terms of equipping developers without any FHE background, Niobium hopes to make The Fog more accessible by providing a tech stack composed of a compiler, software development kit, documentation, and other training materials. “If we can bring FHE computation to more people, then more people can develop privacy-preserving applications,” says Barrus.

The Fog is currently available in private beta, with Niobium targeting May or June for a public launch. The company is also developing an application-specific integrated circuit for its encrypted cloud platform that Barrus says will be up to 25 times as fast as a GPU, depending on the application.

“What we’re trying to do is create value from encrypted data,” he says. “Our vision is that data never has to be exposed to be useful.”

As more AI data centers come on line, concerns are rising about their effects on the grid, and it’s not just the amount of power they consume. They tend to have huge swings in power use, surging up and down by 70 percent or more in milliseconds. Traditional electricity infrastructure isn’t designed to deal with that kind of load fluctuation.

To address the problem, researchers are developing power electronics systems that sit between the data center and the grid to act as a buffer and even as a grid helper in times of need. One such system, developed by the Miami-based company ON.energy, is being implemented across 3 gigawatts’ worth of projects, and has sailed through a battery of tests at the U.S. National Lab of the Rockies (NLR).

In the tests, ON.energy’s system sat between a simulated data center and a simulated grid. The system successfully protected the data center from grid instability and also safeguarded the grid from the major load swings generated by the data center. The company’s technology involves a bidirectional uninterruptible power supply (UPS) that it calls AI UPS.

Such grid buffers are becoming increasingly important as AI facilities expand to gigawatt scale and beyond. Utilities have major concerns about both the amount of power demanded by these data centers and their potential to create system instability due to wild variations in loads. Innovations are needed to help data centers become better grid citizens, and shorten the amount of time they must wait to connect to the grid.

AI Data Centers and Grid Stability

UPS systems have been used for decades to protect data centers from grid events. If frequency varies suddenly or power is lost, these unidirectional systems provide almost instantaneous, short-term backup power to the equipment inside the data center. Because servers can’t tolerate more than minor deviations, UPS electronics also clean up low-quality power, such as voltage spikes or sags and frequency deviation.

UPS has served data centers well. But the scale of modern facilities packed with graphics processing units (GPUs) changes the game. Instead of data centers whose size is measured in tens of megawatts, AI facilities are reaching up to 5 GW. They still require the type of protection afforded by UPS, but their massive scale and load volatility pose dangers to the grid.

During a minor grid fault in Virginia in 2025, for example, several data centers tripped offline, causing 1.5 GW to drop off the grid simultaneously. This caused panic for the system operator, who had to act fast to balance the system and avoid a major power outage.

In addition to major changes in overall load, AI data centers can generate short-lived, high-voltage, or high-current disturbances known as grid transients. They may only last microseconds, but they can break down insulation, overheat transformers, cause electrical arcing, start fires, and destabilize an entire grid.

“The scale of modern data centers could lead to load swings of 1 GW multiple times per minute, which creates frequency variations and oscillations that the grid can’t handle,” says Ricardo de Azevedo, CTO at ON.energy.

These problems have given utilities and government authorities pause. Some authorities in the United States and parts of Europe are implementing moratoriums on new data centers or instituting rules that place responsibility for grid conditions onto the data center.

Texas Senate Bill 6, for example, requires new data centers to pay a share of any new grid infrastructure needed by their facilities. Additional requirements for voltage ride-through—the equipment’s ability to continue operating during power disruptions—are currently being formulated in accordance with this bill. Such rules aim to prevent large data centers from tripping offline suddenly or overwhelming the grid due to severe load variability from AI workloads.

“One of our customers in Texas that is building a 1-GW campus is now being required by the local grid authority to include voltage ride-through,” Azevedo says.

NLR engineers Przemyslaw Koralewicz [left] and Shahil Shah monitor the results of a simulation of ON.energy’s AI UPS in the control center at the NLR Flatirons Campus.Agata Bogucka/NLR

Bidirectional UPS

ON.energy’s 3.5-megawatt units consist of a power conversion system (PCS), batteries to store energy and act as an energy reservoir or buffer, another PCS, and a transformer. The batteries can provide up to eight hours of backup power, depending on the size of the data center. ON.energy sources this equipment from established manufacturers and adds its own software and controls.

The latest PCS units are bidirectional, acting as the interface between the grid, the batteries, and the data center. They convert between the alternating current (AC) from the grid, the direct current (DC) stored in the batteries, and the AC delivered to the data-center load, ensuring power quality and optimal flow when feeding an AI facility. In the other direction, the PCS absorbs and smooths transients caused by sudden load swings in the data center that would otherwise disrupt the grid.

“The batteries act like a reservoir of energy as well as a shock absorber, should there be any disturbances on the grid or from the data center,” says Azevedo.

ON.energy’s system is housed outside the data center, rather than inside as most UPS systems are, which frees up space internally for more compute resources. Being outside also allows the system to harness more advanced power electronics fed by medium voltage. Traditional UPS, on the other hand, operates on the low voltages needed by data-center computers for safety reasons.

The company has about 3 GW of these bidirectional AI UPS units either operating or under construction. It expects to commission a system in May for a 1.5-GW AI data center in Texas, according to Azevedo. For such a facility, hundreds of these 3.5-MW units would be required.

NLR’s Data Center-Grid Simulator

To test its system, ON.energy turned to NLR (formerly known as the National Renewable Energy Laboratory). The facility is likely the only one in the world that can do full-load, bidirectional testing that simulates both grid conditions and variable data-center loads. The facility can test up to 20 MW with voltage levels reaching 13.2 kilovolts. The test consisted of a 7-MW grid simulator that replicates disturbances and voltage ride-through events, and a 20-MW load simulator that reproduces real-world demand dynamics such as those created by an AI data center.

All over the world, researchers are working on an urgent and surprisingly difficult challenge: creating a cost-effective yet powerful permanent magnet that doesn’t use rare earth elements. Rare earth magnets are essential components of the motors for electric vehicles, heating and cooling systems, robots, tools, and appliances, and they’re also essential for wind turbines, audio speakers, and other systems. A strong magnet that doesn’t use rare earths would be of almost incalculable value, because it would free its users from China’s near-monopoly on rare earth elements and magnets. By circumventing that monopoly, it would almost certainly alter geostrategic calculations and global supply chains in short order.

Tantalizingly, no physics theories preclude the existence of a powerful and rare-earth-free magnet. And yet, after more than a decade of intensive efforts by many exceptionally bright people, no such magnet has been discovered.

Now, a small group of researchers in France and the United States has set out to test an intriguing hypothesis—that the problem can be solved with quantum computers. “You need the math of quantum mechanics to solve a problem that lives in the quantum realm,” declares Théau Peronnin, CEO of Alice & Bob, a Paris-based quantum computer startup. Alice & Bob is collaborating with Los Alamos National Laboratory and GE Vernova, with US $3.9 million in funding from the U.S. Department of Energy’s ARPA-E Quantum Computing for Computational Chemistry program.

Why Rare Earth Magnets Still Dominate

More than 67,000 compounds are known to have some degree of permanent magnetism. None, however, come close to the reigning permanent-magnet champ, neodymium iron boron (NdFeB), which dominates high-power applications.

For more than 15 years, researchers have used conventional high-performance computers to search for new and powerful magnets. But no commercially successful magnets have come out of that work. Even the best conventional computers aren’t powerful enough to simulate the detailed magnetic properties of a hypothetical permanent magnet.

To understand why, start with the basics. Permanent magnetism arises in certain crystalline materials when the spins of electrons of some of the atoms in the crystal are forced to point in the same direction, either “up” or “down.” The more of these aligned spins, the stronger the magnetism. The ideal atoms are ones that have unpaired electrons swarming around the nucleus in what are known as 3d orbitals. Tops are iron, with four unpaired 3d electrons, and cobalt, with three.

But 3d electrons alone are not enough to make superstrong magnets. As researchers discovered decades ago, magnetic strength can be greatly improved by adding to the crystalline lattice atoms with unpaired electrons in the 4f orbital—notably the rare earth elements neodymium, praseodymium, and dysprosium. These 4f electrons enhance a characteristic of the crystalline lattice called magnetic anisotropy—in effect, they promote adherence of the magnetic moments of the atoms to the desired directions in the crystal lattice. That, in turn, can be exploited to achieve high coercivity, the essential property that lets a permanent magnet stay magnetized.

“The combinatorial space is just ridiculously large. It’s 2 to the—I don’t know—40th or 50th power. It’s absolutely tremendous.”

The point is that being able to accurately simulate a hypothetical magnet means not only accounting for all those electron orbitals and spin states but also simulating the interaction of all those electron orbitals and spin states. And that’s really, really hard.

“Let’s say you have a chain of atoms, each with a single electron in the 1d orbital,” explains Peronnin. “And then you want to understand: If the spin of this one electron is down, how does it affect its neighbors? Would they be more likely to be up or down? And you need to do so for all the electrons in your chain. And then see if the total system has a tendency to align all its electron spins. Or, once you’ve added a bit of thermal noise and an external magnetic field, for example, how much disorder would there be in that chain? And so those are exactly the properties you want to predict.

“The emergent global properties [such as magnetism] arise from the local behavior of each electron. But each electron’s behavior is highly, highly correlated with how its neighbors behave. And this is what makes the problem extremely difficult, because you cannot treat each of those electrons individually. You need to treat the whole system with all its possible configurations all at once to predict the global properties. And this is where the computing space explodes.

“You have to consider all the possible superpositions of states of those electrons,” Peronnin continues. “And so here, the combinatorial space is just ridiculously large. It’s 2 to the, I don’t know, 40th or 50th power. It’s absolutely tremendous.”

Why Quantum Computers Might Finally Solve This Problem

The great potential advantage of quantum computers here is quantum parallelism, a capability that emerges directly from the qubits that are the heart of a quantum computer. In such a machine, these qubits are entangled with one another. The qubits are also in a state of superposition, which means that they can embody, in the macro world, certain quantum characteristics of subatomic particles. Namely, they can represent a binary 0 or 1 and also exist in a continuous range of states, each with an associated pair of probabilities—a probability that the bit is 0 and a corresponding probability that it’s 1. And the more there are of these superimposed qubits that are entangled, the more states those qubits can represent: A collection of n entangled qubits can represent 2ⁿ states simultaneously. The upshot is that with enough qubits, a quantum computer could handle the stupendous computational challenge of accurately simulating a hypothetical magnetic material.

How many qubits are enough? Peronnin figures things will start getting interesting when he and his colleagues can build a machine that has 100 logical qubits furnished with a proprietary type of error correction that they have pioneered. He figures that will happen around 2030. (IBM and others have already built quantum computers with over 1,000 physical qubits, but these machines did not have the error correction that is the defining characteristic of logical qubits, and none of them ever performed useful work.)

A strong magnet that doesn’t use rare earths would be of almost incalculable value.

Magnetics researchers not involved with the ARPA-E effort are mostly supportive of the project, while noting that progress on quantum computers is notoriously difficult to predict. “This is an interesting approach,” says Jiadong Zang, a professor of materials science and director of the materials science program at the University of New Hampshire. “You need some extraordinary approach to find some new structures,” he adds. Zang is part of a group that has been using a large language model to search the magnetics literature for the purpose of creating a database of experimental magnets, called the Northeast Materials Database for Magnetic Materials.

“This might be a task that quantum computers could do well,” agrees Matthew Kramer, Distinguished Scientist at Ames National Laboratory, in Iowa. (Kramer is working on a project with the U.S. Department of Energy and Fermilab aimed at improving a certain class of qubits.) He cautions, however, that efforts to use conventional computers to identify new magnet materials have often identified new candidates that could not possibly be built in the real world.

Microsoft’s Imaginary Magnets Will Probably Stay That Way

A recent and highly ambitious project at Microsoft, for example, resulted in a system called MatterGen, which the researchers used to design a range of magnets with “low supply-chain risk.” However, the researchers simplified the problem greatly by focusing on “high magnetic density” alone, without trying to incorporate any of the many other characteristics needed for a magnet to be useful. Taking into account such characteristics, including high coercivity, chemical stability, and cost effectiveness, is a big reason why the challenge quickly becomes computationally intractable. In the end, the researchers did not fabricate any of the magnets identified; it’s not even clear that they could.

“They had a lot of unusual structures,” Kramer notes. “The real question there is, can any of those actually be synthesized?”

When it comes to AI models, size matters.

Even though some artificial-intelligence experts warn that scaling up large language models (LLMs) is hitting diminishing performance returns, companies are still coming out with ever larger AI tools. Meta’s latest Llama release had a staggering 2 trillion parameters that define the model.

As models grow in size, their capabilities increase. But so do the energy demands and the time it takes to run the models, which increases their carbon footprint. To mitigate these issues, people have turned to smaller, less capable models and using lower-precision numbers whenever possible for the model parameters.

But there is another path that may retain a staggeringly large model’s high performance while reducing the time it takes to run an energy footprint. This approach involves befriending the zeros inside large AI models.

For many models, most of the parameters—the weights and activations—are actually zero, or so close to zero that they could be treated as such without losing accuracy. This quality is known as sparsity. Sparsity offers a significant opportunity for computational savings: Instead of wasting time and energy adding or multiplying zeros, these calculations could simply be skipped; rather than storing lots of zeros in memory, one need only store the nonzero parameters.

Unfortunately, today’s popular hardware, like multicore CPUs and GPUs, do not naturally take full advantage of sparsity. To fully leverage sparsity, researchers and engineers need to rethink and re-architect each piece of the design stack, including the hardware, low-level firmware, and application software.

In our research group at Stanford University, we have developed the first (to our knowledge) piece of hardware that’s capable of calculating all kinds of sparse and traditional workloads efficiently. The energy savings varied widely over the workloads, but on average our chip consumed one-seventieth the energy of a CPU, and performed the computation on average eight times as fast. To do this, we had to engineer the hardware, low-level firmware, and software from the ground up to take advantage of sparsity. We hope this is just the beginning of hardware and model development that will allow for more energy-efficient AI.

What is sparsity?

Neural networks, and the data that feeds into them, are represented as arrays of numbers. These arrays can be one-dimensional (vectors), two-dimensional (matrices), or more (tensors). A sparse vector, matrix, or tensor has mostly zero elements. The level of sparsity varies, but when zeroes make up more than 50 percent of any type of array, it can stand to benefit from sparsity-specific computational methods. In contrast, an object that is not sparse—that is, it has few zeros compared with the total number of elements—is called dense.

Sparsity can be naturally present, or it can be induced. For example, a social-network graph will be naturally sparse. Imagine a graph where each node (point) represents a person, and each edge (a line segment connecting the points) represents a friendship. Since most people are not friends with one another, a matrix representing all possible edges will be mostly zeros. Other popular applications of AI, such as other forms of graph learning and recommendation models, contain naturally occurring sparsity as well.

Beyond naturally occurring sparsity, sparsity can also be induced within an AI model in several ways. Two years ago, a team at Cerebras showed that one can set up to 70 to 80 percent of parameters in an LLM to zero without losing any accuracy. Cerebras demonstrated these results specifically on Meta’s open-source Llama 7B model, but the ideas extend to other LLM models like ChatGPT and Claude.

The case for sparsity

Sparse computation’s efficiency stems from two fundamental properties: the ability to compress away zeros and the convenient mathematical properties of zeros. Both the algorithms used in sparse computation and the hardware dedicated to them leverage these two basic ideas.

First, sparse data can be compressed, making it more memory efficient to store “sparsely”—that is, in something called a sparse data type. Compression also makes it more energy efficient to move data when dealing with large amounts of it. This is best understood by an example. Take a four-by-four matrix with three nonzero elements. Traditionally, this matrix would be stored in memory as is, taking up 16 spaces. This matrix can also be compressed into a sparse data type, getting rid of the zeros and saving only the nonzero elements. In our example, this results in 13 memory spaces as opposed to 16 for the dense, uncompressed version. These savings in memory increase with increased sparsity and matrix size.

In addition to the actual data values, compressed data also requires metadata. The row and column locations of the nonzero elements also must be stored. This is usually thought of as a “fibertree”: The row labels containing nonzero elements are listed and linked to the column labels of the nonzero elements, which are then linked to the values stored in those elements.

In memory, things get a bit more complicated still: The row and column labels for each nonzero value must be stored as well as the “segments” that indicate how many such labels to expect, so the metadata and data can be clearly delineated from one another.

In a dense, noncompressed matrix data type, values can be accessed either one at a time or in parallel, and their locations can be calculated directly with a simple equation. However, accessing values in sparse, compressed data requires looking up the coordinates of the row index and using that information to “indirectly” look up the coordinates of the column index before finally reaching the value. Depending on the actual locations of the sparse data values, these indirect lookups can be extremely random, making the computation data-dependent and requiring the allocation of memory lookups on the fly.

Second, two mathematical properties of zero let software and hardware skip a lot of computation. Multiplying any number by zero will result in a zero, so there’s no need to actually do the multiplication. Adding zero to any number will always return that number, so there’s no need to do the addition either.

In matrix-vector multiplication, one of the most common operations in AI workloads, all computations except those involving two nonzero elements can simply be skipped. Take, for example, the four-by-four matrix from the previous example and a vector of four numbers. In dense computation, each element of the vector must be multiplied by the corresponding element in each row and then added together to compute the final vector. In this case, that would take 16 multiplication operations and 16 additions (or four accumulations).

In sparse computation, only the nonzero elements of the vector need be considered. For each nonzero vector element, indirect lookup can be used to find any corresponding nonzero matrix element, and only those need to be multiplied and added. In the example shown here, only two multiplication steps will be performed, instead of 16.

The trouble with GPUs and CPUs

Unfortunately, modern hardware is not well suited to accelerating sparse computation. For example, say we want to perform a matrix-vector multiplication. In the simplest case, in a single CPU core, each element in the vector would be multiplied sequentially and then written to memory. This is slow, because we can do only one multiplication at a time. So instead people use CPUs with vector support or GPUs. With this hardware, all elements would be multiplied in parallel, greatly speeding up the application. Now, imagine that both the matrix and vector contain extremely sparse data. The vectorized CPU and GPU would spend most of their efforts multiplying by zero, performing completely ineffectual computations.

Newer generations of GPUs are capable of taking some advantage of sparsity in their hardware, but only a particular kind, called structured sparsity. Structured sparsity assumes that two out of every four adjacent parameters are zero. However, some models benefit more from unstructured sparsity—the ability for any parameter (weight or activation) to be zero and compressed away, regardless of where it is and what it is adjacent to. GPUs can run unstructured sparse computation in software, for example, through the use of the cuSparse GPU library. However, the support for sparse computations is often limited, and the GPU hardware gets underutilized, wasting energy-intensive computations on overhead.

Petra Péterffy

When doing sparse computations in software, modern CPUs may be a better alternative to GPU computation, because they are designed to be more flexible. Yet, sparse computations on the CPU are often bottlenecked by the indirect lookups used to find nonzero data. CPUs are designed to “prefetch” data based on what they expect they’ll need from memory, but for randomly sparse data, that process often fails to pull in the right stuff from memory. When that happens, the CPU must waste cycles calling for the right data.

Apple was the first to speed up these indirect lookups by supporting a method called an array-of-pointers access pattern in the prefetcher of their A14 and M1 chips. Although innovations in prefetching make Apple CPUs more competitive for sparse computation, CPU architectures still have fundamental overheads that a dedicated sparse computing architecture would not, because they need to handle general-purpose computation.

Other companies have been developing hardware that accelerates sparse machine learning as well. These include Cerebras’s Wafer Scale Engine and Meta’s Training and Inference Accelerator (MTIA). The Wafer Scale Engine, and its corresponding sparse programming framework, have shown incredibly sparse results of up to 70 percent sparsity on LLMs. However, the company’s hardware and software solutions support only weight sparsity, not activation sparsity, which is important for many applications. The second version of the MTIA claims a sevenfold sparse compute performance boost over the MTIA v1. However, the only publicly available information regarding sparsity support in the MTIA v2 is for matrix multiplication, not for vectors or tensors.

Although matrix multiplications take up the majority of computation time in most modern ML models, it’s important to have sparsity support for other parts of the process. To avoid switching back and forth between sparse and dense data types, all of the operations should be sparse.

Onyx

Instead of these halfway solutions, our team at Stanford has developed a hardware accelerator, Onyx, that can take advantage of sparsity from the ground up, whether it’s structured or unstructured. Onyx is the first programmable accelerator to support both sparse and dense computation; it’s capable of accelerating key operations in both domains.

CPUs, CGRAs, and FPGAs represent a trade-off between efficiency and flexibility. Each individual logic unit of a CPU is designed for a specific function that it performs efficiently. On the other hand, since each individual bit of an FPGA is configurable, these arrays are extremely flexible, but very inefficient. The goal of CGRAs is to achieve the flexibility of FPGAs with the efficiency of CPUs.

CGRAs are composed of efficient and configurable units, typically memory and compute, that are specialized for a particular application domain. This is the key benefit of this type of array: Programmers can reconfigure the internals of a CGRA at a high level, making it more efficient than an FPGA but more flexible than a CPU.

The Onyx chip, built on a coarse-grained reconfigurable array (CGRA), is the first (to our knowledge) to support both sparse and dense computations. Olivia Hsu

Onyx is composed of flexible, programmable processing element (PE) tiles and memory (MEM) tiles. The memory tiles store compressed matrices and other data formats. The processing element tiles operate on compressed matrices, eliminating all unnecessary and ineffectual computation.

The Onyx compiler handles conversion from software instructions to CGRA configuration. First, the input expression—for instance, a sparse vector multiplication—is translated into a graph of abstract memory and compute nodes. In this example, there are memories for the input vectors and output vectors, a compute node for finding the intersection between nonzero elements, and a compute node for the multiplication. The compiler figures out how to map the abstract memory and compute nodes onto MEMs and PEs on the CGRA, and then how to route them together so that they can transfer data between them. Finally, the compiler produces the instruction set needed to configure the CGRA for the desired purpose.

Since Onyx is programmable, engineers can map many different operations, such as vector-vector element multiplication, or the key tasks in AI, like matrix-vector or matrix-matrix multiplication, onto the accelerator.

We evaluated the efficiency gains of our hardware by looking at the product of energy used and the time it took to compute, called the energy-delay product (EDP). This metric captures the trade-off of speed and energy. Minimizing just energy would lead to very slow devices, and minimizing speed would lead to high-area, high-power devices.

Onyx achieves up to 565 times as much energy-delay product over CPUs (we used a 12-core Intel Xeon CPU) that utilize dedicated sparse libraries. Onyx can also be configured to accelerate regular, dense applications, similar to the way a GPU or TPU would. If the computation is sparse, Onyx is configured to use sparse primitives, and if the computation is dense, Onyx is reconfigured to take advantage of parallelism, similar to how GPUs function. This architecture is a step toward a single system that can accelerate both sparse and dense computations on the same silicon.

Just as important, Onyx enables new algorithmic thinking. Sparse acceleration hardware will not only make AI more performance- and energy efficient but also enable researchers and engineers to explore new algorithms that have the potential to dramatically improve AI.

The future with sparsity

Our team is already working on next-generation chips built off of Onyx. Beyond matrix multiplication operations, machine learning models perform other types of math, like nonlinear layers, normalization, the softmax function, and more. We are adding support for the full range of computations on our next-gen accelerator and within the compiler. Since sparse machine learning models may have both sparse and dense layers, we are also working on integrating the dense and sparse accelerator architecture more efficiently on the chip, allowing for fast transformation between the different data types. We’re also looking at ways to manage memory constraints by breaking up the sparse data more effectively so we can run computations on several sparse accelerator chips.

We are also working on systems that can predict the performance of accelerators such as ours, which will help in designing better hardware for sparse AI. Longer term, we’re interested in seeing whether high degrees of sparsity throughout AI computation will catch on with more model types, and whether sparse accelerators become adopted at a larger scale.

Building the hardware to unstructured sparsity and optimally take advantage of zeros is just the beginning. With this hardware in hand, AI researchers and engineers will have the opportunity to explore new models and algorithms that leverage sparsity in novel and creative ways. We see this as a crucial research area for managing the ever-increasing runtime, costs, and environmental impact of AI.

Many of the world’s most advanced electronic systems—including Internet routers, wireless base stations, medical imaging scanners, and some artificial intelligence tools—depend on field-programmable gate arrays. Computer chips with internal hardware circuits, the FPGAs can be reconfigured after manufacturing.

On 12 March, an IEEE Milestone plaque recognizing the first FPGA was dedicated at the Advanced Micro Devices campus in San Jose, Calif., the former Xilinx headquarters and the birthplace of the technology.

The FPGA earned the Milestone designation because it introduced iteration to semiconductor design. Engineers could redesign hardware repeatedly without fabricating a new chip, dramatically reducing development risk and enabling faster innovation at a time when semiconductor costs were rising rapidly.

The ceremony, which was organized by the IEEE Santa Clara Valley Section, brought together professionals from across the semiconductor industry and IEEE leadership. Speakers at the event included Stephen Trimberger, an IEEE and ACM Fellowwhose technical contributions helped shape modern FPGA architecture. Trimberger reflected on how the invention enabled software-programmable hardware.

Solving computing’s flexibility-performance tradeoff

FPGAs emerged in the 1980s to address a core limitation in computing. A microprocessor executes software instructions sequentially, making it flexible but sometimes too slow for workloads requiring many operations at once.

At the other extreme, application-specific integrated circuits are chips designed to do only one task. ASICs achieve high efficiency but require lengthy development cycles and nonrecurring engineering costs, which are large, upfront investments. Expenses include designing the chip and preparing it for manufacturing—a process that involves creating detailed layouts, building masks for the fabrication machines, and setting up production lines to handle the tiny circuits.

“ASICs can deliver the best performance, but the development cycle is long and the nonrecurring engineering cost can be very high,” says Jason Cong, an IEEE Fellow and professor of computer science at the University of California, Los Angeles. “FPGAs provide a sweet spot between processors and custom silicon.”

Cong’s foundational work in FPGA design automation and high-level synthesis transformed how reconfigurable systems are programmed. He developed synthesis tools that translate C/C++ into hardware designs, for example.

At the heart of his work is an underlying principle first espoused by electrical engineer Ross Freeman: By configuring hardware using programmable memory embedded inside the chip, FPGAs combine hardware-level speed with the adaptability traditionally associated with software.

Silicon Valley origins: the first FPGA

The FPGA architecture originated in the mid-1980s at Xilinx, a Silicon Valley company founded in 1984. The invention is widely credited to Freeman, a Xilinx cofounder and the startup’s CTO. He envisioned a chip with circuitry that could be configured after fabrication rather than fixed permanently during creation.

Articles about the history of the FPGA emphasize that he saw it as a deliberate break from conventional chip design.

At the time, semiconductor engineers treated transistors as scarce resources. Custom chips were carefully optimized so that nearly every transistor served a specific purpose.

Freeman proposed a different approach. He figured Moore’s Law would soon change chip economics. The principle holds that transistor counts roughly double every two years, making computing cheaper and more powerful. Freeman posited that as transistors became abundant, flexibility would matter more than perfect efficiency.

He envisioned a device composed of programmable logic blocks connected through configurable routing—a chip filled with what he described as “open gates,” ready to be defined by users after manufacturing. Instead of fixing hardware in silicon permanently, engineers could configure and reconfigure circuits as requirements evolved.

Freeman sometimes compared the concept to a blank cassette tape: Manufacturers would supply the medium, while engineers determined its function. The analogy captured a profound shift in who controls the technology, shifting hardware design flexibility from chip fabrication facilities to the system designers themselves.

In 1985 Xilinx introduced the first FPGA for commercial sale: the XC2064. The device contained 64 configurable logic blocks—small digital circuits capable of performing logical operations—arranged in an 8-by-8 grid. Programmable routing channels allowed engineers to define how signals moved between blocks, effectively wiring a custom circuit with software.

Fabricated using a 2-micrometer process (meaning that 2 µm was the minimum size of the features that could be patterned onto silicon using photolithography), the XC2064 implemented a few thousand logic gates. Modern FPGAs can contain hundreds of millions of gates, enabling vastly more complex designs. Yet the XC2064 established a design workflow still used today: Engineers describe the hardware behavior digitally and then “compile the design,” a process that automatically translates the plans into the instructions the FPGA needs to set its logic blocks and wiring, according to AMD. Engineers then load that configuration onto the chip.

The breakthrough: hardware defined by memory

Earlier programmable logic devices, such as erasable programmable read-only memory, or EPROM, allowed limited customization but relied on largely fixed wiring structures that did not scale well as circuits grew more complex, Cong says.

FPGAs introduced programmable interconnects—networks of electronic switches controlled by memory cells distributed across the chip. When powered on, the device loads a bitstream configuration file that determines how its internal circuits behave.

“As process technology improved and transistor counts increased, the cost of programmability became much less significant,” Cong says.

From “glue logic” to essential infrastructure

“Initially, FPGAs were used as what engineers called glue logic,” Cong says.

Glue logic refers to simple circuits that connect processors, memory, and peripheral devices so the system works reliably, according to PC Magazine. In other words, it “glues” different components together, especially when interfaces change frequently.

Early adopters recognized the advantage of hardware that could adapt as standards evolved. In “The History, Status, and Future of FPGAs,” published in Communications of the ACM, engineers at Xilinx and organizations such as Bell Labs, Fairchild Semiconductor, IBM, and Sun Microsystems said the earliest uses of FPGAs were for prototyping ASICs. They also used it for validating complex systems by running their software before fabrication, allowing the companies to deploy specialized products manufactured in modest volumes.

Those uses revealed a broader shift: Hardware no longer needed to remain fixed once deployed.

Attendees at the Milestone plaque dedication ceremony included (seated L to R) 2025 IEEE President Kathleen Kramer, 2024 IEEE President Tom Coughlin, and Santa Clara Valley Section Milestones Chair Brian Berg.Douglas Peck/AMD

Semiconductor economics changed the equation

The rise of FPGAs closely followed changes in semiconductor economics, Cong says.

Developing a custom chip requires a large upfront investment before production begins. As fabrication costs increased, products had to ship in large quantities to make ASIC development economically viable, according to a post published by AnySilicon.

FPGAs allowed designers to move forward without that larger monetary commitment.

ASIC development typically requires 18 to 24 months from conception to silicon, while FPGA implementations often can be completed within three to six months using modern design tools, Cong says. The shorter cycle and the ability to reconfigure the hardware enabled startups, universities, and equipment manufacturers to experiment with advanced architectures that were previously accessible mainly to large chip companies.

Lookup tables and the rise of reconfigurable computing

A popular technique for implementing mathematical functions in hardware isthe lookup table (LUT). A LUT is a small memory element that stores the results of logical operations, according to “LUT-LLM: Efficient Large Language Model Inference with Memory-based Computations on FPGAs,” a paper selected for presentation next month at the 34th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Instead of repeatedly recalculating outcomes, the chip retrieves answers directly from memory. Cong compares the approach to consulting multiplication tables rather than recomputing the arithmetic each time.

Research led by Cong and others helped develop efficient methods for mapping digital circuits onto LUT-based architectures, shaping routing and layout strategies used in modern devices.

As transistor budgets expanded, FPGA vendors integrated memory blocks, digital signal-processing units, high-speed communication interfaces, cryptographic engines, and embedded processors, transforming the devices into versatile computing platforms.

Why the gate arrays are distinct from CPUs, GPUs, and ASICs

FPGAs coexist with other processors because each one optimizes different priorities. Central processing units excel at general computing. Graphics processing units, designed to perform many calculations simultaneously, dominate large parallel workloads such as AI training. ASICs provide maximum efficiency when designs remain stable and production volumes are high.

“ASICs can deliver the best performance, but the development cycle is long, and the nonrecurring engineering cost can be very high. FPGAs provide a sweet spot between processors and custom silicon.” —Jason Cong, IEEE Fellow and professor of computer science at UCLA.

“FPGAs are not replacements for CPUs or GPUs,” Cong says. “They complement those processors in heterogeneous computing systems.”

Modern computing platforms increasingly combine multiple types of processors to balance flexibility, performance, and energy efficiency.

A Milestone for an idea, not just a device

This IEEE Milestone recognizes more than a successful semiconductor product. It also acknowledges a shift in how engineers innovate.

Reconfigurable hardware allows designers to test ideas quickly, refine architectures, and deploy systems while standards and markets evolve.

“Without FPGAs,” Cong says, “the pace of hardware innovation would likely be much slower.”

Four decades after the first FPGA appeared, the technology’s enduring legacy reflects Freeman’s insight: Hardware did not need to remain fixed. By accepting a small amount of unused silicon in exchange for adaptability, engineers transformed chips from static products into platforms for continuous experimentation—turning silicon itself into a medium engineers could rewrite.

Among those who attended the Milestone ceremony were 2025 IEEE President Kathleen Kramer; 2024 IEEE President Tom Coughlin; Avery Lu, chair of the IEEE Santa Clara Valley Section; and Brian Berg, history and milestones chair of IEEE Region 6. They joined AMD’s chief executive, Lisa Su, and Salil Raje, senior vice president and general manager of adaptive and embedded computing at AMD.

The IEEE Milestone plaque honoring the field-programmable gate array reads:

“The FPGA is an integrated circuit with user-programmable Boolean logic functions and interconnects. FPGA inventor Ross Freeman cofounded Xilinx to productize his 1984 invention, and in 1985 the XC2064 was introduced with 64 programmable 4-input logic functions. Xilinx’s FPGAs helped accelerate a dramatic industry shift wherein ‘fabless’ companies could use software tools to design hardware while engaging ‘foundry’ companies to handle the capital-intensive task of manufacturing the software-defined hardware.”

Administered by the IEEE History Center and supported by donors, the IEEE Milestone program recognizes outstanding technical developments worldwide that are at least 25 years old.

Check out Spectrum’s History of Technology channel to read more stories about key engineering achievements.

Think one GPU is very much like another? Think again. It turns out that there’s surprising variability in the performance delivered by chips of the same model. That can make getting your money’s worth by renting time on a GPU from a cloud provider a real roll of the dice, according to research from the College of William & Mary, Jefferson Lab, and Silicon Data.

“It’s called the silicon lottery,” says Carmen Li, founder and CEO of Silicon Data, which tracks GPU rental prices and benchmarks cloud-computing performance.

The silicon lottery’s existence has been known since at least 2022, when researchers at the University of Wisconsin tied it to variations in the performance of GPU-dependent supercomputers. Li and her colleagues figured that the effect would be even more pronounced for AI cloud customers.

Performance varies for GPU models in the cloud

So they ran 6,800 instances of the index firm’s benchmark test on 3,500 randomly selected GPUs operated by 11 cloud-computing providers. The 3,500 GPUs comprised 11 models of Nvidia GPU, the most advanced being the Nvidia H200 SXM. (The team wasn’t just picking on Nvidia; the GPU giant makes up most of the rental cloud market.)

The benchmark, called SiliconMark, is intended to provide a snapshot of a GPU’s ability to run large language models, or LLMs. It tests 16-bit floating-point computing performance, measured in trillions of operations per second, and a GPU’s internal-memory bandwidth, measured in gigabytes per second. The results showed that the computing performance varied for all models, but for the 259 H100 PCIe GPUs it differed by as much as 34.5 percent, and the memory bandwidth of the 253 H200 SXM GPUs varied by as much as 38 percent.

Differences in how the GPU is cooled, how cloud operators configure their computers, and how much use the chip has seen can all contribute to variations in performance of otherwise identical chips. But Silicon Data’s analysis showed that the real culprit was variations in the chips themselves, likely due to manufacturing issues.

Such randomness has real dollars-and-cents consequences, the researchers argue, because there’s a chance that a pricier, more advanced GPU won’t deliver better performance than an older model chip.

So what should GPU renters do? “The most practical approach is to benchmark the actual rental they receive,” says Jason Cornick, head of infrastructure at Silicon Data. “Running a benchmark tool [such as SiliconMark] allows them to compare their specific instance’s performance against a broader corpus of data.”

Two weeks ago, Anthropic announced that its new model, Claude Mythos Preview, can autonomously find and weaponize software vulnerabilities, turning them into working exploits without expert guidance. These were vulnerabilities in key software like operating systems and internet infrastructure that thousands of software developers working on those systems failed to find. This capability will have major security implications, compromising the devices and services we use every day. As a result, Anthropic is not releasing the model to the general public, but instead to a limited number of companies.

The news rocked the internet security community. There were few details in Anthropic’s announcement, angering many observers. Some speculate that Anthropic doesn’t have the GPUs to run the thing, and that cybersecurity was the excuse to limit its release. Others argue Anthropic is holding to its AI safety mission. There’s hype and counterhype, reality and marketing. It’s a lot to sort out, even if you’re an expert.

We see Mythos as a real but incremental step, one in a long line of incremental steps. But even incremental steps can be important when we look at the big picture.

How AI Is Changing Cybersecurity

We’ve written about shifting baseline syndrome, a phenomenon that leads people—the public and experts alike—to discount massive long-term changes that are hidden in incremental steps. It has happened with online privacy, and it’s happening with AI. Even if the vulnerabilities found by Mythos could have been found using AI models from last month or last year, they couldn’t have been found by AI models from five years ago.

The Mythos announcement reminds us that AI has come a long way in just a few years: The baseline really has shifted. Finding vulnerabilities in source code is the type of task that today’s large language models excel at. Regardless of whether it happened last year or will happen next year, it’s been clear for a while this kind of capability was coming soon. The question is how we adapt to it.

We don’t believe that an AI that can hack autonomously will create permanent asymmetry between offense and defense; it’s likely to be more nuanced than that. Some vulnerabilities can be found, verified, and patched automatically. Some vulnerabilities will be hard to find but easy to verify and patch—consider generic cloud-hosted web applications built on standard software stacks, where updates can be deployed quickly. Still others will be easy to find (even without powerful AI) and relatively easy to verify, but harder or impossible to patch, such as IoT appliances and industrial equipment that are rarely updated or can’t be easily modified.

Then there are systems whose vulnerabilities will be easy to find in code but difficult to verify in practice. For example, complex distributed systems and cloud platforms can be composed of thousands of interacting services running in parallel, making it difficult to distinguish real vulnerabilities from false positives and to reliably reproduce them.

So we must separate the patchable from the unpatchable, and the easy to verify from the hard to verify. This taxonomy also provides us guidance for how to protect such systems in an era of powerful AI vulnerability-finding tools.

Unpatchable or hard to verify systems should be protected by wrapping them in more restrictive, tightly controlled layers. You want your fridge or thermostat or industrial control system behind a restrictive and constantly updated firewall, not freely talking to the internet.

Distributed systems that are fundamentally interconnected should be traceable and should follow the principle of least privilege, where each component has only the access it needs. These are bog-standard security ideas that we might have been tempted to throw out in the era of AI, but they’re still as relevant as ever.

Rethinking Software Security Practices

This also raises the salience of best practices in software engineering. Automated, thorough, and continuous testing was always important. Now we can take this practice a step further and use defensive AI agents to test exploits against a real stack, over and over, until the false positives have been weeded out and the real vulnerabilities and fixes are confirmed. This kind of VulnOps is likely to become a standard part of the development process.

Documentation becomes more valuable, as it can guide an AI agent on a bug-finding mission just as it does developers. And following standard practices and using standard tools and libraries allows AI and engineers alike to recognize patterns more effectively, even in a world of individual and ephemeral instant software—code that can be generated and deployed on demand.

Will this favor offense or defense? The defense eventually, probably, especially in systems that are easy to patch and verify. Fortunately, that includes our phones, web browsers, and major internet services. But today’s cars, electrical transformers, fridges, and lampposts are connected to the internet. Legacy banking and airline systems are networked.

In 2020, researchers fine-tuned a GPT-2 model to design fragments of logic circuits; in 2023, researchers used GPT-4 to help design an 8-bit processor with a novel instruction set; by 2024, a variety of LLMs could design and test chips with basic functionality, like dice rolls (though often these were flawed).

Now Verkor.io, an AI chip design startup, claims a bigger milestone: a RISC-V CPU core designed entirely by an agentic AI system. The CPU, dubbed VerCore, has a clock speed of 1.5 gigahertz and performance similar to a 2011-era laptop CPU.

Suresh Krishna, cofounder at Verkor.io, says the team’s key claim is that this approach is more effective than using only specialized AI systems for specialized tasks within the overall design process. “ What we learned is that the better approach is to let the AI agent solve the whole problem,” he says.

Bringing Human Workflows to Agentic AI

Verkor.io’s agentic system is called Design Conductor, and it’s not itself an AI model. It’s a harness for large language models (LLMs). A harness is software that forces an AI agent to proceed through structured steps. In this case, the steps are like those a team of human chip architects would follow: design, implementation, testing, and so on. The harness also manages subagents and a database of related files.

That means it can work autonomously with only an initial prompt—in this case a 219-word design specification—from the user. (The prompt is published in the Design Conductor paper.) It outputs a Graphic Design System II (GDSII) file, which can be used in existing electronic design automation (EDA) software.

Synopsys and Cadence, two major players in EDA software, also have agentic AI tools. These allow chip architects to automate some tasks with AI agents. Design Conductor is different because it’s built to handle chip design from spec to completion with full autonomy, something major EDA companies have not yet touted.

Ravi Krishna, founding engineer at Verkor.io, says Design Conductor’s workflow is “mirrored after the traditional process a human engineer might use.” It analyzes the specification, then writes and debugs a register-transfer level, or RTL, file (an abstraction of the CPU’s data flow) before iterating through subtasks like power delivery, signal timings, and layout, which are again checked against the specification. Some tasks, like layout, call tools to assist the agent. “It’s an iterative system.”

The system took 12 hours to create the VerCore design. That’s not long, but, because it uses AI agents, you might imagine it taking more or less time based on the number of agents thrown at it. However, Ravi Krishna says it’s not that simple, because some design tasks aren’t easily parallelized.

However, the general improvement of AI models over time has proven essential. “I remember that around the middle of last year, we tried to build a floating-point multiplier with the models of that time. It was slightly beyond what they could do,” says Ravi Krishna. VerCore—designed in December 2025— represents an increase in capability since then. “If it can’t do it today, it’ll do it in six months,” he says. “I don’t know if that’s a scary thing or a good thing.”

A First for AI Chip Design

VerCore uses the RISC-V instruction set architecture (ISA), a popular open-standard ISA that’s beginning to break out of niche applications, like storage controllers, into systems on a chip (SoCs) that can power laptops or smartphones. The CPU’s exact clock speed is 1.48 GHz and it achieved a score of 3,261 on the CoreMark processor core benchmark.

Verkor says this puts VerCore’s performance in line with the CPU core performance of Intel’s Celeron SU2300. Whether that sounds impressive depends on your perspective. The Celeron SU2300, which arrived in 2011, uses Intel’s Penryn CPU architecture, which debuted in November of 2007.

In other words, VerCore is no threat to leading-edge CPUs, but it’s notable for two reasons.

VerCore is the first RISC-V CPU core designed by an AI agent. Previous examples of AI chip design presented portions of a design but didn’t present a complete core. Ravi Krishna says the company wanted to target a design that an AI agent hadn’t previously accomplished. “From the perspective of trying to push the limits of what AI models can do, that was interesting to us,” he says.

And while VerCore’s theoretical performance has limits, it’s enough to suggest the design could be useful. Indeed, RISC-V is popular because it provides an ISA that’s free to use (RISC-V is an open standard). RISC-V chips generally aren’t as quick as their x86 and Arm peers, but they’re less expensive.

There’s one final caveat worth mentioning; the chip has not been physically produced. VerCore was verified in simulation with Spike, the reference RISC-V ISA simulator, and laid out using the open-source ASAP7 PDK, an academic design kit that simulates a 7-nanometer production node. Both tools are commonly used for RISC-V design. VerCore says its CPU can run a variant of uCLinux in simulation.

Skeptics will have a chance to judge for themselves. Verkor.io plans to release design files at the end of April. This will include the VerCore CPU and several other designs recently completed by the AI agent system. Verkor also plans to show an FPGA implementation of VerCore at DAC, the leading electronic design automation conference.

Should Chip Designers Worry about AI Agents Taking Their Jobs?

An AI chip designer that can bang out a CPU in 12 hours might seem like troubling news for flesh-and-blood engineers, but Design Conductor has its limitations. The team at Verkor.io say that despite improvements, LLMs still lack the intuition a human can bring.

Design Conductor can fall down rabbit holes that a human engineer would avoid. In one instance the agent made a mistake in timing, meaning that data was not moved across the CPU in agreement with its clock cycle. The model didn’t recognize the cause and made broad changes while hunting for the fix. It did eventually find a fix, but only after reaching many dead ends. “Basically, we are trading off experience for compute,” says David Chin, vice president of engineering at the startup.

Suresh Krishna concurs and adds that Design Conductor’s brute-force approach is likely to become less efficient as agentic systems tackle more complex designs. “It’s a nonlinear design space, so the compute grows very quickly,” he says. “As a practical matter, expert guidance and common sense helps a lot.”

Despite such issues, agentic systems like Design Conductor might accelerate chip design by accelerating iteration. They may also make design accessible to small teams that otherwise lack the resources or head count to pull off a project.

“It’s not at the point where you can have one person. I would say you still need five to ten, all experts in different areas,” says Ravi Krishna. “That team could get you to [a production-ready chip design] at this point.”

A practical guide to designing log-periodic dipole array fed parabolic reflector antennas using advanced 3D MoM simulation — from parametric modeling to electrically large structures.

What Attendees will Learn

1. How to set design requirements for LPDA-fed reflector antennas — Understand the key specifications including bandwidth ratio, gain targets, and VSWR matching constraints across the full operating range from 100 MHz to 1 GHz.
2. Why advanced 3D EM solvers enable simulation of electrically large multiscale structures — Learn how higher order basis functions, quadrilateral meshing, geometrical symmetry, and CPU/GPU parallelization extend MoM simulation capability by an order of magnitude.
3. How to apply a systematic three-step design strategy with proven workflow starting with first optimizing the stand-alone LPDA for VSWR and gain, then integrating the reflector, and finally tuning parameters to satisfy all performance requests including gain and impedance matching.
4. How parametric CAD modeling accelerates LPDA design — Discover how self-scaling geometry, automated wire-to-solid conversion, and multiple-copy-with-scaling features enable fully parametrized antenna models that streamline optimization across dozens of design variants.

On 8 January 2026, the Iranian government imposed a near-total communications shutdown. It was the country’s first full information blackout: For weeks, the internet was off across all provinces while services including the government-run intranet, VPNs, text messaging, mobile calls, and even landlines were severely throttled. It was an unprecedented lockdown that left more than 90 million people cut off not only from the world, but from one another.

Since then, connectivity has never fully returned. Following U.S. and Israeli airstrikes in late February, Iran again imposed near-total restrictions, and people inside the country again saw global information flows dry up.

The original January shutdown came amid nationwide protests over the deepening economic crisis and political repression, in which millions of people chanted antigovernment slogans in the streets. While Iranian protests have become frequent in recent years, this was one of the most significant uprisings since the Islamic Revolution in 1979. The government responded quickly and brutally. One report put the death toll at more than 7,000 confirmed deaths and more than 11,000 under investigation. Many sources believe the death toll could exceed 30,000.

Thirteen days into the January shutdown, we at NetFreedom Pioneers (NFP) turned to a system we had built for exactly this kind of moment—one that sends files over ordinary satellite TV signals. During the national information vacuum, our technology, called Toosheh, delivered real-time updates into Iran, offering a lifeline to millions starved of trusted information.

How Iran Censors the Internet

I joined NetFreedom Pioneers, a nonprofit focused on anticensorship technology, in 2014. Censorship in Iran was a defining feature of my youth in the 1990s. After the Islamic Revolution, most Iranians began to lead double lives—one at home, where they could drink, dance, and choose their clothing, and another in public, where everyone had to comply with stifling government laws.

Iran’s internet infrastructure is more centralized than in other parts of the world, making it easier for the government to restrict the flow of information. Morteza Nikoubazl/NurPhoto/Getty Images

That openness didn’t last. As internet use spread in the early 2000s, the Iranian government began reshaping the network itself. Unlike the highly distributed networks in the United States or Europe, where thousands of providers exchange traffic across many independent routes, Iran’s connection to the global internet is relatively centralized. Most international traffic passes through a small number of gateways controlled by state-linked telecom operators. That architecture gives authorities unusual leverage: By restricting or withdrawing those connections, they can sharply reduce the country’s access to the outside world.

Over the past decade, Iran has expanded this control through what it calls the National Information Network, a domestically routed system designed to keep data inside the country whenever possible. Many government services, banking systems, and local platforms are hosted on this internal network. During periods of unrest, access to the global internet can be throttled or cut off while portions of this domestic network continue to function.

The government began its censorship campaign by redirecting or blocking websites. As internet use grew, it adopted more sophisticated approaches. For example, the Telecommunication Company of Iran uses a technique called deep packet inspection to analyze the content of data packets in real time. This method enables it to identify and block specific types of traffic, such as VPN connections, messaging apps, social media platforms, and banned websites.

The Stealth of Satellite Transmissions

Toosheh’s communication workaround builds on a history of satellite TV adoption in Middle Eastern and North African countries. By the early 2000s, satellite dishes were common in Iran; today the majority of households in Iran have access to satellite TV despite its official prohibition.

Unlike subscription services such as DirecTV and Dish Network, “free-to-air” satellite TV broadcasts are unencrypted and can be received by anyone with a dish and receiver—no subscription required. Because the signals are open, users can also capture and store the data they carry, rather than simply watching it live. Tech-savvy people learned that they could use a digital video broadcasting (DVB) card—a piece of hardware that connects to a computer and tunes into satellite frequencies—to transform a personal computer into a satellite receiver. This way, they could watch and store media locally as well as download data from dedicated channels.

Many Iranian citizens have free-to-air satellite dishes, like the ones on this apartment building in Tehran, and can thus download Toosheh transmissions, giving them a lifeline during internet blackouts.Morteza Nikoubazl/NurPhoto/Getty Images

Toosheh, a Persian word that translates to “knapsack,” is the brainchild of Mehdi Yahyanejad, an Iranian-American technologist and entrepreneur. Yahyanejad cofounded NetFreedom Pioneers in 2012. He proposed that the satellite-computer connections enabled by a DVB card could be re-created in software, eliminating the need for specialized hardware. He added a simple digital interface to the software to make it easy for anyone to use. The next breakthrough came when the NFP team developed a new transfer protocol that tricks ordinary satellite receivers into downloading data alongside audio and video content. Thus, Toosheh was born.

Satellite TV uses a file system called an MPEG transport stream that allows multiple audio, video, or data layers to be packaged into a single stream file. When you tune in to a satellite channel and select an audio option or closed captions, you’re accessing data stored in different parts of this stream. The NFP team’s insight was that, by piggybacking on one of these layers, Toosheh could send an MPEG stream that included documents, videos, and more.

HOW TOOSHEH WORKS: At NetFreedom Pioneers, content curators pull together files—news articles, videos, audio, and software [1]. Toosheh’s encoder software [2] compresses the files into a bundle, in .ts format, creating an MPEG transport stream [3]. From there, it’s uploaded to a server for transmission [4] via a free-to-air TV channel on a Yahsat satellite that’s positioned over the Middle East to provide regional coverage [5]. Satellite receivers [6] directly capture the data streams, which are downloaded to computers, smartphones, and other devices, and decoded by Toosheh software [8].Chris Philpot

A satellite receiver can’t tell the difference between our data and normal satellite audio and video data since it only “sees” the MPEG streams, not what’s encoded on them. This means the data can be downloaded and read, watched, and saved on local devices such as computers, smartphones, or storage devices. What’s more, the system is entirely private: No one can detect whether someone has received data through Toosheh; there are no traceable logs of user activity.

Toosheh doesn’t provide internet access, but rather delivers curated data through satellite technology. The fundamental distinction lies in the way users interact with the system. Unlike traditional internet services, where you type a request into your browser and receive data in response, Toosheh operates more like a combination of radio and television, presenting information in a magazine-like format. Users don’t make requests; instead, they receive 1 to 5 gigabytes of prepackaged, carefully selected data.

Access to information is not only about news or politics, but about exposure to possibilities.

During this year’s internet blackout, we distributed official statements from Iranian opposition leader Crown Prince Reza Pahlavi and the U.S. government. We provided first-aid tutorials for medics and injured protesters. We sent uncensored news reports from BBC Persian, Iran International, IranWire, VOA Farsi, and others. We also shared critical software packages including anticensorship and antisurveillance tools, along with how-to guides to help people securely connect to Starlink satellite terminals, allowing them to stay protected and anonymous as they sent their own communications.

How to Combat Signal Interference

Because Toosheh relies on one-way satellite broadcasts, it evades the usual tactics governments use to block internet access. However, it remains vulnerable to satellite signal jamming.

The Iranian government is notorious for deploying signal jamming, especially in larger cities. In 2009, the government used uplink interference, which attacks the satellite in orbit by beaming strong noise in the frequency of the satellite’s receiver. This makes it impossible for the satellite to distinguish the information it’s supposed to receive. However, because this type of attack temporarily disables the entire satellite, Iran was threatened with international sanctions and in 2012 stopped using the method .

A graph of network connectivity in Iran shows that on 9 January 2026, internet access dropped from nearly 100 percent to 0. Samuel Boivin/NurPhoto/Getty Images

The current method, called terrestrial jamming, uses antennas installed at higher elevations than the surrounding buildings to beam strong noise over a specific area in the frequency range of household receivers. This attack is effective in keeping some of the packets from arriving and damaging others, effectively jamming the transmission. But it’s short-range and requires significant power, so it’s impossible to implement nationwide. There are always people somewhere who can still watch TV, download from Toosheh, or tune into a satellite radio despite the jamming. Even so, we wanted a workaround that would keep our transmissions broadly accessible.

NFP’s solution was to add redundancy, similar in principle to a data-storage technique called RAID (redundant array of independent disks). Instead of sending each piece of data once, we send extra information that allows missing or corrupted packets to be reconstructed. Under normal circumstances, we often use 5 percent of our bandwidth for this redundancy. During periods of active jamming, we increase that to as much as 25 to 30 percent, improving the chances that users can recover complete files despite interference.

From Crisis Response to Public Access

Toosheh initially came online in 2015 in Iran and Afghanistan. Its full potential, however, was first realized during the 2019 protests in Iran, which saw the most widespread internet shutdown prior to the blackout this year. Wired called the 2019 shutdown “the most severe disconnection” tracked by NetBlocks in any country in terms of its “technical complexity and breadth.” Our technology helped thousands of people stay informed. We sent crucial local updates, legal-aid guides, digital security tools, and independent news to satellite receivers all over the country, seeing a sixfold increase in our user base.

When that wave of protests subsided, the government allowed some communication services to return. People were again able to access the free internet using VPNs and other antifilter software that allowed them to bypass restrictions. Toosheh then became a public access point for news, educational material, and entertainment beyond government filtering.

Toosheh’s impact is often personal. A traveling teacher in western Iran told NFP that he regularly distributed Toosheh files to students in remote villages. One package included footage of female athletes competing in the Olympic Games, something never broadcast in Iran. For one young girl, it was the first time she realized women could compete professionally in sports. That moment underscores a broader truth: Access to information is not only about news or politics, but about exposure to possibilities.

The Cost of Toosheh

Unlike internet-based systems, Toosheh’s operational cost remains constant regardless of the number of users. A single TV satellite in geostationary earth orbit, deployed and maintained by an international company such as Eutelsat, can broadcast to an entire continent with no increase in cost to audiences. What’s more, the startup cost for users isn’t high: A satellite dish and receiver in Iran costs less than US $50, which is affordable to many. And it costs nothing for people to use Toosheh’s service and receive its files.

We aim not just to build a tool for censorship circumvention, but to redefine access itself.

However, operating the service is costly: NetFreedom Pioneers pays tens of thousands of dollars a month for satellite bandwidth. We had received funding from the U.S. State Department, but in August of 2025, that funding ended, forcing us to suspend services in Iran.

Then the December protests happened, and broadcasting to Iran became an urgent priority. To turn Toosheh back on, we needed roughly $50,000 a month. With the support of a handful of private donors, we were able to meet these costs and sustain operations in Iran for a few months, though our future there and elsewhere is uncertain.

Satellites Against Censorship

Toosheh’s revival in Iran came alongside NFP’s ongoing support for deployments of Starlink, a satellite internet service that allows users to connect directly to satellites rather than relying on domestic networks, which the government can shut down. Unlike Toosheh’s one-way broadcasts, Starlink provides full two-way internet access, enabling users to send messages, upload videos, and communicate with the outside world.

In 2022, we started gathering donations to buy Starlink terminals for Iran. We have delivered more than 300 of the roughly 50,000 there, enabling citizens to send encrypted updates and videos to us from inside the country. Because the technology is banned by the government, access remains limited and carries risk; Iranian authorities have recently arrested Starlink users and sellers. And unlike Toosheh’s receive-only broadcasts, Starlink terminals transmit signals back to orbit, creating a radio footprint that can potentially be detected.

The internet shutdown in Iran continued after the attacks by Israel and the United States began in late February, preventing Iranians from communicating with the outside world and with one another.Fatemeh Bahrami/Anadolu/Getty Images

Looking ahead, we envision Toosheh becoming a foundational part of global digital resilience. It is uncensored, untraceable, and resistant to government shutdowns. Because Toosheh is downlink only, it can sometimes feel hard to explain the value of this technology to those living in the free world, those accustomed to open internet access. Yet, people living under censorship have few other choices when there’s a digital blackout.

Currently, NFP is developing new features like intelligent content curation and automatically prioritizing data packages based on geographic or situational needs. And we’re experimenting with local sharing tools that allow users who receive Toosheh broadcasts to redistribute those files via Wi-Fi hotspots or other offline networks, which could extend the system’s reach to disaster zones, conflict areas, and climate-impacted regions where infrastructure may be destroyed.

We’re also looking at other use cases. Following the Taliban’s return to power in Afghanistan, NetFreedom Pioneers designed a satellite-based system to deliver educational materials. Our goal is to enable private, large-scale distribution of coursework to anyone—including the girls who are banned from Afghanistan’s schools. The system is technically ready but has yet to secure funding for deployment.

We aim not just to build a tool for censorship circumvention, but to redefine access itself. Whether in an Iranian city under surveillance, a Guatemalan village without internet, or a refugee camp in East Africa, Toosheh offers a powerful and practical model for delivering vital information without relying on vulnerable or expensive networks.

Toosheh is a reminder that innovation doesn’t have to mean complexity. Sometimes, the most transformative ideas are the simplest, like delivering data through the sky, quietly and affordably, into the hands of those who need it most.

This article appears in the May 2026 print issue as “The Stealth Signals Bypassing Iran’s Internet Blackout.”

The race to transition online security protocols to ones that can’t be cracked by a quantum computer is already on. The algorithms that are commonly used today to protect data online—RSA and elliptic curve cryptography—are uncrackable by supercomputers, but a large enough quantum computer would make quick work of them. There are algorithms secure enough to be out of reach for both classical and future quantum machines, called post-quantum cryptography, but transitioning to these is a work in progress.

Late last month, the team at Google Quantum AI published a whitepaper that added significant urgency to this race. In it, the team showed that the size of a quantum computer that would pose a cryptographic threat is approximately 20 times smaller than previously thought. This is still far from accessible to the quantum computers that exist today: The largest machines currently consist of approximately 1,000 quantum bits, or qubits, and the whitepaper estimated that about 500 times as much is needed. Nonetheless, this shortens the timeline to switch over to post-quantum algorithms.

The news had a surprising beneficiary: Obscure cryptocurrency Algorand jumped 44% in price in response. The whitepaper called out Algorand specifically for implementing post-quantum cryptography on their blockchain. We caught up with Algorand’s chief scientific officer and professor of computer science and engineering at the University of Michigan, Chris Peikert, to understand how this announcement is impacting cryptography, why cryptocurrencies are feeling the effects, and what the future might hold. Peikert’s early work on a particular type of algorithm known as lattice cryptography underlies most post-quantum security today.

IEEE Spectrum: What is the significance of this Google Quantum AI whitepaper?

Peikert: The upshot of this paper is that it shows that a quantum computer would be able to break some of the cryptography that is most widely used, especially in blockchains and cryptocurrencies, with much, much fewer resources than had previously been established. Those resources include the time that it would take to do so and the number of qubits (or quantum bits) that it would have to use.

This cryptography is very central to not just cryptocurrencies, but more broadly to cryptography on the internet. It is also used for secure web connections between web browsers and web servers. Versions of elliptic curve cryptography are used in national security systems and military encryption. It’s very prevalent and pervasive in all modern networks and protocols.

And not only was this paper improving the algorithms, but there was also a concurrent paper showing that the hardware itself was substantially improved. The claim here was that the number of physical qubits needed to achieve a certain kind of logical qubit was also greatly reduced. These two kinds of improvements are compounding upon each other. It’s a kind of a win-win situation from the quantum computing perspective, but a lose-lose situation for cryptography.

IEEE Spectrum: What do Google AI’s findings mean for cryptocurrencies and the broader cybersecurity ecosystem?

Peikert: There’s always been this looming threat in the distance of quantum computers breaking a large fraction of the cryptography that’s used throughout the cryptocurrency ecosystem. And I think what this paper did was really the loudest alarm yet that these kinds of quantum attacks might not be as far off as some have suspected, or hoped, in recent years. It’s caused a reevaluation across the industry, and a moving up of the timeline for when quantum computers might be capable of breaking this cryptography.

When we think about the timelines and when it’s important to have completed these transitions [to post-quantum cryptography], we also need to factor in the unknown improvements that we should expect to see in the coming years. The science of quantum computing will not stay static, and there will be these further breakthroughs. We can’t say exactly what they will be or when they will come, but you can bet that they will be coming.

IEEE Spectrum: What is your guess on if or when quantum computers will be able to break cryptography in the real world?

Peikert: Instead of thinking about a specific date when we expect them to come, we have to think about the probabilities and the risks as time goes on. There have been huge breakthrough developments, including not only this paper, but also some last year. But even with these, I think that the chance of a cryptographic attack by quantum computers being successful in the next three years is extremely low, maybe less than a percent. But then, as you get out to several years, like five, six, or 10 years, one has to seriously consider a probability, maybe 5 percent or 10 percent or more. So it’s still rather small, but significant enough that we have to worry about the risk, because the value that is protected by this kind of cryptography is really enormous.

The U.S. government has put 2035 as its target for migrating all of the national security systems to post-quantum cryptography. That seems like a prudent date, given the timelines that it takes to upgrade cryptography. It’s a slow process. It has to be done very deliberately and carefully to make sure that you’re not introducing new vulnerabilities, that you’re not making mistakes, that everything still works properly. So, you know, given the outlook for quantum computers on the horizon, it’s really important that we prepare now, or ideally, yesterday, or a few years ago, for that kind of transition.

IEEE Spectrum: Are there significant roadblocks you see to industrial adoption of post-quantum cryptography going forward?

Peikert: Cryptography is very hard to change. We’ve only had one or maybe two major transitions in cryptography since the early 1980s or late 1970s, when the field first was invented. We don’t really have a systematic way of transitioning cryptography.

An additional challenge is that the performance trade-offs are very different in post-quantum cryptography than they are in the legacy systems. Keys and cipher texts and digital signatures are all significantly larger in post-quantum cryptography, but the computations are actually faster, typically. People have optimized cryptography for speed in the past, and we have very good fast speeds now for post-quantum cryptography, but the sizes of the keys are a challenge.

Especially in blockchain applications, like cryptocurrencies, space on the blockchain is at a premium. So it calls for a reevaluation in many applications of how we integrate the cryptography into the system, and that work is ongoing. And, the blockchain ecosystem uses a lot of advanced cryptography, exotic things like zero-knowledge proofs. In many cases, we have rudimentary constructions of these fancy cryptography tools from post-quantum-type mathematics, but they’re not nearly as mature and industry-ready as the legacy systems that have been deployed. It continues to be an important technical challenge to develop post-quantum versions of these very fancy cryptographic schemes that are used in cutting-edge applications.

IEEE Spectrum: As an academic cryptography researcher, what attracted you to work with a cryptocurrency, and Algorand in particular?

Peikert: My former Ph.D. advisor is Silvio Micali, the inventor of Algorand. The system is very elegant. It is a very high-performing blockchain system, and it uses very little energy, has fast transaction finalization, and a number of other great features. And Silvio appreciated that this quantum threat was real and was coming, and the team approached me about helping to improve the Algorand protocol at the basic levels to become more post-quantum secure in 2021. That was a very exciting opportunity, because it was a difficult engineering and scientific challenge to integrate post-quantum cryptography into all the different technical and cryptographic mechanisms that were underlying the protocol.

IEEE Spectrum: What is the current status of post-quantum cryptography in Algorand, and blockchains in general?

Peikert: We’ve identified some of the most pressing issues and worked our way through some of them, but it’s a many-faceted problem overall. We started with the integrity of the chain itself, which is the transaction history that everybody has to agree upon.

Our first major project was developing a system that would add post-quantum security to the history of the chain. We developed a system called state proofs for that, which is a mixture of ordinary post-quantum cryptography and also some more fancy cryptography: It’s a way of taking a large number of signatures and digesting them down into a much smaller number of signatures, while still being confident that these large number of signatures actually exist and are properly formed. We also followed it with other papers and projects that are about adding post-quantum cryptography and security to other aspects of the blockchain in the Algorand ecosystem.

It’s not a complete project yet. We don’t claim to be fully post-quantum secure. That’s a very challenging target to hit, and there are aspects that we will continue to work on into the near future.

IEEE Spectrum: In your view, will we adopt post-quantum cryptography before the risks actually catch up with us?

Peikert: I tend to be an optimist about these things. I think that it’s a very good thing that more people in decision-making roles are recognizing that this is an important topic, and that these kinds of migrations have to be done. I think that we can’t be complacent about it, and we can’t kick the can down the road much longer. But I do see that the focus is being put on this important problem, so I’m optimistic that most important systems will eventually have good either mitigations or full migrations in place.

But it’s also a point on the horizon that we don’t know exactly when it will come. So, there is the possibility that there is a huge breakthrough, and we have many fewer years than we might have hoped for, and that we don’t get all the systems upgraded that we would like to have fixed by the time quantum computers arrive.

Photonic devices, which rely on light instead of electricity, have the potential to be faster and more energy efficient than today’s electronics. They also present a unique opportunity to develop devices using soft materials, such as polymers and gels, which are poor conductors of electricity but are easier to manufacture and more environmentally friendly. The development of these potentially squishy, flexible photonics, however, requires the ability to manipulate light using only light, not electricity.

In soft matter, that’s been done primarily by changing the physical properties of optical materials or by using intense light pulses to change the direction of light. Now, an international team of scientists has developed a new way of controlling light with light using very low light intensities and without changing any of the physical properties of materials.

Igor Muševič, a professor of physics at the University of Ljubljana who led the project, says that he first got the idea for the device while at a conference in San Francisco, listening to a talk by Stefan W. Hell about stimulated emission depletion (STED) microscopy. The imaging technique, for which Hell won a Nobel Prize in Chemistry in 2014, uses two lasers to produce an extremely small light beam to scan objects. “When I saw this, I said, This is manipulation light by light, right?” Muševič recalls.

His realization inspired a device into which a laser pulse is fired. Whether or not this beam makes it out of the device depends on whether or not a second pulse is fired less than a nanosecond afterwards.

A liquid crystal photonic switch

The device consists of a spherically shaped bead of liquid crystal, held in shape by its elastic material properties and the forces between its molecules, infused with a fluorescent dye and trapped between four upright cone-shaped polymer structures that guide light in and out of the device. When a laser pulse is sent through one of the four polymer waveguides, the light is quickly transferred into the liquid crystal, exciting the fluorescent dye. In a process known as whispering gallery mode resonance, the photons inside the liquid crystal are reflected back inside each time they hit the liquid’s spherical surface. The result is that light circulates inside the cavity until it is eventually reflected into one of the waveguides, which then emits the photons out in a laser beam.

The team realized that sending a second laser pulse of a different color into the waveguides before the liquid crystal started emitting light from the first laser pulse resulted in stimulated emission of the excited dye molecules. The photons from the second laser pulse, which had to be fired into the waveguides after the first laser pulse, interact with the already-excited dye molecules. The interaction causes the dye to emit photons identical to those in the second pulse while depleting the energy from the first pulse. The second laser beam, called the STED beam, is amplified by the process, while the light from the first pulse is so diminished that it isn’t emitted at all. Because the outcome of the first laser pulse could be controlled using the second laser pulse, the team had successfully demonstrated the control of light by light.

Vandna Sharma, Jaka Zaplotnik, et al.

According to the Ljubljana team, the energy efficiency of the liquid crystal approach is much better than previous soft-matter techniques, which had typically involved using intense light fields to change material properties of the soft matter, such as the index of refraction. The new method reduces the energy needed by more than a factor of a hundred. Because the STED laser pulse circulates repeatedly in the crystal, a single photon can deplete many dye molecules of the energy from the first laser pulse.

Miha Ravnik, a theoretical physicist also at the University of Ljubljana who worked on the project, explains that control of light by light is essential in soft-matter photonic logic gates. “You can very much control when [light] is generated and in which direction,” Ravnik says of the light shined into the polymer waveguides. “And this gives you, then, this capability that you create logical operations with light.”

Aside from its potential in photonic logical circuits, the team’s approach presents several technical advantages over photonics made from silicon or other hard materials, Muševič says. For example, using soft matter greatly simplifies the manufacturing process. The liquid crystal in the team’s device can be inserted in less than a second, but manufacturing a similar structure with hard materials is difficult. Additionally, soft-matter devices can be manufactured at much lower temperatures than silicon and other hard materials. Muševič also points out that soft matter presents an opportunity to experiment with the geometry of the device. With liquid crystals “you can make many different kinds of cavities,” says Muševič. “You have, I would say, a lot of engineering space.”

Ravnik is excited for the potential of the team’s breakthrough, particularly as a step toward photonic computing and even photonic neural networks. But, he recognizes that these developments are far down the line. “There’s no way this technology can compete with current neural network implementation at all,” he admits. Still, the possibilities are tantalizing. “The energy losses are predicted to be extremely low, the speeds for calculation extremely high.”

This article is part of our exclusive IEEE Journal Watch series in partnership with IEEE Xplore.

Most people are all too familiar with attempting to type out a password multiple times—only to get locked out of their accounts, triggering a vicious cycle of new passwords that are quickly forgotten. Password managers can be a helpful solution to sidestep this issue but also come with some risk if the saved passwords become compromised.

However, there is a different solution that does not involve saving passwords on a server. Instead, it requires a single master password that is easily remembered or written down on paper.

In a recent study, researchers found that people are willing to complete one extra step to access their accounts using the approach, which they report feeling is more secure and easier to use than traditional manual password entry. The results were published 27 February in IEEE Internet Computing.

HIPPO Password Manager Security

Remembering multiple passwords across various accounts is a challenge for many people. Password managers avoid the need to memorize every single password by storing encrypted passwords in a secure online “vault.” Still, these vaults can be hacked. Malicious attackers can break into the vaults’ servers or steal the passwords by hacking the user’s own computer.

To overcome these challenges, a team of researchers created a password manager that doesn’t store the passwords, called HIPPO (Hidden-Password Online Password), which works like a browser extension.

The user needs to remember or write down only one master password. As they visit each site that requires them to log in, they enter their master password, and then HIPPO generates a site-specific password on the spot.

To do so, HIPPO’s browser extension first applies a cryptographic function called an oblivious pseudorandom function to the master password. The result is a website-specific “masked” password that is sent to the HIPPO server. That server applies its own secret cryptographic key and sends the result back. The browser then removes its temporary mask and uses the result to generate the site-specific password on the spot.

“You can think of it as a calculator computing the exact same complex password on the spot every time you visit the site, eliminating the need to save it anywhere,” says Mohammed Jubur, an assistant professor of computer science at Jazan University, in Saudi Arabia, and co-creator of HIPPO. “Neither the master secret nor the derived site password is ever stored locally or remotely—the fresh-derived [password] is simply autofilled into the target site’s login field.”

User Perception and Trust for Password Managers

In their study, Jubur and colleagues had 25 volunteers provide feedback on HIPPO, comparing it to traditional manual password entry. Participants were tasked with setting up their accounts with a password given to them on a piece of paper. They were then asked to log in to a site 10 times using traditional manual password entry, and another 10 times using HIPPO. Participants rated their experience with each approach, evaluating different factors such as perceived security and ease of use.

The results show that users rated both approaches with a “good” usability score. However, Jubur notes, “participants perceived HIPPO to be significantly more secure and trustworthy compared to traditional password-only authentication.”

Whereas HIPPO received an average score of 4.04 out of 5 for perceived security, traditional manual password entry received a score of 3.09. Users also reported higher trust scores for HIPPO, at 4.00, compared to 3.30 for traditional password entry.

The researchers were surprised to learn that users also reported HIPPO as being easier to use—even though it requires an extra activation step, such as pressing F2 or entering a prefix like “@@” to activate the password-generation mode.

“We initially expected HIPPO’s usability to be merely comparable [to traditional password entry],” explains Nitesh Saxena, a professor in the Department of Computer Science and Engineering and associate director of the Global Cyber Research Institute (GCRI) at Texas A&M University, who co-created HIPPO with Jubur. “However, participants found the cognitive burden of repeatedly typing a complex random password to be so substantial, that even a tool with an extra step improved their experience.”

The researchers note that this was a small-scale, single-session study, so a follow-up study over a longer period is needed to explore HIPPO’s performance.

Jubur adds that, in future work, the team plans to evaluate longer-term life-cycle events, such as measuring the completion time, error rates, and lockout risk associated with HIPPO.

For example, he says, “we also plan to evaluate the user experience and the risk of account lockouts when a user needs to change their master password, which forces them to update their credentials across all their connected websites.”

By many estimates, quantum computers will need millions of qubits to realize their potential applications in cybersecurity, drug development, and other industries. The problem is, anyone who has wanted to simultaneously control millions of a certain kind of qubit has run into the problem of trying to control millions of laser beams.

That’s exactly the challenge that was faced by scientists working on the MITRE Quantum Moonshot project, which brought together scientists from MITRE, MIT, the University of Colorado at Boulder, and Sandia National Laboratories. The solution they developed came in the form of an image projection technology that they realized could also be the fix for a host of other challenges in augmented reality, biomedical imaging, and elsewhere. The device is a 1-square-millimeter photonic chip capable of projecting the Mona Lisa onto an area smaller than the size of two human egg cells.

“When we started, we certainly never would have anticipated that we would be making a technology that might revolutionize imaging,” says Matt Eichenfield, one of the leaders of the Quantum Moonshot project, a collaborative research effort focused on developing a scalable, diamond-based quantum computer, and a professor of quantum engineering at the University of Colorado at Boulder. Each second, their chip is capable of projecting 68.6 million individual spots of light—called scannable pixels—to differentiate them from physical pixels. That’s more than 50 times the capability of previous technology, such as micro-electromechanical systems (MEMS) micromirror arrays.

“We have now made a scannable pixel that is at the absolute limit of what diffraction allows,” says Henry Wen, a visiting researcher at MIT and a photonics engineer at QuEra Computing.

The chip’s distinguishing feature is an array of tiny microscale cantilevers, which curve away from the plane of the chip in response to voltage and act as miniature “ski jumps” for light. Light is channeled along the length of each cantilever via a waveguide and exits at its tip. The cantilevers contain a thin layer of aluminum nitride, a piezoelectric that expands or contracts under voltage, thus moving the micromachine up and down and enabling the array to scan beams of light over a two-dimensional area.

Despite the magnitude of the team’s achievement, Eichenfield says that the process of engineering the cantilevers was “pretty smooth.” Each cantilever is composed of a stack of several submicrometer layers of material and curls approximately 90 degrees out of the plane at rest. To achieve such a high curvature, the team took advantage of differences in the contraction and expansion of individual layers caused by physical stresses in the material resulting from the fabrication process. The materials are first deposited flat onto the chip. Then, a layer in the chip below the cantilever is removed, allowing the material stresses to take effect, releasing the cantilever from the chip and allowing it to curl out. The top layer of each cantilever also features a series of silicon dioxide bars running perpendicular to the waveguide, which keep the cantilever from curling along its width while also improving its lengthwise curvature.

A micro-cantilever wiggles and waggles to project light in the right place.Matt Saha, Y. Henry Wen, et al.

What was more of a challenge than engineering the chip itself was figuring out the details of actually making the chip project images and videos. Working out the process of synchronizing and timing the cantilevers’ motion and light beams to generate the right colors at the right time was a substantial effort, according to Andy Greenspon, a researcher at MITRE who also worked on the project. Now, the team has successfully projected a variety of videos from a single cantilever, including clips from the movie A Charlie Brown Christmas.

The chip projected a roughly 125-micrometer image of the Mona Lisa.Matt Saha, Y. Henry Wen, et al.

Because the chip can project so many more spots in any given time interval than any previous beam scanners, it could also be used to control many more qubits in quantum computers. The Quantum Moonshot program’s mission is to build a quantum computer that can be scaled to millions of qubits. So clearly, it needs a scalable way of controlling each one, explains Wen. Instead of using one laser per qubit, the team realized that not every qubit needed to be controlled at every given moment. The chip’s ability to move light beams over a two-dimensional area would allow them to control all of the qubits with many fewer lasers.

Another process that Wen thinks the chip could improve is scanning objects for 3D printing. Today, that typically involves using a single laser to scan over the entire surface of an object. The new chip, however, could potentially employ thousands of laser beams. “I think now you can take a process that would have taken hours and maybe bring it down to minutes,” says Wen.

Wen is also excited to explore the potential of different cantilever shapes. By changing the orientations of the bars perpendicular to the waveguide, the team has been able to make the cantilevers curl into helixes. Wen says that such unusual shapes could be useful in making a lab-on-a-chip for cell biology or drug development. “A lot of this stuff is imaging, scanning a laser across something, either to image it or to stimulate some response. And so we could have one of these ski jumps curl not just up, but actually curl back around, and then move around and scan over a sample,” Wen explains. “If you can imagine a structure that will be useful for you, we should try it.”

Large language models have already transformed software engineering, for better or worse. Now, so-called large physics models are also starting to transform design engineering. These tools are beginning to replace—or at least amend—the role of full-fledged physics simulation in the automotive and aerospace industries, semiconductor engineering, and more.

Before the advent of computer simulation, a car manufacturer, for example, would create prototypes to test their designs, says Thomas von Tschammer, managing director at physics-based AI company Neural Concept. “For the past 40 years, we reduced a lot of the need for prototypes by using numerical simulations for aerodynamics, for crash testing, and so on.” Now, von Tschammer explains, AI is drastically reducing the need for simulation, the same way simulation reduced the need for physical prototypes.

Growing adoptions of this type of AI was a topic of interest at Nvidia GTC in March. Chris Johnston, senior technical specialist at Jaguar Land Rover, presented how his company is using Neural Concept’s technology. PhysicsX, another physics-based AI company, announced a collaboration with Nvidia to advance open standards for such models, also at GTC.

The AI design engineering workflow

Over the past six months, General Motors (GM) has introduced large physics models into their car design process to speed up the workflow.

Previously, a creative design engineer would develop a 3D model of a new car concept. This model would be sent to aerodynamics specialists, who would run physics simulations to determine the coefficient of drag of the proposed car—an important metric for energy efficiency of the vehicle. This simulation phase would take about two weeks, and the aerodynamics engineer would then report the drag coefficient back to the creative designer, possibly with suggested modifications.

Now, GM has trained an in-house large physics model on those simulation results. The AI takes in a 3D car model and outputs a coefficient of drag in a matter of minutes. “We have experts in the aerodynamics and the creative studio now who can sit together and iterate instantly to make decisions [about] our future products,” says Rene Strauss, director of virtual integration engineering at GM.

For GM and other companies, running inference on an AI model trained on physics simulations, instead of running the simulation itself, can bring immense time savings. “Depending on the kinds of physics [being simulated], or the resolution, it can be anywhere between 10,000 to close to a million times faster,” says Jacomo Corbo, CEO and co-founder of PhysicsX.

How accurate are large physics models?

But what about accuracy? For GM’s purposes, Strauss says accuracy is not a huge concern at the design stage because finer details are ironed out later in the process. “When it really starts to matter is when we’re getting close to launching a vehicle, and the coefficient of drag is going to be used for our energy calculation, which eventually goes to the certification of our miles per gallon on the sticker.” At that stage, Strauss says, a physical model of the car will be put into a wind tunnel for an exact number.

PhysicsX’s Corbo argues that, with the right data, the AI model accuracy can supersede the accuracy of the simulation it’s trained on. The trick is to incorporate experimental measurements to fine-tune the model. If a physics simulation doesn’t agree exactly with experimental data, it is often difficult to figure out why and tweak the model until they agree. With AI, incorporating a few experimental examples into the training process is a lot more straightforward, and it’s not necessary to understand where exactly the model went wrong.

All in all, by drastically bringing down the time it takes to model the physics, large physics models enable engineers to explore a much greater range of possibilities before a final design is reached.

Training large physics models

There is no one-size-fits-all approach to training large physics models. Depending on the types of data available, and the physics in question, the models may use the transformer architecture that underlies LLMs, a generalized version of convolutional neural networks known as geometric deep learning, or an architecture that can solve partial differential equations called neural operators.

Currently, most companies are training their own models on their simulation data, catering to specific use cases. In GM’s aerodynamics implementation, there are different AI models for different types of cars: think SUVs versus sedans. But PhysicsX’s Corbo says his team is working on building more “foundational” physics models that can be applied across different scenarios.

Both LLMs and robotics have benefited from scaling laws, which describe how a system improves as the models increase in size or get trained on more data. In AI, models tend to improve quickly, in a nonlinear way. Along the way, the models also become more generalizable—extending them to new settings takes less and less fine-tuning to reach the same accuracy. Corbo says his team is now starting to see the same types of scaling laws for large physics models.

“What we’re seeing here is maybe a little bit unsurprising,” Corbo says, “but it’s also pretty incredible. And it’s given us the confidence to make these models bigger, because they perform a whole lot better, and they cover broader domains, and they have these really amazing emergent properties.”

Developing open standards for the data formats used in training, as well as the model architectures, should help develop these more powerful foundational models. That’s the goal of PhysicsX’s collaboration with Nvidia, and of Nvidia’s physicsNeMo open source platform.

“The thing that we’re collaborating on is being able to compose architectures from building blocks,” Corbo says, making it easy for those in both academia and industry to reuse and build upon existing models.

A type of AI called a large physics model is used by an engineer to quickly generate heat flow in a 3D data center server design. Neural Concept

The long-term role of simulations and engineers

While some are working on developing more powerful models, others are pushing to implement what’s already available into existing workflows, which is no easy task. “With any innovation, it’s not a straight line. There’s some steps forward and then some steps back and improvements that we find along the way. But that’s part of the joy of the innovation process and using new tools like this,” GM’s Strauss says.

This technology is still in the early stages, and it’s unclear what the final role of AI tools will be in the engineering workflow. For one, opinions vary on whether AI will replace simulations completely, or just reduce their use.

“We will never fully replace simulations,” Neural Concept’s von Tschammer says. “But the idea is to make a much smarter usage of simulation at the most major phase of developments, and you use AI to speed up the early design stages, where you need to explore a very wide set of options.”

PhysicsX’s Corbo begs to differ. “The whole idea is to take numerical simulation … out of the workflow,” he says, “and to move that to inference.”

Whatever the role of simulation will be, everyone in the field is adamant that human design engineers will continue to be in the driver’s seat, enabled by these newfangled tools to do their best work. (After all, when has AI ever threatened to replace human labor?)

“What we’re seeing is that actually, these tools are empowering the engineers to be much more efficient,” von Tschammer says. “Before, these engineers would spend a lot of time on low-added-value tasks, whereas now these manual tasks from the past can be automated using these AI models, and the engineers can focus on taking the design decisions at the end of the day. We still need engineers more than ever.”

Artificial intelligence harbors an enormous energy appetite. Such constant cravings are evident in the hefty carbon footprint of the data centers behind the AI boom and the steady increase over time of carbon emissions from training frontier AI models.

No wonder big tech companies are warming up to nuclear energy, envisioning a future fueled by reliable, carbon-free sources. But while nuclear-powered data centers might still be years away, some in the research and industry spheres are taking action right now to curb AI’s growing energy demands. They’re tackling training as one of the most energy-intensive phases in a model’s life cycle, focusing their efforts on decentralization.

Decentralization allocates model training across a network of independent nodes rather than relying on one platform or provider. It allows compute to go where the energy is—be it a dormant server sitting in a research lab or a computer in a solar-powered home. Instead of constructing more data centers that require electric grids to scale up their infrastructure and capacity, decentralization harnesses energy from existing sources, avoiding adding more power into the mix.

Hardware in harmony

Training AI models is a huge data center sport, synchronized across clusters of closely connected GPUs. But as hardware improvements struggle to keep up with the swift rise in the size of large language models, even massive single data centers are no longer cutting it.

Tech firms are turning to the pooled power of multiple data centers—no matter their location. Nvidia, for instance, launched the Spectrum-XGS Ethernet for scale-across networking, which “can deliver the performance needed for large-scale single job AI training and inference across geographically separated data centers.” Similarly, Cisco introduced its 8223 router designed to “connect geographically dispersed AI clusters.”

Other companies are harvesting idle compute in servers, sparking the emergence of a GPU-as-a-Service business model. Take Akash Network, a peer-to-peer cloud computing marketplace that bills itself as the “Airbnb for data centers.” Those with unused or underused GPUs in offices and smaller data centers register as providers, while those in need of computing power are considered as tenants who can choose among providers and rent their GPUs.

“If you look at [AI] training today, it’s very dependent on the latest and greatest GPUs,” says Akash cofounder and CEO Greg Osuri. “The world is transitioning, fortunately, from only relying on large, high-density GPUs to now considering smaller GPUs.”

Software in sync

In addition to orchestrating the hardware, decentralized AI training also requires algorithmic changes on the software side. This is where federated learning, a form of distributed machine learning, comes in.

It starts with an initial version of a global AI model housed in a trusted entity such as a central server. The server distributes the model to participating organizations, which train it locally on their data and share only the model weights with the trusted entity, explains Lalana Kagal, a principal research scientist at MIT’s Computer Science and Artificial Intelligence Laboratory (CSAIL) who leads the Decentralized Information Group. The trusted entity then aggregates the weights, often by averaging them, integrates them into the global model, and sends the updated model back to the participants. This collaborative training cycle repeats until the model is considered fully trained.

But there are drawbacks to distributing both data and computation. The constant back-and-forth exchanges of model weights, for instance, result in high communication costs. Fault tolerance is another issue.

“A big thing about AI is that every training step is not fault-tolerant,” Osuri says. “That means if one node goes down, you have to restore the whole batch again.”

To overcome these hurdles, researchers at Google DeepMind developed DiLoCo, a distributed low-communication optimization algorithm. DiLoCo forms what Google DeepMind research scientist Arthur Douillard calls “islands of compute,” where each island consists of a group of chips. Every island holds a different chip type, but chips within an island must be of the same type. Islands are decoupled from each other, and synchronizing knowledge between them happens once in a while. This decoupling means islands can perform training steps independently without communicating as often, and chips can fail without having to interrupt the remaining healthy chips. However, the team’s experiments found diminishing performance after eight islands.

An improved version, dubbed Streaming DiLoCo, further reduces the bandwidth requirement by synchronizing knowledge “in a streaming fashion across several steps and without stopping for communicating,” says Douillard. The mechanism is akin to watching a video even if it hasn’t been fully downloaded yet. “In Streaming DiLoCo, as you do computational work, the knowledge is being synchronized gradually in the background,” he adds.

AI development platform Prime Intellect implemented a variant of the DiLoCo algorithm as a vital component of its 10-billion-parameter INTELLECT-1 model trained across five countries spanning three continents. Upping the ante, 0G Labs, makers of a decentralized AI operating system, adapted DiLoCo to train a 107-billion-parameter foundation model under a network of segregated clusters with limited bandwidth. Meanwhile, popular open-source deep learning framework PyTorch included DiLoCo in its repository of fault-tolerance techniques.

“A lot of engineering has been done by the community to take our DiLoCo paper and integrate it in a system learning over consumer-grade internet,” Douillard says. “I’m very excited to see my research being useful.”

A more energy-efficient way to train AI

With hardware and software enhancements in place, decentralized AI training is primed to help solve AI’s energy problem. This approach offers the option of training models “in a cheaper, more resource-efficient, more energy-efficient way,” says MIT CSAIL’s Kagal.

And while Douillard admits that “training methods like DiLoCo are arguably more complex, they provide an interesting trade-off of system efficiency.” For instance, you can now use data centers across far apart locations without needing to build ultrafast bandwidth in between. Douillard adds that fault tolerance is baked in because “the blast radius of a chip failing is limited to its island of compute.”

Even better, companies can take advantage of existing underutilized processing capacity rather than continuously building new energy-hungry data centers. Betting big on such an opportunity, Akash created its Starcluster program. One of the program’s aims involves tapping into solar-powered homes and employing the desktops and laptops within them to train AI models. “We want to convert your home into a fully functional data center,” Osuri says.

Osuri acknowledges that participating in Starcluster will not be trivial. Beyond solar panels and devices equipped with consumer-grade GPUs, participants would also need to invest in batteries for backup power and redundant internet to prevent downtime. The Starcluster program is figuring out ways to package all these aspects together and make it easier for homeowners, including collaborating with industry partners to subsidize battery costs.

Back-end work is already underway to enable homes to participate as providers in the Akash Network, and the team hopes to reach its target by 2027. The Starcluster program also envisions expanding into other solar-powered locations, such as schools and local community sites.

Decentralized AI training holds much promise to steer AI toward a more environmentally sustainable future. For Osuri, such potential lies in moving AI “to where the energy is instead of moving the energy to where AI is.”

This year marks the 80th anniversary of ENIAC, the first general-purpose digital computer. The computer was built during World War II to speed up ballistics calculations, but its contributions to computing extend well beyond military applications.

Two of ENIAC’s key architects—John W. Mauchly, its co-inventor, and Kathleen “Kay” McNulty, one of the six original programmers—married a few years after its completion and raised seven children together. Mauchly and McNulty’s grandchild Naomi Most delivered a talk as part of a celebration in honor of ENIAC’s anniversary on 15 February, which was held online and in-person at the American Helicopter Museum in West Chester, Pa. The following is adapted from that presentation.

RELATED: ENIAC, the First General-Purpose Digital Computer, Turns 80

There was a library at my grandparents’ farmhouse that felt like it went on forever. September light through the windows, beech leaves rustling outside on the stone porch, the sounds of cousins and aunts and uncles somewhere in the house. And in the corner of that library, an IBM personal computer.

When I spent summers there as a child, I didn’t yet know that the computer was closely tied to my family’s story.

My grandparents are known for their contributions to creating the Electronic Numerical Integrator and Computer, or ENIAC. But both were interested in more than just crunching numbers: My grandfather wanted to predict the weather. My grandmother wanted to be a good storyteller.

In Irish, the first language my grandmother Kathleen “Kay” McNulty ever spoke, a word existed to describe both of these impulses: ríomh.

I began to learn the Irish language myself five years ago, and I was struck by how certain words and phrases had multiple meanings. According to renowned Irish cultural historian Manchán Magan—from whom I took lessons—the word ríomh has at different times been used to mean to compute, but also to weave, to narrate, or to compose a poem. That one word that can tell the story of ENIAC, a machine with wires woven like thread that was built to compute, make predictions, and search for a signal in the noise.

John Mauchly’s Weather-Prediction Ambitions

Before working on ENIAC, John Mauchly spent years collecting rainfall data across the United States. His favorite pastime was meteorology, and he wanted to find patterns in storm systems to predict the weather.

The Army, however, funded ENIAC to make simpler predictions: calculating ballistic trajectory tables. Start there, co-inventors J. Presper Eckert and Mauchly realized, and perhaps the weather would soon be computable.

Co-inventors John Mauchly [left] and J. Presper Eckert look at a portion of ENIAC on 25 November 1966. Hulton Archive/Getty Images

Weather is a system unfolding through time, and a model of a storm is a story about how that system might unfold. There’s an old Irish saying related to this idea: Is maith an scéalaí an aimsir. Literally, “weather is a good storyteller.” But aimsir also means time. So the usual translation of this phrase into English becomes “time will tell.”

Mauchly wanted to ríomh an aimsire—to weave the weather into pattern, to compute the storm, to narrate the chaos. He realized that complex systems don’t reveal their full purpose at conception. They reveal it through aimsir—through weather, through time, through use.

ENIAC’s First Programmers Were Weavers

Kathleen “Kay” McNulty was born on 12 February 1921, in Creeslough, Ireland, on the night her father—an IRA training officer—was arrested and imprisoned in Derry Gaol.

Family oral history holds that her people were weavers. She spoke only Irish until her family reached Philadelphia when she was 4 years old, entering American school the following year knowing virtually no English. She graduated in 1942 from Chestnut Hill College with a mathematics degree, was recruited to compute artillery firing tables by hand for the U.S. Army, and was then selected—along with five other women—to program ENIAC.

They had no manual. They had only blueprints.

McNulty and her colleagues learned ENIAC and its quirks the way you learn a loom: by touch, by memory, by routing threads of electricity into patterns. They developed embodied knowledge the designers could only approximate. They could narrow a malfunction to a specific failed vacuum tube before any technician could locate it.

McNulty and Mauchly are also credited with conceiving the subroutine, the sequence of instructions that can be repeatedly recalled to perform a task, now essential in any programming. The subroutine was not in ENIAC’s blueprints, nor in the funding proposal. The concept emerged as highly determined people extended their imagination into the machine’s affordances.

The engineers designed the loom. Weavers discovered its true capabilities.

In 1950, four years after ENIAC was switched on, Mauchly’s dream was realized as it was used in the world’s first computer-assisted weather forecast. That was made possible after Klara von Neumann and Nick Metropolis reassembled and upgraded the ENIAC with a small amount of digital program memory. The programmers who transformed the math into operational code for the ENIAC were Norma Gilbarg, Ellen-Kristine Eliassen, and Margaret Smagorinsky. Their names are not as well-known as they should be.

Before programming ENIAC, Kay McNulty [left] was recruited by the U.S. Army to compute artillery firing tables. Here, she and two other women, Alyse Snyder [center] and Sis Stump, operate a mechanical analog computer designed to solve differential equations in the basement of the University of Pennsylvania’s Moore School of Electrical Engineering.University of Pennsylvania

Kay McNulty, Family Storyteller

Kay married John Mauchly in 1948, describing him as “the greatest delight of my life. He was so intelligent and had so many ideas.... He was not only lovable, he was loving.” She spent the rest of her life ensuring he, Eckert, and the ENIAC programmers would be recognized.

When she died in 2006, I came to her funeral in shock, not fully knowing what I’d lost. As she drifted away, it was said, she had been reciting her prayers in Irish. This understanding made it quickly over to Creeslough, in County Donegal, and awaited me when I visited to honor her memory with the dedication of a plaque right there in the center of town.

In her own memoir, she wrote: “If I am remembered at all, I would like to be remembered as my family storyteller.”

In Irish, the word for computer is ríomhaire. One who ríomhs. One who weaves, computes, and tells. My grandfather wanted to tell the story of the weather through computing. My grandmother wanted to be remembered as a storyteller. The language of her childhood already had a word that contained both of those ambitions.

Computers as Narrative Engines

When it was built, ENIAC looked like the back room of a textile production house. Panels. Switchboards. A room full of wires. Thread.

Thread does not tell you what it will become. We tend to think of computing as calculation—discrete and deterministic. But a model is a structured story about how something behaves.

Weather models, ballistic tables, economic forecasts, neural networks: These are all narrative engines, systems that take raw inputs and produce accounts of how the world might unfold. In complex systems, when parts are woven together through use, new structures arise that no one specified in advance.

Like ENIAC, the machines we are building now—the large models, the autonomous systems—are not merely calculators. They are looms.

Their most important properties will not be specified in advance. They will emerge through use, through the people who learn how to weave with them.

Through imagination.

Through aimsir.

A traditional data center protects the expensive hardware inside it with a “shell” constructed from steel and concrete. Constructing a data center’s shell is inexpensive compared to the cost of the hardware and infrastructure inside it, but it’s not trivial. It takes time for engineers to consider potential sites, apply for permits, and coordinate with construction contractors.

That’s a problem for those looking to quickly deploy AI hardware, which has led companies like Duos Edge AI and LG CNS to respond with a more modular approach. They use pre-fabricated, self-contained boxes that can be deployed in months instead of years. The boxes can operate alone or in tandem with others, providing the option to add more if required.

“I just came back from Nvidia’s GTC, and a lot of [companies] are sitting on their deployment because their data centers aren’t ready, or they can’t find the space,” said Doug Recker, CEO of Duos Edge AI. “We see the demand there, and we can deploy faster.”

GPUs shipped straight to you

Duos Edge AI’s modular compute pods are 55 feet long and 12.5 feet wide. Though they look similar to a shipping container, they’re actually a bit larger and designed primarily for transportation by truck. Each compute pod contains racks of GPUs much like those used in other data centers. Duos recently entered a deal with AI infrastructure company Hydra Host to deploy four pods with 576 GPUs per pod. That’s a total of 2,304 GPUs, with the option to later double the deployment to 4,608 GPUs.

Modular data centers aren’t new for Duos; the company previously deployed edge data centers for rural customers, such as the Amarillo, Texas, school district. However, the pods for the Hydra Host deployment will be upgraded to handle more intense AI workloads. They’ll contain more racks, draw more power, and use liquid cooling to keep the GPUs running efficiently.

Across the Pacific, Korean technology giant LG is taking a similar approach. The company’s CNS subsidiary, which provides IT infrastructure and services, has announced the AI Modular Data Center, which, like the Duos unit, contains racks of GPUs and supporting hardware in a pre-fabricated enclosure.

Also like Duos’ deployment, LG’s AI Modular Data Center contains 576 Nvidia GPUs with the option to scale up in the future. “We are currently developing an expanded version that can support more than 4,600 GPUs within a single unit, with a service launch planned within this year,” said Heon Hyeock Cho, vice president and head of the data center business unit at LG CNS. LG’s first Modular Data Center will roll out in the South Korean port city of Busan, where it could deploy up to 50 units.

LG and Duos are not alone. Hewlett Packard Enterprise, Vertiv, and Schneider Electric now have modular data centers available or in development. A report from market research firm Grand View Research estimates that the market for modular data centers could more than double by 2030.

On the grid, but under the radar

A modular data center site is quite different from a traditional data center because there’s no need to construct a large steel-and-concrete shell. Instead, the site can be made ready by pouring a concrete pad. The pre-fabricated modules are delivered by truck, placed on the pad where desired, and then networked on-site.

Duos’ deployments, for instance, include power modules placed alongside the compute pods, and the pods are networked together with redundant fiber connections that allow the pods to operate in unison. Recker compared it to lining up school buses in a parking lot. “Everything is built off-site at a factory, and we can put it together like a jigsaw puzzle,” he said.

That simplicity is the point. Both Duos and LG CNS expect a modular data center can be deployed in about six months, compared to the roughly two or three years a conventional data center requires. Recker said that, for Duos, the turnaround is so quick that building the pre-fabricated unit isn’t always the constraint. While it’s possible to construct a pre-fabricated unit in 60 or 90 days, site preparation extends the timeline “because you can’t get the permits that fast.”

Modular data centers may also provide good value. Recker said a 5-megawatt modular deployment can be built for about $25 million, and that Duos’ cost per megawatt is roughly half what larger facilities charge. For Duos, savings are possible in part because its modular data centers can target smaller deployments where the permitting is less complex. Smaller, modular deployments also meet less resistance from local governments, which are increasingly skeptical about data center construction.

While Duos targets smaller deployments, LG hopes to go big. Its planned Busan campus of 50 AI Modular Data Centers suggests an ambition to achieve deployments that rival the capacity of conventional facilities. A site with 50 units would bring the total number of GPUs to over 28,000. Here, the benefits of a modular approach could stem mostly from scalability, as a modular data center could start small and grow as required.

“By adopting a modular approach, the AI Modular Data Center can be incrementally expanded through the combination of dozens of AI Boxes,” Cho said. “It’s enabling the construction of even hyperscale-level AI data centers.”

Facial recognition technology (FRT) dates back 60 years. Just over a decade ago, deep-learning methods tipped the technology into more useful—and menacing—territory. Now, retailers, your neighbors, and law enforcement are all storing your face and building up a fragmentary photo album of your life.

Yet the story those photos can tell inevitably has errors. FRT makers, like those of any diagnostic technology, must balance two types of errors: false positives and false negatives. There are three possible outcomes.

In best-case scenarios—such as comparing someone’s passport photo to a photo taken by a border agent—false-negative rates are around two in 1,000 and false positives are less than one in 1 million.

In the rare event you’re one of those false negatives, a border agent might ask you to show your passport and take a second look at your face. But as people ask more of the technology, more ambitious applications could lead to more catastrophic errors. Let’s say that police are searching for a suspect, and they’re comparing an image taken with a security camera with a previous “mug shot” of the suspect.

Training-data composition, differences in how sensors detect faces, and intrinsic differences between groups, such as age, all affect an algorithm’s performance. The United Kingdom estimated that its FRT exposed some groups, such as women and darker-skinned people, to risks of misidentification as high as two orders of magnitude greater than it did to others.

Less clear photographs are harder for FRT to process.iStock

What happens with photos of people who aren’t cooperating, or vendors that train algorithms on biased datasets, or field agents who demand a swift match from a huge dataset? Here, things get murky.

Consider a busy trade fair using FRT to check attendees against a database, or gallery, of images of the 10,000 registrants, for example. Even at 99.9 percent accuracy you’ll get about a dozen false positives or negatives, which may be worth the trade-off to the fair organizers. But if police start using something like that across a city of 1 million people, the number of potential victims of mistaken identity rises, as do the stakes.

What if we ask FRT to tell us if the government has ever recorded and stored an image of a given person? That’s what U.S. Immigration and Customs Enforcement agents have done since June 2025, using the Mobile Fortify app. The agency conducted more than 100,000 FRT searches in the first six months. The size of the potential gallery is at least 1.2 billion images.

At that size, assuming even best-case images, the system is likely to return around 1 million false matches, but at a rate at least 10 times as high for darker-skinned people, depending on the subgroup.

Responsible use of this powerful technology would involve independent identity checks, multiple sources of data, and a clear understanding of the error thresholds, says computer scientist Erik Learned-Miller of the University of Massachusetts Amherst: “The care we take in deploying such systems should be proportional to the stakes.”

This sponsored article is brought to you by NYU Tandon School of Engineering.

Within a 6 mile radius of New York University’s (NYU) campus, there are more than 500 tech industry giants, banks, and hospitals. This isn’t just a fact about real estate, it’s the foundation for advancing quantum discovery and application.

While the world races to harness quantum technology, NYU is betting that the ultimate advantage lies not solely in a lab, but in the dense, demanding, and hyper-connected urban ecosystem that surrounds it. With the launch of its NYU Quantum Institute (NYUQI), NYU is positioning itself as the central node in this network; a “full stack” powerhouse built on the conviction that it has found the right place, and the right time, to turn quantum science into tangible reality.

Proximity advantage is essential because quantum science demands it. Globally, the quest for practical quantum solutions — whether for computing, sensing, or secure communications — has been stalled, in part, by fragmentation. Physicists and chemical engineers invent new materials, computer scientists develop new algorithms, and electrical engineers build new devices, but all three often work in isolated academic silos.

Gregory Gabadadze, NYU’s dean for science, NYU physicist and Quantum Institute Director Javad Shabani, and Juan de Pablo, Anne and Joel Ehrenkranz Executive Vice President for Global Science and Technology and executive dean of the Tandon School of Engineering.Veselin Cuparić/NYU

NYUQI’s premise is that breakthroughs happen “at the interfaces between different domains,” according to Juan de Pablo, Executive Vice President for Global Science and Technology at NYU and Executive Dean of the NYU Tandon School of Engineering. The Institute is built to actively force those necessary collisions — to integrate the physicists, engineers, materials scientists, computer scientists, biologists, and chemists vital to quantum research into one holistic operation. This institutional design ensures that the hardware built by one team can be immediately tested by software developed by another, accelerating progress in a way that isolated departments never could.

NYUQI’s premise is that breakthroughs happen at the interfaces between different domains. —Juan de Pablo, NYU Tandon School of Engineering

NYUQI’s integrated vision is backed by a massive physical commitment to the city. The NYUQI is not just a theoretical concept; its collaborators will be housed in a renovated, million-square-foot facility in the heart of Manhattan’s West Village, backed by a state-of-the-art Nanofabrication Cleanroom in Brooklyn serving as a high-tech foundry. This is where the theoretical meets physical devices, allowing the Institute to test and refine the process from materials science to deployment.

NYUQI will be housed in a renovated, million-square-foot facility in the heart of Manhattan’s West Village.Tracey Friedman/NYU

Leading this effort is NYUQI Director Javad Shabani, who, along with the other members, is turning the Institute into a hub for collaboration with private and public sector partners with quantum challenges that need solving. As de Pablo explains, “Anybody who wants to work on quantum with NYU, you come in through that door, and we’ll send you to the right place.” For New York’s vast ecosystem of tech giants and financial institutions, the NYUQI offers a resource they can’t build on their own: a cohesive team of experts in quantum phenomena, quantum information theory, communication, computing, materials, and optics, and a structured path to applying theoretical discoveries to advanced quantum technologies.

Solving the Challenge of Quantum Research

The NYUQI’s integrated structure is less about organizational management, and more about scientific requirement. The challenge of quantum is that the hardware, the software, and the programming are inherently interconnected — each must be designed to work with the other. To solve this, the Institute focuses on three applications of quantum science: Quantum Computing, Quantum Sensing, and Quantum Communications.

For Shabani, this means creating an integrated environment that bridges discovery with experimentation, starting with the physical components all the way to quantum algorithm centers. That will include a fabrication facility in the new building in Manhattan, as well as the NYU Nanofab in Brooklyn directed by Davood Shahjerdi. New York Senators Charles Schumer and Kirsten Gillibrand recently secured $1 million in congressionally-directed spending to bring Thermal Laser Epitaxy (TLE) technology — which allows for atomic-level purity, minimal defects, and streamlined application of a diverse range of quantum materials — to NYU, marking the first time the equipment will be used in the U.S.

NYU Nanofab manager Smiti Bhattacharya and Nanofab Director Davood Shahjerdi at the nanofab ribbon-cutting in 2023. The nanofab is the first academic cleanroom in Brooklyn, and serves as a prototyping facility for the NORDTECH Microelectronics Commons consortium.NYU WIRELESS

Tight control over fabrication, and can allow researchers to pivot quickly when a breakthrough in one area — say, finding a cheaper, more reliable material like silicon carbide — can be explored for use across all three applications, and offers unique access to academics and the private sector alike to sophisticated pieces of specialty equipment whose maintenance knowledge and costs make them all-but-impossible to maintain outside of the right staffing and environment.

The NYU Nanofab is Brooklyn’s first academic cleanroom, with a strategic focus on superconducting quantum technologies, advanced semiconductor electronics, and devices built from quantum heterostructures and other next-generation materials.NYU Nanofab

That speed and adaptability is the NYUQI’s competitive edge. It turns fragmented challenges into holistic solutions, positioning the Institute to solve real-world problems for its New York neighbors—from highly secure data transmission to next-generation drug discovery.

Testing Quantum Communication in NYC

The integrated approach also makes the NYUQI a testbed for the most critical near-term applications. Take Quantum Communications, which is essential for creating an “unhackable” quantum internet. In an industry first, NYU worked with the quantum start-up Qunnect to send quantum information through standard telecom fiber in New York City between Manhattan and Brooklyn through a 10-mile quantum networking link. Instead of simulating communication challenges in a lab, the NYUQI team is already leveraging NYU’s city-wide campus by utilizing existing infrastructure to test secure quantum transmission between Manhattan and Brooklyn.

The NYUQI team is already leveraging NYU’s city-wide campus by utilizing existing infrastructure to test secure quantum transmission between Manhattan and Brooklyn.

This isn’t just theory; it is building a functioning prototype in the most demanding, dense urban environment in the world. Real-time, real-world deployment is a critical component missing in other isolated institutions. When the NYUQI achieves results, the technology will be that much more readily available to the massive financial, tech, and communications organizations operating right outside their door.

NYUQI includes a state-of-the-art Nanofabrication Cleanroom in Brooklyn serving as a high-tech foundry.NYU Tandon

While the Institute has built the physical infrastructure and designed the necessary scientific architecture, its enduring contribution will be the specialized workforce it creates for the new quantum economy. This addresses the market’s greatest deficit: a lack of individuals trained not just in physics, but in the integrated, full-stack approach that quantum demands.

By creating a pipeline of 100 to 200 graduate and doctoral students who are encouraged to collaborate across Computing, Sensing, and Communications, the NYUQI is narrowing the skills gap. These will be future leaders who can speak the language of the physicist, the materials scientist, and the engineer simultaneously. This commitment to interdisciplinary talent is also fueled by the launch of the new Master of Science in Quantum Science & Technology program at NYU Tandon, positioning the university among a select group worldwide offering such a specialized degree.

Interdisciplinary education creates the shared language and understanding poised to make graduates coming from collaborations in the NYUQI extremely valuable in the current landscape. Quantum challenges are not just technical; they are managerial and philosophical as well. An engineer working with the NYUQI will understand the requirements of the nanofabrication cleanroom and the foundations of superconducting qubits for quantum computing, just as a physicist will understand the application needs of an industry partner like a large financial institution. In a field where the entire team must be able to communicate seamlessly, these are professionals truly equipped to rapidly translate discovery into deployable technology. Creating a talent pipeline at scale will provide a missing link that converts New York’s vast commercial energy into genuine quantum advantage.

NYUQI: Building Talent, Technology, and Structure

The vision for the NYUQI is an act of strategic geography that plays directly into the sheer volume of opportunity and demand right outside their new facility. By building the talent, the technology, and the structure necessary to capitalize on this dense environment, NYU is not just participating in the quantum race, it is actively steering it.

Attendees of NYU’s 2025 Quantum Summit.Tracey Friedman/NYU

The initial hypothesis for the NYUQI was simple: the ultimate advantage lies in pursuing the science in the right place at the right time. Now, the institute will ensure that the next wave of scientific discovery, capable of solving previously intractable problems in finance, medicine, and security, will be conceived, built, and tested in the heart of New York City.

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Last week’s Nvidia GTC conference highlighted new chip architectures to power AI. But as the chips become faster and more powerful, the remainder of data center infrastructure is playing catch-up. The power-delivery community is responding: Announcements from Delta, Eaton, Schneider Electric, and Vertiv showcased new designs for the AI era. Complex and inefficient AC-to-DC power conversions are gradually being replaced by DC configurations, at least in hyperscale data centers.

“While AC distribution remains deeply entrenched, advances in power electronics and the rising demands of AI infrastructure are accelerating interest in DC architectures,” says Chris Thompson, vice president of advanced technology and global microgrids at Vertiv.

AC-to-DC Conversion Challenges

Today, nearly all data centers are designed around AC utility power. The electrical path includes multiple conversions before power reaches the compute load. Power typically enters the data center as medium-voltage AC (1 to 35 kilovolts), is stepped down to low-voltage AC (480 or 415 volts) using a transformer, converted to DC inside an uninterruptible power supply (UPS) for battery storage, converted back to AC, and converted again to low-voltage DC (typically 54 V DC) at the server, supplying the DC power computing chips actually require.

“The double conversion process ensures the output AC is clean, stable, and suitable for data center servers,” says Luiz Fernando Huet de Bacellar, vice president of engineering and technology at Eaton.

That setup worked well enough for the amounts of power required by traditional data centers. Traditional data center computational racks draw on the order of 10 kW each. For AI, that is starting to approach 1 megawatt. At that scale, the energy losses, current levels, and copper requirements of AC-to-DC conversions become increasingly difficult to justify. Every conversion incurs some power loss. On top of that, as the amount of power that needs to be delivered grows, the sheer size of the convertors, as well as the connector requirements of copper busbars, becomes untenable. According to an Nvidia blog, a 1-MW rack could require as much as 200 kilograms of copper busbar. For a 1-gigawatt data center, it could amount to 200,000 kg of copper.

Benefits of High-Voltage DC Power

By converting 13.8-kV AC grid power directly to 800 V DC at the data center perimeter, most intermediate conversion steps are eliminated. This reduces the number of fans and power-supply units, and leads to higher system reliability, lower heat dissipation, improved energy efficiency, and a smaller equipment footprint.

“Each power conversion between the electric grid or power source and the silicon chips inside the servers causes some energy loss,” says Bacellar.

Switching from 415-V AC to 800-V DC in electrical distribution enables 85 percent more power to be transmitted through the same conductor size. This happens because higher voltage reduces current demand, lowering resistive losses and making power transfer more efficient. Thinner conductors can handle the same load, reducing copper requirements by 45 percent, a 5 percent improvement in efficiency, and 30 percent lower total cost of ownership for gigawatt-scale facilities.

“In a high-voltage DC architecture, power from the grid is converted from medium-voltage AC to roughly 800-V DC and then distributed throughout the facility on a DC bus,” said Vertiv’s Thompson. “At the rack, compact DC-to-DC converters step that voltage down for GPUs and CPUs.”

A report from technology advisory group Omdia claims that higher voltage DC data centers have already appeared in China. In the Americas, the Mt. Diablo Initiative (a collaboration among Meta, Microsoft, and the Open Compute Project) is a 400-V DC rack power distribution experiment.

Innovations in DC Power Systems

A handful of vendors are trying to get ahead of the game. Vertiv’s 800-V DC ecosystem that integrates with Nvidia Vera Rubin Ultra Kyber platforms will be commercially available in the second half of 2026. Eaton, too, is well advanced in its 800-V DC systems innovation courtesy of a medium-voltage solid-state transformer (SST) that will sit at the heart of DC power distribution system. Meanwhile Delta, has released 800-V DC in-row 660-kW power racks with a total of 480 kW of embedded battery backup units. And, SolarEdge is hard at work on a 99%-efficient SST that will be paired with a native DC UPS and a DC power distribution layer.

But much of the industry is far behind. Patrick Hughes, senior vice president of strategy, technical, and industry affairs for the National Electrical Manufacturers Association, says most innovation is happening at the 400-V DC level, though some are preparing 800-V DC. He believes the industry needs a complete, coordinated ecosystem, including power electronics, protection, connectors, sensing, and service‑safe components that scale together rather than in isolation. That, in turn, requires retooling manufacturing capacity for DC‑specific equipment, expanding semiconductor and materials supply, and clear, long‑term demand commitments that justify major capital investment across the value chain.

“Many are taking a cautious approach, offering limited or adapted solutions while waiting for clearer standards, safety frameworks, and customer commitments,” said Hughes. “Building the supply chain will hinge on stabilizing standards and safety frameworks so suppliers can design, certify, manufacture, and install equipment with confidence.”

The undying thirst for smarter (historically, that means larger) AI models and greater adoption of the ones we already have has led to an explosion in data-center construction projects, unparalleled both in number and scale. Chief among them is Meta’s planned 5-gigawatt data center in Louisiana, called Hyperion, announced in June of 2025. Meta CEO Mark Zuckerberg said Hyperion will “cover a significant part of the footprint of Manhattan,” and the first phase—a 2-GW version—will be completed by 2030.

Though the project’s stated 5-GW scale is the largest among its peers, it’s just one of several dozen similar projects now underway. According to Michael Guckes, chief economist at construction-software company ConstructConnect, spending on data centers topped US $27 billion by July of 2025 and, once the full-year figures are tallied, will easily exceed $60 billion. Hyperion alone accounts for about a quarter of that.

For the engineers assigned to bring these projects to life, the mix of challenges involved represent a unique moment. The world’s largest tech companies are opening their wallets to pay for new innovations in compute, cooling, and network technology designed to operate at a scale that would’ve seemed absurd five years ago.

At the same time, the breakneck pace of building comes paired with serious problems. Modern data-center construction frequently requires an influx of temporary workers and sharply increases noise, traffic, pollution, and often local electricity prices. And the environmental toll remains a concern long after facilities are built due to the unprecedented 24/7 energy demands of AI data centers which, according to one recent study, could emit the equivalent of tens of millions of tonnes of CO₂ annually in the United States alone.

Regardless of these issues, large AI companies, and the engineers they hire, are going full steam ahead on giant data-center construction. So, what does it really take to build an unprecedentedly large data center?

AI Rewrites Building Design

The stereotypical data-center building rests on a reinforced concrete slab foundation. That’s paired with a steel skeleton and poured concrete wall panels. The finished building is called a “shell,” a term that implies the structure itself is a secondary concern. Meta has even used gigantic tents to throw up temporary data centers.

Still, the scale of the largest AI data centers brings unique challenges. “The biggest challenge is often what’s under the surface. Unstable, corrosive, or expansive soils can lead to delays and require serious intervention,” says Robert Haley, vice president at construction consulting firm Jacobs. Amanda Carter, a senior technical lead at Stantec, said a soil’s thermal conductivity is also important, as most electrical infrastructure is placed underground. “If the soil has high thermal resistivity, it’s going to be difficult to dissipate [heat].” Engineers may take hundreds or thousands of soil samples before construction can begin.

GPUs

Modern AI data centers often use rack-scale systems, such as the Nvidia GB200 NVL72, which occupy a single data-center rack. Each rack contains 72 GPUs, 36 CPUs, and up to 13.4 terabytes of GPU memory. The racks measure over 2.2 meters tall and weigh over one and a half tonnes, forcing AI data centers to use thicker concrete with more reinforcement to bear the load.

A single GB200 rack can use up to 120 kilowatts. If Hyperion meets its 5-gigawatt goals, the data-center campus could include over 41,000 rack-scale systems, for a total of more than 3 million GPUs. The final number of GPUs used by Hyperion is likely to be less than that, though only because future GPUs will be larger, more capable, and use more power.

Money

According to ConstructConnect, spending on data centers neared US $27 billion through July of 2025 and, according to the latest data, will tally close to $60 billion through the end of the year. Meta’s Hyperion project is a big slice of the pie, at $10 billion.

Data-center spending has become an important prop for the construction industry, which is seeing reduced demand in other areas, such as residential construction and public infrastructure. ConstructConnect’s third quarter 2025 financial report stated that the quarter’s decline “would have been far more severe without an $11 billion surge in data center starts.”

There’s apparently no shortage of eligible sites, however, as both the number of data centers under construction, and the money spent on them, has skyrocketed. The spending has allowed companies building data centers to throw out the rule book. Prior to the AI boom, most data centers relied on tried-and-true designs that prioritized inexpensive and efficient construction. Big tech’s willingness to spend has shifted the focus to speed and scale.

The loose purse strings open the door to larger and more robust prefabricated concrete wall and floor panels. Doug Bevier, director of development at Clark Pacific, says some concrete floor panels may now span up to 23 meters and need to handle floor loads up to 3,000 kilograms per square meter, which is more than twice the load international building codes normally define for manufacturing and industry. In some cases, the concrete panels must be custom-made for a project, an expensive step that the economics of pre-AI data centers rarely justified.

Simultaneously, the time scale for projects is also compressed: Jamie McGrath, senior vice president of data-center operations at Crusoe, says the company is delivering projects in “about 12 months,” compared to 30 to 36 months before. Not all projects are proceeding at that pace, but speed is universally a priority.

That makes it difficult to coordinate the labor and materials required. Meta’s Hyperion site, located in rural Richland Parish, Louisiana, is emblematic of this challenge. As reported by NOLA.com, at least 5,000 temporary workers have flocked to the area, which has only about 20,000 permanent residents. These workers earn above-average wages and bring a short-term boost for some local businesses, such as restaurants and convenience stores. However, they have also spurred complaints from residents about traffic and construction noise and pollution.

This friction with residents includes not only these obvious impacts, but also things you might not immediately suspect, such as light pollution caused by around-the-clock schedules. Also significant are changes to local water tables and runoff, which can reduce water quality for neighbors who rely on well water. These issues have motivated a few U.S. cities to enact data-center bans.

Data Centers Often Go BYOP (bring your own power)

Meta’s Richland Parish site also highlights a problem that’s priority No. 1 for both AI data centers and their critics: power.

Data centers have always drawn large amounts of power, which nudged data-center construction to cluster in hubs where local utilities were responsive to their demands. Virginia’s electric utility, Dominion Energy, met demand with agreements to build new infrastructure, often with a focus on renewable energy.

The power demands of the largest AI data centers, though, have caught even the most responsive utilities off guard. A report from the Lawrence Berkeley National Laboratory, in California, estimated the entire U.S. data-center industry consumed an average load of roughly 8 GW of power in 2014. Today, the largest AI data-center campuses are built to handle up to a gigawatt each, and Meta’s Hyperion is projected to require 5 GW.

“Data centers are exasperating issues for a lot of utilities,” says Abbe Ramanan, project director at the Clean Energy Group, a Vermont-based nonprofit.

Ramanan explains that utilities often use “peaker plants” to cope with extra demand. They’re usually older, less efficient fossil-fuel plants which, because of their high cost to operate and carbon output, were due for retirement. But Ramanan says increased electricity demand has kept them in service.

Meta secured power for Hyperion by negotiating with Entergy, Louisiana’s electric utility, for construction of three new gas-turbine power plants. Two will be located near the Richland Parish site, while a third will be located in southeast Louisiana.

Entergy frames the new plants as a win for the state. “A core pillar of Entergy and Meta’s agreement is that Meta pays for the full cost of the utility infrastructure,” says Daniel Kline, director of power-delivery planning and policy at Entergy. The utility expects that “customer bills will be lower than they otherwise would have been.” That would prove an exception, as a recent report from Bloomberg found electricity rates in regions with data centers are more likely to increase than in regions without.

CO2

Research published in Nature in 2025 projects that data-center emissions will range from 24 million to 44 million CO2-equivalent metric tonnes annually through 2030 in the United States alone. While some materials used in data centers, such as concrete, lead to significant emissions, the majority of these emissions will result from the high energy demands of AI servers.

Estimating the carbon emissions of Hyperion is difficult, as the project won’t be completed until 2030. Assuming that the three new natural gas plants that are planned for construction as part of the project produce emissions typical for their type, however, the plants could lead to full life-cycle emissions of between 4 million and 10 million metric tons of CO2 annually—roughly equivalent to the annual emissions of a country like Latvia.

Concrete

Data centers are typically built from concrete, with steel used as a skeleton to reinforce and shape the concrete shell. While the foundation is often poured concrete, the walls and floors are most often built from prefabricated concrete panels that can span up to 23 meters. Floors use a reinforced T-shape, similar to a steel girder, measuring up to 1.2 meters across at its thickest point. The largest data centers include hundreds of these concrete panels.

The America Cement Association projects that the current surge in building will require 1 million tonnes of cement over the next three years, though that’s still a tiny fraction of the overall cement industry, which weighed in at roughly 103 million tonnes in 2024.

The plants, which will generate a combined 2.26 GW, will use combined-cycle gas turbines that recapture waste heat from exhaust. This boosts thermal efficiency to 60 percent and beyond, meaning more fuel is converted to useful energy. Simple-cycle turbines, by contrast, vent the exhaust, which lowers efficiency to around 40 percent.

Even so, total life-cycle emissions for the Hyperion plants could range from 4 million to over 10 million tonnes of CO2 each year, depending on how frequently the plants are put in use and the final efficiency benchmarks once built. On the high end, that’s as much CO2 as produced by over 2 million passenger cars. Fortunately, not all of Meta’s data centers take the same approach to power. The company has announced a plan to power Prometheus, a large data-center project in Ohio scheduled to come online before the end of 2026, with nuclear energy.

But other big tech companies, spurred by the need to build data centers quickly, are taking a less efficient approach.

xAI’s Colossus 2, located in Memphis, is the most extreme example. The company trucked dozens of temporary gas-turbine generators to power the site located in a suburban neighborhood. OpenAI, meanwhile, has gas turbines capable of generating up to 300 megawatts at its new Stargate data center in Abilene, Texas, slated to open later in 2026. Both use simple-cycle turbines with a much lower efficiency rating than the combined-cycle plants Entergy will build to power Hyperion.

Demand for gas turbines is so intense, in fact, that wait times for new turbines are up to seven years. Some data centers are turning toward refurbished jet engines to obtain the turbines they need.

AI Racks Tip the Scales

The demand for new, reliable power is driven by the power-hungry GPUs inside modern AI data centers.

In January of 2025, Mark Zuckerberg announced in a post on Facebook that Meta planned to end 2025 with at least 1.3 million GPUs in service. OpenAI’s Stargate data center plans to use over 450,000 Nvidia GB200 GPUs, and xAI’s Colossus 2, an expansion of Colossus, is built to accommodate over 550,000 GPUs.

GPUs, which remain by far the most popular for AI workloads, are bundled into human-scale monoliths of steel and silicon which, much like the data centers built to house them, are rapidly growing in weight, complexity, and power consumption.

Memory

In addition to raw compute performance, Nvidia GB200 NVL72 racks also require huge amounts of memory. An Nvidia GB200 NVL72 rack may include up to 13.4 terabytes of high-bandwidth memory, which implies a data-center campus at Hyperion’s scale will require at least several dozen petabytes.

The immense demand has sent memory prices soaring: The price of DRAM, specifically DDR5, has increased 172 percent in 2025.

Power

Hyperion is expected to use 5 gigawatts of power across 11 buildings, which works out to just under 500 megawatts per building, assuming each will be similar to its siblings. That’s enough to power roughly 4.2 million U.S. homes.

Just one Hyperion data center built at the Richland Parish site will consume twice as much power as xAI’s Colossus which, at the time of its completion in the summer of 2024, was among the largest data centers yet built.

Nvidia’s GB200 NVL72—a rack-scale system—is currently a leading choice for AI data centers. A single GB200 rack contains 72 GPUs, 36 CPUs, and up to 17 terabytes of memory. It measures 2.2 meters tall, tips the scales at up to 1,553 kilograms, and consumes about 120 kilowatts—as much as around 100 U.S. homes. And this, according to Nvidia, is just the beginning. The company anticipates future racks could consume up to a megawatt each.

Viktor Petik, senior vice president of infrastructure solutions at Vertiv, says the rapid change in rack-scale AI systems has forced data centers to adapt. “AI racks consume far more power and weigh more than their predecessors,” says Petik. He adds that data centers must supply racks with multiple power feeds, without taking up extra space.

The new power demands from rack-scale systems have consequences that are reflected in the design of the data center—even its footprint.

In 2022 Meta broke ground on a new data center at a campus in Temple, Texas. According to SemiAnalysis, which studies AI data centers, construction began with the intent to build the data center in an H-shaped configuration common to other Meta data centers.

LAND

Meta CEO Mark Zuckerberg kicked off the buzz around Hyperion by saying it would cover a large chunk of Manhattan. Many took that to mean Hyperion would be a single building of that size, which isn’t correct. Hyperion will actually be a cluster of data centers—11 are currently planned—with over 370,000 square meters of floor space. That’s a lot smaller even than New York City’s Central Park, which covers 6 percent of Manhattan.

Meta has room to grow, however. The Richland Parish site spans 14.7 million square meters in total, which is about a quarter the area of Manhattan. And the 370,000 square meters of floor space Hyperion is expected to provide doesn’t include external infrastructure, such as the three new combined-cycle gas power plants Louisiana utility Entergy is building to power the project.

Construction was paused midway in December of 2022, however, as part of a company-wide review of its data-center infrastructure. Meta decided to knock down the structure it had built and start from scratch. The reasons for this decision were never made public, but analysts believe it was due to the old design’s inability to deliver sufficient electricity to new, power-hungry AI racks. Construction resumed in 2023.

Meta’s replacement ditches the H-shaped building for simple, long, rectangular structures, each flanked by rows of gas-turbine generators. While Meta’s plans are subject to change, Hyperion is currently expected to comprise 11 rectangular data centers, each packed with hundreds of thousands of GPUs, spread across the 13.6-square-kilometer Richland Parish campus.

Cooling, and Connecting, at Scale

Nvidia’s ultradense AI GPU racks are changing data centers not only with their weight, and power draw, but also with their intense cooling and bandwidth requirements.

Data centers traditionally use air cooling, but that approach has reached its limits. “Air as a cooling medium is inherently inferior,” says Poh Seng Lee, head of CoolestLAB, a cooling research group at the National University of Singapore.

Instead, going forward, GPUs will rely on liquid cooling. However, that adds a new layer of complexity. “It’s all the way to the facilities level,” says Lee. “You need pumps, which we call a coolant distribution unit. The CDU will be connected to racks using an elaborate piping network. And it needs to be designed for redundancy.” On the rack, pipes connect to cold plates mounted atop every GPU; outside the data-center shell, pipes route through evaporation cooling units. Lee says retrofitting an air-cooled data center is possible but expensive.

The networking used by AI data centers is also changing to cope with new requirements. Traditional data centers were positioned near network hubs for easy access to the global internet. AI data centers, though, are more concerned with networks of GPUs.

These connections must sustain high bandwidth with impeccable reliability. Mark Bieberich, a vice president at network infrastructure company Ciena, says its latest fiber-optic transceiver technology, WaveLogic 6, can provide up to 1.6 terabytes per second of bandwidth per wavelength. A single fiber can support 48 wavelengths in total, and Ciena’s largest customers have hundreds of fiber pairs, placing total bandwidth in the thousands of terabits per second.

This is a point where the scale of Meta’s Hyperion, and other large AI data centers, can be deceptive. It seems to imply the physical size of a single data center is what matters. But rather than being a single building, Hyperion is actually a set of buildings connected by high-speed fiber-optics.

“Interconnecting data centers is absolutely essential,” says Bieberich. “You could think about it as one logical AI training facility, but with geographically distributed facilities.” Nvidia has taken to calling this “scale across,” to contrast it with the idea that data centers must “scale up” to larger singular buildings.

The Big but Hazy Future

The full scale of the challenges that face Hyperion, and other future AI data centers of similar scale, remain hazy. Nvidia has yet to introduce the rack-scale AI GPU systems it will host. How much power will it demand? What type of cooling will it require? How much bandwidth must be provided? These can only be estimated.

In the absence of details, the gravity of AI data-center design is pulled toward one certainty: It must be big. New data-center designers are rewriting their rule book to handle power, cooling, and network infrastructure at a scale that would’ve seemed ridiculous five years ago.

This innovation is fueled by big tech’s fat wallet, which shelled out tens of billions of dollars in 2025 alone, leading to questions about whether the spending is sustainable. For the engineers in the trenches of data-center design, though, it’s viewed as an opportunity to make the impossible possible.

“I tell my engineers, this is peak. We’re being engineers. We’re being asked complicated questions,” says Stantec’s Carter. “We haven’t got to do that in a long time.”

This article appears in the April 2026 print issue.

This is a sponsored article brought to you by PNY Technologies.

Key Challenges for Data Science

• Data Preparation: Data preparation is a complex, time-consuming process that takes most of a data scientist’s time.
• Scaling: Volume of data is growing at a rapid pace. Data scientists may resort to downsampling datasets to make large datasets more manageable, leading to suboptimal results.
• Hardware: Demand for accelerated AI hardware for data centers and cloud service providers (CSPs) is exceeding supply. Current desktop computing resources may not be suitable for data science workflows.

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Accelerate Every Step of Your Workflow

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NVIDIA RTX PRO 6000 Blackwell Workstation Edition is designed to transform the entire data science pipeline, delivering end-to-end acceleration from data preparation to model deployment

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Light-warping physics made “invisibility cloaks” a possibility. Now two startups hope to harness the science underlying this advance to boost the bandwidth of data centers and speed artificial intelligence.

Roughly 20 years ago, scientists developed the first structures capable of curving light around objects to conceal them. These are composed of optical metamaterials—materials with structures smaller than the wavelengths they are designed to manipulate, letting them bend light in unexpected ways.

The problem with optical cloaks? “There’s no market for them,” says Patrick Bowen, cofounder and CEO of photonic computing startup Neurophos in Austin, Texas. For instance, each optical cloak typically works only on a single color of light instead of on all visible colors as you might want for stealth applications.

Now companies are devising more practical uses for the science behind cloaks, such as improving the switches that connect computers in data centers for AI and other cloud services. Increasingly, data centers are looking to use optical circuit switches to overcome the bandwidth limits and power consumption of conventional electronic switches and networks that require converting data between light to electrons multiple times.

RELATED: Semiconductor Industry Closes in on 400 Gb/s Photonics Milestone

However, today’s optical switching technologies have drawbacks of their own. For instance, ones that depend on silicon photonics face problems with energy efficiency, while those that rely on microelectromechanical systems (MEMS) can prove unreliable, says Sam Heidari, CEO of optical metasurface startup Lumotive in Redmond, Wash.

Instead, Lumotive has developed metamaterials with adjustable properties. Its new microchip, which debuted 19 March, is covered with copper structures built using standard chipmaking techniques. Between these copper features are liquid crystal elements. The structure of these elements are electronically programmable, just like in liquid crystal displays (LCDs), to alter the optical properties of the metamaterial chip.

The microchip can precisely steer, lens, shape, and split beams of light reflected off its surface. It can perform all the same functions as multiple optical components with no moving parts in a programmable way in real time, according to Lumotive. “Having no moving parts significantly improves reliability,” Heidari says.

“We had to go through a lot of R&D at the foundries to not only make our devices functional, but also commercially viable in terms of the right cost and right reliability,” Heidari says.

The company says its new chips are capable of manipulating not only the industry’s standard of 256 by 256 ports, but could scale up to 10,000 by 10,000. “We think this is game-changing for data centers,” Heidari says. Lumotive plans to launch its first optical switches at the end of 2026.

Optical Computing With Metamaterials

Similarly, Neurophos hopes its technology may be transformative for artificial intelligence. Since AI is proving energy hungry when run on conventional electronics, scientists are exploring optical computing as a low-power alternative by processing data with light instead of electrons.

However, optical processors in the works today are typically far too bulky to achieve a compute density competitive with the best modern electronic processors, Bowen says. Neurophos says it can use metamaterials to build optical modulators—the optical equivalent of a transistor—that are 1/10,000th the size of today’s designs using standard chipmaking processes. “It’s entirely CMOS,” Bowen says. “There are no exotic materials in it.”

When a laser beam encoding data shines on a Neurophos chip, the way in which each metamaterial element is configured alters the reflected beam to encode results from complex AI tasks. “We basically fit a 1,000- by-1,000 array of optical modulators on a tiny 5-by-5-millimeter area on a chip,” Bowen says. “If you wanted to do that with off-the-shelf silicon photonics, your chip would be a square meter in size.”

All in all, Bowen claims the Neurophos microchip will offer 50 times greater compute density and 50 times greater energy efficiency than Nvidia’s Blackwell-generation GPU. The company says that hyperscalers—the world’s biggest cloud service providers—will evaluate two upcoming proof-of-concept chips this year. Neurophos is targeting its first systems for early 2028, with production ramping mid-2028.

Happy 80th anniversary, ENIAC! The Electronic Numerical Integrator and Computer, the first large-scale, general-purpose, programmable electronic digital computer, helped shape our world.

On 15 February 1946, ENIAC—developed in the Moore School of Electrical Engineering at the University of Pennsylvania, in Philadelphia—was publicly demonstrated for the first time. Although primitive by today’s standards, ENIAC’s purely electronic design and programmability were breakthroughs in computing at the time. ENIAC made high-speed, general-purpose computing practicable and laid the foundation for today’s machines.

On the eve of its unveiling, the U.S. Department of War issued anews release hailing it as a new machine “expected to revolutionize the mathematics of engineering and change many of our industrial design methods.” Without a doubt, electronic computers have transformed engineering and mathematics, as well as practically every other domain, including politics and spirituality.

ENIAC’s success ushered the modern computing industry and laid the foundation for today’s digital economy. During the past eight decades, computing has grown from a niche scientific endeavor into an engine of economic growth, the backbone of billion-dollar enterprises, and a catalyst for global innovation. Computing has led to a chain of innovations and developments such as stored programs, semiconductor electronics, integrated circuits, networking, software, the Internet, and distributed large-scale systems.

Inside the ENIAC

The motivation for developing ENIAC was the need for faster computation during World War II. The U.S. military wanted to produce extensive artillery firing tables for field gunners to quickly determine settings for a specific weapon, a target, and conditions. Calculating the tables by hand took “human computers” several days, and the available mechanical machines were far too slow to meet the demand.

80 Years of Electronic Computer Milestones

1946

ENIAC operational

Birth of electronic computing

1951

UNIVAC I

Start of commercial computing

1958

Integrated circuit

Foundation for modern computer hardware

1964

IBM System/360

Popular mainframe computer

1970

Programmed Data Processor (PDP-11)

Popular 16-bit minicomputer

1971

Intel 4004

Beginning of the microprocessor and microcomputer era

1975

Cray-1

First supercomputer

1977

VAX

Popular 32-bit minicomputer

1981

IBM PC

Personal and small-business computing

1989

World Wide Web

Digital communication, interaction, and transaction (e-commerce)

2002

Amazon Web Services

Beginning of the cloud computing revolution

2010

Apple iPad

Handheld computer/tablet

2010

Industry 4.0

Delivered real-time decision-making, smart manufacturing, and logistics

2016

First reprogrammable quantum computer demonstrated

Ignited interest in quantum computing

2023

Generative AI boom

Widespread use of GenAI by individuals, businesses, and academia

2026

ENIAC’s 80th anniversary

80 years of computing evolution

In 1942 John Mauchly, an associate professor of electrical engineering at Penn’s Moore School, suggested using vacuum tubes to speed up computer calculations. Following up on his theory, the U.S. Army Ballistic Research Laboratory, which was responsible for providing artillery settings to soldiers in the field, commissioned Mauchly and his colleaguesJ. Presper Eckert and Adele Katz Goldstine, to work on a new high-speed computer. Eckert was a lab instructor at Moore, and Goldstine became one of ENIAC’s programmers. It took them a year to design ENIAC and 18 months to build it.

ENIAC contained about 18,000 vacuum tubes, which were cooled by 80 air blowers, and measured 8 feet by 3 feet (2.44 meters by 0.91 meters), and was almost 100 feet long (30.5 meters). It filled a large 30 feet by 50 feet (9.14m by 15.24m) room and weighed 30 tons (30,000 kilograms or 30 megagrams). It consumed as much electricity as a small town.

Programming the machine was difficult. ENIAC did not have stored programs, so to reprogram the machine, operators manually reconfigured cables with switches and plugboards, a process that took several days.

By the 1950s, large universities either had acquired or built their own machines to rival ENIAC. The schools included Cambridge (EDSAC), MIT (Whirlwind), and Princeton (IAS). Researchers used the computers to model physical phenomena, solve mathematical problems, and perform simulations.

After almost nine years of operation, ENIAC officially was decommissioned on 2 October 1955.

ENIAC in Action: Making and Remaking the Modern Computer, a book by Thomas Haigh, Mark Priestley, and Crispin Rope, describes the design, construction, and testing processes and dives into its afterlife use. The book also outlines the complex relationship between ENIAC and its designers, as well as the revolutionary approaches to computer architecture.

In the early 1970s, there was a controversy over who invented the electronic computer and who would be assigned the patent. In 1973 Judge Earl Richard Larson of U.S. District Court in Minnesota ruled in the Honeywell v. Sperry Rand case that Eckert and Mauchly did not invent the automatic electronic digital computer but instead had derived their subject matter from a computer prototyped in 1939 by John Vincent Atanasoff and Clifford Berry at Iowa State College (now Iowa State University). The ruling granted Atanasoff legal recognition as the inventor of the first electronic digital computer.

IEEE’s ENIAC Milestone

In 1987 IEEEdesignated ENIAC as an IEEE Milestone, citing it as “a major advance in the history of computing” and saying the machine “established the practicality of large-scale electronic digital computers and strongly influenced the development of the modern, stored-program, general-purpose computer.”

The commemorative Milestone plaque is displayed at the Moore School, by the entrance to the classroom where ENIAC was built.

“The ENIAC legacy heralded the computer age, transforming not only science and industry but also education, research, and human communication and interaction.”

A paper on the machine, published in 1996 in IEEE Annals of the History of Computing and available in the IEEE Xplore Digital Library, is a valuable source of technical information.

“The Second Life of ENIAC,” an article published in the annals in 2006, covers a lesser-known chapter in the machine’s history, about how it evolved from a static system—configured and reconfigured through laborious cable plugging—into a precursor of today’s stored-program computers.

A classic history paper on ENIAC was published in the December 1995 IEEE Technology and Society Magazine.

The IEEE Inspiring Technology: 34 Breakthroughs book, published in 2023, features an ENIAC chapter.

The women behind ENIAC

One of the most remarkable aspects of the ENIAC story is the pivotal role women played, according to the book Proving Ground: The Untold Story of the Six Women Who Programmed the World’s First Modern Computer, highlighted in an article in The Institute. There were no “programmers” at that time; only schematics existed for the computer. Six women, known as the ENIAC 6, became the machine’s first programmers.

The ENIAC 6 were Kathleen Antonelli, Jean Bartik, Betty Holberton, Marlyn Meltzer, Frances Spence, and Ruth Teitelbaum.

“These six women found out what it took to run this computer, and they really did incredible things,” a Penn professor, Mitch Marcus, said in a 2006 PhillyVoice article. Marcus teaches in Penn’s computer and information science department.

In 1997 all six female programmers wereinducted into the Women in Technology International Hall of Fame, in Los Angeles.

Two other women contributed to the programming. Goldstine wrote ENIAC’s five-volume manual, and Klára Dán von Neumann, wife of John von Neumann, helped train the programmers and debug and verify their code.

To honor thewomen of ENIAC, the IEEE Computer Society established the annualComputer Pioneer Award in 1981. Eckert and Mauchly were among the award’s first recipients. In 2008 Bartik was honored with the award. Nominations are open to all professionals, regardless of gender.

An ENIAC replica

Last year a group of 80 autistic students, ages 12 to 16, fromPS Academy Arizona, in Gilbert, recreated the ENIAC using 22,000 custom parts. It took the students almost six months to assemble.

A ceremony was held in January to display their creation. The full-scale replica features actual-size panels made from layered cardboard and wood. Although all electronic components are simulated, they are not electrically active. The machine, illuminated by hundreds of LEDs, is accompanied by a soundtrack that simulates the deep hum of ENIAC’s transformers and the rhythmic clicking of relays.

“Every major unit, accumulators, function tables, initiator, and master programmer is present and placed exactly where it was on the original machine,” Tom Burick, the teacher who mentored the project, said at the ceremony.

The replica, still on display at the school, is expected to be moved to a more permanent spot in the near future.

ENIAC’s legacy

ENIAC’s significance is both technical and symbolic. Technically, it marks the beginning of the chain of innovations that created today’s computational infrastructure. Symbolically, it made governments, militaries, universities, and industry view computation as a tool for improvement and for innovative applications that had previously been impossible. It marked a tectonic shift in the way humans approach problem-solving, modeling, and scientific reasoning.

The ENIAC legacy heralded the computer age, transforming not only science and industry but also education, research, and human communication and interaction.

As Eckert is reported to have said, “There are two epochs in computer history: Before ENIAC and After ENIAC.”

Coevolution of programming languages

The remarkable evolution of computer hardware during the past 80 years has been sparked by advances in programming languages—the essential drivers of computing.

From the manual rewiring of ENIAC to the orchestration of intelligent, distributed systems, programming languages have steadily evolved to make computers more powerful, expressive, and accessible.

Lessons From Computing’s Remarkable Journey

Computing history teaches us that flexibility, accessibility, collaboration, sound governance, and forward thinking are essential for sustained technological progress. In a recent Communications of the ACM article, Richa Gupta identified four historic shifts that led to computing’s rapid, transformative progress:

1. Programmable machines taught us that flexibility is key; technologies that adapt and are repurposed scale better.
2. The Internet showed that connection and standard protocols drive explosive growth but also bring new risks such as data security issues, invasion of privacy, and misuse.
3. Personal computers illustrated that accessibility and usability matter more than raw power. When nonexperts can use a tool easily, adoption rises.
4. The open-source movement revealed that collaborative innovation accelerates growth and helps spot problems early.

Predictions for computing in the decades ahead

The evolution of computing will continue along multiple trajectories, with the emphasis moving from generalization to specialization (for AI, graphics, security, and networking), from monolithic system design to modular integration, and from performance-centric metrics alone to energy efficiency and sustainability as primary objectives.

Increasingly, security will be built into hardware by design. Computing paradigms will expand beyond traditional deterministic models to embrace probabilistic, approximate, and hybrid approaches for certain tasks.

Those developments will usher in a new era of computing and a new class of applications.

This article was updated on 22 April 2026.

Looming over the internet lasers and firestarting phones companies were touting at Mobile World Congress in Barcelona this month, was a more nebulous but much larger announcement: a pan-European cloud called EURO-3C.

EURO-3C’s backers—Spanish telecoms giant Telefónica, dozens of other European companies, and the European Commission (EC)—aim to fill a gap. U.S.-based cloud giants dominate in the EU, and European policymakers want their growing portfolio of digital government services on a “sovereign cloud” under full EU control.

But the EU lacks a real equivalent to the likes of AWS or Microsoft Azure. Indeed, any effort to build one will inevitably run up against the same U.S. cloud giants.

Just four U.S.-based hyperscalers—AWS, Microsoft Azure, Google Cloud, and IBM Cloud—together account for some 70 percent of EU cloud services. This is despite the fact that the 2018 U.S. CLOUD Act allows U.S. federal law enforcement—at least in theory—to compel U.S.-based firms to hand over data that’s stored abroad.

Who Do You Trust?

But those hypothetical risks to digital services have become more real as transatlantic relations have soured under the second Trump administration. The U.S. has openly threatened to invade an EU member state and sanctioned a European Commissioner for passing legislation the White House dislikes.

After the White House sanctioned the Netherlands-based International Criminal Court in February 2025, Court staffers claimed Microsoft locked the Court’s chief prosecutor out of his email (Microsoft has denied this). Around the same time, the U.S. reportedly threatened to sever EU ally Ukraine’s access to crucial Starlink satellite internet as leverage during trade negotiations.

“The geopolitical risk isn’t just the most extreme form of a doomsday ‘kill switch’ where Washington turns off Europe’s internet,” says Stéfane Fermigier of EuroStack, an industry group that supports European digital independence. “It is the selective degradation of services and a total lack of retaliatory leverage.”

What, then, is the EU to do? France offers an example. Even before 2025, France implemented harsh restrictions on non-EU cloud providers in public services—providers must locate data in the EU, rely on EU-based staff, and may not have majority non-EU shareholders. Now, EU policymakers are following France’s lead.

In October 2025, the EC issued a two-part framework for judging cloud providers bidding for public-sector contracts. In the first part, the framework lays out a sort of sovereignty ladder. The more that a provider is subject to EU law, the higher its sovereignty level on this ladder. Any prospective bidder must first meet a certain level, depending on the tender.

Qualifying bidders then move to the second part, where their “sovereignty” is scored in more detail. Using too much proprietary software; over-relying on supply chains from outside the EU; having non-EU support staff; liability to non-EU laws like the CLOUD Act: All hurt a bidder’s score.

The framework was created for one tender, but observers say it sets a major precedent. Cloud providers bidding for state contracts across Europe may need to follow it, and it may influence legislation on both national and EU-wide levels.

A Question of Scale

Who, then, will receive high marks? At the moment, the answer is not simple. The EU cloud scene is quite fragmented. Numerous modest EU providers offer “sovereign cloud” services—such as Deutsche Telekom’s T-Systems, OVHcloud, and Scaleway—but none are on the scale of AWS or Google Cloud.

Inertia is on the side of the U.S. cloud giants, which can invest in their infrastructure and services on a far grander scale than their European counterparts. Some U.S. providers now offer cloud services they say comply with the Commission’s “cloud sovereignty” demands.

Some European observers, like EuroStack, say such promises are hollow so long as a provider’s parent company is subject to the likes of the CLOUD Act and loopholes in the Commission’s process remain open. An AWS spokesperson told IEEE Spectrum it had not disclosed any non-US enterprise or government data to the U.S. government under the CLOUD Act; a Google spokesperson said that its most sensitive EU offerings “are subject to local laws, not U.S. law”.

Even if a project like EURO-3C can offer a large-scale alternative, the U.S. cloud giants have another sort of inertia. Many developers—and many public purchasers of their services—will need convincing to leave behind a familiar environment.

“If you look at AWS, you look at Google, they’ve created some super technology. It’s very convenient, it’s easy to use,” says Arnold Juffer, CEO of the Netherlands-based cloud provider Nebul. “Once you’re in that platform, in that ecosystem, it’s very hard to get out.”

Martyna Chmura, an analyst at the Bloomsbury Intelligence and Security Institute, a London-based think tank, sees some EU developers taking a mixed approach. “Many organizations are already moving toward multicloud setups, using European or sovereign providers for sensitive workloads while still relying on hyperscalers for certain services,” she says.

In that case, the EU’s top-down demands may encourage developers to use EU providers for sensitive applications—like government services, transport, autonomous vehicles, and some industrial automation—even if it’s inconvenient in the short term, or if it causes even more fragmentation of the EU cloud scene. “Running systems across different platforms can increase integration costs and make security and data governance more complicated. In some cases, organisations could lose some of the efficiency and cost advantages that come from using large hyperscale platforms,” Chmura says.

“Overall, the EU appears willing to accept some of these trade-offs,” Chmura says.

This week, over 30,000 people are descending upon San Jose, Calif., to attendNvidia GTC, the so-called Superbowl of AI—a nickname that may or may not have been coined by Nvidia. At the main event Jensen Huang, Nvidia CEO, took the stage to announce (among other things) a new line ofnext-generation Vera Rubin chips that represent a first for the GPU giant: a chip designed specifically to handle AI inference. The Nvidia Groq 3 language processing unit (LPU) incorporates intellectual property Nvidialicensed from the startup Groq last Christmas Eve for US $20 billion.

“Finally, AI is able to do productive work, and therefore the inflection point of inference has arrived,” Huang told the crowd. “AI now has to think. In order to think, it has to inference. AI now has to do; in order to do, it has to inference.”

Training and inference tasks have distinct computational requirements. While training can be done on huge amounts of data at the same time and can take weeks, inference must be run on a user’s query when it comes in. Unlike training, inference doesn’t require running costlybackpropagation. With inference, the most important thing is low latency—users expect the chatbot to answer quickly, and for thinking or reasoning models, inference runs many times before the user even sees an output.

Over the past few years, inference-specific chip startups were experiencing a sort of Cambrian explosion, with different companies exploring distinct approaches to speed up the task. The startups includeD-matrix, with digital in-memory compute;Etched, with an ASIC for transformer inference;RainAI, with neuromorphic chips;EnCharge, with analog in-memory compute;Tensordyne, with logarithmic math to make AI computations more efficient;FuriosaAI, with hardware optimized for tensor operation rather than vector-matrix multiplication, and others.

Late last year, it looked like Nvidia had picked one of the winners among the crop of inference chips when it announced its deal with Groq. The Nvidia Groq 3 LPU reveal came a mere two and a half months after, highlighting the urgency of the growing inference market.

Memory bandwidth and data flow

Groq’s approach to accelerating inference relies on interleaving processing units with memory units on the chip. Instead of relying on high-bandwidth memory (HBM) situated next to GPUs, it leans on SRAM memory integrated within the processor itself. This design greatly simplifies the flow of data through the chip, allowing it to proceed in a streamlined, linear fashion.

“The data actually flows directly through the SRAM,”Mark Heaps said at the Supercomputing conference in 2024. Heaps was a chief technology evangelist at Groq at the time and is now director of developer marketing at Nvidia. “When you look at a multicore GPU, a lot of the instruction commands need to be sent off the chip, to get into memory and then come back in. We don’t have that. It all passes through in a linear order.”

Using SRAM allows that linear data flow to happen exceptionally fast, leading to the low latency required for inference applications. “The LPU is optimized strictly for that extreme low latency token generation,” saysIan Buck, VP and general manager of hyperscale and high-performance computing at Nvidia.

Comparing the Rubin GPU and Groq 3 LPU side by side highlights the difference. The Rubin GPU has access to a whopping 288 gigabytes of HBM and is capable of 50 quadrillion floating-point operations per second (petaFLOPS) of 4-bit computation. The Groq 3 LPU contains a mere 500 megabytes of SRAM memory and is capable of 1.2 petaFLOPS of 8-bit computation. On the other hand, while the Rubin GPU has a memory bandwidth of 22 terabytes per second, at 150 TB/s the Groq 3 LPU is seven times as fast. The lean, speed-focused design is what allows the LPU to excel at inference.

The new inference chip underscores the ongoing trend of AI adoption, which shifts the computational load from just building ever bigger models to actually using those models at scale. “Nvidia’s announcement validates the importance of SRAM-based architectures for large-scale inference, and no one has pushed SRAM density further than d-Matrix,” says d-Matrix CEO Sid Sheth. He’s betting that data center customers will want a variety of processors for inference. “The winning systems will combine different types of silicon and fit easily into existing data centers alongside GPUs.”

Inference-only chips may not be the only solution. Late last week, Amazon Web Services said that it will deploy a new kind of inferencing system in its data centers. The system is a combination of AWS’s Tranium AI accelerator and Cerebras Systems’ third generation computer CS-3, which is built around the largest single chip ever made. The two-part system is meant to take advantage of a technique called inference disaggregation. It separates inference into two parts—processing the prompt, called prefill, and generating the output, called decode. Prefill is inherently parallel, computationally intensive, and doesn’t need much memory bandwidth, while decode is a more serial process that needs a lot of memory bandwidth. Cerebras has maximized the memory bandwidth issue by building 44 GB of SRAM on its chip connected by a 21 PB/s network.

Nvidia, too, intends to take advantage of inference disaggregation in its new compute rack, called the Nvidia Groq 3 LPX. Each tray within the rack will house 8 Groq 3 LPUs. The LPX will split the inference task with a Vera Rubin NVL72, Nvidia’s existing GPU and CPU rack. The prefill and the more computationally intensive parts of the decode are done on Vera Rubin, while the final part is done on the Groq 3 LPU, leveraging the strengths of each chip. “We’re in volume production now,” Huang said.

Correction on 4/8/26: a previous version of this article incorrectly stated that the Nvidia Groq 3 LPX contains a Vera Rubin chip in each tray. In fact, each tray contains 8 Groq 3 LPUs and no Vera Rubins, but the whole rack is designed to work in concert with an NVL72 rack, which houses Vera Rubin chips.

This article appears in the May 2026 print issue as “The Era of AI Inference Is Almost Here.”

Worried that your latest ask to a cloud-based AI reveals a bit too much about you? Want to know your genetic risk of disease without revealing it to the services that compute the answer?

There is a way to do computing on encrypted data without ever having it decrypted. It’s called fully homomorphic encryption, or FHE. But there’s a rather large catch. It can take thousands—even tens of thousands—of times as long to compute on today’s CPUs and GPUs than simply working with the decrypted data.

So universities, startups, and at least one processor giant have been working on specialized chips that could close that gap. Last month at the IEEE International Solid-State Circuits Conference (ISSCC) in San Francisco, Intel demonstrated its answer, Heracles, which sped up FHE computing tasks as much as 5,000-fold compared to a top-of the-line Intel server CPU.

Startups are racing to beat Intel and each other to commercialization. But Sanu Mathew, who leads security circuits research at Intel, believes the CPU giant has a big lead, because its chip can do more computing than any other FHE accelerator yet built. “Heracles is the first hardware that works at scale,” he says.

The scale is measurable both physically and in compute performance. While other FHE research chips have been in the range of 10 square millimeters or less, Heracles is about 20 times that size and is built using Intel’s most advanced, 3-nanometer FinFET technology. And it’s flanked inside a liquid-cooled package by two 24-gigabyte high-bandwidth memory chips—a configuration usually seen only in GPUs for training AI.

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In terms of scaling compute performance, Heracles showed muscle in live demonstrations at ISSCC. At its heart the demo was a simple private query to a secure server. It simulated a request by a voter to make sure that her ballot had been registered correctly. The state, in this case, has an encrypted database of voters and their votes. To maintain her privacy, the voter would not want to have her ballot information decrypted at any point; so using FHE, she encrypts her ID and vote and sends it to the government database. There, without decrypting it, the system determines if it is a match and returns an encrypted answer, which she then decrypts on her side.

On an Intel Xeon server CPU, the process took 15 milliseconds. Heracles did it in 14 microseconds. While that difference isn’t something a single human would notice, verifying 100 million voter ballots adds up to more than 17 days of CPU work versus a mere 23 minutes on Heracles.

Looking back on the five-year journey to bring the Heracles chip to life, Ro Cammarota, who led the project at Intel until last December and is now at University of California, Irvine, says “We have proven and delivered everything that we promised.”

FHE Data Expansion

FHE is fundamentally a mathematical transformation, sort of like the Fourier transform. It encrypts data using a quantum-computer-proof algorithm, but, crucially, uses corollaries to the mathematical operations usually used on unencrypted data. These corollaries achieve the same ends on the encrypted data.

One of the main things holding such secure computing back is the explosion in the size of the data once it’s encrypted for FHE, Anupam Golder, a research scientist at Intel’s circuits research lab, told engineers at ISSCC. “Usually, the size of cipher text is the same as the size of plain text, but for FHE it’s orders of magnitude larger,” he said.

While the sheer volume is a big problem, the kinds of computing you need to do with that data is also an issue. FHE is all about very large numbers that must be computed with precision. While a CPU can do that, it’s very slow going—integer addition and multiplication take about 10,000 more clock cycles in FHE. Worse still, CPUs aren’t built to do such computing in parallel. Although GPUs excel at parallel operations, precision is not their strong suit. (In fact, from generation to generation, GPU designers have devoted more and more of the chip’s resources to computing less-and-less-precise numbers.)

FHE also requires some oddball operations with names like “twiddling” and “automorphism,” and it relies on a compute-intensive noise-cancelling process called bootstrapping. None of these things are efficient on a general-purpose processor. So, while clever algorithms and libraries of software cheats have been developed over the years, the need for a hardware accelerator remains if FHE is going to tackle large-scale problems, says Cammarota.

The Labors of Heracles

Heracles was initiated under a Defense Advanced Research Projects Agency (DARPA) program five years ago to accelerate FHE using purpose-built hardware. It was developed as “a whole system-level effort that went all the way from theory and algorithms down to the circuit design,” says Cammarota.

Among the first problems was how to compute with numbers that were larger than even the 64-bit words that are today a CPU’s most precise. There are ways to break up these gigantic numbers into chunks of bits that can be calculated independently of each other, providing a degree of parallelism. Early on, the Intel team made a big bet that they would be able to make this work in smaller, 32-bit chunks, yet still maintain the needed precision. This decision gave the Heracles architecture some speed and parallelism, because the 32-bit arithmetic circuits are considerably smaller than 64-bit ones, explains Cammarota.

At Heracles’s heart are 64 compute cores—called tile-pairs—arranged in an eight-by-eight grid. These are what are called single instruction multiple data (SIMD) compute engines designed to do the polynomial math, twiddling, and other things that make up computing in FHE and to do them in parallel. An on-chip 2D mesh network connects the tiles to each other with wide, 512-byte, buses.

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Important to making encrypted computing efficient is feeding those huge numbers to the compute cores quickly. The sheer amount of data involved meant linking 48-GB-worth of expensive high-bandwidth memory to the processor with 819-GB-per-second connections. Once on the chip, data musters in 64 megabytes of cache memory—somewhat more than an Nvidia Hopper-generation GPU. From there it can flow through the array at 9.6 terabytes per second by hopping from tile-pair to tile-pair.

To ensure that computing and moving data don’t get in each other’s way, Heracles runs three synchronized streams of instructions simultaneously, one for moving data onto and off of the processor, one for moving data within it, and a third for doing the math, Golder explained.

It all adds up to some massive speedups, according to Intel. Heracles—operating at 1.2 gigahertz—takes just 39 microseconds to do FHE’s critical math transformation, a 2,355-fold improvement over an Intel Xeon CPU running at 3.5 GHz. Across seven key operations, Heracles was 1,074 to 5,547 times as fast.

The differing ranges have to do with how much data movement is involved in the operations, explains Mathew. “It’s all about balancing the movement of data with the crunching of numbers,” he says.

FHE Competition

“It’s very good work,” Kurt Rohloff, chief technology officer at FHE software firm Duality Technology, says of the Heracles results. Duality was part of a team that developed a competing accelerator design under the same DARPA program that brought forth Intel’s Heracles. “When Intel starts talking about scale, that usually carries quite a bit of weight.”

Duality’s focus is less on new hardware than on software products that do the kind of encrypted queries that Intel demonstrated at ISSCC. At the scale in use today “there’s less of a need for [specialized] hardware,” says Rohloff. “Where you start to need hardware is emerging applications around deeper machine-learning-oriented operations like neural net, LLMs, or semantic search.”

Last year, Duality demonstrated an FHE-encrypted language model called BERT. Like more famous LLMs such as ChatGPT, BERT is a transformer model. However it’s only one-tenth the size of even the most compact LLMs.

John Barrus, vice president of product at Dayton, Ohio–based Niobium Microsystems, an FHE chip startup spun out of another DARPA competitor, agrees that encrypted AI is a key target of FHE chips. “There are a lot of smaller models that, even with FHE’s data expansion, will run just fine on accelerated hardware,” he says.

With no stated commercial plans from Intel, Niobium expects its chip to be “the world’s first commercially viable FHE accelerator, designed to enable encrypted computations at speeds practical for real-world cloud and AI infrastructure.” Although it hasn’t announced when a commercial chip will be available, last month the startup revealed that it had inked a deal worth 10 billion South Korean won (US $6.9 million) with Seoul-based chip design firm Semifive to develop the FHE accelerator for fabrication using Samsung Foundry’s 8-nanometer-process technology.

Other startups including Cornami, Fabric Cryptography, and Optalysys have been working on chips to accelerate FHE. Optalysys CEO Nick New says Heracles hits about the level of speedup you could hope for using an all-digital system. “We’re looking at pushing way past that digital limit,” he says. His company’s approach is to use the physics of a photonic chip to do FHE’s compute-intensive transform steps. That photonics chip is on its seventh generation, he says, and among the next steps is to 3D integrate it with custom silicon to do the nontransform steps and coordinate the whole process. A full 3D-stacked commercial chip could be ready in two or three years, says New.

While competitors develop their chips, so will Intel, says Mathew. It will be improving on how much the chip can accelerate computations by fine-tuning the software. It will also be trying out more massive FHE problems, and exploring hardware improvements for a potential next generation. “This is like the first microprocessor…the start of a whole journey,” says Mathew.

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