At Computex 2026, an annual computer trade show held in Taipei, Taiwan, Nvidia made a long anticipated announcement—a version of the company’s Blackwell GB10 superchip for Windows PCs, called RTX Spark. Originally rumored to launch in 2025, it was finally introduced at this year’s show.

It came with full support from Microsoft, which announced two new devices powered by RTX Spark: the Surface Laptop Ultra and the Surface RTX Spark Dev Box. Asus, Dell, Lenovo, HP, and MSI also announced Windows PCs with RTX Spark.

If this is triggering déjà vu, that’s for good reason. In June 2024, Qualcomm and Microsoft partnered to launch AI-focused Copilot+ PCs. Qualcomm’s Arm-based chips provided an alternative to x86-based chips from AMD and Intel used across dozens of budget and mid-range Windows laptops. It was met with mixed commercial success, however, and Intel remains the dominant supplier of chips for Windows laptops. But that doesn’t mean RTX Spark will follow the same path, as Nvidia’s involvement is an important part of the equation.

“Nvidia just has more clout and more industry weight to push and make things happen that Qualcomm couldn’t do early on, and that even Microsoft struggled with,” says Ryan Shrout, president at Signal65, a third-party testing firm. “They can get game developers on board, and get software developers in the emerging AI space to pay attention.”

What is RTX Spark?

At its core, RTX Spark is an iteration of the hardware found in the DGX Spark mini-workstation, which was released in late 2025. Officially badged N1X, the silicon is Nvidia’s Blackwell GB10 “superchip,” a system-on-a-chip with 20 Arm CPU cores, 6,144 GPU cores, and support for up to 128 gigabytes of LPDDR5X memory.

There are some small differences between the mini-workstation and PC system, and the most significant is power consumption. The DGX Spark was designed for GB10 to operate with a power consumption up to 140 watts without overheating. RTX Spark laptops are likely to use less power, which may lower performance, though the details will depend on each PC maker’s particular implementation and remain to be seen.

RTX Spark will also include a neural processing unit (NPU) that qualifies the system for Microsoft’s Copilot+ certification. The NPU is used for some background AI features, like Windows Recall. However, the GPU will remain in the driver’s seat for active AI tasks, including large language models (LLMs) and image generation.

Though RTX Spark laptops took the spotlight, the news is also relevant to desktop workstations. Currently, DGX Spark ships with a custom version of Linux called DGX OS, not Windows. Nvidia says RTX Spark desktops with Windows are coming in the third quarter of 2026. Windows is also coming to Nvidia’s DGX Station, the full-sized desktop iteration of Nvidia’s hardware.

The launch of RTX Spark is of course in part an AI play, and that is taking the lion’s share of attention. But Anshel Sag, principal analyst at Moor Insights & Strategy, thinks Spark is just as relevant for professional work and gaming. “I think the AI play is mostly to appease investors,” he says. “Creators and gamers are also excited about RTX Spark, and someone like me who does all three is even more excited, because having a machine that can do all three well has been a challenge.”

Nvidia’s advantage may lie in software

Though Nvidia refers to the GB10 as a “superchip,” it’s similar to other high-performance system-on-a-chip designs, such as Apple’s M-series silicon and AMD’s Ryzen AI Max. All three include a CPU, GPU, and NPU. All three support large amounts of DRAM. And all three have a unified memory architecture (meaning the system memory is a shared resource accessible to the CPU, GPU, and NPU).

The existing DGX Spark also provides a baseline for performance expectations. RTX Spark will likely deliver GPU performance similar to an RTX 5070 mobile GPU which, if correct, would put it ahead of Apple and AMD’s competing systems. On the other hand, GB10’s CPU cores aren’t as quick as the CPU cores found in leading competitors.

Nvidia’s biggest edge might stem not from hardware performance, but from software. The company’s GPUs are essentially the industry standard across gaming and professional work, with estimates placing Nvidia’s GPU market share above 90 percent. That in turn has made Nvidia the target for most software that benefits from a GPU.

“Nobody doubts that Nvidia is the leader in GPU capability and the software stack around it,” says Shrout. Sag agrees, saying Nvidia has the advantage of “extremely mature drivers.”

Microsoft touts AI, but Windows on Arm remains a question

Nvidia announced RTX Spark was in lockstep with Microsoft, which held its Build developer conference in San Francisco while Computex was taking place across the Pacific in Taipei.

Repeating the Copilot+ PC launch, Microsoft’s vision of Windows on the RTX Spark leans heavily on AI. But unlike Copilot+ PCs—which used the NPU to accelerate AI features integrated into the Windows user experience, such as quickly recalling anything you’ve opened or translating live video calls—the pitch for Windows running on RTX Spark seems more focused on using the Spark’s GPU to accelerate LLMs.

Microsoft announced an “early preview” of Windows SDK called Microsoft Execution Containers (MXC), which sandboxes AI agents, allowing them to work autonomously while isolating them from functions the user doesn’t want the agent to access.

Still, the real test for both Nvidia and Microsoft remains the same challenge Microsoft and Qualcomm faced: establishing Windows on Arm PCs as an alternative to Windows PCs powered by x86 chips from Intel and AMD. Whether RTX Spark will succeed in this remains to be seen.

“Even with all of the talk from Nvidia and Microsoft about the future of the PC and revolutionizing the PC, everybody understands that it needs to be a great general-purpose PC first,” says Shrout.

Uncle Sam wants you to solve big scientific and engineering bottlenecks outside the hallowed walls of academia. On 14 May, the U.S. National Science Foundation (NSF) issued a solicitation inviting what it calls “X-Labs,” or independent research organizations, to apply for a total of US $1.5 billion over 10 years. The structure of the X-labs solicitation is new for the United States government and closely matches an emerging private funding model for what are known as focused-research organizations (FROs), which various think tanks and philanthropies have proposed and tested during the last six years.

A focused-research organization is a team of scientists, engineers, and other technology developers that works on a well-defined problem with a target duration of three to seven years and on a budget in the tens of millions of dollars. Some examples have sought to build an ultrasound-based brain-computer interface, quantify marine CO₂ removal, and improve formal verification in mathematics. The funding for these FROs required a team approach to science larger and more agile than a typical academic lab but with a more academic appetite for scientific risk than a commercial venture might have. In some ways, they echo work done by the Defense Advance Research Projects Agency (DARPA), which is known for helping bridge high-risk research and early-stage commercialization of many technologies.

“The NSF’s X-Labs announcement is a welcome signal that the global research community is serious about finding new ways to fund ambitious, high-risk science,” says Pippy James, deputy CEO of the Advanced Research + Invention Agency (ARIA), a United Kingdom government funding body in London that uses a similar model to the X-Labs.

The NSF’s first two X-Lab research areas are scientific instrumentation for sensing and imaging and interconnects and integrated photonics for quantum systems, and the solicitation says the agency will announce additional topics within weeks.

The funding is structured in phases, with $1.5 million per project in the first year, then up to $50 million per project over the next two to three years for selected projects, with a third, more open-ended phase after that. That first-year funding is more than seven times as much as for the typical NSF project of around $200,000.

“Compared to incremental, project-based grants, larger institutional grants and longer-horizon grants let teams take on harder, more infrastructure-heavy problems with the agility to pivot as they learn,” says Jenn Gustetic, director of metascience and R&D policy at the Institute for Progress (IFP), a Washington, D.C. think tank that made a proposal last year for how the U.S. government could support more independent research organizations.

The NSF solicitation also requires applicants to demonstrate “substantial” independence from any non-X-Lab institutions such as a university or company, which the NSF defined in part to mean the ability to make decisions on research direction, partnerships, and staff in days rather than weeks. It would be difficult for a full-time researcher at a university to qualify, for example, which opens the door to industry researchers or academics willing to take extended leave.

What should new money for science look like?

“People have been kind of wanting to do [focused research organizations] in a fairly bipartisan way since 2020,” says Adam Marblestone, an early proponent who now directs Convergent Research, a Cambridge, Mass., nonprofit that has spent almost $400 million building a dozen FROs. Some larger goal-directed, rather than principal-investigator-centered, funding has existed for decades in other federal agencies in the form of the Advanced Research Projects Agencies for defense, intelligence, energy, and most recently health. ARPA program managers often took a more hands-on and flexible approach than typical three-year National Institutes of Health (NIH) or NSF grant managers could. On 2 June, the IFP published an Atlas of Innovation comparing many different research funding structures.

The NSF announcement comes against a backdrop of administration requests for dramatic cuts to the agency’s budget, though Congress has generally appropriated stable amounts. NSF has, however, not disbursed all its appropriated funding, because the Trump administration has been feuding with many universities, accusing them of discrimination, and suing them. Most recently, NSF stopped new funding for several prominent universities, Nature reported. MIT’s president in May said that the university has won 10 percent less federal money than the previous year.

The big-ticket nature of the X-labs might make administrators and principal investigators at those universities worry about whether it will impact their own funding. “I don’t think it’s a zero-sum game,” says Erica Goldman, director of policy entrepreneurship at the Federation of American Scientists, a Washington, D.C. science-policy think tank, “but the way the timing of the announcements have come out and the rhetoric out there make it very hard to see that.”

“NSF X-Labs is structured to complement the existing system, not displace it—adding an independent institutional type alongside universities, national labs, small businesses and corporate R&D,” the IFP’s Gustetic says. The X-Labs annual sticker price represents less than 2 percent of the agency’s overall budget of $8.75 billion in 2026.

The emerging field of metascience, which investigates how best to do science, has been debating how governments should build the proper pipelines for converting blue-sky research into returns for all taxpayers. Metascientists differ over how FROs should fit into the research system. Some argue that governments can’t expect to apply the vaunted DARPA model to everything. Others write that FROs are a great idea and that the federal government already has a version of them in the form of the Department of Energy’s National Labs, which have spun off science platforms such as the Human Genome Project and the Protein Data Bank.

NSF media affairs head Mike England told IEEE Spectrum that “X-labs creates space and provides funding for new institutions to achieve breakthroughs in scientific discovery, research, and translation, and ultimately helps create new platform technologies.” In addition, on 27 May NSF requested information for a new funding idea adjacent to X-Labs it calls Tech Accelerators. These would use NSF money and accelerator expertise to fund and guide “deep-tech” commercialization efforts in agriculture, materials, ocean, and scientific instrumentation.

Other elements of government are also exploring how to incorporate the FRO funding model. In December 2025, U.S. Representative Josh Harder (D-Calif.) introduced a bill that would apply the X-labs model to the NIH. England says that NSF is having conversations with other government agencies about the model and welcomes more agencies to explore it.

“We don’t have great evidence comparing how different funding mechanisms perform—individual project grants, milestone-based contracts, prize challenges, etc.” Gustetic says. “X-Labs is a chance to actually learn something about which institutional designs work for which kinds of problems.”

Universities will likely have to adapt to the new model. Mid-career academics may well want to take time away from their university homes to participate in an X-Lab or other FRO project, says Monica Dus, director of the Office of National Laboratories at the University of Michigan and a holder of NSF grants. Institutions will need to figure out how to cover teaching duties in their absence and how to assess commercial experience for tenure or other internal promotions. “Universities should adapt to make sure the research does really reach the people it is meant for,” she says.

Academics may also need to change their approach to succeed, Convergent’s Marblestone says. “When we go to academics at Convergent, it takes a few conversations to plan it, because they don’t always know how they’d manage $50 million and a professional engineering team. You really need a CEO.”

Quantum computers promise to one day solve problems beyond the most powerful supercomputers imaginable. But it’s often underappreciated how much classical computing it takes just to operate these machines. As qubit counts rise, innovations in this supporting infrastructure will be essential if they’re to live up to their promise.

To prepare for the scale of quantum computers the industry is working toward, many companies are also gearing up the classical hardware, and software, required to support them. In April, Nvidia announced new AI-based software to accelerate the classical tasks that enable quantum computers. Sydney-based quantum software company Q-CTRL has developed an automatic calibration algorithm for quantum computers, and is now leveraging Nvidia’s agent-based system. Other companies, including IBM Quantum, Cambridge, England–based Riverlane, which develops quantum-error correction, and Google Quantum AI, are developing similar tools.

The Role of Classical in Quantum

Digital computer chips are marvels of engineering, operating flawlessly out of the box and capable of trillions of operations without error. The quantum bits, or qubits, at the heart of a quantum computer, by contrast, are temperamental and unreliable, requiring regular calibration and complex error-correcting schemes to keep them on track.

Calibration and error-correction are fundamentally classical, not quantum, problems, and they require dedicated classical hardware to solve. As quantum computers get bigger, the scale of those resources will need to rise in lockstep. That means that for the foreseeable future, quantum computers are going to be hybrid devices with a healthy dose of classical computing on the side.

“The cheapest and fastest way to execute most computer programs is to run them on a classical computer—even if a quantum computer is available,” says Adam Zalcman, a quantum software engineer at Google Quantum AI. “This is true of most of the information processing involved in running a quantum computer itself.... Therefore, I expect that every practical and efficient quantum-computer architecture will incorporate fast classical devices.”

Tuning Quantum Hardware

While the transistor has cemented its place as the foundational component of classical chips, the qubits at the heart of a quantum computer come in many flavors—superconducting circuits, trapped ions, neutral atoms, even individual photons. Using them for computation requires a painstaking calibration process to turn the “bare metal” of the underlying hardware into a qubit that can be controlled to run quantum circuits, says Jay Guilmart, lead product manager at Q-CTRL.

Calibration has two stages. The first, known as “bring up,” determines the frequency at which each qubit resonates, how long it holds its quantum state, its sensitivity to control pulses, and the strength of its interactions with neighboring qubits. All of these factors determine its error propensity and response to control signals.

Done by hand, the process still requires someone with a Ph.D. and can take days or even weeks, says Guilmart. This isn’t a scalable solution and so there’s a growing drive to automate the process. This is challenging because every step relies on results from the previous step. So rather than relying on a predefined script, Q-CTRL has therefore built intelligent calibration software that examines the result of each measurement, diagnoses failures, and adjusts the approach before retrying.

“After each step, we analyze that data and we say, are we okay to proceed to the next step? Do we have to go back to the previous step? Do we have to re-recreate this step?” says Guilmart.

Calibration is also not a one-and-done process: key parameters drift over time, gradually degrading performance. Q-CTRL’s software performs “runtime recalibration” to nudge things back into place, but there’s a limit to how much on-the-fly adjustment is practical.

“If I’m running a recalibration, I’m not running a circuit,” he says. “Even though I’m maintaining some high system state and high fidelities, if it takes all of my uptime it’s worthless.”

Decoding Errors in Real Time

Even a well-calibrated quantum computer remains fault-prone, which is why companies are investing heavily in quantum error correction (QEC). This typically involves encoding quantum information across large numbers of physical qubits in their shared state—a “logical qubit“—so that errors in individual qubits can be detected and compensated for without destroying the encoded information.

Because measuring a qubit directly collapses its quantum state, errors are detected via parity checks, which query whether pairs of qubits share the same state. This produces a series of measurements known as a “syndrome,” which classical algorithms called decoders analyze to locate errors.

The process must happen extremely quickly. While many errors can be logged and corrected mathematically after an operation, some must be fixed immediately before the algorithm can proceed. Superconducting and silicon spin qubits can hold their quantum states only for microseconds or milliseconds, so errors must be decoded and corrected within that window.

These tight requirements mean decoders typically run on specialized silicon like field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs) optimized for speed, says Jerry Chow, CTO of quantum-centric supercomputing at IBM. “You need to be able to keep up and you need to be able to effectively decode on the fly,” he says. “The best way to do that is through very tightly integrated FPGA or ASIC decoder capabilities.”

To AI or Not to AI

There is growing interest in using AI to simplify quantum hardware control. In April, Nvidia released two models targeting calibration and decoding. The first uses a vision-language model to analyze calibration-measurement outputs—typically plotted as graphs—and passes that evaluation to an AI agent that decides how to tweak the processor. The second uses a convolutional neural network to identify the simpler, localized errors that make up the bulk of faults. More complex errors are passed to a traditional algorithmic decoder, but the first pass reduces computational load enough to deliver a 2x speedup.

The attraction of AI for decoding, says Sam Stanwyck, director of quantum product at Nvidia, is that while models are time-consuming to train, they are extremely fast at inference—and thanks to parallelization across many chips, that speed holds even as qubit counts grow.

But offloading to a GPU still introduces significant latency, says Marco Ghibaudi, vice president of engineering at Riverlane. “You can have a really fat pipe, but it’s really long,” he says. “Our job [approach] has always been to try to remove as many unnecessary steps and shorten the pipe, and then make every section of the pipe as fast as possible.”

IBM’s Chow agrees that GPU latency currently makes them infeasible for real-time decoding. He’s also cautious about AI for calibration, given its computational expense. The approach holds promise for understanding the physics of novel architectures or new kinds of circuits. But for well-characterized devices where you’re simply looking for small deviations, simpler physics-informed techniques can be considerably cheaper.

The two approaches aren’t mutually exclusive, however, says Google’s Zalcman. Neural networks excel at discovering hidden patterns in syndrome data that help identify complex errors algorithmic decoders sometimes miss. Google is therefore developing a hardware architecture that can incorporate both traditional and AI-based decoders, including its AlphaQubit 2 model.

In the long run, Andi Gu, a Harvard Ph.D. student working on AI decoders, thinks “the bitter lesson” will come for decoding. This refers to AI pioneer Richard Sutton’s argument that general-purpose learning methods consistently outperform handcrafted algorithms over time. “If you make the model large enough and you throw enough training data at it, it will learn to capture the hidden correlations better than any other handwritten algorithm,” says Gu.

Latency remains a barrier, but his group is researching ways to make AI decoders more efficient and smaller so that they can fit on an FPGA, cutting response times. This can degrade accuracy though, so finding the right balance is still a work in progress.

Regardless of which approach wins out, one thing is certain—future quantum computers will require massive classical support. Decoding is a continuous, computationally expensive process whatever technique you use, says Gu, so you will need a “healthy chunk” of classical hardware dedicated to that task.

Calibration compute overheads will similarly “blow up” as devices scale to thousands or millions of qubits, says Q-CTRL’s Guilmart. Current techniques are unlikely to scale, he adds, so new approaches will be needed. “We’re going to have to rearchitect and do things differently when we get to even 1,000 qubits,” he says. “So no one’s winning the battle today.”

Memory is arguably the most serious constraint on modern AI large language models (LLMs). According to one influential paper, LLM token generation is an inherently memory-bound task, meaning the rate at which models output text is limited by how quickly data can be read in from memory. The severity of this bottleneck grows with model size. This creates a “memory wall” that holds back LLM inference performance.

AI hardware startup Majestic Labs is taking a direct—and comprehensive—approach to solving this problem. It’s developing a new AI server, Prometheus, with up to 128 terabytes of memory. That’s over 60 times more than Nvidia’s DGX B300 server, a cutting-edge AI processing rack.

Sha Rabii, co-founder and president of Majestic Labs, believes that this drastic increase in memory will provide his company an edge. While he acknowledges that “Nvidia’s done a phenomenal job creating a system that can scale out,” he argues that it becomes less economical as models grow and “ends up greatly over-provisioning on compute and starving on memory.”

DRAM-Centric Architecture for LLM Memory

Majestic Labs plans to surmount the “memory wall” with an architecture that fundamentally differs from competitors’.

Nvidia’s current servers have fast high-bandwidth memory (HBM), which is typically used to read in an LLM’s model weights. In addition, there’s an often larger but slower pool of dynamic random access memory (DRAM), which handles LLM and server overhead. Majestic instead goes all in on DRAM (specifically LPDDR6) in a unified architecture.

Rabii says that most memory interfaces are designed to operate over a short physical distance—sometimes only a few millimeters. That limits how much memory can be placed. “You get this shoreline at the compute die where you can put your HBM. If you wanted to put more, you can’t,” Rabii explains.

To solve that, Majestic uses a proprietary memory interface constructed from miniature copper cables that’s effective up to a meter. This is paired with custom memory aggregation chips that sit physically next to memory modules and coordinate memory across the server.

“It’s an endpoint for that high-speed interface and fans out to many, many commodity DRAM chips,” explains Rabii. In addition to addressing large pools of memory, Majestic says this design offers memory bandwidth up to 25.6 terabytes per second.

Ignite AI Processor for LLM Acceleration

More memory is good, but it needs to be paired with AI acceleration, something akin to Nvidia’s GPU. Majestic’s solution to this is Ignite, a custom AI processing unit that serves as the server’s compute engine. The Prometheus server contains 12 Ignite chips.

Ignite combines data-center-class ARM application cores with RISC-V vector and tensor cores on a single die, all sharing the same memory space. The ARM cores act as an on-chip host processor to orchestrate the AI model. The RISC-V cores carry out the actual LLM processing. The result is a single chip that handles multiple aspects of LLM inference demands without handing off between processors. Majestic Labs has yet to reveal specific metrics for Prometheus’ compute performance.

Rabii acknowledges that software is important as well, given that many AI frameworks are already entrenched. “We’re trying to reduce friction as much as possible in every aspect of our customer adoption, whether it’s physical or software,” he says. Prometheus will support PyTorch, vLLM, and OpenAI’s Triton inference frameworks without requiring code modifications. That means existing models compatible with these frameworks can run as-is.

Prometheus Server Design and Pricing

All of this combines in the server itself, which is Open Compute Project-compliant. Up to four servers can fit in a server rack; power draw is expected to total up to 120 kilowatts per rack; and heat will be managed with cold-plate liquid cooling. The server’s memory design is modular, which means servers purchased with less than the maximum of 128 TB of memory can be upgraded at a later date.

Despite the breadth of the project, Majestic wants to position Prometheus on price, too—which might be a surprise given how much memory each server can contain. Majestic argues that this will be possible because it uses DRAM instead of HBM. Pricing has not yet been announced, as Prometheus is expected to ship in 2027.

“Our customers’ capital expenditure will come down by, depending on the workload, 10 to 50 times, and the power consumption comes down by a similar amount,” Rabii claims.

The ongoing instability in the Middle East has put fertilizer availability at the center of global food security concerns. Up to 30 percent of the global fertilizer trade typically passes through the Strait of Hormuz, along with major flows of liquefied natural gas, a key feedstock for its production. Delayed shipments are rippling through agricultural supply chains, and the United Nation’s Food and Agriculture Organization has warned that the price of urea, a widely used nitrogen fertilizer, had increased by 52 percent in the United States and by 60 percent in Brazil by mid-April.

“Traditionally, because fertilizers are relatively cheap, farmers often apply the maximum allowed amount,” says Ioannis Athanasiadis, a professor at Wageningen University in the Netherlands who works on AI for agriculture and food systems. “It acts as insurance against uncertain weather conditions.” But for farmers already squeezed by the cost of fuel, machinery, and seeds, volatile fertilizer prices are making waste increasingly expensive.

Precision agriculture has already helped farmers reduce chemical use and save money, with computer-vision systems able to identify weeds and trigger herbicide nozzles only where needed. But fertilizer is a tougher challenge. Nitrogen, the key nutrient in many fertilizers, is invisible, highly mobile in soil, and can be washed below the root zone before crops absorb it.

“The difficulty is that you never actually know how much nitrogen the plant and the soil have,” says Chris Padwick, a technical fellow at Blue River Technology, a California-based company that develops computer-vision technologies for agriculture.

Precision Fertilizer Technologies

Along with its parent company John Deere, Blue River developed a precision fertilizer technology called ExactShot, which can be deployed only at the time of planting. The system detects each seed as it goes into the soil and sprays a few drops of starter fertilizer directly onto it, instead of applying fertilizer continuously along the row. Blue River says the system can cut starter fertilizer use by more than 60 percent and could save more than 93 million gallons annually across the U.S. corn crop.

The harder task comes later in the plant’s life, when crop needs depend on weather, soil type, previous applications, and what has already happened in that patch of field. Many sprayers for precision herbicide applications can be fitted with attachments in the shape of an inverted-Y that drag hoses near corn plants, dribbling liquid nitrogen close to the row during the growing season. But without reliable information on which parts of the field actually need nitrogen, the application remains nonselective.

John Deere’s ExactShot technology detects each seed as it is planted and applies a few drops of starter fertilizer.Blue River Technology

Padwick says Blue River is testing whether its crop imaging systems could also become “digital scanners” for plant health, using broader spectral coverage to analyze vegetation as sprayers pass close to the canopy. But getting insights isn’t the same as accurately interpreting them. Yellowing leaves or reduced chlorophyll may point to a nutrient deficiency, but they can also indicate drought stress, disease, or insect damage. That is why some companies are moving below the canopy and into the soil, where direct measurements can provide a more objective picture of what nutrients are available.

Elsewhere in the United States, Iowa-based N-Sense is betting on a mobile machine for soil analysis. Its prototype soil-nitrate sensor can be pulled through the field by a truck to measure nitrate concentration in real time. The system uses a ruggedized miniature Fourier-transform infrared spectrometer operating in the mid-infrared, coupled with a diamond interface. Soil is pressed against one end of the diamond while infrared light passes through the other, allowing the instrument to detect nitrate while the diamond protects the optical surface from abrasion.

“Nitrate is particularly difficult to detect,” says David Laird, N-Sense’s president and CEO. “In the ultraviolet, many things in the soil are responsive, so it is very difficult to separate the nitrate signal. But in the mid-infrared, we are able to isolate the nitrate band and get a strong signal.”

N-Sense’s sensor measures nitrate in real time as it moves through a crop field.N-Sense

The sensor feeds nitrate data into machine learning software that also taps into soil-survey data, satellite imagery, and yield data to generate fertilizer prescriptions that can be uploaded directly to a tractor.

“You do not want to look at nitrogen in isolation,” says Laird. “The soil may have low nitrogen content, but if water availability is what is limiting productivity, adding nitrogen will not help.”

In one field tested last year, Laird says the company achieved about a 30 percent reduction in total nitrogen fertilizer applied.

Real-Time Soil Analysis

In Potsdam, Germany, an agricultural tech company called Stenon has developed FarmLab, a mobile soil-analysis device designed to give farmers real-time measurements directly in the field. The handheld probe is pushed into the soil and combines optical spectroscopy, which reads how soil absorbs and reflects light, with impedance-based electrical measurements, which send a small electrical signal through the ground to capture properties affected by moisture, salts, and nutrient ions. Environmental sensors capture the temperature and humidity, and there is also a GPS tag that associates each reading with a location. Cloud computing and machine learning turn the raw signals into usable soil data. The goal is to infer key soil parameters, including nitrate, mineral nitrogen, moisture, and other indicators that can guide fertilizer decisions.

Stenon’s FarmLab uses optical spectroscopy, electrical impedance sensing, and machine learning to generate soil nutrient maps for precision fertilization.Stenon

The company’s founder and CEO, Niels Grabbert, says the idea came when Europe began enforcing the Nitrates Directive, a law aimed at protecting groundwater and surface water from agricultural nitrate pollution. Back then, farmers were required to reduce nitrogen losses but lacked real-time information on the nitrogen present in their fields.

“Depending on the country and on what parameters you are testing for, it can take anywhere from two to eight weeks before you receive soil-testing results,” says Grabbert. “That means farmers do not know in real time how much nutrition the soil itself can provide.”

FarmLab is meant to replace sparse lab testing with faster, denser field data. On a 100-hectare farm, an agronomist could take one reading every two hectares, then use the software to turn those GPS-tagged measurements into nutrient maps and fertilizer rates that can be sent to farm machinery or management platforms.

Grabbert says the technology can reduce fertilizer use by around 20 percent on average while increasing yields by 2 to 8 percent, depending on the crop and production system.

For Dutch professor Athanasiadis, these systems point in the right direction, but they are not enough on their own. “There are no magic solutions,” he says. “We need sensors, robotics, AI, government support, and farmer participation all working together.”

Chipmakers are struggling to shrink the amount of area a transistor takes up, so researchers are trying to build layers of devices on top of each other. However, many experimental 3D chips rely on exotic materials and perform poorly compared with regular silicon devices. But researchers at the University of Illinois Urbana-Champaign have found a new way to build 3D circuits from silicon. The secret is a process that lets them roll multiple layers of nanometers-thin silicon onto a wafer at relatively low temperatures.

Today’s 3D microchips, such as the AMD MI300 series, stack prefabricated layers on top of each other and connect them with the help of metal pillars known as through-silicon vias. However, the challenge of properly aligning the connections between these layers limits how many links can be made and therefore how useful 3D stacking can be.

By contrast, in monolithic 3D chips, layers of devices are fabricated directly on top of each other. This enables alignment of these layers with nanometer-scale precision, and with orders of magnitude denser connectivity than today’s 3D chips.

However, experimental monolithic 3D chips require transistors and other devices in the upper layers to be fabricated at 400 °C or less to preserve the wiring that connects their components together. Such 3D chips have been made using a variety of materials, but their performance and reliability all proved much worse than the metal-oxide-semiconductor field-effect transistors (MOSFETs) found in virtually all conventional microchips, erasing most of the gains offered by a monolithic 3D design.

Now scientists have created monolithic 3D chips from silicon at less than 200 ℃. “For years, people assumed monolithic 3D would require exotic new materials such as carbon nanotubes, metal-oxide semiconductors, or 2D semiconductors,“ says Qing Cao, an associate professor of materials science and engineering at the University of Illinois Urbana-Champaign. “Demonstrating that silicon can do the job means this technology can plug directly into existing manufacturing ecosystems, which dramatically accelerates its path toward real impact.”

Low-temperature junctionless transistors

Instead of the MOSFETs used in most chips, the new 3D chips rely on junctionless transistors. Regular MOSFETs are made using both n-type semiconductors, which are doped to contain an excess of electrons, and p-type semiconductors, which are doped to produce a deficit of electrons. Charges enter a transistor through its source terminal, travel down a channel, and exit out the drain terminal. In MOSFETs, if the the source and drain are made of p-type silicon, the channel will be made of n-type, and vice versa. The p-n junctions where these semiconductor types meet interrupt the flow of current. When a gate electrode applies voltage to the channel, current can flow across.

Each layer of a new kind of 3D contains so-called junctionless transistors. The bottom layer is made from silicon with excess mobile electrons, the top from silicon with excess holes. The transistors are linked together vertically to form complementary logic.Bao Lam, Yung Man Yu, et al.

In contrast, in junctionless transistors, the source, channel and drain are all completely either p-type or n-type, and so operate without p-n junctions. When a voltage is applied to the gates, they switch on, allowing current to flow. First proposed in 1925, they were not built until 2010 due to limits in fabrication technology; they require highly and uniformly doped channels at most about 10 nanometers thick. In MOSFETs, chipmakers use high heat to make sure dopants are located precisely where they are needed to be in the silicon crystal to create p-n junctions. Junctionless transistors don’t need these high temperatures.

“Junctionless devices also use a simpler process flow, which can reduce costs and improve yield,” Cao says.

The new 3D chips are made by laying down uniformly doped single-crystal silicon membranes each 10 nm or less thick using a wafer-scale roll-transfer-printing process. “Because the membranes are so thin and flexible, they conform to the underlying surface, avoiding the voids and warpage that often plague wafer bonding between rigid wafers,” Cao says.

That the nano-membranes can transfer onto surfaces that are not necessarily perfectly flat “is important because the current method typically used in industry requires sub-1-nanometer roughness for the surfaces to be bonded together and extremely flat—only a few microns of variations across the wafer,” says Veeresh Deshpande, an associate professor of electrical engineering at the Indian Institute of Technology Bombay, who did not participate in this study. “The proposed method simplifies the process complexity and allows stacking several tiers of transistors, both for advanced computing and memory like DRAM.”

Cao and his colleagues fabricated three levels of junctionless transistors on a 75-millimeter silicon wafer, with each tier composed of 625 transistors over a 1,600-square-mm area. From these transistors they constructed a variety of logic gates and circuits—including inverters, NAND and NOR gates, and static random access memory (SRAM) cells—using vertical connections between the layers that were aligned with sub-10-nm accuracy.

The researchers were able to form circuits made up of transistors distributed over all three layers of the 3D chips. That led to a six-transistor SRAM cell with a footprint as little as one-third the size of its 2D layout.

A transistor’s switching speed depends on its current density, and the junctionless transistors showed a current density that could exceed 650 milliamperes per micrometer, which is comparable to older commercial silicon MOSFETs. More advanced MOSFETs do show current densities exceeding 1,000 mA per micrometer, but Cao and his colleagues say that future engineering could further improve the performance of their devices.

“The key implication is that vertical stacking may not have to come with a severe transistor-performance penalty,” says Saptarshi Das, a professor of engineering science and mechanics at Pennsylvania State University, who did not take part in this research. “If scalable, this could open a practical path to denser, more energy-efficient chips with much shorter interconnects.”

Roll-transfer processes

The silicon wafers Cao’s team used are much smaller than the 300-mm ones most fabs use today. But transferring and stacking silicon membranes even across a 75-mm wafer without cracks, wrinkles, or defects “required a series of engineering innovations,” Cao says. These included adding surfactants during certain etching steps to reduce surface tension; adding polymer support layers for mechanical stability and surface protection; and adopting a roll-lamination process to apply uniform pressure during transfer.

“We began in 2019,” Cao says. “By 2024, we realized we had solved the fundamental barriers. The following year and a half was spent refining the process and demonstrating multilayered devices at wafer scale and 3D logic circuits.”

Beyond computing, integrating silicon with other materials in monolithic 3D devices may open up new applications “that were previously out of reach.” Cao says. “For example, vertically stacking different types of single-crystalline semiconductors could enable ultrasensitive X-ray-detector panels or compact multispectral imaging systems.”

A new 3D chip has three layers of silicon transistors separated by about 90 nanometers of dielectric.Bao Lam, Yung Man Yu, et al.

One challenge monolithic devices will face is yield. “When you stack devices vertically, the traditional assumption is that every transistor in every layer must work perfectly, which can reduce overall chip yield,” Cao says. “We are working with circuit designers on defect-tolerant architectures that can absorb imperfections with minimal area and power overhead.”

Another hurdle is the way these 3D chips increase power density, concentrating heat. “We are collaborating with circuit and architecture teams on solutions such as dynamic voltage and frequency scaling and AI-assisted on-chip power regulation to actively manage heat,” Cao says.

Cao suggests the new approach is initially only promising for research and low-volume prototyping applications. “Once the benefits of monolithic 3D integration are clearly established, we can work toward high-volume manufacturing,” Cao says. “We simply want to be realistic and avoid over-claiming before the technology has been validated in those settings with full cost analysis.”

The scientists now want to partner with semiconductor foundries to demonstrate and refine the technology in a manufacturing environment, Cao says. Ultimately, “because our approach is silicon based and compatible with foundry processes, it has a realistic path to adoption,” he notes. “It will be especially valuable for AI workloads that are increasingly limited by communication bottlenecks, which is directly addressed by this technology by bringing compute layers physically closer together.”

This article is adapted by the author with permission from Tech Policy Press. Read the original article.

South Africa is not just another developing country struggling to govern artificial intelligence; it is the exception with leverage, and the window to act on it is closing. It holds approximately 88 percent of global platinum-group metal reserves, critical inputs to parts of the semiconductor and data-center supply chains that make AI infrastructure possible. It hosts the largest data-center market on the continent. Its existing hyperscaler relationships give it procurement leverage that most African states will never have. And a major geopolitical contest over AI infrastructure is being fought on its soil right now, between Chinese and American technology companies competing for control of the systems that will underpin an entire continent’s public sector.

In physics, leverage requires three things: a fulcrum, a lever arm, and the ability to apply force. The Bushveld Complex, the world’s largest platinum-group metal deposit, is the fulcrum: a mineral endowment that gives South Africa a position in the semiconductor supply chain that no other African state holds. The since-withdrawn draft policy is the lever arm. The unresolved “OPTION” provisions in the policy are where force would be applied. Without a policy that specifies what South Africa wants in return for market access, the lever arm sits unused, and the weight of two of the world’s largest technology ecosystems settles exactly where those ecosystems want it to settle.

This makes South Africa a global test case. Not because its proposed means of governance is exemplary, but because it is the one developing country with enough structural leverage to negotiate genuinely different terms, and the one that is choosing, through inaction, not to. The recent announcement of a new panel to update the draft policy by January 2027 is an important opportunity. But the deeper failure is not that an AI policy contained bad references. It is that no verification process caught them before the document entered the public domain. That is a systems problem, not merely a political one. It points to a missing layer in how governments are adopting AI.

The contest already underway

Last year, Huawei pitched an emerging-product bundle to tech executives across the continent. Huawei was now bundling access to DeepSeek’s large language model with its own cloud and storage infrastructure. The price differential was stark—in some cases by more than 90 percent.

At the same time, Microsoft announced plans to spend ZAR 5.4 billion ($300 million) by the end of 2027 on cloud and AI infrastructure in South Africa, building on a prior ZAR 20.4 billion investment. Google, Amazon Web Services, and Oracle already have cloud regions in the country. According to one analysis, the country’s data-center market was valued at US $2.16 billion in 2024, the largest in Africa.

These are not commercially neutral investments. Huawei’s infrastructure reach has been explicitly linked to Chinese strategic objectives, including a documented track record of providing governments with surveillance infrastructure through its Safe Cities network. U.S. hyperscaler investment comes with its own dependency structure: closed models, pricing set unilaterally, and terms of access that no African government has meaningfully shaped. South Africa is being asked to choose between these dependency models without a policy that specifies what it wants in return.

The leverage it has

There is a particular irony in South Africa’s position. The country whose mines supply platinum-group metals essential to semiconductor manufacturing, and through them to AI compute, has drafted a policy that treats it as a consumer of AI systems rather than a stakeholder in their governance. South Africa digs up the minerals that make AI possible. It has no say over the AI built from them.

The AI triad framework covers algorithms, compute, and data. South Africa has no frontier model development capacity. South Africa holds significant data assets in financial services, health care, and agriculture, with no clear framework for their sovereign management. South Africa possesses PGM (Platinum Group Metals) leverage of global significance on the compute axis, currently being transferred without meaningful condition. It also has exceptionally high solar irradiance and significant renewable-energy potential. A country that can offer both critical mineral inputs and the energy to power the infrastructure those minerals help build occupies a negotiating position of unusual strength.

The Draft Policy proposes no minimum terms for hyperscaler investment, no data sovereignty requirements, no technology transfer conditions and no compute visibility mechanism. Multiple provisions are explicitly left unresolved, marked “OPTION,” including the most consequential choices about how governance will function. Infrastructure decisions made now determine what is renegotiable later, and the answer is: very little.

Three futures, one default

The three infrastructure futures on offer each create a structurally different form of dependency, and only one creates sovereign capability. The Huawei-hosted DeepSeek integration offers low cost and open-source weights, but with data stored on infrastructure potentially accessible under Chinese legal frameworks, creating surveillance dependency in a pattern already documented across Africa. The second is U.S. closed-model dependency: higher capability, more reliable data protection, but complete API dependency on developers abroad. The third is locally hosted open-weight infrastructure: models governed under South African data-sovereignty rules, on infrastructure subject to minimum terms, developed with South African data. As Nathan Lambert at Interconnects has observed, open-weight models are likely the only realistic way to get sovereign AI off the ground as a real effort, enabling local communities and economies to integrate meaningfully with the technology. But this requires procurement conditions, not goodwill.

What binding governance looks like

The GovAI “Governing Through the Cloud” framework identifies four roles compute providers should accept as conditions of operating at scale: securers (protecting model weights and training data), record keepers (maintaining infrastructure usage logs), verifiers (confirming customer compliance with safety standards) and enforcers (restricting access when violations occur). These are operational requirements, not theoretical categories—specific, enforceable, and well within the bargaining power of a market of South Africa’s size and mineral position.

A detailed policy analysis submitted to the Department of Communications and Digital Technologies (DCDT) identifies the specific provisions the final policy must contain: mandatory minimum terms for foreign compute infrastructure investments above ZAR 500 million (~$30 million); a compute reporting threshold; a National AI Safety Institute mandate covering defensive monitoring of AI capability accumulation; and National AI Champion Sector designations to create data assets for domestic model development. Each provision converts a structural advantage into a governance instrument before that advantage is foreclosed by market reality. Just as modern software security increasingly depends on knowing what components are inside a system—model provider, training data, compute environment, evaluation methods, update cadence, human review points, and failure-reporting procedures—public-sector AI governance requires a clear account of the stack before deployment, not after a problem surfaces. A public institution that cannot verify the sources in its own AI policy is unlikely to be ready to verify the AI systems it procures, deploys, or regulates.

Why this is the continental test case

South Africa’s choices will establish a regional precedent for what is commercially negotiable in AI infrastructure. If South Africa negotiates data-sovereignty guarantees and technology-transfer conditions as requirements for hyperscaler investment, it creates a replicable model. If Microsoft’s $300 million investment and Huawei’s infrastructure expansion proceed on standard commercial terms, as they are currently, it normalizes extractive AI infrastructure across the continent. The lesson is not specific to Africa. Governments everywhere are producing AI strategies while lacking AI assurance infrastructure. South Africa is an early warning, not an isolated case.

The public comment period closed when the policy was withdrawn. But a parallel process remains live: the National Treasury’s Draft General Public Procurement Regulations—the legal instrument that will govern every government AI contract—closes for comment on June 15. Those regulations contain no AI-specific provisions.

South Africa has more AI leverage than any country on the continent. Some argue, with force, that governance requirements risk deterring the infrastructure investment South Africa urgently needs: compute capacity, reliable energy, venture capital, and talent retention. That concern deserves a direct answer. Minimum procurement terms, compute reporting thresholds, and technology transfer conditions are not barriers to investment. They are the conditions under which investment serves the host country rather than extracting from it. Infrastructure built without minimum terms produces dependency. Infrastructure built with them produces leverage. To serve the public interest, its AI policy must use it.

Floppy disks are several decades old—many of the disks are degrading and the data stored on them is at risk of being lost. In response, Leontien Talboom, a technical analyst at Cambridge University Libraries and Archives, led a roughly year-long project preserving floppy disks called “Future Nostalgia,” which concluded in January.

Leontien Talboom

Leontien Talboom is a technical analyst at Cambridge University Libraries and Archives, where she transfers material from a wide range of storage media to make them accessible to archivists.

IEEE Spectrum spoke to Talboom about her work preserving data from Cambridge’s collection of floppy disks and collecting knowledge about the disks themselves.

Why is it important to preserve floppy disks now?

Leontien Talboom: Two reasons. First, the physical media is starting to degrade. Floppy disks are made from plastic, but they’ve got a magnetic layer of iron oxide, and that’s deteriorating. A lot of floppy disks are found in attics or garages, which means they also suffer from mold.

Second, a lot of people who developed floppy disks and systems that use floppy disks are starting to retire or pass away, which means that a lot of tacit knowledge is disappearing.

Whom did you go to for that tacit knowledge?

Talboom: I went to the retro computing community. Their work is more around preserving these machines to keep them running [than] the data that lives on the floppy disk. But they know their stuff about floppy disks.

For example, they know that in a lot of the older disks, the inside of the disk—the doughnut—gets stuck to the top. So if you flex the casing, the doughnut falls down again. If I hadn’t known that, I would have assumed that those disks in our collection were broken or corrupt.

What is the most difficult part of working with floppy disks?

Talboom: Accessing the files can be quite challenging if we don’t understand the file system. Within libraries and archives, we get a lot of material from machines that are not as well loved. Many of the personal computers that you had at home, such as the Amstrad or ZX Spectrum or BBC Micro, are very well documented. But a bunch of our material comes from business or research systems. They’re not as nostalgic for people, so there’s not as big a community preserving this type of material.

Do you have a favorite type of floppy disk?

Talboom: Five and a quarter. The weirder the system, the more frustrating and fun it is. I quite like doing that detective work.

The Amstrad disk has also really stolen my heart. The popularity of floppy disks is very geographically dependent. Our library, for example, has these Amstrad 3-inch disks. But if you go to the U.S., they’re really uncommon. They weren’t able to manufacture enough of these drives, and [3.5-inch disks] took over at a certain point. But they’re really cute.

What’s the best method for sustainably storing data?

Talboom: The main thing is actively looking after it. A lot of the floppy disks we get in the library haven’t been accessed for 20 or 30 years, which means that you need certain special hardware to actually read them, and then work with emulators or other tools to make these file formats accessible.

Now that we’ve done that work and transferred it, we can monitor it and make sure it’s not suffering from anything like bit rot. We can also make decisions around migrating it to other file formats or working on specific file systems or unknown file formats in more detail.

This article appears in the June 2026 print issue as “Leontien Talboom.”

Open-source software is ubiquitous: Linux is the dominant operating system on servers and supercomputers worldwide; Wordpress powers over 40 percent of all websites, among other major projects. Open-source hardware has existed since the late 1990s, but it hasn’t seen nearly the same level of interest or adoption as its software-focused cousin.

Dominic Rizzo, CEO and founder of the startup zeroRISC, aims to change that. Today, the nonprofit global security standards consortium GlobalPlatform launched Pavona, where Rizzo will be a governing board chair. The goal of Pavona is to facilitate the adoption of open hardware into all kinds of applications, including tiny IoT devices and massive data centers, by making the elements modular, standardized, and trusted.

Pavona is a new open-hardware ecosystem. It provides a starting kit of hardware modules, coupled with reference designs, a set of software tools to streamline adoption in different types of chips, and software tooling to ease integration. It also has a governance structure aimed at lowering the barrier to entry for adding new open-hardware designs and collaborating on development.

“I think it’s foundational,” says Andrew “bunnie” Huang, hacker and founder of Baochip, which is a founding member of Pavona. “We are now at the point where we finally have enough of a nugget of something open that we can spread it around. The outcome of this experiment is going to determine the shape of how we interact with hardware and open source for a long time.”

How open-source hardware differs from open-source software

The main reason open-source hardware hasn’t seen as much of a boom as software is almost too obvious to name: hardware needs to be manufactured, and manufacturing costs money. “Hardware, when it’s built, requires atoms,” Huang says, “which requires logistics and payment.”

At bottom, manufacturing itself is closed source. Because of this, open-sourcing hardware is inherently layered: While the chip fabrication, physical design kit, and foundry process remain closed, the layers on top of that, such as the design verification, system architecture, instruction-set architecture, and firmware, may be open source.

The Pavona ecosystem isn’t meant to deepen the penetration of open source through the layers. Instead, it’s meant to take the available open-source layers and facilitate their adoption and repurposing into as broad an application set as possible. “A lot of the work we’re putting into Pavona has to do with the infrastructure and the architecture that connects all this stuff together,” Rizzo says, “so it becomes much more like Legos, so you can use it in one configuration for a small IoT device and in another configuration for some large data-center system-on-a-chip.”

Part of making the hardware components more modular is software. Rizzo and his team built what they call an architectural composition engine that serves as a wrapper around the hardware, allowing it to interact with different types of computing cores, be they ARM or RISC-V. This way, a company can integrate the open hardware into their existing architecture without changing the software stack.

Pavona begins with security chip OpenTitan

Pavona’s starting kit of open-hardware designs includes components of OpenTitan, a chip that provides a “hardware root-of-trust,” a chip-level source of security that serves as a foundation for all secure operations in a computer. They also include extensions of the OpenTitan design that incorporate efficient cryptography that’s safe against possible future attacks from a large-scale quantum computer.

According to OpenTitan’s proponents, security hardware benefits from openness more than other chips, because if anyone can inspect and verify the design, and there is an active community of people stress-testing the hardware, it can become more trustworthy, and therefore more secure. It also makes the process of proving compliance with various regulatory requirements more straightforward.

Rizzo is counting on three factors to drive adoption of these open-security chips. The first is the AI boom, which has caused a massive increase in demand for chips of all kinds, not only the GPUs but also less well-known components like networking cards, monitors, and more. The second is the regulatory push toward transitioning to postquantum security, which both the U.S. and European governments have legislated to happen by the end of 2030. And third is new regulatory requirements in the European Cyber Resilience Act, which adds new security verification and reporting requirements for products sold in the European market.

“I think those three things together are all driving people in this direction of using secure, open-source silicon,” Rizzo says.

Security hardware may be just the beginning. Pavona is designed to make it as easy as possible to pull in new hardware modules. One need not be a paying member of Pavona to contribute new designs. “We absolutely are rejecting gatekeeping,” Rizzo says.

To increase trust from both individual contributors and large companies, Rizzo and his team developed a governance structure based on large open-source projects from the software world, such as Yocto. Contributing-member companies get representation on Pavona’s governing board. However, an independent technical committee makes the high-level technical decisions. This separation of managerial and technical oversight is meant to increase trust and transparency. “People get very discouraged when they feel like, ‘Hey, I made a contribution, and then someone made a decision in a hallway somewhere and told us later.’ So this is more consensus based, it’s more discussion based. And so those discussions have to be open,” Rizzo says.

Frank Nagle, the Linux Foundation’s advising chief economist and a research scientist at MIT, says compliance with standards and transparent governance are the keys to adoption of open-source technologies. “Having that type of structure in place will hopefully give it a fighting chance and allow it to reach scale, without people being concerned that it’s controlled by any one company.”

Pavona’s architectural-composition engine allows hardware to interact with different types of computing cores, so a company can integrate open hardware into its existing architecture without changing the software stack.Dominic Rizzo

The open-hardware future

Nagle argues that an underappreciated benefit of open source is that it allows private companies to work together, collaborating on core technology while still competing on specialized implementations.

“My favorite example of this I heard from a car manufacturer,” Nagle says. “The seat in your car has a little button that slides your seat backward and forward. Nobody’s buying one car rather than another car because that little toggle is better. But if you didn’t have one of those in your car, then somebody might not buy your car.”

Many technologies fall into the same category as the car seat’s button—technologies that are necessary but not a differentiator of the product. Security chips are a great example: Every piece of hardware needs security; however, few have it as their main function. These are the parts that benefit from open source, Nagle explains.

Collaborating on such hardware may enable cost savings for chip manufacturers and their customers, making the AI boom more economically sustainable.

Perhaps even more important, open sourcing some hardware development can lower the barrier to entry for new people to enter the field. To aid in this quest, Pavona also provides multiple “getting started” guides, software emulation tools, and FPGA code that anyone can download onto a board and get up and running in under 10 minutes.

“I want to get more people involved,” says bunnie Huang. “Particularly young people, particularly new people. Because we need a more robust ecosystem, more new ideas to ensure that we have the ability to maintain these technologies we depend upon.”

“Social engineering” sounds like something out of a conspiracy thriller, charged with totalitarian control and fringe paranoia. More mundanely, it’s come to be associated with phishing and other scams, in which fraudsters manipulate people into disclosing personal information.

Yet the concept is older and more benign: it is the deliberate shaping of human behavior, often at scale. It predates silicon—and became pervasive, and ungoverned, especially once its practitioners learned to hide it. Authoritarian regimes and more recently scammers and big companies have profited from it. To defend ourselves from bad actors, and to benefit from social engineering’s good side, we need to reclaim the name, and govern it prudently.

The roots of engineering

In 1894, Dutch entrepreneur Jacques van Marken urged companies to hire “social engineers” to manage human systems such as insurance, education, and profit sharing for workers as carefully as they did mechanical ones. Fifteen years later, reformer William H. Tolman published Social Engineering, describing how U.S. industrialists optimized workers’ conditions alongside manufacturing methods. If industrialists could shape steel and electricity on demand, why not society itself?

By the 1920s, that confidence had spread. The architect Le Corbusier declared that dwellings were “machines for living in,” imagining cities as orderly lattices where people moved like parts on a conveyor belt. Civilization would run like a Swiss watch.

The idea soon darkened. Authoritarian regimes pushed it to extremes, promising to fashion “the New Man.” In Nazi Germany, engineer Fritz Todt founded Organization Todt, a vast state engineering enterprise that emerged from the autobahn highway system and later operated concentration camps using slave labor.

In the Soviet Union, leaders adopted U.S. scientific management techniques to plan factory-worker movements and classify populations through centralized records, feeding both rapid industrialization drives and the gulag system of forced labor. The same tools and managerial methods used to build highways and enact five-year plans worked for repression and mass control.

By the 1950s, “social engineering” had become a contaminated phrase. The revelations of Nazi and Soviet abuses, along with Cold War critiques of grand social planning turned the term from a progressive slogan into a warning label. Banishing the words pushed the practice underground, making it harder to recognize when it resurfaced in new forms—such as organizational psychology and systems management that still relied on classification and behavioral influence techniques but under softer, less loaded labels.

Social engineering’s more subtle spread

In the postwar years, the new social-engineering lexicon included “human factors” and “urban planning,” all promising integration rather than command. As computing advanced, the language shifted again: “customer journey mapping” to track interactions, “user experience” to script them. Engineering, which began as a means of reshaping physical space, set its sights on shaping behavior. Digital design features embedded in our smartphones now target our attention and desire.

Language helps conceal these modern forms of social engineering. “Data analytics” sounds neutral beside “surveillance.” “Personalization” flatters individuality while still sorting users into predictable categories. “Behavioral nudges” guide decisions without the sense of intrusion. We attach “social” as a favorable modifier to sciences, capital, and media, yet recoil when it meets “engineering.”

That discomfort is a clue. Engineering implies control, and control prompts us to ask who directs whom, toward what ends, and with whose permission.

Not all social engineering these days is hidden. Hackers don’t need to break a firewall if someone hands over their password. Romance scammers cultivate intimacy the way farmers cultivate crops. They succeed not through force but by exploiting trust. If even these obvious attacks work, the invisible kind, with roots in social engineering, are a shoo-in.

Most of the social engineering we encounter is proprietary and beyond our control. Firms build recommendation algorithms tuned to boost engagement and profit with no hearings or right of appeal. Browser and cookie defaults decide what data we surrender. A single autoplay toggle can cost users hours and build unhealthy habits. These are acts of engineering as deliberate as laying a road or redrawing an electoral district. They create a kind of curated itch by which boredom never settles, and satisfaction never arrives. The results are predictable—users click on targeted ads, make purchases, form habits, and lock in opinions.

Consent has transformed along with it. Once straightforward and revocable, it is now subtle and persistent, buried in defaults or opaque terms of service too quickly accepted. You remain free to opt out, much as you are free to refuse roads or electricity. Consent has become the preselected setting of modern life.

When social engineering operated more in the open, citizens could contest it, at least in societies with responsive government. Today’s invisible version diffuses accountability so thoroughly that scrutiny becomes hard to direct. Despite recent congressional hearings on social media’s impact on youth mental health and juries agreeing that firms are knowingly designing algorithms that cause harm, pinpointing responsibility remains elusive. When the mechanism is buried inside a system used by billions, we cannot easily point to a single decision-maker or trace the precise moment of manipulation.

Today’s social engineering is less overt and theatrical than its predecessors. Earlier versions arrived on public posters and loudspeakers for mass audiences. Today’s version is more intimate, delivered through personal devices and constant feeds tailored to the individual. The model succeeds because participation feels like freedom, not control.

Not all social engineering is dystopian. Well-kept parks foster community, accessible buildings extend dignity, vaccines and seatbelts save lives. Even in the digital realm, positive examples exist: browser extensions that automatically block hidden trackers, search engines that refuse to build personalized surveillance profiles, and decentralized social platforms that give users greater control over their own data and feeds.

The term “social engineering” still unsettles, though. But “asocial” engineering, which ignores human consequences entirely, is worse. Recognition of the human dimension to engineering is the beginning of repair. Only by seeing the machinery clearly and naming it honestly can we decide who engineers what and why. The machinery will not dismantle itself. Once named, it becomes subject to choice. That negotiation of purpose, power, and process are the defining political questions of any real democracy. We cannot ensure that social engineering serves and sustains society so long as we dodge the words.

Darwesh Singh thinks Nvidia has a weakness.

The last decade of Nvidia’s history was among the most consequential stories in technology ever. The company’s stock price has increased over 200-fold since 2016, and deployed Nvidia AI compute capacity has surged to 225 times greater than the first quarter of 2021, according to data tracked by Epoch AI.

Yet Nvidia may in some ways be a victim of its own success. Its dominance in AI has led to GPU designs that prioritize tensor units and low precision math. These decisions make sense for AI, but less so for some creative, scientific, and industrial work.

Singh’s five-year-old startup, Bolt Graphics, sees an opportunity to build a GPU specifically for these use cases. Jill Mueller, Bolt’s chief marketing officer, puts it bluntly. Nvidia has “a fundamental lack of understanding of their customer,” she says. “They just throw stuff at you, and there you go.”

Bolt aims for this potential weak spot with Zeus, a GPU that will be sold as both a PCIe (peripheral component interconnect express) card for desktop workstations and, for those who require more performance, a rack-mountable server containing four Zeus GPUs (for up to 96 per rack).

While Nvidia goes low-precision, Bolt goes high

Jacob Feldgoise, senior data research analyst at Georgetown University’s Center for Security and Emerging Technology, has also noticed a shift in Nvidia’s recent hardware.

“AI is sucking the computational units used for high-precision workloads out of that hardware,” he says. “If you look at Nvidia’s highest performance GPUs, generation to generation, a greater share of the hardware has been allocated to low-precision compute, as opposed to high-precision compute, which is generally needed for scientific computing.”

Precision refers to how many bits a GPU uses to represent each number. High-precision formats like FP64 (64-bit floating point) preserve more digits and a wider range, while FP16 and INT8 sacrifice precision for speed. Recently, Nvidia introduced a new 4-bit number format, NVFP4, to accelerate AI workloads, which generally tolerate low-precision math.

But some tasks require precision. Singh cited geographical information systems, such as Esri’s ArcGIS, as an example. When rendering the planet on a GPU, low-precision arithmetic applied to large coordinate values can introduce errors that cause objects to drift.

Because Zeus, unlike so many other GPUs, is not designed primarily for AI, its design makes FP64-native vector cores a focus and allocates a large share of silicon to them.

“[Nvidia and AMD] make a conscious trade-off to allocate more die space to matrix multiplication and tensor units and less towards fixed function hardware,” Singh says. ”We decided to allocate the die space a bit differently.”

Rasterization is out, path tracing is in

A focus on FP64 isn’t the only way Bolt differs from the norm. Zeus is also built to render graphics with path tracing instead of rasterization.

Rasterization is the traditional method of high-performance 3D rendering. It projects 3D triangles onto a pixel grid and uses mathematical abstractions to determine the correct color for each pixel. Path tracing instead does the equivalent of shooting rays from a camera to simulate how light should bounce and interact. It delivers more accurate lighting but is computationally expensive.

As with high-precision math, Bolt believes it can find an edge by placing more emphasis on path tracing than do today’s GPUs. Rasterization is supported by Zeus but significantly scaled back; Singh estimates that Zeus’s raster performance is about half that of a comparable Nvidia card.

Bolt’s fresh arrival to the GPU arena also allows the company to take a clean sheet approach unburdened by legacy support. This differs from Nvidia and AMD, which must integrate path tracing alongside rasterization in a way that can support numerous existing applications and application programming interfaces (APIs).

Bolt claims that a server rack with 28 Zeus GPUs will deliver real-time path traced performance equivalent to 280 Nvidia RTX 5090 GPUs. The aim is for this configuration of Zeus hardware to support real-time path tracing that simulates up to 20 “bounces”—a reflection or collision of the simulated light—at 4K resolution and 30 frames per second. This is a high degree of accuracy required for professional rendering workloads; for comparison, even the most graphically attractive path traced games simulate just a few bounces.

Can a startup really launch a new GPU?

There’s a logic to Bolt’s approach. Nvidia and AMD are focused on AI, but GPUs are still useful for many tasks besides AI. However, Bolt will need to overcome two key technical hurdles.

The first is production. Cutting-edge silicon production is in short supply, and leaders like Nvidia have most leading-edge production capacity tied up. The Zeus GPU will instead be fabricated on TSMC’s older N5 process node. Bolt is betting that an older process node will keep Zeus competitive with Nvidia on price.

Bolt may also find it challenging to convince users that an unproven GPU is a safe bet. Driver support for software is always a headache in the GPU arena—just ask Intel—and the use cases that might benefit Zeus’s high precision and path tracing will also require reliable drivers.

Bolt plans to address this by launching with support only for specific applications. “We know that PC gaming is a huge segment,” Singh says. “But our approach is we want to target professional, creative, and high-performance compute first.” The company is working with software companies including Blender, Autodesk, and SideFX.

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This sponsored article is brought to you by Wetour Robotics.

A field technician on a wind turbine, harness clipped, both hands on a wrench, needs to send a command to the diagnostic device hanging at her belt. A logistics worker on a loading dock, gloves on, eyes on the pallet, needs to redirect a connected lift. A person using an assistive mobility device on a crowded street wants to nudge it forward without taking out a phone or speaking aloud. None of these moments call for a smarter robot. They call for a smarter way to be heard by the machines that already exist.

The industry has been building from one side

The past three years of Physical AI have been a story of remarkable progress on the robot side of the loop. Companies like Boston Dynamics, Figure, and Unitree have advanced actuators, locomotion, and dexterity to a level that would have seemed implausible a decade ago. Google DeepMind’s Gemini Robotics has redefined what vision-language-action models can do in unstructured settings. The trajectory of the hardware and the foundation models is real, and it is accelerating.

But there is another side to this loop, and it has been treated as a solved problem for too long. The interface between humans and machines has defaulted, for 40 years, to three input modalities: screens, buttons, and voice. Each of those assumes the user can stop, look down, and translate intent into structured commands. That assumption breaks the moment the work moves into a real environment. On a turbine. On a dock. On a sidewalk. In any setting where hands are occupied, eyes are committed, or speaking is impractical, the conventional interface stack quietly fails.

Spatial Intent Fusion is the simultaneous processing of three streams of human-centered information, namely spatial position, visual context, and gestural intent: Your body is the interface.

The bottleneck on the human side of the loop is becoming as important as the one on the machine side. And solving it requires a different question. Not how do we make the robot more capable, but how do we let the human participate in the computing system as naturally as the robot already does.

Wetour Robotics’ bet: put the human back into the computing loop

Wetour Robotics is betting that the next architectural leap in Physical AI is not about making the robot more capable. It is about making the human a first-class node in the computing network, with the same kind of low-latency, high-fidelity participation that connected devices already enjoy.

Wetour Robotics’ engineers frame the problem this way: a wristband that recognizes a gesture is not enough. A camera that recognizes a scene is not enough. The information a human carries about what they are about to do is distributed across multiple channels, including where their body is in space, what their eyes are attending to, and what their muscles are preparing to do, and any single channel observed in isolation is ambiguous. Reconstructing intent reliably means fusing those channels at the operating system level, with latency low enough that the loop feels closed rather than mediated.

This approach has a name. Wetour Robotics calls it Spatial Intent Fusion: the simultaneous processing of three streams of human-centered information, namely spatial position, visual context, and gestural intent, fused into a single real-time command for any connected physical device. It is the technical implementation behind a simpler positioning statement the company uses externally: your body is the interface.

Orchestra is a portable intelligent hub running the operating system that handles sensor fusion, intent inference, command translation, and safety arbitration. The reference compute platform is NVIDIA Jetson Orin Nano Super, which provides enough on-device inference capacity to keep the entire control loop at the edge, with no cloud dependency on the critical path. Wetour Robotics

The architecture: three layers, four engines, one loop

Orchestra is not a single device but a layered platform, designed from the start to be sensor-flexible and actuator-agnostic. The architecture decomposes into three perception layers and four coordination engines.

Orchestra itself is the local compute and orchestration core: a portable intelligent hub running the operating system that handles sensor fusion, intent inference, command translation, and safety arbitration. The reference compute platform is NVIDIA Jetson Orin Nano Super, which provides enough on-device inference capacity to keep the entire control loop at the edge, with no cloud dependency on the critical path. Edge inference is non-negotiable for this application. Full-chain latency from biosignal acquisition to actuator command is held under 100 milliseconds, the envelope inside which closed-loop control feels natural rather than laggy.

VisionLink handles visual and spatial perception. Cameras feed into vision models that identify objects, estimate distances, and track environmental context. VisionLink is designed not as a passive recognition layer but as a real-time command generator: its outputs feed directly into Orchestra OS to be fused with biosignal data.

Conductor is the biosignal pipeline. It ingests raw surface electromyographic (sEMG) data from a wrist-worn device, classifies temporal patterns into discrete gestures or continuous control signals, and outputs actuator commands. The technically interesting property of sEMG for this use case is that the signal precedes visible motion. Motor unit action potentials appear at the skin surface roughly 50 to 80 milliseconds before a finger completes the corresponding gesture. Wetour Robotics calls this property pre-motion intent sensing, and it is what allows Orchestra to anticipate user intent rather than react to it.

On top of the three perception layers, Orchestra OS runs four coordination engines. The Perception Engine ingests and normalizes raw sensor streams. The Intent Engine performs Spatial Intent Fusion across modalities, resolving what the user is trying to do given where they are, what they are looking at, and what their hand is signaling. The Orchestration Engine translates intent into device-specific command sequences for any connected actuator. The Safety Engine arbitrates conflicting commands, enforces operational envelopes, and gates execution against runtime safety conditions.

The trade-offs we’re honest about

No system that bridges the human body and the digital world is finished. Three engineering challenges remain open, and the company addresses each with a deliberate trade-off rather than a claim of having fully solved it.

Baseline stability of sEMG under motion. In a stationary user, continuous gesture recognition from sEMG is reliable. Once the user is walking, climbing, or otherwise moving, motion artifacts and electrode drift degrade the signal in ways that are difficult to fully compensate for. Rather than overpromise on continuous control in dynamic settings, Orchestra defaults to a smaller set of robust discrete gestures in complex operating environments, and reserves continuous control modes for contexts where the signal-to-noise ratio supports them.

Miniaturization of edge AI compute. Running the Orchestra control loop entirely at the edge requires real on-device inference, which has historically meant trading off between compute capacity, battery life, and form factor. Wetour Robotics’ approach has been a compact carrier board paired with a thermal design and a battery module sized for all-day wearability. The result is a hub that travels with the user rather than tethering them to a desk, and that performs the full perception-to-actuation loop without offloading to the cloud.

Heterogeneity of third-party device protocols. The actuator side of the loop is a fragmented landscape. Different manufacturers expose different command interfaces, different communication stacks, and different safety conventions, and a Physical AI operating system has to integrate with all of them. Wetour Robotics uses an AI-agent layer to negotiate connection and protocol translation adaptively, so that Orchestra OS can ingest data from a wide range of devices, run them through neural network models that infer human intent, and emit the right command on the right protocol for the device on the other end.

Why this matters, and why it helps the rest of the field

The history of computing is a history of interface revolutions. Command lines gave way to graphical user interfaces, which gave way to touch, which gave way to voice. Each transition expanded who could participate in the system and what they could do with it. The next transition is not about a new screen or a new microphone. It is about treating the human body itself as a participant in the computing network, capable of contributing intent at the same speed and fidelity that any other connected node can.

The history of computing is a history of interface revolutions. The next transition is not about a new screen or a new microphone — it is about treating the human body itself as a participant in the computing network.

This path is not a competitor to the work being done on humanoid robots, foundation models for embodied AI, and dexterous manipulation. It is the missing complement to that work. The hardest open problem for humanoid systems is the data: every natural interaction between a human and the physical world is a potential training signal, and most of those interactions are currently invisible to any computing system. As more humans become first-class nodes in the loop, those interactions become observable, structured, and ultimately useful for training the next generation of embodied AI, including the humanoid robots being developed today.

In other words: putting the human back into the computing loop is not just about better interfaces for individual users. It is about generating the kind of grounded, in-the-wild human-machine interaction data that the broader Physical AI ecosystem will need to keep advancing. The robot side and the human side of the loop are not two competing futures. They are two halves of the same one.

That is what Wetour Robotics means when it says: Your body is the interface.

Learn more at wetourrobotics.com.

In the late 1940s—when computer engineers were grappling with unreliable hardware and noisy transmission environments—a team of engineers inside a modest lab at the University of Manchester, England, confronted a problem so fundamental that it threatened the viability of digital computing itself. Machines could generate bits, but they could not reliably read them back.

The inconsistent reading back of memory data did not initially present itself as a grand theoretical challenge. It showed up as something more mundane: inconsistent computing results.

Engineers including Frederic C. Williams, Tom Kilburn, and G. E. (Tommy) Thomas traced the failures not to logic errors but to the physical behavior of the machines themselves. The team devised a technique for keeping a transmitter and a receiver synchronized without relying on a separate clock signal. Their innovation, known as Manchester code or phase encoding, encoded each bit with a transition in the middle of the bit period, effectively embedding timing information directly into the data stream to be a self-clocking signal. So, even if the signal degraded or the timing drifted slightly, the receiver could continually keep time based on those regular transitions.

By eliminating the need for separate clocks and reducing synchronization errors, Manchester code made data transfer more robust across cables and circuits.

Those qualities later made it a natural fit for technologies such as Ethernet and early data storage systems. Its self-clocking nature helped standardize how machines communicate, and it laid the groundwork for modern networking and digital communication protocols.

On 13 April 2026, this breakthrough was honored with an IEEE Milestone plaque during a ceremony at the University of Manchester. Dignitaries from IEEE and the university attended the ceremony.

Embedding timing in signals

Those 1940s Manchester University engineers were working on systems that fed into the Manchester Mark I, one of the first practical stored-program machines.

When troubles arose, they used oscilloscopes to probe signals. They found that electrical pulses did not arrive with consistent timing. Memory signals also blurred over time, making them harder to read, and when long runs of identical bits occurred, the waveform flattened into stretches with no transitions.

That led to a crucial insight: The problem was not just detecting whether a signal was high or low; the system also lost track of when to sample the signal. Without reliable timing markers, even correctly formed signals were misread. Bits could effectively be lost or miscounted because the system fell out of sync.

At first, the engineers tried to tame the hardware. They experimented with stabilizing circuits and more consistent pulse generation, attempting to impose a regular rhythm on an inherently unstable system. But the fixes proved fragile, and the electronics of the day could not maintain the required precision. So the Manchester group took a different approach.

If the hardware could not provide a dependable clock, the signal itself would have to carry one. Instead of representing data as static levels, each bit changed state, with a guaranteed transition in the middle.

Embedding timing in the signal reduced erratic behavior. Machines were suddenly able to reliably transmit, store, and read back data—an essential step toward practical stored-program computing.

Making signals unmistakable

The Manchester code addressed several issues at once. Regular transitions allowed continuous timing recovery. Transitions proved easier to detect than static levels, and long runs of identical bits no longer produced flat, ambiguous waveforms. Rather than fighting the imperfections of early electronics, the design worked with them.

From lab curiosity to a global standard

What began as a local solution in Manchester shaped digital communication systems for decades, including early Ethernet technology, for which timing and shared-medium communication were central challenges.

According to Robert Metcalfe, a member of the team that built the first Ethernet system at Xerox PARC in 1973, he and his colleagues relied on Manchester code.

“Manchester code solved a fundamental problem for us: timing,” Metcalfe says, explaining that each bit carried its own clock and removed the need for a global synchronized signal.

That self-clocking property wasn’t the only benefit provided by the encoding scheme. On a shared coaxial cable, Manchester encoding did more than provide timing. Each transceiver left the medium undriven—effectively “off”—most of the time, allowing packets from other machines to pass without interference. Even during transmission, a station drove the signal only about half the time, leaving the line undriven during the other half of each bit cycle.

This distinction—between a driven signal and an undriven line, rather than simple 1s and 0s—allowed receivers to recover both data and clock timing while also monitoring the cable for other activity. If a transceiver detected a signal when it expected the line to be undriven, the signal indicated that another station was transmitting at the same time. In other words, the system could detect collisions in real time and respond accordingly.

The idea has proven durable far beyond local networks. Manchester code is being used aboard the Voyager spacecraft, which are now cruising through interstellar space—underscoring its reliability in extreme environments.

The code also has found its way into everyday consumer electronics. Infrared remote controls for televisions and audio equipment commonly rely on Manchester code through protocols such as RC-5, developed by Philips in the early 1980s. The protocol encodes commands as timed infrared signals transmitted by a handset’s integrated circuit and LED, allowing devices to reliably interpret button presses even through noise and signal distortion. Manufacturers across Europe—and many in the United States—adopted the approach, extending Manchester code into the home.

Why the Milestone matters

An IEEE Milestone designation recognizes technologies with enduring impact. Manchester code qualifies because it solved a foundational timing problem at a critical moment in computing history.

Without a way to embed timing in the data itself, early digital systems would have remained fragile and unreliable. Manchester code helped transform them into dependable machines, and it enabled much of today’s digital communication.

“Manchester code solved a fundamental problem for us: timing,” —Robert Metcalfe, an Ethernet inventor

Key participants at the plaque dedication ceremony included Tom Coughlin, 2024 IEEE president; Duncan Ivison, University of Manchester president and vice chancellor, and Nagham Saeed, chair of the IEEE U.K. and Ireland Section.

Talks by Kees Schouhamer Immink (the 2017 IEEE Medal of Honor laureate probably best known for his work that made compact discs and other high-density digital media practical) and Peter Green (Manchester’s deputy dean for the engineering faculty) highlighted the code’s lasting impact on digital data storage and communications.

The IEEE Milestone plaque for the Manchester code reads:

“At this site in 1948–1949, Manchester code was invented for reliably encoding digital data stored on the Manchester Mark I computer’s magnetic drum. It became a standard for computer magnetic tapes and floppy disks and was used in digital communications, including the Voyager 1 and 2 spacecraft and early Ethernet networks. It found wide use in domestic remote controllers, radio frequency identification (RFID) tags, and many control network standards.”

This sponsored article is brought to you by Melbourne Convention Bureau (MCB) supported by Business Events Australia.

Melbourne’s reputation as a global events city, from the Australian Open tennis and Formula 1 Australian Grand Prix to hosting NFL regular season games, now intersects with a different form of scale: large-scale compute, data-intensive research, and advanced engineering. Long recognized for delivering complex international events, the city is applying the same organisational capability to the infrastructure that underpins modern AI research, positioning Melbourne at the convergence of global convening and high-performance digital systems.

Consistently ranked among the world’s most livable cities, Melbourne was named Time Out’s Best City in the World in 2026, the first Australian city to hold the title.

Melbourne, Australia’s premier conference destination. Tourism Australia

Australia’s artificial intelligence (AI) ecosystem is entering a new phase, defined less by isolated initiatives and more by the convergence of compute infrastructure, research intensity and international collaboration. Melbourne sits at this intersection.

Melbourne’s trajectory highlights what enables research at scale: access to frontier-grade compute, proximity to industry-ready infrastructure, and repeated opportunities for global research communities to convene.

Sovereign AI compute, expanding hyperscale data center campuses and a growing pipeline of international research-led conferences are reshaping the city’s research landscape. Together, these elements position Melbourne as a focal point for applied AI research, advanced engineering and data-intensive science.

The growing global influence of AI engineering, underscored by NVIDIA CEO Jensen Huang receiving the 2026 IEEE Medal of Honor, reflects the scale of this shift. In Melbourne, these factors form a reinforcing research flywheel linking infrastructure, discovery and collaboration.

Rather than focusing on startup density or short-term commercial output, Melbourne’s trajectory highlights what enables research at scale: access to frontier-grade compute, proximity to industry-ready infrastructure, and repeated opportunities for global research communities to convene.

NVIDIA CEO Jensen Huang received the 2026 IEEE Medal of Honor.IEEE

Sovereign AI foundations

The most recent cornerstone of Melbourne’s AI capability is MAVERIC (Monash AdVanced Environment for Research and Intelligent Computing), Australia’s largest university-based AI supercomputer. Built and deployed by Monash University in partnership with NVIDIA, Dell Technologies, and CDC Data Centres, MAVERIC has been engineered specifically for large scale AI and data intensive science, with medical research representing a key priority. Indeed, in these regards MAVERIC has been designed to function as a Next Generation Trusted Research Environment thus ensuring that it is state-of-the-art and provides a safe and secure framework for the analysis of large sensitive datasets.

Designed to support research projects including cancer and neurodegenerative disease detection, clinical trial analysis and drug discovery through to materials science and engineering, MAVERIC enables Australian researchers to train and evaluate large models domestically while keeping highly sensitive datasets secure and under national jurisdiction. This sovereign design is particularly relevant in fields such as medical research where privacy, regulation or intellectual property constraints limit the use of offshore cloud resources.

Monash University Vice-Chancellor and President Professor Sharon Pickering with researchers [left to right] Professor Anton Peleg, Professor Victoria Mar, Professor James Whisstock, Vice-President (Strategy and Major Projects) Teresa Finlayson, and Professor Patrick Kwan.Eamon Gallagher (Australian Financial Review)

Technically, the system reflects the latest shifts in high performance AI architecture. Built on NVIDIA GB200 NVL72 platforms and integrated using Dell’s rack scale infrastructure, MAVERIC employs closed loop liquid cooling to reduce water consumption compared with conventional air-cooled systems, aligning large scale compute growth with sustainability objectives while supporting high density, high throughput workloads.

Professor James Whisstock, Deputy Dean Research of Monash’s Faculty of Medicine, Nursing, and Health Sciences commented, “MAVERIC provides a huge leap forward in our compute capability that will revolutionize our researchers’ ability to address the most challenging and important research questions across the fields of medical research, information technology, and STEM disciplines. It will seed wonderful new cross-disciplinary collaborations, underpin the work of our best and brightest young researchers and will allow our scientists to continue to make major discoveries that positively impact the Australian and global population more broadly.”

“MAVERIC provides a huge leap forward in our compute capability that will revolutionize our researchers’ ability to address the most challenging and important research questions across the fields of medical research, information technology, and STEM disciplines.” —Professor James Whisstock, Deputy Dean Research of Monash’s Faculty of Medicine, Nursing, and Health Sciences

Monash University frames MAVERIC not as a standalone asset, but as part of the national research infrastructure, intended to strengthen collaboration across academia, healthcare, government and industry. This approach positions Melbourne at the forefront of sovereign AI enabled research in the region.

Data center scale as research infrastructure

The infrastructure demands of modern AI research extend well beyond individual systems. Melbourne’s expanding data center footprint now supports hyperscale compute, applied AI deployment and large-scale research workloads simultaneously.

Total data center investment, US$ billions.Source: Data Centres Global Report 2025

In February 2026, CDC Data Centres opened its first Melbourne campus in Brooklyn, with two live facilities and a third in planning. Combined with CDC’s Laverton campus, Melbourne is projected to host more than 800 megawatts of sovereign digital capacity, critical for AI workloads requiring sustained access to high-density power, cooling and secure environments.

Parallel investment is underway in Fishermans Bend, where NEXTDC is developing a AUD $2 billion AI and digital infrastructure hub adjacent to the Innovation Precinct. Planned facilities include an AI Factory, a Mission Critical Operations Center and a Technology Center of Excellence, enabling sovereign AI, high-performance computing and cross-sector collaboration across health, defence and finance.

Melbourne hosts Australia’s largest cluster of AI firms, with 188 companies, and more than 40 data centers currently operate across Victoria. The Victorian Government has complemented this growth with an initial AUD $5.5 million investment in the Sustainable Data Center Action Plan.

Together, these developments reinforce Melbourne’s role as a national and increasingly global hub for high-performance AI infrastructure as model complexity and infrastructure dependency continue to accelerate.

Applied AI research at scale

Monash University is home to MAVERIC, Australia’s largest university-based AI supercomputer, built and deployed by Monash in partnership with NVIDIA, Dell Technologies, and CDC Data Centres.Monash University

Melbourne’s research strength is underpinned by a dense university network with deep capability across AI, data science and engineering. Institutions including Monash University, the University of Melbourne, Deakin University, La Trobe University, RMIT University and Swinburne University of Technology collectively support research across machine learning, robotics, human-computer interaction, extended reality and advanced manufacturing.

This concentration fosters applied collaboration where AI intersects with medicine, sustainability, cognitive systems and immersive technologies. For visiting researchers, it provides access not only to academic expertise but also to live infrastructure environments where research can be tested and validated, reinforcing Melbourne’s position as one of the Asia-Pacific’s most integrated AI research ecosystems.

Conferences as research accelerators

Plenary session at Melbourne Convention and Exhibition Center.Melbourne Convention Bureau

Melbourne’s selection as host city for a growing number of international technology conferences reflects the convergence of research capability and infrastructure maturity.

In September 2026, Data Center World Australia and The AI Summit Australia will be co-located at the Melbourne Convention and Exhibition Center, bringing together global leaders across AI, digital infrastructure and enterprise technology. The pairing highlights a broader reality: advances in AI are inseparable from the infrastructure that enables them.

Melbourne’s expanding data center footprint now supports hyperscale compute, applied AI deployment and large-scale research workloads simultaneously.

Research-led conferences are also expanding Melbourne’s global footprint. ICONIP 2026, hosted by Deakin University, will bring up to 700 researchers in neural networks and machine learning, followed in 2027 by IEEE VR, the leading conference on virtual reality and 3D user interfaces, attracting up to 1,000 delegates.

In this context, conferences function not simply as events, but as infrastructure for knowledge transfer, supporting standards exchange, collaboration and system-level learning at global scale.

A global platform for advancing research

Sovereign compute, data center scale and a strong conference pipeline create a reinforcing cycle, enabling researchers to engage directly with infrastructure and industry well beyond the event itself.

By closing the gap between theory and deployment, Melbourne supports deeper technical exchange and more enduring global research networks.

This role was recognized in 2025 when the IEEE awarded Melbourne Convention Bureau the 2025 Organisational Supporting Friend of IEEE Member and Geographic Activities (MGA) — the first convention bureau in the Asia Pacific region to receive the acknowledgement as a result of the longstanding partnership with the IEEE Victorian Section.

Melbourne Convention Bureau (MCB) representative Fatima Aboudrar, Senior Business Development Manager, with Vijay S. Paul, Immediate Past Chair, IEEE Victorian Section, receiving Supporting Friend Member recognition in 2025.

As AI research becomes increasingly dependent on infrastructure scale, sovereign capability, and global collaboration, Melbourne is moving beyond hosting conversations to actively enabling the systems that advance AI and data‑driven research at global scale.

Conference support in Melbourne

Why host a conference in Melbourne, Australia.Melbourne Convention Bureau

This ecosystem is underpinned by Melbourne’s highly accessible city center, where world-class venues, research institutions and industry hubs are located in close proximity. Free public transport and a compact city footprint enable seamless movement from conference floor to real-world application.

Melbourne Convention Bureau (MCB) is a not-for-profit state government agency with over 60 years’ experience, that provides IEEE and its members with free support to bring international conferences to Melbourne, Australia. MCB’s support spans early-stage exploration and international bidding through to securing government funding, connecting organizers with venues, accommodation and event suppliers, and providing destination support for conference planning and delivery. Organizations considering a conference in Australia are encouraged to connect with MCB’s dedicated team, which supports IEEE conferences in Melbourne. Enquiries can be directed to info@melbournecb.com.au.

This sponsored article is brought to you by Applied Materials.

At pivotal moments in history, progress has required more than individual brilliance. The most consequential breakthroughs — such as those achieved under the Human Genome Project — required a new operating paradigm: Concentrate the world’s best talent around a single mission, establish a common platform, share critical infrastructure, and collapse feedback loops. When stakes are high and timelines are compressed, sequential and siloed innovation simply cannot keep pace.

Today’s AI era is creating an engineering race with similar demands. Every company is pushing to deliver higher-performance AI systems, faster. But performance is no longer defined by compute alone. AI workloads are increasingly dominated by the movement of data: In many cases, moving bits consumes as much — or more — energy than compute itself. As a result, reducing energy per bit can extend system‑level performance alongside gains in peak compute.

The path to energy‑efficient AI therefore runs through system‑level engineering, spanning three tightly interconnected domains:

• Logic, where performance per watt depends on efficient transistor switching, low‑loss power, and signal delivery through dense wiring stacks.
• Memory, where surging bandwidth and capacity demands expose the memory wall, with processor capability advancing faster than memory access.
• Advanced packaging, where 3D integration, chiplet architectures, and high‑density interconnects bring compute and memory closer together — enabling system designs monolithic scaling can no longer sustain.

These domains can no longer be optimized independently. Gains in logic efficiency stall without sufficient memory bandwidth. Advances in memory bandwidth fall short if packaging cannot deliver proximity within thermal and mechanical constraints. Packaging, in turn, is constrained by the precision of both front‑end device fabrication and back‑end integration processes.

In the angstrom era, the hardest problems arise at the boundaries — between compute and memory in the package, front‑end and back‑end integration, and the tightly coupled process steps needed for precise 3D fabrication. And it is precisely this boundary‑driven complexity where the traditional innovation model breaks down.

The Traditional R&D Workflow Is Too Slow for Angstrom‑Era AI

For decades, the semiconductor industry’s R&D model has resembled a relay race. Capabilities are developed in one part of the ecosystem, handed off downstream through integration and manufacturing, evaluated by chip and system designers, and only then fed back for the next iteration. That model worked when progress was dominated by relatively modular steps that could be scaled independently and simply dropped into the manufacturing flow.

But the AI timeline has upended these rules. At angstrom‑scale dimensions, the physics enforces inescapable coupling across the entire stack: materials choices shape integration schemes; integration defines design rules; design rules dictate power delivery; wiring sets thermal budgets; and thermals ultimately constrain packaging scaling. System architects simply cannot wait 10–15 years for each major semiconductor technology inflection to mature.

Representing a roughly $5 billion investment, EPIC is the largest commitment to advanced semiconductor equipment R&D in U.S. history.

A long‑term perspective is essential to align materials innovation with emerging device architectures — and to develop the tools and processes required to integrate both with manufacturable precision. At Applied Materials, together with our customers, we are charting a course across the next 3–4 generations, extending as far as 10 years down the roadmap.

The angstrom era demands that we break down silos and bring together the industry’s best minds — from leading companies to leading academic institutions. If the problem is coupled, the solution must be coupled. If the timeline is compressed, the learning loop must be compressed. It’s not enough to just innovate — we must innovate how we innovate.

EPIC: A Center and Platform for High‑Velocity Co‑Innovation

This is the challenge that Applied Materials EPIC Center is designed to solve.

Representing a roughly US $5 billion investment, EPIC is the largest commitment to advanced semiconductor equipment R&D in U.S. history. When it opens in 2026, it will deliver state‑of‑the‑art cleanroom capabilities built from the ground up to shorten the path from early‑stage research to full‑scale manufacturing. But the facilities are only one component of the model. EPIC is also a platform, an operating system for high-velocity co‑innovation that revolutionizes how ideas move from the lab to the fab.

EPIC is a platform, an operating system for high-velocity co‑innovation that revolutionizes how ideas move from the lab to the fab.Applied Materials

The EPIC model compresses the traditional workflow. Customer engineers work side‑by‑side with Applied technologists from day one — moving beyond isolated process optimization and downstream handoffs. Within a shared, secure environment, EPIC tightly integrates atomistic modeling, test vehicles, process development, validation, and metrology feedback. Constraints that once surfaced late in development are identified and addressed early.

The result is a potentially 2x faster path that benefits the entire ecosystem under one roof:

• Chipmakers gain earlier access to Applied’s R&D portfolio, faster learning cycles, and accelerated transfer of next‑generation technologies into high‑volume manufacturing.
• Ecosystem partners gain earlier access to advanced manufacturing technology and collaboration opportunities that expand what is possible through materials innovation.
• Academic institutions gain opportunities to strengthen the lab‑to‑fab pipeline and help develop future semiconductor talent.

Building on decades of co‑development, we are reinventing the innovation pipeline with our partners across logic, memory, and advanced packaging to deliver the next leap in energy‑efficient AI.

Accelerating Advanced Logic

Logic remains the engine of AI compute. In the angstrom era, however, system‑level gains are increasingly constrained by power and energy. Extending AI performance now depends on architectures that deliver more performance per watt — accelerating the move to 3D devices such as gate‑all‑around (GAA) transistors, which boost density within a compact footprint while preserving power efficiency.

These architectural shifts are unfolding at unprecedented scale, with the logic roadmap already extending beyond first‑generation GAA toward more advanced designs. One key example is GAA with backside power delivery, which relocates thick power lines to the backside of the wafer, reducing resistive losses and freeing front‑side routing for tighter logic cell integration. Another example brings adjacent GAA PMOS and NMOS transistors closer together while inserting a dielectric isolation wall between them to minimize electrical interference. Further out, complementary FETs (CFETs) push density scaling even more by stacking PMOS and NMOS devices directly atop one another.

While these architectures deliver compelling gains in performance per watt and logic density without relying solely on tighter lithography, they significantly raise integration complexity. Manufacturing a single GAA device today can involve more than 2,000 tightly interdependent process steps. At the same time, wiring stacks continue to grow taller and denser to connect these advanced logic devices. Modern leading‑edge GPUs now in development pack more than 300 billion transistors into an area little larger than a postage stamp, interconnected by over 2,000 miles of wiring.

At this level of complexity, the process steps used to create these precise 3D devices and wiring stacks cannot be optimized independently. Design and process must evolve in lockstep, and materials innovation and fabrication methods must advance alongside device architecture. EPIC’s co‑innovation model is designed to accelerate exactly this convergence — enabling logic compute to continue advancing the frontiers of AI at the pace the roadmap demands.

Powering the Memory Roadmap

At the same time, the AI computing era is fundamentally reshaping how data is generated, moved, and processed — making memory technologies, especially DRAM, central to delivering the energy‑efficient performance AI systems require. As models grow larger and more data‑hungry, the DRAM roadmap is shifting toward architectures that deliver higher density, greater bandwidth, and faster access per watt.

At the DRAM cell level, this shift is driving a transition from 6F² buried‑channel array transistors (BCAT) to more compact 4F² architectures, which orient the transistor vertically to boost density and reduce chip area. Looking beyond 4F², sustaining gains in performance per watt will require moving past what 2D scaling alone can deliver. The industry is therefore turning to 3D DRAM, stacking memory cells vertically to add capacity within a constrained footprint. As these structures grow taller and aspect ratios intensify, high-mobility materials engineering in three dimensions becomes increasingly critical to performance and reliability.

Beyond the memory cell array, another powerful lever for DRAM scaling is shrinking the peripheral circuitry, which includes logic transistors and interconnect wiring. One emerging approach places select periphery functions beneath the DRAM array by bonding two wafers — one optimized for the DRAM cells and the other for CMOS logic — using multiple wiring layers.

In parallel, DRAM performance is being extended by leveraging logic‑proven enhancers in the memory periphery. These include mobility boosters such as embedded silicon germanium and stress films, along with wiring upgrades like improved low‑k dielectrics and advanced copper interconnects. Memory manufacturers are also transitioning periphery transistors from planar devices to FinFET architectures, following the logic roadmap to further improve I/O speed. These valuable inflections are central to EPIC’s mission — where they can be co-developed and rapidly validated for next‑generation memory systems.

Driving System Scaling With Advanced Packaging

As data movement becomes the dominant energy cost in AI systems, advanced packaging has emerged as a critical lever for improving system‑level efficiency—shortening interconnect distances, increasing bandwidth density, and reducing the power required to move data between logic and memory.

High‑bandwidth memory (HBM) marks a major inflection along this path. By stacking DRAM dies — scaling to 16 layers and beyond — and placing memory much closer to the processor, HBM enables rapid access to ever‑larger working datasets. This delivers step‑function gains in both bandwidth and energy efficiency.

More broadly, the rise of 3D packages such as HBM underscores why advanced packaging is becoming central to the AI era. Packaging now addresses system‑level constraints that logic and memory device scaling alone can no longer overcome. It also enables a move away from monolithic systems‑on‑chip toward chiplet‑based architectures, as AI workloads increasingly demand flexible designs that combine logic, memory, and specialized accelerators optimized for specific tasks.

A vital technology powering this roadmap is hybrid bonding. With interconnect pitches approaching those of on‑chip wiring, conventional bumps and microbumps run into fundamental limits in density, power, and signal integrity. Hybrid bonding removes these barriers by allowing dramatically higher interconnect and I/O density, supporting a broad range of chiplet architectures — from memory stacking to tighter compute‑memory integration.

As bonded structures like HBM stacks grow larger and more complex, warpage control, die placement, stack alignment, and thermal management become first‑order challenges. EPIC tackles these and other high‑value advanced‑packaging challenges through early, parallel co‑innovation across materials, integration, and manufacturing.

Bringing It All Together

Across logic, memory, and advanced packaging, our industry faces an ambitious roadmap that promises significant gains in energy efficiency for AI systems. But realizing that potential demands breakthrough materials innovation at a time when feature sizes are shrinking, interfaces are multiplying, and process interdependencies are escalating. These challenges cannot be solved on 10–15‑year timelines under the traditional relay‑race model. We must break down silos, align earlier across the ecosystem, and parallelize learning to keep pace with AI’s demands.

In the AI era, progress will be defined by the speed at which lightbulb moments turn into manufacturing and commercialization reality. The only viable path forward is a new innovation model — and EPIC is how we are driving it.

The rise of electricity-guzzling data centers has forced the artificial intelligence industry to get creative about finding power. One of the latest ideas: Build micro data centers next to utility substations and operate them in concert, shifting the computation around based on power availability.

That’s the approach Nvidia and its collaborators are taking in a new pilot project they plan to build later this year. They’ll construct about 25 of these small data centers, each ranging from 5 to 20 megawatts, across five utilities in the United States. If one substation is overloaded with power demand, or if there’s an outage, the compute will be shifted to a different data center near a substation that has spare capacity.

To develop the fleet, Nvidia is partnering with data center builder InfraPartners, real estate service provider Prologis, and the nonprofit EPRI (formerly known as the Electric Power Research Institute).

The project aims to demonstrate a new way for data centers to be more flexible and accommodating of electricity availability. It’s also a way for data center developers to quickly secure power from the grid—an increasingly precious commodity, even in small chunks.

“We started looking at how much [unused] power is available at individual substations, and what we found was that on average, like 5 MW is nominally available…max 20 MW,” says Ben Sooter, director of Agentic AI Initiatives and Distributed AI Architecture at EPRI.

That’s too small to interest most data center operators, but building several at that size and operating them as if they’re one larger one is useful, Sooter says. Plus, shifting compute away from overburdened substations to those with more headroom can double the overall available power, he says.

“There are 55,000 substations in the U.S., and if they each have 5, 10, or 20 MW of spare capacity, that number adds up pretty fast,” adds Marc Spieler, senior director of energy at Nvidia.

Building energy flexibility into data centers

Squeezing every spare megawatt out of the grid will become increasingly important as data center construction continues to ramp up. In the United States, where half of all new data centers are being built, data centers could consume 9 to 17 percent of electricity generation by 2030. That’s more than double the current use, according to EPRI’s estimates. Facilities that train AI models are being built at the gigawatt scale, drawing about the same amount of power as a midsize U.S. city.

As grid operators figure out how to accommodate such massive new loads, data center developers sometimes end up waiting up to a decade to get approved for a grid connection. In response, the developers are making incredibly bold decisions around power—moves that would have been unthinkable just two years ago.

Many are building their own gas power plants on site. Some are offering to pay for the cost of new transmission lines and other grid infrastructure. And a few are even investing in startup companies that are developing fusion and next-generation nuclear fission reactors, in the hope of meeting power needs a decade from now.

But there’s a lot more power available on the grid than is used day to day. U.S. grid operators use only about 53 percent of their generation capacity on average, according to a landmark 2025 report from Duke University’s Nicholas Institute for Energy, Environment and Sustainability.

That’s because the U.S. electricity supply was built to meet peak demand—periods of the highest energy use of the year, such as the hottest days of the summer. Those peak loads can be almost double the load on a mild-temperature day and typically occur for less than 200 hours a year. The rest of the time, whole power plants sit idle.

If AI data centers can find a way to reduce or shift power consumption during these periods of peak demand, the extraordinary measure of building on-site power generation may not always be necessary. U.S. grids could provide an additional 76 GW—about 10 percent of peak demand—if large loads like data centers curtailed their power use just 0.25 percent of the time, according to the Nicholas Institute report.

Energy flexibility could also allow data centers to connect to the grid faster because they wouldn’t have to wait for new power plants to be built. And placing small data centers right next to substations reduces the need for new grid infrastructure, such as power lines and poles, and upgraded transformers and switch gear. As a bonus, these substations already have fiber-optic lines for high-speed internet, Nvidia’s Spieler points out. So the small data center can connect to those existing lines.

The inference advantage

The type of flexibility data centers can offer depends, in part, on the workload. The two main types of workload are AI training (the process of developing, say, a large language model or image generation model) and inference (using that model to, say, generate responses to users’ chatbot questions and requests for images).

Training requires huge data centers with tightly interconnected GPUs. For example, Meta’s Llama 3.1 405B model took about two and a half months to train on 16,000 GPUs. During training, adjusting all the model weights at once at each step requires the GPUs to be connected via high-speed links, such as Nvidia’s NVLink and InfiniBand interconnects. It wouldn’t be practical to spread out AI training workloads among a fleet of mini data centers. On the bright side, because training takes months, it’s possible to pause for short periods of time to curtail energy use during peak demand.

Inference doesn’t require as many GPUs or as much fancy networking. Instead of a huge corpus of data, a single user’s query is fed into the model, and the model spits out the answer. No backpropagation is involved—that is, no large-scale coordination between different chunks of input data is needed. And so inference is amenable to smaller data centers. However, timing is key. When you ask an image generator for a picture of your face pasted onto a cute cat, you understandably expect to see the result right away. So rather than briefly pausing compute during peak demand, the energy flexibility can come through creatively shifting the workload to a different location.

“Inference is one of the few workloads that can be dynamically routed,” says Valerie Crafton, senior vice president of strategy and operations at modular data center company Mod42. “Which means that you can align the compute with wherever the power is actually available. That’s one unique piece that’s really driving the push for a lot of these smaller data centers where the power exists.”

Both Nvidia and EPRI have been on a tear to demonstrate different kinds of data center flexibility. They’re calling their substation-based strategy “distributed inference.” Announced in February, the project aims to begin construction of the pilot fleet of small data centers by the end of 2026. Nvidia and EPRI estimate that compute workloads will need to be moved to a different substation only about 0.1 percent of the time.

Going micro in data center size is an idea that’s picking up speed. “We’re in this compute wave currently where everybody’s building these really large data centers—5 gigawatt, mammoth things,” says Sooter. But “there’s a second compute wave coming,” involving much smaller data centers handling inference, he says. Tech companies are “really beating the drum on this because they see demand for inference compute really picking up in 2027,” he says.

This story was updated on 13 May, 2026 to correct the source of the 76-GW figure.

The rapid advancement of large language models (LLMs) is fueling a global data center boom and driving a surge in energy demand. But the electricity required to power data centers is straining the grid, pushing infrastructure operators to search for alternative sources of power. Some are even looking beyond Earth.

One company that’s looking to the stars for energy is Orbital Inc. In mid-April, the Los Angeles–based startup emerged from stealth and announced plans to build space data centers. Backed by Andreessen Horowitz (A16z), Orbital is designing infrastructure for AI inference, where trained models generate outputs. Much like other companies advocating for space-based data centers, Orbital is banking on the “free” energy generated by the sun to power compute for workloads such as chatbots and agents, sidestepping terrestrial energy constraints.

“There simply isn’t enough capacity here [on Earth], and the only way is up,” says Euwyn Poon, Orbital’s founder and CEO. “There’s actually abundant solar energy that’s not being harnessed.”

Orbital’s vision is a mesh constellation of small satellites in low Earth orbit. Each satellite would be equipped with a GPU server rack powered by solar panels roughly the size of a tennis court, plus radiative cooling panels of comparable size. The long-term goal is up to 10,000 fridge-sized satellites—each with 100 kilowatts of power—forming a distributed cloud, similar to SpaceX’s proposed AI Sat Mini.

Orbital’s first test will come in 2027, when it plans to launch a prototype satellite aboard a SpaceX Falcon 9 to validate its GPU operations in orbit and run commercial inference workloads. Another company, Starcloud, has already run a similar test last year. Orbital’s differentiator is their plans to match the solution with a problem: Small satellites equipped to run inference workloads specifically could benefit from lower launch costs. However, they face the same difficulties as other space data center hopefuls. Every watt of “free” energy must be dissipated as heat via large radiative coolers; radiation in low Earth orbit degrades compute equipment; and regular maintenance in space is difficult and costly.

Orbital’s inference focus

Poon says Orbital’s focus on a distributed network of smaller satellites designed to run inference workloads across independent GPU nodes, rather than large, tightly-coupled systems, makes the execution more feasible.

That idea shapes Orbital’s design. Training large AI models typically relies on tightly-coupled GPU clusters optimized for massive compute throughput. Inference workloads, by contrast, are generally less compute-intensive per request and can often run on smaller numbers of GPUs, making them easier to distribute across systems. Capping each satellite at roughly 100 kilowatts, Poon says, greatly simplifies the design. “It’s very simple,” Poon says, referring to the concept behind the satellites’ engineering. “Engineers would appreciate this.”

In Orbital’s design, a user request—like, say, asking ChatGPT to analyze a data set—is routed from a data center on Earth to a ground station, a terrestrial relay that connects satellites to the internet, then transmits the request to a satellite. Satellites communicate through optical interlinks, which use lasers to pass data between nodes. That routes the request to an available GPU, which processes the user’s query and generates the output before sending the result back through the network to the user. These links rely on ground stations that only communicate with satellites when they pass within range.

If the satellites are proven to work, Orbital is set on tapping “big model labs” as customers, including firms like OpenAI and Anthropic that run massive inference workloads. Orbital plans to serve them through direct API access for buying tokens and enterprise deals that shift inference demand into its network in space.

Engineering challenges

Poon recognizes that running data centers in space introduces major technical hurdles.

Radiation can strike GPUs and cause bit flips or other errors. Thermal management is also difficult. Without air, systems must rely on radiating heat into space rather than conventional cooling. Maintenance is another constraint, as satellites cannot be easily repaired or replaced if they malfunction in space. It’s why Poon says the test launch will be critical to identify and troubleshoot these issues. “Part of the mission is to figure out the unknowns,” he says.

Dr. Amit Verma, an electrical engineering professor at Texas A&M University–Kingsville, who researches semiconductor device modeling, raised similar concerns. Deploying thousands of satellites, Dr. Verma says, increases failure risk with limited repair options. He added that operational feasibility depends on the applications performed on the satellites. While some workloads like chatbots or algorithmic recommendations can tolerate added delays (data traveling to lower Earth orbit takes tens of milliseconds to return), others like real-time stock trading cannot.

“Outer space data centers that involve heavy use of AI-related processing certainly do need to overcome power and deployment and reliability issues to be meaningful,” Verma says.

Orbital plans to test extensively before launch. Poon says his company is exploring radiation hardening for GPUs and ammonia-based liquid cooling loops to transfer heat to external radiators. Reducing system weight is also top of mind to lower launch costs.

Even with these mitigations, the timeline is ambitious. In a Substack post on space data centers, Andrew Côté, an engineering physicist, predicts that space data centers won’t be operational for at least another 10 to 20 years. Orbital, however, expects to finalize the satellite designs by 2026, launch in 2027, and build a manufacturing facility in Los Angeles by 2028.

With the engineering challenges complex and the costs of launch high, the ability for Orbital’s satellite systems to operate reliably at scale remains an open question.

Despite those uncertainties, Poon remains laser focused on the long-term opportunity.

“I trust that our engineering efforts can start making progress towards solving these problems,” he says.

Cybersecurity consultants have never been more in demand. Information security analyst roles are projected to grow nearly 30 percent between now and 2034, according to the U.S. Bureau of Labor Statistics. More than 15 million cybercrime incidents occurred worldwide in 2024, Statista reported.

Data breaches are costly and pose direct safety risks. Statista reported that more than US $10 trillion is spent annually repairing the damage caused by cybercrime, most commonly phishing, spoofing, extortion, and data breaches. In one example in the United States, breathalyzer devices installed in vehicles became disabled, leaving hundreds of drivers stranded, as detailed in an IEEE Spectrum article.

To help you acquire the skills you need to distinguish yourself from other cybersecurity job candidates, the IEEE Computer Society offers a “What Makes a Great Cybersecurity Consultant” guide. The 23-page PDF includes hard and soft skills you need, a list of certifications to pursue, and key IEEE cybersecurity conferences for staying updated on developments in the field.

The guide includes advice from two cybersecurity experts. John D. Johnson, an IEEE senior member, is the founder and CEO of Aligned Security in Bettendorf, Iowa. Ricardo J. Rodriguez is an associate professor of computer science and systems engineering at the Universidad de Zaragoza, in Spain, who researches digital forensics and other cybersecurity topics.

“Technology, remote work, and a shortage of skilled workers make this the ideal time to consider becoming a cybersecurity consultant,” Johnson says in the guide. “Consulting can give you the flexibility, variety, and control over where you want your career to go.”

Hard and soft skills

At a minimum, cybersecurity professionals should have a general understanding of IT including operating systems, communication protocols, network architecture, and programming languages such as C++, Java, and Python. They also should be well-versed in security auditing, firewall management, penetration testing, and encryption technologies.

The principles of ethical hacking and coding would be handy as well.

“To be able to defend a system well, you first have to know how to attack it,” Rodriguez says.

The guide explains that there are now more technologies available to help cybersecurity consultants monitor threats and protect systems. They include security orchestration, automation, and response (SOAR) platforms, which automate workflows to collect security data, streamline incident response, and automate repetitive tasks.

Rodriguez points to advances in domain name system security extensions (DNSSEC), which uses digital signatures based on public-key cryptography to strengthen the authentication of the domain name system. By validating data authenticity, DNSSEC safeguards against attacks such as DNS spoofing and guarantees that users connect to the correct IP address.

Technologies such as artificial intelligence, blockchain, and quantum computing will increasingly be used to help thwart cyberattacks, the guide suggests. AI is expected to enhance the quality of data analysis, Rodriguez says.

Although hard skills are important, soft skills are just as crucial, according to the guide. Critical thinking, project management, flexibility, teamwork, and organizational and presentation skills are essential.

It’s not enough to be good at analyzing security vulnerabilities; you also need to clearly describe the situation and explain possible solutions.

“Soft skills are important to achieve good team cohesion,” Rodriguez says, “because consultants often lead diverse teams from within their client’s organization.”

“It’s essential,” Johnson adds, “that you demonstrate to clients you’re a team player and a capable communicator, and that you meet your commitments.”

Security certifications

Possessing security-specific credentials is a valuable way to demonstrate your expertise to potential clients, according to the guide. Because hundreds of certifications are available, Johnson says, pinpointing the most relevant ones can be challenging. Some people focus on theoretical knowledge, while others want to cover practical applications of technology.

“Survey the industry and compare it to your skills,” Johnson recommends. “Decide what you want to do, and identify where you have gaps in your skills and experience.”

Here are four of the nine certifications listed in the guide that are frequently cited as being important. All the providers are cybersecurity organizations.

• Certified information security manager. This globally recognized certification from the ISACA is for professionals managing enterprise information security.
• Certified cloud security professional. Offered by ISC2, this credential validates advanced technical skills in designing, managing, and securing cloud infrastructure.
• Certified ethical hacker. This certification from the International Council of E-Commerce Consultants (C-Council) confirms proficiency in using methods commonly employed by malicious hackers to detect vulnerabilities.
• Offensive security certified professional. A hands-on, 24-hour certification exam offered by OffSec covers practical testing skills.

Additional industry-specific certifications might be required for organizations in finance, government, health care, or manufacturing.

Sound general knowledge—backed by experience, training, and certification—is an essential foundation for being a specialist, Johnson says.

Conferences and networking opportunities

Events sponsored by the IEEE Computer Society can help you learn about the latest research and advancements in cybersecurity:

• IEEE Symposium on Security and Privacy, from 18 to 21 May in San Francisco.
  
• IEEE European Symposium on Security and Privacy, from 6 to 10 July in Lisbon.
  
• IEEE International Conference on Cyber Security and Resilience, from 3 to 5 August in Lisbon.
  
• IEEE Secure Development Conference, from 14 to 16 October in Indianapolis.

Conferences can give you insight into the field and let you do some networking, but it’s important to network elsewhere as well, experts say. Consider joining the IEEE Technical Community on Security and Privacy, which connects experts and professionals advancing research in areas such as encryption, operating system security, and data privacy.

Learning and meeting people keeps your knowledge sharp and can lead to mentorship opportunities with established cybersecurity consultants, Johnson says.

Other IEEE resources

The IEEE Computer Society’s cybersecurity resources page offers a wealth of information including fundamentals, possible career paths, and standards development. To keep you updated on trends, the society publishes IEEE Transactions on Privacy and the IEEE Security and Privacy magazine.

In addition to the guide, the IEEE Learning Network offers nearly 30 courses on cybersecurity. And you can find research papers in the IEEE Xplore Digital Library.

Managing heat in AI data centers is a growing challenge. As hyperscalers cram more and more high-power computing systems into huge facilities, they generate more and more heat. Data center designs are switching from fan-based systems to liquid ones, which pipe water near electronics to gather up waste heat. That hot water is then cooled, dissipating the heat into the environment.

Michael Abdelmaseh has a different idea: What if some of that waste heat could be utilized and converted back into usable electricity? The thermoelectric effect, by which certain materials can convert thermal energy into electrical energy and vice versa, has been known for about 200 years. The company Phononic is using thermoelectrics to cool data centers using electricity.

Reversing that process, thermoelectric generators harvest heat to produce electricity, but they currently aren’t very durable nor versatile. Abdelmaseh, founder and head engineer of PyroDelta Energy, wants to make thermoelectric generators that can easily be integrated with data center liquid cooling systems, in engines, and in drones. This will not replace traditional cooling methods, since thermoelectric materials are currently limited in efficiency, but it could introduce some heat reuse. PyroDelta is a subsidiary of Vancouver-based First Tellurium.

The main thermoelectric material in commercial use today is bismuth telluride. The material is grown in large crystals—which is necessary, because the quality of the crystal contributes to its ultimate thermoelectric performance—and then sawed into smaller pieces that can be soldered together to make devices. Slicing and dicing the crystals generates waste material, which increases costs. And bismuth telluride cylinders can only be hewn into a limited number of shapes, typically tiny cubes, says Abdelmaseh. The crystals themselves are also prone to cracking. Another drawback is the assembly of the devices themselves. They are typically soldered together and melt when exposed to very high temperatures.

Abdelmaseh, previously an engineer at Toyota, wanted to make a more versatile thermoelectric generator. He developed a way to grow bismuth telluride crystals into a variety of shapes. This eliminates process steps and materials waste, he says. Instead of growing large crystals, PyroDelta relies on the capillary effect to draw the raw materials into molds during crystallization.

“Based on the cavity where the crystal grows, you can decide the final size and shape of the crystal,” he says. Using these methods, it’s possible to make curved shapes, not just cubes. These curved designs can be made in the shape of rings to create a tube-shaped thermoelectric generator that goes around a water pipe in a cooling system, for instance. And the materials are less brittle than those made by sawing, which improves durability.

Thermoelectric generators that can convert some of the waste heat in data centers back into electricity. Michael Abdelmaseh

Abdelmaseh says this capillary casting method leads to a 60-80 percent reduction in materials waste, and approximately 10 times longer durability.

The company has developed a prototype energy harvester for data centers. While the electricity generated with the prototype is not nearly enough to run an AI data center, Abdelmaseh says it should be sufficient to power temperature sensors, security cameras, and other sensors within data centers. The company has also developed a prototype thermoelectric car radiator that gathers heat to produce energy to run the electrical systems in gas-powered cars. Abdelmaseh says this could improve the efficiency of internal combustion engines by 5 percent.

AI image processing aboard satellites in space has been a goal of the Earth observation industry for years. Now it has finally been achieved. Planet Labs, based in Calif., released an image captured by its Pelican-4 multispectral satellite showing an airport in Alice Springs, Australia. On the tarmac, more than a dozen aircraft are scattered, each highlighted in a neat green box, identified by an AI model running aboard the satellite.

Planet Labs’ engineers had worked 18 months to accomplish reliable autonomous object classification from space. They hope the technology will put Earth observation on steroids, enabling autonomous tasking and real-time sharing of insights with users on Earth.

“The entire remote-sensing industry has been known to put exotic sensors in space,” said Kiruthika Devaraj, vice president of engineering at Planet Labs. “We have very good eyes in space looking at everything that’s going on. But then, we collect so much data and have to wait six to 12 hours to get the information out. So, you’re essentially looking at the past.”

Planet Labs currently operates a constellation of several hundred Dove and SuperDove CubeSats, each only 30 centimeters long. These low-cost space cameras scan the entire surface of Earth multiple times a day at a resolution of around 5 meters. The company is also building up a fleet of larger satellites, called Pelicans, which image the planet’s surface in 30-centimeter detail. The fourth of these, deployed into orbit in 2025, ran the airplane-recognition algorithm.

All Planet’s satellites combined generate 30 terabytes of data per day—equivalent to 10,000 hours of high-definition video, which gets beamed to the ground for processing and analysis via tens of radio stations scattered all over the world.

Transferring the downloaded data into the cloud for processing and subsequent AI analysis takes hours, leading to delays, which could mean that a sparked wildfire gets noticed only when it’s too large to quickly contain.

“Minutes matter in some sectors,” Devaraj said. “And real-time insights really enable us to provide answers to problems as they’re unfolding.”

The AI image-recognition algorithms developed by Devaraj and her team analyze a single Pelican image comprising 16,000 pixels in half a second, using onboard GPUs. The results can be in the hands of users in minutes from the moment the image was taken.

Planet Labs

So far, only the Pelican satellites are fitted with AI-capable processors—the Nvidia Jetson Orin GPU modules frequently used in autonomous drones. But Devaraj says Planet plans to augment the SuperDove constellation with a new type of satellite, called the Owl. The satellite will provide daily revisits with a higher resolution of up to 1 meter and will also be fitted with Nvidia’s Jetson processors, which are capable of AI detection.

The new fleet would enable the company to begin working on what Devaraj describes as “planetary intelligence.” Working as a single intelligent-satellite network, the Owls would constantly monitor the planet and autonomously flag potential problems directly to the higher-resolution Pelicans to revisit without the need for human interference.

“We want to put the brain, all the compute, right next to the sensors,” Devaraj said, “so that the system of satellites we build acts like a biological network that is responding to stimuli in real time.”

In the future, the company wants to switch to more-powerful Nvidia Jetson Thor processors and eventually run large language models (LLMs) in space.

“In five or 10 years, when we all get used to just accepting what Gemini and Claude and other LLMs give you, we may train some generic LLM on satellite imagery and just get text answers to what it sees,” said Devaraj. “You could just get a text message on your phone that says, ‘Three minutes ago, I detected this ship without an AIS transmitter, so it’s an illegal ship, and these are the specific coordinates.’ ”

The Earth-observation industry has been talking about onboard AI processing for almost a decade. But until recently, the technology wasn’t ready to run AI algorithms in space fast enough and reliably enough.

“We started with the early Nvidia Jetson processors, but until the Orin iteration, they didn’t have enough compute power,” Devaraj said.

To run onboard AI image analysis in space, the algorithms need to be able to handle unprocessed raw data that hasn’t been smoothened out and corrected, unlike data crunched by AI algorithms on Earth.

“There’s a lot of satellite-level uncertainties,” said Devaraj. “The satellite’s moving, the satellite’s wobbling, vibrating. On the ground, the processing takes hours to correct all of that.”

It took Planet engineers 18 months to achieve 80 percent detection reliability with the AI onboard model, Devaraj said. The team hopes the next iteration of their algorithm will increase that accuracy to over 95 percent.

The space-based real-time AI-detection service will only be made available to customers in the next six to nine months.

Devaraj thinks that when it comes to AI in space, this is only a start. Planet is collaborating with Google on the Suncatcher project, which intends to deploy a vast constellation of data-processing satellites into Earth’s orbit. The project is one in a plethora of recently discussed ventures that envision moving Earth-based data-crunching infrastructure off the planet. Proponents, including tech giants SpaceX and Amazon, believe that in Earth’s orbit, power-hungry computers will be able to run on free solar power and be easily cooled without straining water supplies. But critics question whether large-scale computing infrastructure could ever be launched cheaply enough to compete with technology on Earth.

Google and Planet plan to fly two prototype satellites in 2027.

This story was updated on 4 May, 2026 to correct the number of Pelican satellites that Planet Labs is planning to launch. The original version of this story said 32 satellites, but the company has not committed to a final specific number at this time.

Most cloud computing services encrypt data in transit and at rest. But that data still needs to be decrypted before cloud servers or virtual machines can perform any kind of computation on it. This risks exposing data—especially sensitive information such as financial transactions or medical records—during processing. This is where the Fog comes in.

Launched in early April by chip startup Niobium, the Fog is an encrypted cloud platform. It follows a client-server architecture, where a person or organization (the client) can encrypt data or workloads locally using their own private keys and deploy the encrypted data or workloads to the Fog (the server) without sharing their keys. These private keys remain with data owners, and only they can decrypt any results from the platform.

Much as actual fog obscures everything it envelops, so does the encrypted cloud platform named after it. Yet unlike physical fog that eventually lifts, the Fog keeps data opaque at all times—even as computation happens.

“The data in our cloud will never be exposed—it’s always encrypted,” says John Barrus, vice president of product at Niobium. “It’s a new category of cloud.”

Fully Homomorphic Encryption keeps the Fog secure

Beneath the Fog lies a cryptographic technique known as fully homomorphic encryption, or FHE, which allows for computing on encrypted data without the need to decrypt it. But FHE is often slow and requires a lot of computing power and memory.

Niobium aims to address these bottlenecks using Mistic, its FPGA (field-programmable gate array) chip, which is configured to run FHE. For some applications the company is testing, this accelerator hardware runs FHE about twice as fast as today’s GPUs, Barrus says.

To demonstrate the usability of its encrypted cloud platform, Niobium has developed a handful of template applications “that solve typical problems where you might want to hide the data or keep it encrypted, so people can start there and just try it out,” says Barrus. One such template application involves encrypted semantic search, which queries databases or datasets and returns relevant results based on the context or meaning of the search terms rather than keywords that match them. Both the query and the data source are encrypted, helping ensure data privacy.

“Let’s say you’re a legal firm, and you have sensitive case documents. You encrypt all those documents and store them encrypted in the cloud,” Barrus says. In this scenario, you can ask questions about the documents using encrypted semantic search “and get pointers to those documents back, and then just download and decrypt the documents you need.”

Niobium takes FHE from theory to practice

Kurt Rohloff, cofounder and CTO at Duality Technologies, is excited about the prospect of running his company’s privacy-enhancing software products on the Fog. Duality provides software that uses FHE, including an LLM inference framework. Without a platform like the Fog, users may need to purchase dedicated FHE acceleration hardware, he says. But “the Niobium encrypted cloud platform allows users to rapidly scale their use of FHE-protected computing [and] get much more value from their data,” he says.

Echoing the sentiment is Rashmi Agrawal, cofounder and CTO at CipherSonic Labs, a company building FHE-powered encrypted AI infrastructure. “Platforms like Niobium are important because they help move FHE from theory into deployable infrastructure,” she says. “An encrypted cloud platform built on FHE fundamentally changes the trust model of cloud computing. This significantly reduces exposure to data leakage, insider threats, and compliance risks while enabling organizations to safely process highly sensitive data in the cloud.”

However, Agrawal points out that despite FHE’s rapid progress, there are still practical challenges. These include performance overheads for complex tasks or workloads that need to be completed with low latency, as well as filling in skills gaps for software developers who have no FHE knowledge or experience. “Building FHE-compatible applications often requires rethinking traditional approaches. The ecosystem is still maturing as tooling, standards, and interoperability continue to evolve,” she adds.

Barrus acknowledges these hurdles. “I think the real challenge is large language models with a lot of matrix and vector multiplications. We have to be fast enough that you’re not waiting minutes for every token but seconds or so. That’s going to be much harder to solve,” he says.

In terms of equipping developers without any FHE background, Niobium hopes to make the Fog more accessible by providing a tech stack composed of a compiler, software development kit, documentation, and other training materials. “If we can bring FHE computation to more people, then more people can develop privacy-preserving applications,” says Barrus.

The Fog is currently available in private beta, with Niobium targeting May or June for a public launch. The company is also developing an application-specific integrated circuit for its encrypted cloud platform that Barrus says will be up to 25 times as fast as a GPU, depending on the application.

“What we’re trying to do is create value from encrypted data,” he says. “Our vision is that data never has to be exposed to be useful.”

This article was updated on May 7 to clarify the nature of the Mistic FPGA.

As more AI data centers come on line, concerns are rising about their effects on the grid, and it’s not just the amount of power they consume. They tend to have huge swings in power use, surging up and down by 70 percent or more in milliseconds. Traditional electricity infrastructure isn’t designed to deal with that kind of load fluctuation.

To address the problem, researchers are developing power electronics systems that sit between the data center and the grid to act as a buffer and even as a grid helper in times of need. One such system, developed by the Miami-based company ON.energy, is being implemented across 3 gigawatts’ worth of projects, and has sailed through a battery of tests at the U.S. National Lab of the Rockies (NLR).

In the tests, ON.energy’s system sat between a simulated data center and a simulated grid. The system successfully protected the data center from grid instability and also safeguarded the grid from the major load swings generated by the data center. The company’s technology involves a bidirectional uninterruptible power supply (UPS) that it calls AI UPS.

Such grid buffers are becoming increasingly important as AI facilities expand to gigawatt scale and beyond. Utilities have major concerns about both the amount of power demanded by these data centers and their potential to create system instability due to wild variations in loads. Innovations are needed to help data centers become better grid citizens, and shorten the amount of time they must wait to connect to the grid.

AI Data Centers and Grid Stability

UPS systems have been used for decades to protect data centers from grid events. If frequency varies suddenly or power is lost, these unidirectional systems provide almost instantaneous, short-term backup power to the equipment inside the data center. Because servers can’t tolerate more than minor deviations, UPS electronics also clean up low-quality power, such as voltage spikes or sags and frequency deviation.

UPS has served data centers well. But the scale of modern facilities packed with graphics processing units (GPUs) changes the game. Instead of data centers whose size is measured in tens of megawatts, AI facilities are reaching up to 5 GW. They still require the type of protection afforded by UPS, but their massive scale and load volatility pose dangers to the grid.

During a minor grid fault in Virginia in 2025, for example, several data centers tripped offline, causing 1.5 GW to drop off the grid simultaneously. This caused panic for the system operator, who had to act fast to balance the system and avoid a major power outage.

In addition to major changes in overall load, AI data centers can generate short-lived, high-voltage, or high-current disturbances known as grid transients. They may only last microseconds, but they can break down insulation, overheat transformers, cause electrical arcing, start fires, and destabilize an entire grid.

“The scale of modern data centers could lead to load swings of 1 GW multiple times per minute, which creates frequency variations and oscillations that the grid can’t handle,” says Ricardo de Azevedo, CTO at ON.energy.

These problems have given utilities and government authorities pause. Some authorities in the United States and parts of Europe are implementing moratoriums on new data centers or instituting rules that place responsibility for grid conditions onto the data center.

Texas Senate Bill 6, for example, requires new data centers to pay a share of any new grid infrastructure needed by their facilities. Additional requirements for voltage ride-through—the equipment’s ability to continue operating during power disruptions—are currently being formulated in accordance with this bill. Such rules aim to prevent large data centers from tripping offline suddenly or overwhelming the grid due to severe load variability from AI workloads.

“One of our customers in Texas that is building a 1-GW campus is now being required by the local grid authority to include voltage ride-through,” Azevedo says.

NLR engineers Przemyslaw Koralewicz [left] and Shahil Shah monitor the results of a simulation of ON.energy’s AI UPS in the control center at the NLR Flatirons Campus.Agata Bogucka/NLR

Bidirectional UPS

ON.energy’s 3.5-megawatt units consist of a power conversion system (PCS), batteries to store energy and act as an energy reservoir or buffer, another PCS, and a transformer. The batteries can provide up to eight hours of backup power, depending on the size of the data center. ON.energy sources this equipment from established manufacturers and adds its own software and controls.

The latest PCS units are bidirectional, acting as the interface between the grid, the batteries, and the data center. They convert between the alternating current (AC) from the grid, the direct current (DC) stored in the batteries, and the AC delivered to the data-center load, ensuring power quality and optimal flow when feeding an AI facility. In the other direction, the PCS absorbs and smooths transients caused by sudden load swings in the data center that would otherwise disrupt the grid.

“The batteries act like a reservoir of energy as well as a shock absorber, should there be any disturbances on the grid or from the data center,” says Azevedo.

ON.energy’s system is housed outside the data center, rather than inside as most UPS systems are, which frees up space internally for more compute resources. Being outside also allows the system to harness more advanced power electronics fed by medium voltage. Traditional UPS, on the other hand, operates on the low voltages needed by data-center computers for safety reasons.

The company has about 3 GW of these bidirectional AI UPS units either operating or under construction. It expects to commission a system in May for a 1.5-GW AI data center in Texas, according to Azevedo. For such a facility, hundreds of these 3.5-MW units would be required.

NLR’s Data Center-Grid Simulator

To test its system, ON.energy turned to NLR (formerly known as the National Renewable Energy Laboratory). The facility is likely the only one in the world that can do full-load, bidirectional testing that simulates both grid conditions and variable data-center loads. The facility can test up to 20 MW with voltage levels reaching 13.2 kilovolts. The test consisted of a 7-MW grid simulator that replicates disturbances and voltage ride-through events, and a 20-MW load simulator that reproduces real-world demand dynamics such as those created by an AI data center.

All over the world, researchers are working on an urgent and surprisingly difficult challenge: creating a cost-effective yet powerful permanent magnet that doesn’t use rare earth elements. Rare earth magnets are essential components of the motors for electric vehicles, heating and cooling systems, robots, tools, and appliances, and they’re also essential for wind turbines, audio speakers, and other systems. A strong magnet that doesn’t use rare earths would be of almost incalculable value, because it would free its users from China’s near-monopoly on rare earth elements and magnets. By circumventing that monopoly, it would almost certainly alter geostrategic calculations and global supply chains in short order.

Tantalizingly, no physics theories preclude the existence of a powerful and rare-earth-free magnet. And yet, after more than a decade of intensive efforts by many exceptionally bright people, no such magnet has been discovered.

Now, a small group of researchers in France and the United States has set out to test an intriguing hypothesis—that the problem can be solved with quantum computers. “You need the math of quantum mechanics to solve a problem that lives in the quantum realm,” declares Théau Peronnin, CEO of Alice & Bob, a Paris-based quantum computer startup. Alice & Bob is collaborating with Los Alamos National Laboratory and GE Vernova, with US $3.9 million in funding from the U.S. Department of Energy’s ARPA-E Quantum Computing for Computational Chemistry program.

Why Rare Earth Magnets Still Dominate

More than 67,000 compounds are known to have some degree of permanent magnetism. None, however, come close to the reigning permanent-magnet champ, neodymium iron boron (NdFeB), which dominates high-power applications.

For more than 15 years, researchers have used conventional high-performance computers to search for new and powerful magnets. But no commercially successful magnets have come out of that work. Even the best conventional computers aren’t powerful enough to simulate the detailed magnetic properties of a hypothetical permanent magnet.

To understand why, start with the basics. Permanent magnetism arises in certain crystalline materials when the spins of electrons of some of the atoms in the crystal are forced to point in the same direction, either “up” or “down.” The more of these aligned spins, the stronger the magnetism. The ideal atoms are ones that have unpaired electrons swarming around the nucleus in what are known as 3d orbitals. Tops are iron, with four unpaired 3d electrons, and cobalt, with three.

But 3d electrons alone are not enough to make superstrong magnets. As researchers discovered decades ago, magnetic strength can be greatly improved by adding to the crystalline lattice atoms with unpaired electrons in the 4f orbital—notably the rare earth elements neodymium, praseodymium, and dysprosium. These 4f electrons enhance a characteristic of the crystalline lattice called magnetic anisotropy—in effect, they promote adherence of the magnetic moments of the atoms to the desired directions in the crystal lattice. That, in turn, can be exploited to achieve high coercivity, the essential property that lets a permanent magnet stay magnetized.

“The combinatorial space is just ridiculously large. It’s 2 to the—I don’t know—40th or 50th power. It’s absolutely tremendous.”

The point is that being able to accurately simulate a hypothetical magnet means not only accounting for all those electron orbitals and spin states but also simulating the interaction of all those electron orbitals and spin states. And that’s really, really hard.

“Let’s say you have a chain of atoms, each with a single electron in the 1d orbital,” explains Peronnin. “And then you want to understand: If the spin of this one electron is down, how does it affect its neighbors? Would they be more likely to be up or down? And you need to do so for all the electrons in your chain. And then see if the total system has a tendency to align all its electron spins. Or, once you’ve added a bit of thermal noise and an external magnetic field, for example, how much disorder would there be in that chain? And so those are exactly the properties you want to predict.

“The emergent global properties [such as magnetism] arise from the local behavior of each electron. But each electron’s behavior is highly, highly correlated with how its neighbors behave. And this is what makes the problem extremely difficult, because you cannot treat each of those electrons individually. You need to treat the whole system with all its possible configurations all at once to predict the global properties. And this is where the computing space explodes.

“You have to consider all the possible superpositions of states of those electrons,” Peronnin continues. “And so here, the combinatorial space is just ridiculously large. It’s 2 to the, I don’t know, 40th or 50th power. It’s absolutely tremendous.”

Why Quantum Computers Might Finally Solve This Problem

The great potential advantage of quantum computers here is quantum parallelism, a capability that emerges directly from the qubits that are the heart of a quantum computer. In such a machine, these qubits are entangled with one another. The qubits are also in a state of superposition, which means that they can embody, in the macro world, certain quantum characteristics of subatomic particles. Namely, they can represent a binary 0 or 1 and also exist in a continuous range of states, each with an associated pair of probabilities—a probability that the bit is 0 and a corresponding probability that it’s 1. And the more there are of these superimposed qubits that are entangled, the more states those qubits can represent: A collection of n entangled qubits can represent 2ⁿ states simultaneously. The upshot is that with enough qubits, a quantum computer could handle the stupendous computational challenge of accurately simulating a hypothetical magnetic material.

How many qubits are enough? Peronnin figures things will start getting interesting when he and his colleagues can build a machine that has 100 logical qubits furnished with a proprietary type of error correction that they have pioneered. He figures that will happen around 2030. (IBM and others have already built quantum computers with over 1,000 physical qubits, but these machines did not have the error correction that is the defining characteristic of logical qubits, and none of them ever performed useful work.)

A strong magnet that doesn’t use rare earths would be of almost incalculable value.

Magnetics researchers not involved with the ARPA-E effort are mostly supportive of the project, while noting that progress on quantum computers is notoriously difficult to predict. “This is an interesting approach,” says Jiadong Zang, a professor of materials science and director of the materials science program at the University of New Hampshire. “You need some extraordinary approach to find some new structures,” he adds. Zang is part of a group that has been using a large language model to search the magnetics literature for the purpose of creating a database of experimental magnets, called the Northeast Materials Database for Magnetic Materials.

“This might be a task that quantum computers could do well,” agrees Matthew Kramer, Distinguished Scientist at Ames National Laboratory, in Iowa. (Kramer is working on a project with the U.S. Department of Energy and Fermilab aimed at improving a certain class of qubits.) He cautions, however, that efforts to use conventional computers to identify new magnet materials have often identified new candidates that could not possibly be built in the real world.

Microsoft’s Imaginary Magnets Will Probably Stay That Way

A recent and highly ambitious project at Microsoft, for example, resulted in a system called MatterGen, which the researchers used to design a range of magnets with “low supply-chain risk.” However, the researchers simplified the problem greatly by focusing on “high magnetic density” alone, without trying to incorporate any of the many other characteristics needed for a magnet to be useful. Taking into account such characteristics, including high coercivity, chemical stability, and cost effectiveness, is a big reason why the challenge quickly becomes computationally intractable. In the end, the researchers did not fabricate any of the magnets identified; it’s not even clear that they could.

“They had a lot of unusual structures,” Kramer notes. “The real question there is, can any of those actually be synthesized?”

When it comes to AI models, size matters.

Even though some artificial-intelligence experts warn that scaling up large language models (LLMs) is hitting diminishing performance returns, companies are still coming out with ever larger AI tools. Meta’s latest Llama release had a staggering 2 trillion parameters that define the model.

As models grow in size, their capabilities increase. But so do the energy demands and the time it takes to run the models, which increases their carbon footprint. To mitigate these issues, people have turned to smaller, less capable models and using lower-precision numbers whenever possible for the model parameters.

But there is another path that may retain a staggeringly large model’s high performance while reducing the time it takes to run an energy footprint. This approach involves befriending the zeros inside large AI models.

For many models, most of the parameters—the weights and activations—are actually zero, or so close to zero that they could be treated as such without losing accuracy. This quality is known as sparsity. Sparsity offers a significant opportunity for computational savings: Instead of wasting time and energy adding or multiplying zeros, these calculations could simply be skipped; rather than storing lots of zeros in memory, one need only store the nonzero parameters.

Unfortunately, today’s popular hardware, like multicore CPUs and GPUs, do not naturally take full advantage of sparsity. To fully leverage sparsity, researchers and engineers need to rethink and re-architect each piece of the design stack, including the hardware, low-level firmware, and application software.

In our research group at Stanford University, we have developed the first (to our knowledge) piece of hardware that’s capable of calculating all kinds of sparse and traditional workloads efficiently. The energy savings varied widely over the workloads, but on average our chip consumed one-seventieth the energy of a CPU, and performed the computation on average eight times as fast. To do this, we had to engineer the hardware, low-level firmware, and software from the ground up to take advantage of sparsity. We hope this is just the beginning of hardware and model development that will allow for more energy-efficient AI.

What is sparsity?

Neural networks, and the data that feeds into them, are represented as arrays of numbers. These arrays can be one-dimensional (vectors), two-dimensional (matrices), or more (tensors). A sparse vector, matrix, or tensor has mostly zero elements. The level of sparsity varies, but when zeroes make up more than 50 percent of any type of array, it can stand to benefit from sparsity-specific computational methods. In contrast, an object that is not sparse—that is, it has few zeros compared with the total number of elements—is called dense.

Sparsity can be naturally present, or it can be induced. For example, a social-network graph will be naturally sparse. Imagine a graph where each node (point) represents a person, and each edge (a line segment connecting the points) represents a friendship. Since most people are not friends with one another, a matrix representing all possible edges will be mostly zeros. Other popular applications of AI, such as other forms of graph learning and recommendation models, contain naturally occurring sparsity as well.

Beyond naturally occurring sparsity, sparsity can also be induced within an AI model in several ways. Two years ago, a team at Cerebras showed that one can set up to 70 to 80 percent of parameters in an LLM to zero without losing any accuracy. Cerebras demonstrated these results specifically on Meta’s open-source Llama 7B model, but the ideas extend to other LLM models like ChatGPT and Claude.

The case for sparsity

Sparse computation’s efficiency stems from two fundamental properties: the ability to compress away zeros and the convenient mathematical properties of zeros. Both the algorithms used in sparse computation and the hardware dedicated to them leverage these two basic ideas.

First, sparse data can be compressed, making it more memory efficient to store “sparsely”—that is, in something called a sparse data type. Compression also makes it more energy efficient to move data when dealing with large amounts of it. This is best understood by an example. Take a four-by-four matrix with three nonzero elements. Traditionally, this matrix would be stored in memory as is, taking up 16 spaces. This matrix can also be compressed into a sparse data type, getting rid of the zeros and saving only the nonzero elements. In our example, this results in 13 memory spaces as opposed to 16 for the dense, uncompressed version. These savings in memory increase with increased sparsity and matrix size.

In addition to the actual data values, compressed data also requires metadata. The row and column locations of the nonzero elements also must be stored. This is usually thought of as a “fibertree”: The row labels containing nonzero elements are listed and linked to the column labels of the nonzero elements, which are then linked to the values stored in those elements.

In memory, things get a bit more complicated still: The row and column labels for each nonzero value must be stored as well as the “segments” that indicate how many such labels to expect, so the metadata and data can be clearly delineated from one another.

In a dense, noncompressed matrix data type, values can be accessed either one at a time or in parallel, and their locations can be calculated directly with a simple equation. However, accessing values in sparse, compressed data requires looking up the coordinates of the row index and using that information to “indirectly” look up the coordinates of the column index before finally reaching the value. Depending on the actual locations of the sparse data values, these indirect lookups can be extremely random, making the computation data-dependent and requiring the allocation of memory lookups on the fly.

Second, two mathematical properties of zero let software and hardware skip a lot of computation. Multiplying any number by zero will result in a zero, so there’s no need to actually do the multiplication. Adding zero to any number will always return that number, so there’s no need to do the addition either.

In matrix-vector multiplication, one of the most common operations in AI workloads, all computations except those involving two nonzero elements can simply be skipped. Take, for example, the four-by-four matrix from the previous example and a vector of four numbers. In dense computation, each element of the vector must be multiplied by the corresponding element in each row and then added together to compute the final vector. In this case, that would take 16 multiplication operations and 16 additions (or four accumulations).

In sparse computation, only the nonzero elements of the vector need be considered. For each nonzero vector element, indirect lookup can be used to find any corresponding nonzero matrix element, and only those need to be multiplied and added. In the example shown here, only two multiplication steps will be performed, instead of 16.

The trouble with GPUs and CPUs

Unfortunately, modern hardware is not well suited to accelerating sparse computation. For example, say we want to perform a matrix-vector multiplication. In the simplest case, in a single CPU core, each element in the vector would be multiplied sequentially and then written to memory. This is slow, because we can do only one multiplication at a time. So instead people use CPUs with vector support or GPUs. With this hardware, all elements would be multiplied in parallel, greatly speeding up the application. Now, imagine that both the matrix and vector contain extremely sparse data. The vectorized CPU and GPU would spend most of their efforts multiplying by zero, performing completely ineffectual computations.

Newer generations of GPUs are capable of taking some advantage of sparsity in their hardware, but only a particular kind, called structured sparsity. Structured sparsity assumes that two out of every four adjacent parameters are zero. However, some models benefit more from unstructured sparsity—the ability for any parameter (weight or activation) to be zero and compressed away, regardless of where it is and what it is adjacent to. GPUs can run unstructured sparse computation in software, for example, through the use of the cuSparse GPU library. However, the support for sparse computations is often limited, and the GPU hardware gets underutilized, wasting energy-intensive computations on overhead.

Petra Péterffy

When doing sparse computations in software, modern CPUs may be a better alternative to GPU computation, because they are designed to be more flexible. Yet, sparse computations on the CPU are often bottlenecked by the indirect lookups used to find nonzero data. CPUs are designed to “prefetch” data based on what they expect they’ll need from memory, but for randomly sparse data, that process often fails to pull in the right stuff from memory. When that happens, the CPU must waste cycles calling for the right data.

Apple was the first to speed up these indirect lookups by supporting a method called an array-of-pointers access pattern in the prefetcher of their A14 and M1 chips. Although innovations in prefetching make Apple CPUs more competitive for sparse computation, CPU architectures still have fundamental overheads that a dedicated sparse computing architecture would not, because they need to handle general-purpose computation.

Other companies have been developing hardware that accelerates sparse machine learning as well. These include Cerebras’s Wafer Scale Engine and Meta’s Training and Inference Accelerator (MTIA). The Wafer Scale Engine, and its corresponding sparse programming framework, have shown incredibly sparse results of up to 70 percent sparsity on LLMs. However, the company’s hardware and software solutions support only weight sparsity, not activation sparsity, which is important for many applications. The second version of the MTIA claims a sevenfold sparse compute performance boost over the MTIA v1. However, the only publicly available information regarding sparsity support in the MTIA v2 is for matrix multiplication, not for vectors or tensors.

Although matrix multiplications take up the majority of computation time in most modern ML models, it’s important to have sparsity support for other parts of the process. To avoid switching back and forth between sparse and dense data types, all of the operations should be sparse.

Onyx

Instead of these halfway solutions, our team at Stanford has developed a hardware accelerator, Onyx, that can take advantage of sparsity from the ground up, whether it’s structured or unstructured. Onyx is the first programmable accelerator to support both sparse and dense computation; it’s capable of accelerating key operations in both domains.

CPUs, CGRAs, and FPGAs represent a trade-off between efficiency and flexibility. Each individual logic unit of a CPU is designed for a specific function that it performs efficiently. On the other hand, since each individual bit of an FPGA is configurable, these arrays are extremely flexible, but very inefficient. The goal of CGRAs is to achieve the flexibility of FPGAs with the efficiency of CPUs.

CGRAs are composed of efficient and configurable units, typically memory and compute, that are specialized for a particular application domain. This is the key benefit of this type of array: Programmers can reconfigure the internals of a CGRA at a high level, making it more efficient than an FPGA but more flexible than a CPU.

The Onyx chip, built on a coarse-grained reconfigurable array (CGRA), is the first (to our knowledge) to support both sparse and dense computations. Olivia Hsu

Onyx is composed of flexible, programmable processing element (PE) tiles and memory (MEM) tiles. The memory tiles store compressed matrices and other data formats. The processing element tiles operate on compressed matrices, eliminating all unnecessary and ineffectual computation.

The Onyx compiler handles conversion from software instructions to CGRA configuration. First, the input expression—for instance, a sparse vector multiplication—is translated into a graph of abstract memory and compute nodes. In this example, there are memories for the input vectors and output vectors, a compute node for finding the intersection between nonzero elements, and a compute node for the multiplication. The compiler figures out how to map the abstract memory and compute nodes onto MEMs and PEs on the CGRA, and then how to route them together so that they can transfer data between them. Finally, the compiler produces the instruction set needed to configure the CGRA for the desired purpose.

Since Onyx is programmable, engineers can map many different operations, such as vector-vector element multiplication, or the key tasks in AI, like matrix-vector or matrix-matrix multiplication, onto the accelerator.

We evaluated the efficiency gains of our hardware by looking at the product of energy used and the time it took to compute, called the energy-delay product (EDP). This metric captures the trade-off of speed and energy. Minimizing just energy would lead to very slow devices, and minimizing speed would lead to high-area, high-power devices.

Onyx achieves up to 565 times as much energy-delay product over CPUs (we used a 12-core Intel Xeon CPU) that utilize dedicated sparse libraries. Onyx can also be configured to accelerate regular, dense applications, similar to the way a GPU or TPU would. If the computation is sparse, Onyx is configured to use sparse primitives, and if the computation is dense, Onyx is reconfigured to take advantage of parallelism, similar to how GPUs function. This architecture is a step toward a single system that can accelerate both sparse and dense computations on the same silicon.

Just as important, Onyx enables new algorithmic thinking. Sparse acceleration hardware will not only make AI more performance- and energy efficient but also enable researchers and engineers to explore new algorithms that have the potential to dramatically improve AI.

The future with sparsity

Our team is already working on next-generation chips built off of Onyx. Beyond matrix multiplication operations, machine learning models perform other types of math, like nonlinear layers, normalization, the softmax function, and more. We are adding support for the full range of computations on our next-gen accelerator and within the compiler. Since sparse machine learning models may have both sparse and dense layers, we are also working on integrating the dense and sparse accelerator architecture more efficiently on the chip, allowing for fast transformation between the different data types. We’re also looking at ways to manage memory constraints by breaking up the sparse data more effectively so we can run computations on several sparse accelerator chips.

We are also working on systems that can predict the performance of accelerators such as ours, which will help in designing better hardware for sparse AI. Longer term, we’re interested in seeing whether high degrees of sparsity throughout AI computation will catch on with more model types, and whether sparse accelerators become adopted at a larger scale.

Building the hardware to unstructured sparsity and optimally take advantage of zeros is just the beginning. With this hardware in hand, AI researchers and engineers will have the opportunity to explore new models and algorithms that leverage sparsity in novel and creative ways. We see this as a crucial research area for managing the ever-increasing runtime, costs, and environmental impact of AI.

This article appears in the June 2026 print issue.

Many of the world’s most advanced electronic systems—including Internet routers, wireless base stations, medical imaging scanners, and some artificial intelligence tools—depend on field-programmable gate arrays. Computer chips with internal hardware circuits, the FPGAs can be reconfigured after manufacturing.

On 12 March, an IEEE Milestone plaque recognizing the first FPGA was dedicated at the Advanced Micro Devices campus in San Jose, Calif., the former Xilinx headquarters and the birthplace of the technology.

The FPGA earned the Milestone designation because it introduced iteration to semiconductor design. Engineers could redesign hardware repeatedly without fabricating a new chip, dramatically reducing development risk and enabling faster innovation at a time when semiconductor costs were rising rapidly.

The ceremony, which was organized by the IEEE Santa Clara Valley Section, brought together professionals from across the semiconductor industry and IEEE leadership. Speakers at the event included Stephen Trimberger, an IEEE and ACM Fellow whose technical contributions helped shape modern FPGA architecture. Trimberger reflected on how the invention enabled software-programmable hardware.

Solving computing’s flexibility-performance tradeoff

FPGAs emerged in the 1980s to address a core limitation in computing. A microprocessor executes software instructions sequentially, making it flexible but sometimes too slow for workloads requiring many operations at once.

At the other extreme, application-specific integrated circuits are chips designed to do only one task. ASICs achieve high efficiency but require lengthy development cycles and nonrecurring engineering costs, which are large, upfront investments. Expenses include designing the chip and preparing it for manufacturing—a process that involves creating detailed layouts, building masks for the fabrication machines, and setting up production lines to handle the tiny circuits.

“ASICs can deliver the best performance, but the development cycle is long and the nonrecurring engineering cost can be very high,” says Jason Cong, an IEEE Fellow and professor of computer science at the University of California, Los Angeles. “FPGAs provide a sweet spot between processors and custom silicon.”

Cong’s foundational work in FPGA design automation and high-level synthesis transformed how reconfigurable systems are programmed. He developed synthesis tools that translate C/C++ into hardware designs, for example.

At the heart of his work is an underlying principle first espoused by electrical engineer Ross Freeman: By configuring hardware using programmable memory embedded inside the chip, FPGAs combine hardware-level speed with the adaptability traditionally associated with software.

Silicon Valley origins: the first FPGA

The FPGA architecture originated in the mid-1980s at Xilinx, a Silicon Valley company founded in 1984. The invention is widely credited to Freeman, a Xilinx cofounder and the startup’s CTO. He envisioned a chip with circuitry that could be configured after fabrication rather than fixed permanently during creation.

Articles about the history of the FPGA emphasize that he saw it as a deliberate break from conventional chip design.

At the time, semiconductor engineers treated transistors as scarce resources. Custom chips were carefully optimized so that nearly every transistor served a specific purpose.

Freeman proposed a different approach. He figured Moore’s Law would soon change chip economics. The principle holds that transistor counts roughly double every two years, making computing cheaper and more powerful. Freeman posited that as transistors became abundant, flexibility would matter more than perfect efficiency.

He envisioned a device composed of programmable logic blocks connected through configurable routing—a chip filled with what he described as “open gates,” ready to be defined by users after manufacturing. Instead of fixing hardware in silicon permanently, engineers could configure and reconfigure circuits as requirements evolved.

Freeman sometimes compared the concept to a blank cassette tape: Manufacturers would supply the medium, while engineers determined its function. The analogy captured a profound shift in who controls the technology, shifting hardware design flexibility from chip fabrication facilities to the system designers themselves.

In 1985 Xilinx introduced the first FPGA for commercial sale: the XC2064. The device contained 64 configurable logic blocks—small digital circuits capable of performing logical operations—arranged in an 8-by-8 grid. Programmable routing channels allowed engineers to define how signals moved between blocks, effectively wiring a custom circuit with software.

Fabricated using a 2-micrometer process (meaning that 2 µm was the minimum size of the features that could be patterned onto silicon using photolithography), the XC2064 implemented a few thousand logic gates. Modern FPGAs can contain hundreds of millions of gates, enabling vastly more complex designs. Yet the XC2064 established a design workflow still used today: Engineers describe the hardware behavior digitally and then “compile the design,” a process that automatically translates the plans into the instructions the FPGA needs to set its logic blocks and wiring, according to AMD. Engineers then load that configuration onto the chip.

The breakthrough: hardware defined by memory

Earlier programmable logic devices, such as erasable programmable read-only memory, or EPROM, allowed limited customization but relied on largely fixed wiring structures that did not scale well as circuits grew more complex, Cong says.

FPGAs introduced programmable interconnects—networks of electronic switches controlled by memory cells distributed across the chip. When powered on, the device loads a bitstream configuration file that determines how its internal circuits behave.

“As process technology improved and transistor counts increased, the cost of programmability became much less significant,” Cong says.

From “glue logic” to essential infrastructure

“Initially, FPGAs were used as what engineers called glue logic,” Cong says.

Glue logic refers to simple circuits that connect processors, memory, and peripheral devices so the system works reliably, according to PC Magazine. In other words, it “glues” different components together, especially when interfaces change frequently.

Early adopters recognized the advantage of hardware that could adapt as standards evolved. In “The History, Status, and Future of FPGAs,” published in Communications of the ACM, engineers at Xilinx and organizations such as Bell Labs, Fairchild Semiconductor, IBM, and Sun Microsystems said the earliest uses of FPGAs were for prototyping ASICs. They also used it for validating complex systems by running their software before fabrication, allowing the companies to deploy specialized products manufactured in modest volumes.

Those uses revealed a broader shift: Hardware no longer needed to remain fixed once deployed.

Attendees at the Milestone plaque dedication ceremony included (seated L to R) 2025 IEEE President Kathleen Kramer, 2024 IEEE President Tom Coughlin, and Santa Clara Valley Section Milestones Chair Brian Berg.Douglas Peck/AMD

Semiconductor economics changed the equation

The rise of FPGAs closely followed changes in semiconductor economics, Cong says.

Developing a custom chip requires a large upfront investment before production begins. As fabrication costs increased, products had to ship in large quantities to make ASIC development economically viable, according to a post published by AnySilicon.

FPGAs allowed designers to move forward without that larger monetary commitment.

ASIC development typically requires 18 to 24 months from conception to silicon, while FPGA implementations often can be completed within three to six months using modern design tools, Cong says. The shorter cycle and the ability to reconfigure the hardware enabled startups, universities, and equipment manufacturers to experiment with advanced architectures that were previously accessible mainly to large chip companies.

Lookup tables and the rise of reconfigurable computing

A popular technique for implementing mathematical functions in hardware is the lookup table (LUT). A LUT is a small memory element that stores the results of logical operations, according to “LUT-LLM: Efficient Large Language Model Inference with Memory-based Computations on FPGAs,” a paper selected for presentation next month at the 34th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM).

Instead of repeatedly recalculating outcomes, the chip retrieves answers directly from memory. Cong compares the approach to consulting multiplication tables rather than recomputing the arithmetic each time.

Research led by Cong and others helped develop efficient methods for mapping digital circuits onto LUT-based architectures, shaping routing and layout strategies used in modern devices.

As transistor budgets expanded, FPGA vendors integrated memory blocks, digital signal-processing units, high-speed communication interfaces, cryptographic engines, and embedded processors, transforming the devices into versatile computing platforms.

Why the gate arrays are distinct from CPUs, GPUs, and ASICs

FPGAs coexist with other processors because each one optimizes different priorities. Central processing units excel at general computing. Graphics processing units, designed to perform many calculations simultaneously, dominate large parallel workloads such as AI training. ASICs provide maximum efficiency when designs remain stable and production volumes are high.

“ASICs can deliver the best performance, but the development cycle is long, and the nonrecurring engineering cost can be very high. FPGAs provide a sweet spot between processors and custom silicon.” —Jason Cong, IEEE Fellow and professor of computer science at UCLA.

“FPGAs are not replacements for CPUs or GPUs,” Cong says. “They complement those processors in heterogeneous computing systems.”

Modern computing platforms increasingly combine multiple types of processors to balance flexibility, performance, and energy efficiency.

A Milestone for an idea, not just a device

This IEEE Milestone recognizes more than a successful semiconductor product. It also acknowledges a shift in how engineers innovate.

Reconfigurable hardware allows designers to test ideas quickly, refine architectures, and deploy systems while standards and markets evolve.

“Without FPGAs,” Cong says, “the pace of hardware innovation would likely be much slower.”

Four decades after the first FPGA appeared, the technology’s enduring legacy reflects Freeman’s insight: Hardware did not need to remain fixed. By accepting a small amount of unused silicon in exchange for adaptability, engineers transformed chips from static products into platforms for continuous experimentation—turning silicon itself into a medium engineers could rewrite.

Among those who attended the Milestone ceremony were 2025 IEEE President Kathleen Kramer; 2024 IEEE President Tom Coughlin; Avery Lu, chair of the IEEE Santa Clara Valley Section; and Brian Berg, history and milestones chair of IEEE Region 6. They joined AMD’s chief executive, Lisa Su, and Salil Raje, senior vice president and general manager of adaptive and embedded computing at AMD.

The IEEE Milestone plaque honoring the field-programmable gate array reads:

“The FPGA is an integrated circuit with user-programmable Boolean logic functions and interconnects. FPGA inventor Ross Freeman cofounded Xilinx to productize his 1984 invention, and in 1985 the XC2064 was introduced with 64 programmable 4-input logic functions. Xilinx’s FPGAs helped accelerate a dramatic industry shift wherein ‘fabless’ companies could use software tools to design hardware while engaging ‘foundry’ companies to handle the capital-intensive task of manufacturing the software-defined hardware.”

Administered by the IEEE History Center and supported by donors, the IEEE Milestone program recognizes outstanding technical developments worldwide that are at least 25 years old.

Check out Spectrum’s History of Technology channel to read more stories about key engineering achievements.

Think one GPU is very much like another? Think again. It turns out that there’s surprising variability in the performance delivered by chips of the same model. That can make getting your money’s worth by renting time on a GPU from a cloud provider a real roll of the dice, according to research from the College of William & Mary, Jefferson Lab, and Silicon Data.

“It’s called the silicon lottery,” says Carmen Li, founder and CEO of Silicon Data, which tracks GPU rental prices and benchmarks cloud-computing performance.

The silicon lottery’s existence has been known since at least 2022, when researchers at the University of Wisconsin tied it to variations in the performance of GPU-dependent supercomputers. Li and her colleagues figured that the effect would be even more pronounced for AI cloud customers.

Performance varies for GPU models in the cloud

So they ran 6,800 instances of the index firm’s benchmark test on 3,500 randomly selected GPUs operated by 11 cloud-computing providers. The 3,500 GPUs comprised 11 models of Nvidia GPU, the most advanced being the Nvidia H200 SXM. (The team wasn’t just picking on Nvidia; the GPU giant makes up most of the rental cloud market.)

The benchmark, called SiliconMark, is intended to provide a snapshot of a GPU’s ability to run large language models, or LLMs. It tests 16-bit floating-point computing performance, measured in trillions of operations per second, and a GPU’s internal-memory bandwidth, measured in gigabytes per second. The results showed that the computing performance varied for all models, but for the 259 H100 PCIe GPUs it differed by as much as 34.5 percent, and the memory bandwidth of the 253 H200 SXM GPUs varied by as much as 38 percent.

Differences in how the GPU is cooled, how cloud operators configure their computers, and how much use the chip has seen can all contribute to variations in performance of otherwise identical chips. But Silicon Data’s analysis showed that the real culprit was variations in the chips themselves, likely due to manufacturing issues.

Such randomness has real dollars-and-cents consequences, the researchers argue, because there’s a chance that a pricier, more advanced GPU won’t deliver better performance than an older model chip.

So what should GPU renters do? “The most practical approach is to benchmark the actual rental they receive,” says Jason Cornick, head of infrastructure at Silicon Data. “Running a benchmark tool [such as SiliconMark] allows them to compare their specific instance’s performance against a broader corpus of data.”

Two weeks ago, Anthropic announced that its new model, Claude Mythos Preview, can autonomously find and weaponize software vulnerabilities, turning them into working exploits without expert guidance. These were vulnerabilities in key software like operating systems and internet infrastructure that thousands of software developers working on those systems failed to find. This capability will have major security implications, compromising the devices and services we use every day. As a result, Anthropic is not releasing the model to the general public, but instead to a limited number of companies.

The news rocked the internet security community. There were few details in Anthropic’s announcement, angering many observers. Some speculate that Anthropic doesn’t have the GPUs to run the thing, and that cybersecurity was the excuse to limit its release. Others argue Anthropic is holding to its AI safety mission. There’s hype and counterhype, reality and marketing. It’s a lot to sort out, even if you’re an expert.

We see Mythos as a real but incremental step, one in a long line of incremental steps. But even incremental steps can be important when we look at the big picture.

How AI Is Changing Cybersecurity

We’ve written about shifting baseline syndrome, a phenomenon that leads people—the public and experts alike—to discount massive long-term changes that are hidden in incremental steps. It has happened with online privacy, and it’s happening with AI. Even if the vulnerabilities found by Mythos could have been found using AI models from last month or last year, they couldn’t have been found by AI models from five years ago.

The Mythos announcement reminds us that AI has come a long way in just a few years: The baseline really has shifted. Finding vulnerabilities in source code is the type of task that today’s large language models excel at. Regardless of whether it happened last year or will happen next year, it’s been clear for a while this kind of capability was coming soon. The question is how we adapt to it.

We don’t believe that an AI that can hack autonomously will create permanent asymmetry between offense and defense; it’s likely to be more nuanced than that. Some vulnerabilities can be found, verified, and patched automatically. Some vulnerabilities will be hard to find but easy to verify and patch—consider generic cloud-hosted web applications built on standard software stacks, where updates can be deployed quickly. Still others will be easy to find (even without powerful AI) and relatively easy to verify, but harder or impossible to patch, such as IoT appliances and industrial equipment that are rarely updated or can’t be easily modified.

Then there are systems whose vulnerabilities will be easy to find in code but difficult to verify in practice. For example, complex distributed systems and cloud platforms can be composed of thousands of interacting services running in parallel, making it difficult to distinguish real vulnerabilities from false positives and to reliably reproduce them.

So we must separate the patchable from the unpatchable, and the easy to verify from the hard to verify. This taxonomy also provides us guidance for how to protect such systems in an era of powerful AI vulnerability-finding tools.

Unpatchable or hard to verify systems should be protected by wrapping them in more restrictive, tightly controlled layers. You want your fridge or thermostat or industrial control system behind a restrictive and constantly updated firewall, not freely talking to the internet.

Distributed systems that are fundamentally interconnected should be traceable and should follow the principle of least privilege, where each component has only the access it needs. These are bog-standard security ideas that we might have been tempted to throw out in the era of AI, but they’re still as relevant as ever.

Rethinking Software Security Practices

This also raises the salience of best practices in software engineering. Automated, thorough, and continuous testing was always important. Now we can take this practice a step further and use defensive AI agents to test exploits against a real stack, over and over, until the false positives have been weeded out and the real vulnerabilities and fixes are confirmed. This kind of VulnOps is likely to become a standard part of the development process.

Documentation becomes more valuable, as it can guide an AI agent on a bug-finding mission just as it does developers. And following standard practices and using standard tools and libraries allows AI and engineers alike to recognize patterns more effectively, even in a world of individual and ephemeral instant software—code that can be generated and deployed on demand.

Will this favor offense or defense? The defense eventually, probably, especially in systems that are easy to patch and verify. Fortunately, that includes our phones, web browsers, and major internet services. But today’s cars, electrical transformers, fridges, and lampposts are connected to the internet. Legacy banking and airline systems are networked.

In 2020, researchers fine-tuned a GPT-2 model to design fragments of logic circuits; in 2023, researchers used GPT-4 to help design an 8-bit processor with a novel instruction set; by 2024, a variety of LLMs could design and test chips with basic functionality, like dice rolls (though often these were flawed).

Now Verkor.io, an AI chip design startup, claims a bigger milestone: a RISC-V CPU core designed entirely by an agentic AI system. The CPU, dubbed VerCore, has a clock speed of 1.5 gigahertz and performance similar to a 2011-era laptop CPU.

Suresh Krishna, cofounder at Verkor.io, says the team’s key claim is that this approach is more effective than using only specialized AI systems for specialized tasks within the overall design process. “ What we learned is that the better approach is to let the AI agent solve the whole problem,” he says.

Bringing Human Workflows to Agentic AI

Verkor.io’s agentic system is called Design Conductor, and it’s not itself an AI model. It’s a harness for large language models (LLMs). A harness is software that forces an AI agent to proceed through structured steps. In this case, the steps are like those a team of human chip architects would follow: design, implementation, testing, and so on. The harness also manages subagents and a database of related files.

That means it can work autonomously with only an initial prompt—in this case a 219-word design specification—from the user. (The prompt is published in the Design Conductor paper.) It outputs a Graphic Design System II (GDSII) file, which can be used in existing electronic design automation (EDA) software.

Synopsys and Cadence, two major players in EDA software, also have agentic AI tools. These allow chip architects to automate some tasks with AI agents. Design Conductor is different because it’s built to handle chip design from spec to completion with full autonomy, something major EDA companies have not yet touted.

Ravi Krishna, founding engineer at Verkor.io, says Design Conductor’s workflow is “mirrored after the traditional process a human engineer might use.” It analyzes the specification, then writes and debugs a register-transfer level, or RTL, file (an abstraction of the CPU’s data flow) before iterating through subtasks like power delivery, signal timings, and layout, which are again checked against the specification. Some tasks, like layout, call tools to assist the agent. “It’s an iterative system.”

The system took 12 hours to create the VerCore design. That’s not long, but, because it uses AI agents, you might imagine it taking more or less time based on the number of agents thrown at it. However, Ravi Krishna says it’s not that simple, because some design tasks aren’t easily parallelized.

However, the general improvement of AI models over time has proven essential. “I remember that around the middle of last year, we tried to build a floating-point multiplier with the models of that time. It was slightly beyond what they could do,” says Ravi Krishna. VerCore—designed in December 2025— represents an increase in capability since then. “If it can’t do it today, it’ll do it in six months,” he says. “I don’t know if that’s a scary thing or a good thing.”

A First for AI Chip Design

VerCore uses the RISC-V instruction set architecture (ISA), a popular open-standard ISA that’s beginning to break out of niche applications, like storage controllers, into systems on a chip (SoCs) that can power laptops or smartphones. The CPU’s exact clock speed is 1.48 GHz and it achieved a score of 3,261 on the CoreMark processor core benchmark.

Verkor says this puts VerCore’s performance in line with the CPU core performance of Intel’s Celeron SU2300. Whether that sounds impressive depends on your perspective. The Celeron SU2300, which arrived in 2011, uses Intel’s Penryn CPU architecture, which debuted in November of 2007.

In other words, VerCore is no threat to leading-edge CPUs, but it’s notable for two reasons.

VerCore is the first RISC-V CPU core designed by an AI agent. Previous examples of AI chip design presented portions of a design but didn’t present a complete core. Ravi Krishna says the company wanted to target a design that an AI agent hadn’t previously accomplished. “From the perspective of trying to push the limits of what AI models can do, that was interesting to us,” he says.

And while VerCore’s theoretical performance has limits, it’s enough to suggest the design could be useful. Indeed, RISC-V is popular because it provides an ISA that’s free to use (RISC-V is an open standard). RISC-V chips generally aren’t as quick as their x86 and Arm peers, but they’re less expensive.

There’s one final caveat worth mentioning; the chip has not been physically produced. VerCore was verified in simulation with Spike, the reference RISC-V ISA simulator, and laid out using the open-source ASAP7 PDK, an academic design kit that simulates a 7-nanometer production node. Both tools are commonly used for RISC-V design. VerCore says its CPU can run a variant of uCLinux in simulation.

Skeptics will have a chance to judge for themselves. Verkor.io plans to release design files at the end of April. This will include the VerCore CPU and several other designs recently completed by the AI agent system. Verkor also plans to show an FPGA implementation of VerCore at DAC, the leading electronic design automation conference.

Should Chip Designers Worry about AI Agents Taking Their Jobs?

An AI chip designer that can bang out a CPU in 12 hours might seem like troubling news for flesh-and-blood engineers, but Design Conductor has its limitations. The team at Verkor.io say that despite improvements, LLMs still lack the intuition a human can bring.

Design Conductor can fall down rabbit holes that a human engineer would avoid. In one instance the agent made a mistake in timing, meaning that data was not moved across the CPU in agreement with its clock cycle. The model didn’t recognize the cause and made broad changes while hunting for the fix. It did eventually find a fix, but only after reaching many dead ends. “Basically, we are trading off experience for compute,” says David Chin, vice president of engineering at the startup.

Suresh Krishna concurs and adds that Design Conductor’s brute-force approach is likely to become less efficient as agentic systems tackle more complex designs. “It’s a nonlinear design space, so the compute grows very quickly,” he says. “As a practical matter, expert guidance and common sense helps a lot.”

Despite such issues, agentic systems like Design Conductor might accelerate chip design by accelerating iteration. They may also make design accessible to small teams that otherwise lack the resources or head count to pull off a project.

“It’s not at the point where you can have one person. I would say you still need five to ten, all experts in different areas,” says Ravi Krishna. “That team could get you to [a production-ready chip design] at this point.”

A practical guide to designing log-periodic dipole array fed parabolic reflector antennas using advanced 3D MoM simulation — from parametric modeling to electrically large structures.

What Attendees will Learn

1. How to set design requirements for LPDA-fed reflector antennas — Understand the key specifications including bandwidth ratio, gain targets, and VSWR matching constraints across the full operating range from 100 MHz to 1 GHz.
2. Why advanced 3D EM solvers enable simulation of electrically large multiscale structures — Learn how higher order basis functions, quadrilateral meshing, geometrical symmetry, and CPU/GPU parallelization extend MoM simulation capability by an order of magnitude.
3. How to apply a systematic three-step design strategy with proven workflow starting with first optimizing the stand-alone LPDA for VSWR and gain, then integrating the reflector, and finally tuning parameters to satisfy all performance requests including gain and impedance matching.
4. How parametric CAD modeling accelerates LPDA design — Discover how self-scaling geometry, automated wire-to-solid conversion, and multiple-copy-with-scaling features enable fully parametrized antenna models that streamline optimization across dozens of design variants.