This story was originally published by Tech Policy Press.

The European Union’s push for technological sovereignty faces an uncomfortable contradiction.

As the E.U. rolls out AI factories, gigafactories, and new data centers, it is creating a surge in demand for the advanced semiconductors that underpin artificial intelligence. Yet Europe produces fewer than 10 percent of the world’s chips and remains heavily dependent on U.S. designers and Asian manufacturers for the most advanced processors.

That tension sits at the heart of Chips Act 2.0, the European Commission’s planned overhaul of its flagship semiconductor strategy.

The original Chips Act, adopted in 2023, sought to raise Europe’s share of global semiconductor production to 20 percent by 2030. But the European Court of Auditors has warned that target is unlikely to be met, while the Commission’s own projections put Europe’s market share at about 11.7 percent.

The Commission now wants to correct what officials see as a major weakness in the first law: It focused on expanding supply without doing enough to stimulate demand. To address that gap, Chips Act 2.0 is expected to introduce demand-side measures, including public procurement tools, demand accelerators, and closer coordination between semiconductor producers and industrial users. The Commission’s calculation is straightforward: Stronger domestic demand will encourage companies to invest in designing and manufacturing chips in Europe.

But the strategy carries a paradox. The AI infrastructure that the Commission hopes will anchor a European semiconductor ecosystem will initially rely almost entirely on advanced processors designed by U.S. companies and manufactured in Asia.

“Key positions are held by a small number of firms, mostly outside Europe,” Claire Godfrey, executive director of the Balanced Economy Project, told Tech Policy Press.

AI factories create a demand trap

The European Commission’s AI Continent action plan includes 19 AI factories, computing facilities that integrate energy sources, specialized chips, and other infrastructure for running AI models and applications, plans for up to five AI gigafactories (since upgraded to seven), and a proposal to at least triple the bloc’s data-center capacity within five to seven years under the Cloud and AI Development Act. That expansion will require a large supply of advanced AI processors.

The Center for European Policy Studies (CEPS) estimates that each planned AI factory site requires up to 25,000 advanced chips, while a gigafactory requires at least 100,000.

Almost all of those processors are expected to come from Nvidia. The company supplies most of the graphics processing units deployed in Europe, while its proprietary CUDA software underpins much of the AI software ecosystem. CEPS warns this could create an “Nvidia dependency trap,” where computing infrastructure is physically located in Europe but remains technologically dependent on a single U.S. supplier.

Recent AI infrastructure projects in Europe illustrate the problem. Mistral has lined up 13,800 Nvidia GPUs for a data center near Paris. Deutsche Telekom’s Munich Industrial AI Cloud is being built with nearly 10,000 Nvidia Blackwell GPUs. And Nscale says its deployment for Microsoft, in Sines, Portugal, will start with more than 12,600 Nvidia Blackwell Ultra GPUs before expanding to more than 66,000 in 2027.

Europe still doesn’t control the chip supply chain

The challenge extends well beyond Nvidia. Even if Europe succeeds in expanding semiconductor manufacturing, the global supply chain limits how much autonomy any single region can achieve.

“Europe depends on both the United States and Asia, but at different stages of the value chain,” Toni Roldán-Monés, economist and assistant professor of public policy at IE University, told Tech Policy Press.

“The United States maintains a dominant position in areas such as chip design, intellectual property, and certain frontier equipment. Meanwhile, the manufacturing of the most advanced semiconductors is highly concentrated in Asia, especially in Taiwan and South Korea, while China plays a fundamental role in various materials, industrial processes, and critical minerals,” said Roldán.

Europe’s reliance on third countries is more evident in some parts of the chip value chain. In fabrication, Taiwan produces around 90 percent of the world’s most advanced chips. In packaging, assembly, and testing, the E.U. holds just 4 percent of the market and remains highly dependent on Asia, according to Laith Altimime, President of SEMI Europe.

“The objective is…to avoid excessive dependence on a single country, company, or technology.” —Toni Roldán-Monés

“No top 20 assembly, test, and packaging company is headquartered in the E.U.,” Godfrey said. “There is also the materials issue. China dominates several inputs used in key parts of the semiconductor and advanced electronics supply chain.”

Europe nevertheless retains important advantages.

The region is home to ASML, the Dutch company that dominates the market for extreme ultraviolet lithography systems, and to Belgium’s Imec, one of the world’s leading semiconductor-research centers. Europe also remains a key supplier of specialist materials and power electronics.

Those strengths, however, “do not translate into autonomy across the semiconductor value chain,” Roldán said.

Sovereignty means resilience, not self-sufficiency

Few experts believe complete semiconductor self-sufficiency is achievable.

Instead, the goal should be to reduce strategic vulnerabilities rather than eliminate international interdependence. “It is not conceivable that one country can rebuild the supply chain. Global collaboration is key,” SEMI Europe’s Altimime told Tech Policy Press. SEMI forecasts that by 2028 the Europe, Middle East, and Africa region will only manufacture about 68 percent by volume of the non-memory semiconductor chips it demands.

“The challenge is to reduce dependencies that could become geopolitical vulnerabilities,” argues Roldán. “The sensible approach is to strengthen critical parts of the value chain, diversify suppliers, protect sensitive data, and develop domestic capabilities in strategic sectors. That can coexist perfectly well with foreign suppliers: The objective is not to expel them, but to avoid excessive dependence on a single country, company, or technology.”

That distinction is especially relevant for Europe’s sovereignty ambitions. As Godfrey notes, “European firms are building around Nvidia hardware, CUDA, cloud infrastructure, and the software choices that come with them. That leaves Europe with two problems. It relies on Asian manufacturing and materials chokepoints. It is also at risk of trying to address that exposure by tying itself more closely to U.S.-controlled AI and cloud infrastructure. The Chips Act 2.0 needs to deal with both, or it will miss a large part of the problem.”

Roldán said Europe’s greatest vulnerability is dependence on partners willing to use global supply chains for geopolitical leverage. Whether Chips Act 2.0 reduces that risk, experts say, will depend on whether it diversifies suppliers rather than just shifting dependence from Asian manufacturers to U.S. technology companies.

On 6 August, the U.S. Government Accountability Office (GAO) released a report on the state of the 2022 CHIPS and Science Act, a bipartisan federal law passed under the Biden administration to boost U.S. semiconductor manufacturing and R&D. While manufacturing projects funded by the act are making notable progress, the money earmarked for R&D remains mostly unused, and the Department of Commerce, which administers the funds, has not published a plan for meeting the requirements of the law, according to the report. GAO says this lapse could put the U.S. at risk of missing out on the opportunity to advance semiconductor tech.

The industry experts we spoke with agree with GAO’s assessment. That includes Donna Dubinsky, serial entrepreneur and former Commerce Department official.

“We need to be the leader in manufacturing as well as in research, both advanced manufacturing technology and advanced designs, and Congress apportioned money to do it,” she says. Dubinsky was a trustee of Natcast, the public-private research consortium tasked with administering the National Semiconductor Technology Center (NSTC), the CHIPS Act’s R&D component, until August 2025, when the Department of Commerce canceled its US $7.4 billion contract in favor of operating NSTC itself.

The April 2026 charter that the Department of Commerce wrote for the NSTC “does not mention the strategy or contain sufficient detail to demonstrate plans for the NSTC to align with” the National Strategy on Microelectronics Research, a requirement of the CHIPS Act, GAO wrote. The Department of Commerce has also failed to involve the private sector in establishing its investment fund, another requirement of the Act. The department did not respond to a request for an update on its plans for meeting the national strategy and other CHIPS Act R&D requirements.

Instead of carrying out the original goals of the CHIPS Act, Dubinsky says, “we are choosing to not invest in future semiconductor technology leadership in the U.S, and I don’t understand that choice…Now it’s going to be in Belgium. It’s going to be in Tokyo. It’s going to be in Korea. It’s not going to be in the U.S.”

What is working in the United States, according to the GAO report, is the disbursement of manufacturing incentives.

CHIPS manufacturing incentives are working

Bars show the number of CHIPS Act manufacturing incentive award projects anticipated to complete in a given year. The line shows the running percentage of total projects anticipated to complete by the end of that year. Source: U.S. Government Accountability Office

The GAO report shows that CHIPS Act–funded manufacturing programs are progressing. As of April 2026, 24 out of the 144 milestones across 49 projects had been completed, and the funding associated with them had been disbursed. Since April, Commerce has announced seven additional projects (five for USA Rare Earth, one each for Bosch and Powerex).

GlobalWafers, a silicon-wafer company headquartered in Taiwan, is building wafer-production facilities in Texas and Missouri with CHIPS Act direct-grant support. The company has had no problems receiving their milestone-based incentives so far, says Brent Omdahl, senior vice-president of government affairs. GlobalWafers completed phase one of their Texas facility last year, receiving the promised $200 million shortly afterward.

“Obviously everybody in industry got perhaps a little anxious when President Trump, at the beginning of the administration, said he didn’t like the direct-grant program,” Omdahl says. But he says he hasn’t heard of the government coming back to awardees to ask for equity positions, something industry watchers were concerned about. If anything, the Trump administration’s changes to the CHIPS direct-grant program have made the company’s work run more smoothly, he says.

According to the GAO report, a majority of CHIPS Act manufacturing projects will be complete by 2028, with all expected to finish by 2033.

R&D is floundering

The GAO reports that the Department of Commerce has disbursed only about $506.8 million of $11 billion appropriated for R&D. Commerce has also made new awards totaling $900 million outside the original CHIPS Act R&D framework.Source: U.S. Government Accountability Office

Since the arrival of the new administration, the Commerce department has canceled $7.8 billion of the $11 billion appropriated for R&D under the CHIPS Act. Most of that was intended to go to Natcast to operate NSTC.

The Commerce department has funded two components of the R&D arm of the CHIPS Act, GAO reports: about $347 million for metrology research conducted by the National Institute of Standards and Technology and less than $5 million on the Act’s Small Business Innovation Research component.

Outside the canceled NSTC framework, the Department of Commerce has since awarded $900 million to xLight, SandboxAQ, and I-Pulse, and promised an additional $2 billion in preliminary awards for quantum computing it intends to take from CHIPS Act R&D funds, the GAO reports.

Unlike awards under the NSTC framework, these awards required equity from the companies in exchange for the government funds. “They’re using these funds for investment in equity, when these are companies that have access to the capital markets,” Dubinsky says, “If private capital is serving a sector well, then there’s no need for the government to play a role. The whole idea of this program was to provide leverage that would enable substantially more private-sector investment.”

VJ Sahi, a partner and vice-president at the government funding consultancy Clark Street Associates, notes that “there were no significant developmental awards in flight” within the NSTC, so its cancellation may not have harmed valuable research or development so much as delayed it. “The trade-off has been a delay…but it has also provided more available capital [which is positive] if they can now move to deploy those R&D dollars on a reasonable schedule.”

There are 17 rare earth elements. While almost all of them have vital industrial uses, you could be forgiven for believing, based on news coverage, that there are only four that matter: neodymium, praseodymium, dysprosium, and terbium.

To be sure, those are the essential ingredients in the powerful permanent-magnet motors that go into electric vehicles, heating and cooling systems, appliances, tools, fighter jets, bombs, and many other systems. But the industrial and national-security importance of rare earth elements goes far beyond magnets. Among the 13 other rare earths are two—erbium and yttirum—whose importance is no less vital, and which are now facing a looming geopolitical deadline this November. Depending on how negotiations play out, the post-deadline framework could erode U.S. national security—or redraw U.S.–China trade relations.

Erbium is used in the amplifiers that boost optical signals in the fiber-optic cables that crisscross the planet. Yttrium is a key component of the thermal barrier coatings that protect turbine blades and other structures from blistering heat in jet engines and in the combustion turbines so in demand to power new data centers.

Yttrium is more broadly used than erbium; besides thermal barrier coatings, it is also used in white LED lights and displays, microwave filters, and solid-state lasers, among other applications. Also, “small quantities of yttrium feed into trillions of multilayer ceramic capacitors that keep our electronics world going, including AI data centers,” notes Thomas Kruemmer, a rare-earths consultant based in Singapore.

Erbium and yttrium, Kruemmer writes in an email, are good examples of how “tiny quantities of rare earths can have an outsized impact by enabling core functionality in their respective applications.” Taken together, all of these rare earths “literally affect almost anything we can switch on and off.”

Chinese dominance of the markets for these two rare earths is essentially 100 percent. Take erbium: “There is no one that I’m aware of, outside of China, that makes erbium oxide on a commercial scale,” says Eric Bender, vice president of strategy and corporate development at Tronox, a mining, processing, and chemicals company headquartered in Stamford, Conn. Erbium oxide is the molecular form that is typically produced by separation facilities and bought by industrial users of the element.

For yttrium, too, industrialized economies are entirely dependent on China. China mines 90 percent of the world’s yttrium, but it processes essentially all of the world’s mined ore into an industrially usable form, such as yttrium oxide.

Yttrium coatings help turbine blades in generators and jet engines survive the heat. Sergii Zhmurchak/iStock

China’s Monopoly and the Yttrium-Erbium Supply Squeeze

Twelve rare earth elements, including erbium and yttrium, are subject to global export restrictions instituted by China in April and October 2025. The restrictions for some of them, including erbium but not yttrium, were suspended for one year in November 2025. Exports of yttrium, and a few other rare earths, have become erratic and sharply reduced. In March 2026, China approved a single, 60-tonne shipment of yttrium oxide to the United States, followed by a 10-tonne shipment in April. But overall, shipments of yttrium to the U.S. are down around 75 percent this year in comparison with 2025.

In November, China is expected to either extend or remove the suspensions for some or all of the 12 rare earths currently under export controls. And yet there is little movement apparent on the part of U.S. and European governments to cope with the possible cutoff of yttrium and erbium supplies. “Very few folks outside of China are talking yet about ‘How do we produce erbium, how do we produce yttrium?’” says Gareth Hatch, managing director of Strategic Minerals Advisory. “We’re lagging behind the geopolitics, the realities, of the day.”

The most important thermal barrier coating is yttria-stabilized zirconia. GE Vernova is one of the world’s largest manufacturers of turbines and a major user of the compound. At an investor day meeting last December, GE Vernova’s CEO, Scott Strazik, said the company had enough yttrium to last into 2026, but did not specify how far into 2026. An emailed request for elaboration, sent to GE Vernova’s media organization, did not elicit a response by press time.

Nevertheless, there are clear signs that the reduced availability of yttrium is having an effect on the industry. Oerlikon Metco is one of the largest of the small group of companies that produce yttria-stabilized zirconia and the equipment that applies it to the blades and other parts of jet-engine and combustion turbines. The erratic availability of yttrium has “thrown us upside down in the last year or less,” says Riston Rocchio-Heller, an engineer and lab manager at the company. Demand for combustion turbines in the United States is now at an all-time high, driven mainly by the need to power new data centers, including huge “hyperscale” facilities for AI training and inference and general cloud computing.

Yttria-stabilized zirconia is a ceramic produced by mixing yttrium oxide with zirconium dioxide. Alternatives to it exist, but some unique advantages of the yttrium-containing version have made it the standard choice, according to Roccio-Heller. Researchers are trying to find better alternatives, he says: “A lot of collaborative work is going on right now,” he reports. But it’s unlikely to come to fruition soon.

The erbium market is dominated by just a couple of applications: the coloring of consumer glass and erbium-doped fiber amplifiers. These amplifiers are spaced along long-haul fiber-optic lines, typically every 80 to 120 kilometers on a terrestrial cable, and every 50 to 80 kilometers for a submarine cable.

The amplifiers consist of a piece of erbium-doped optical fiber, usually between 10 and 30 meters long. The doped fiber is illuminated, or “pumped,” with laser light at 980 or 1,480 nanometers. That laser light excites the erbium atoms into a higher energy state. When a weak optical signal enters the length of fiber, it triggers the excited erbium atoms, which fall to lower energy states and release photons in the exact phase, direction, and wavelength—1,550 nm—of the incoming signal. That wavelength corresponds to the spectral “window” in which silica optical-glass fibers cause the least loss of the signal. That’s why nothing but erbium will do here: It naturally re-radiates at the necessary wavelength.

Engineers are starting to use erbium-doped amplifiers in the free-space optical communication systems that connect low-Earth-orbit (LEO) communications satellites, such as the Starlink satellites, with each other and with ground stations. Groups of these LEO satellites are being launched into orbit on an almost daily basis. Because their signals don’t go through glass, satellites could use a much wider variety of wavelengths. But engineers are using the erbium amplifiers anyway to take advantage of their relatively low cost and the large existing industrial base for the 1550-nm hardware, says Michel Corriveau, a researcher at MPB Communications, in Pointe Claire, Quebec, Canada, a leading provider of erbium-doped fiber amplifiers.

Corriveau says MPB obtains erbium-doped fiber for its amplifiers from a couple of companies, including Lightera (formerly OFS) in Denmark, which is now a business unit of Japan-based Furukawa Electric. An executive at Lightera, Annette Lundby, declined to comment on the company’s ability to secure stocks of erbium.

Project Vault and a geopolitical deadline

Erbium and yttrium, along with 14 other rare earths and a couple of dozen critical minerals, are stockpiled by the U.S. government. This National Defense Stockpile is managed by the Defense Logistics Agency, which does not comment on its specific contents. In February 2026, the Trump administration announced a US $12 billion public-private initiative called Project Vault to stockpile rare earths and other critical materials. The funding includes $10 billion in financing from the Export-Import Bank of the United States—the largest single financing in the bank’s history.

Curtis Stough, a “defense stockpile liaison” at the Defense Logistics Agency, did not respond to a request for an interview. The U.S. Geological Survey, which tracks availability of critical minerals, also declined to make anyone available for an interview. The White House press office, too, did not make anyone available. But spokesman Kush Desai did provide a statement, which read, in part: “The Administration continues to take a multifaceted and nimble approach to reshore critical mineral supply chains back to the United States.”

That approach will surely be tested in the event that China’s 2025 export restrictions take full effect, which could happen on 10 November. But a lot will probably happen before then, says Hatch, making the outcome hard to predict. “This whole thing is ostensibly about dual-use control of materials” that have essential military uses. “But in reality, it’s part of the bigger trade picture.” So Hatch expects a wider discussion, leading up to November, involving leading-edge GPU chips, extreme-ultraviolet lithographic equipment, high-bandwidth memory, design-automation software, and other tech goodies that the United States and its allies are currently denying China.

This article is brought to you by Emerson.

I’ve spent much of my career as an engineer, including years in the semiconductor industry. And one lesson has stayed with me through every major technology shift: innovation always creates new complexity.

In semiconductors, we have seen that repeatedly. Every generation has delivered breakthroughs in performance and capability, but each step forward made it harder to understand system behavior. What used to be easy to validate on the component level with a test bench now needs a much wider view.

“The future of engineering will be defined by who can verify, understand, and improve complex systems fast enough to safely keep innovation moving forward,” says Ritu Favre, President of Emerson’s Test & Measurement business group.Emerson

Chiplet-based designs are a prime example. A chiplet from one supplier, an interposer from another, and a packaging process from a third may all perform perfectly on their own. Yet there is a chance for unexpected behavior when you put them together in a system. More and more often, the hardest engineering challenges are not in the individual components themselves. The problems are found when we start to combine components and have them interact with each other.

These challenges extend far beyond semiconductors. Products are becoming more software-defined and dependent on interactions across different technologies and environments. Think about the interactions needed for a modern car using adaptive cruise control on a bumpy road in a rainstorm. Or a passenger jet adjusting wing flaps and engine speeds in turbulent weather to maintain safety and stability. Both the car and the jet are being guided by complex computer systems with thousands of sensors leading to thousands of interactions every second. And in many cases, there are multiple computer systems working together. We are building systems of remarkable capability but understanding how they will act under real-world conditions is getting harder.

That is why I believe we are entering a new era of test. The defining challenge of modern engineering is no longer simply what we can design and build. It is what we can confidently verify.

Rethinking the Role of Test

In this new era, test can’t be an afterthought. For decades, test was treated as the final checkpoint before release. Design teams developed a product, test teams validated performance, and organizations looked for a final pass/fail to determine whether they were ready to move forward. That model worked fine when systems were more self-contained and predictable. Today, that approach can lead to more risk.

I believe we are entering a new era of test. The defining challenge of modern engineering is no longer simply what we can design and build. It is what we can confidently verify.

Many of the delays and fire drills we face come from issues that were not visible early enough. Problems discovered late in development are more difficult to diagnose, more expensive to fix, and more likely to get you off schedule. The solution is not more testing at the end. The solution is to make test and verification part of the engineering workflow from the start.

When validation is integrated throughout development, teams catch problems early when change is easier. Test also stops being a barrier to release. Instead, it becomes a source of insight, helping us understand how systems behave as they become more connected.

Why Connected Platforms Matter

When confidently verifying technology becomes the key challenge, the tools we choose take on a different level of importance. The tools have a direct impact on how quickly we can diagnose a problem and keep moving forward. In an environment where technology changes rapidly, disconnected tools get in the way of progress. Modern test strategy requires linking information across design, validation, and production, turning measurement data into decisions made quickly enough to keep pace with innovation.

This reminds me of when EDA was first introduced. Before it came along, engineers spent much of their time hand-drawing circuit layouts and placing transistors. EDA eliminated that tedious work by letting teams describe complex behavior in high-level code. It enabled them to focus on overall architecture instead.

A connected test platform does a similar thing for validation. Because a platform can adapt and scale alongside technology, it cuts down on maintenance and downtime, keeping teams from having to rebuild their workflows from scratch as requirements change.

Grounding AI in Engineering Reality

Today, AI is rapidly entering the engineering toolkit to accelerate design and analysis. But in test and measurement, AI cannot reach its potential in isolation.

An AI model is only as effective as the data feeding it. Without context, even the smartest algorithm will struggle to tell the difference between normal hardware variance and a critical failure. A connected platform supplies the structured, traceable data stream AI requires to deliver real insight.

AI can correlate complex multi-system interactions, flag unexpected behavior, and direct an engineer’s attention right at the root cause.

When measurement data flows seamlessly across the workstream, AI moves from being a standalone tool to an active layer of intelligence. It can correlate complex multi-system interactions, flag unexpected behavior, and direct an engineer’s attention right at the root cause.

Every technology shift that accelerates how fast we create new designs also increases the complexity we must verify. AI can help teams keep pace with that complexity. Not by replacing human judgment, but by giving engineers the context we need to act with confidence.

Innovation Demands Confidence

Ultimately, the goal of modern platforms and AI-enabled workflows is to help technical teams spend more time building new things and solving hard problems. Most of us didn’t choose this profession to spend our time searching for data or dealing with last minute surprises. We want to innovate and integrating test directly into development provides a better view of system behavior, allowing teams to focus on that innovation rather than managing complexity.

The future of engineering will not be defined by who can build the most advanced product or technology. It will be defined by who can verify, understand, and improve complex systems fast enough to safely keep innovation moving forward.

That is the new era of test. As the pace of innovation accelerates, every breakthrough creates new paths to failure, and test is how engineers find those failures before the real world does. In an increasingly complex world, that capability is becoming as important as innovation itself.

Innovation has always required great engineering. And now, more than ever, it also requires confidence. Confidence that comes from knowing that we are not only building what is possible, but we are also building technology that people can trust.

Supply chains in many industries are full of tangles, but for semiconductor tech, that’s putting it lightly. Many chip components are location-constrained and can easily be throttled by geopolitical factors. Chipmaking is also tied up with social and environmental concerns, and if any seemingly small strand gives way, the whole thing could fall apart.

Researchers at the University of Michigan, in Ann Arbor, are working with nanoelectronics research giant Imec to find ways around material bottlenecks, dubbing their project “Common Earth” to contrast with the semiconductor industry’s reliance on rare earths. They’re looking for clever solutions to replace critical elements and forever chemicals in the semiconductor supply chain.

IEEE Spectrum spoke with two researchers leading the effort at the University of Michigan: Valeria Bertacco, a professor of computer engineering and a vice provost, and John Heron, an associate professor of materials science and engineering.

How exactly are you defining this idea of “common earth” semiconductor materials?

Valeria Bertacco: The goal of the project is to eliminate supply chain bottlenecks in the manufacturing of silicon chips. There are multiple sources of bottlenecks in the global supply chain. At the material level, we have a strong dependency on rare earth materials. We also, whenever we produce semiconductors, involve PFAS [per- and polyfluoroalkyl substances], these chemical byproducts that can never be eliminated from the environment.

John Heron: When we came up with this idea, we focused on a couple of the more controlled and maybe more fragile supply chain materials—those being hafnium [which is used in transistor gate dielectrics] and then some of the rare earth materials that are not directly integrated into the CMOS technology but facilitate the fabrication of the CMOS technology.

More broadly, the proper language is ‘critical element.’ Hafnium is one of our elements in focus, which is not strictly a rare earth element. It’s not as geopolitically controlled as rare earth, but there are other bottlenecks. It turns out that hafnium is a byproduct of zirconium mining, and zirconium mining is done for nuclear development, and so the hafnium is a byproduct of the nuclear industry. Some critical elements are byproducts of another industry, so if you want to scale semiconductor manufacturing, you basically have to scale a second industry.

And of course, related to these things, directly and indirectly, you create waste products. These waste products are often fluorinated, and these fluorinated compounds are classified as PFAS chemicals, which get dumped into the water waste. We’ve been taking the viewpoint that there is an ethical part to the project: Removing these forever chemicals, thinking about the health and safety of the byproduct that we make, as well as the ethics of where the materials come from and how they are being sourced. It’s trying to take a more holistic view on chipmaking.

Chip tech commonly relies on rare earth and specific materials for a reason, right? How are you trying to work around that?

Bertacco: Once we start changing the materials involved in the production of semiconductors, the characteristics of the transistor or the memory device will change. There is a reason why people use a specific dielectric—because it provides the low latency and high performance that they need. Our solutions may be able to reach a good approximation, and they may actually have other potential positive traits, but they will be different. The way we’re thinking to deal with that is to develop better circuit technologies, better architectures, and better systems. For instance, if your transistor has more leakage because you use a different dielectric, what we need is a better power gating solution, better frequency throttling, better circuit level solutions that contain that leakage.

Heron: The rare earth materials themselves show up typically in coatings for plasma-based deposition processes, so they’re like barriers to protect equipment. It’s not that rare earths are rare on the planet. It’s that the processing is most efficiently done with the ore that China has access to. So what we’ve been thinking about is just using other more accessible materials that are easy to refine and trying to find those unique chemistries that are robust to these plasmas.

RELATED: How to Build EV Motors Without Rare Earth Elements

You’re working with Imec on this project. How has collaboration outside of academia helped your research?

Heron: As Imec manufactures chips and technology, they offer a platform for testing not only just a new technology but a process. They also have a division that considers these PFAS chemicals and how to mitigate them, how to control them, what are critical processes for them, what are non-critical processes for them, those kinds of things. Their customers are the bigger manufacturers, and they buy into these things. So we have a way to engage with these potential customers or users of any technology from that collaboration.

The “Common Earth” effort is being carried out by researchers including, from left, Karina Calhoun, Pat Kezer, John Heron, Valeria Bertacco, Jim Foresi, Tersiteab Adem, and Aymen Ahmed. All are at the University of Michigan except Foresi, who is at Imec.Brenda Ahearn/University of Michigan

What “common earth” and supply chain solutions are you exploring or have found so far?

Heron: One of the things we’re considering is a nitrogen-based precursor [a chemical layer deposited on semiconductors during manufacturing], trying to get rid of the fluorine. We’re also looking at elemental alternatives to hafnium; for those, we’re looking at more salt-based solutions.

I address PFAS from the processing level, but at the University of Michigan, there’s also effort at the filtration level, developing novel filtration materials to capture these chemicals and then eliminate them from the waste stream. That’s where most of the effort is currently.

Bertacco: We’re also looking to commoditize the production of silicon chips so that there is much more access to them. In particular, we want to explore solutions that eliminate the single-source nature of many of today’s designs. For that, we’re looking for solutions at the architecture level that leverage emerging technologies like chiplets. Future composable chiplet-based designs could implement a reusable “slice” of a design—use a single slice for a low-end solution, or combine multiple slices to attain a higher-end design. GPUs and CPUs lend themselves to this style of scalable approach.

How can these solutions help address social, environmental, and economic issues in the typical semiconductor supply chain?

Bertacco: By eliminating the dispersing of PFAS in the environment, there are significant benefits that could be gained. There is an incredible push for very strong growth in semiconductor production at the planet level, so unless something is done on this front, there will be an incredible growth in PFAS production as well.

RELATED: Piezoelectric Catalyst Destroys Forever Chemicals

We also always think about rare earth materials due to social and political reasons—like some country doesn’t want to sell the material to another country or is trying to keep more for itself. But that is not the only type of dynamic. I learned from John [Heron] that a couple of years ago the price of neon gas went up 10 times because it’s a byproduct of steel manufacturing, and the two biggest steel manufacturing companies in the world are in Ukraine. When their production halted, the price of neon went up.

There are so many events that are external to the control of any engineer and any semiconductor manufacturer that can completely disrupt the industry. If the ‘Common Earth’ project could lead to a more robust supply chain and to locally sourced materials, we could control the situation a little bit better.

Do you think manufacturers are going to be eager to address some of these problems?

Heron: It’s a tricky space with many active directions that could emerge. But I’ll just use PFAS as an example. If legislation comes down really hard and says, ‘Hey, you can’t have this waste product,’ then that’s basically going to be a knife to the heart, if it doesn’t get addressed. So these issues are important, and if the U.S. wants to maintain manufacturing while also considering emissions and waste products, then we will need these processes. They will become critical. So the answer I think is yes. Is it yes today? Maybe not so much. But if things continue in the direction that they will likely go, based on where the U.S. has been going historically, then I think it will have to be.

This article is brought to you by COMSOL.

In pursuit of improved range, greater reliability, and faster charging, electric vehicles are driving the demand for high-voltage electronics. Other applications driving this demand include wind farms, data centers, and server farms, to name a few. As the interest for high-voltage electronics increases, the risks associated with their sudden failure must be considered.

Much of what causes high-voltage equipment to malfunction can be linked to the conditions of the climate in which it operates. Specifically, condensation on electronic surfaces caused by humidity can lead to corrosion, which can result in stray leak current and dendrite shorting during Electrochemical Migration (ECM).

Predicting, mitigating, and helping proactively design to account for corrosion is the focus of the Centre for Electronic Corrosion (CELCORR) research group at the Technical University of Denmark (DTU). The group’s researchers are working with industry partners to develop models and simulation apps that will help in building robust electronics designs. Their goal is to develop knowledge that can be used for manufacturing electronics to withstand humid operating conditions.

Electronic Failure: “It’s Not the Heat; It is the Humidity”

Automotive electrification and renewable energy systems rely on electronics at all stages of the energy chain. When these electronics, such as the example PCB in Figure 1, are exposed to the effects of moisture, they can become potential failure points.

“Anywhere you are producing, converting, transporting, and using energy, you need these high-power electronic systems that get affected by the humidity,” explained Dr. Rajan Ambat, DTU professor and manager of CELCORR. Ambient moisture can seep into the devices and machines that require these electronics and cause unexpected functional issues through corrosion. When these electronics are involved in particularly high-voltage applications (such as wind farms, data centers, electric vehicles, and server farms), failure due to humidity exposure can even lead to fire.

“There might be a situation where somebody installs a solar panel near the seashore or in an area with high humidity, and within a short period of time, a conducive condition forms inside the electronics that results in a failure,” Ambat said. “This is why we need to understand exactly how the conducive condition of condensation is created, when the condition is created, and how the system is failing.”

Figure 1. The electrolyte potential and current density distributions on a PCB surface (with pinholes).CELCORR/DTU

Identifying corrosion as the underlying cause of some electronic failures is still a challenge. “Fifty percent of failures in electronics are currently branded with an unidentified root cause,” Ambat explained. “When engineers open up the system, they do not realize that the failure was due to corrosion, because moisture disappears without leaving any sign of corrosion unless there is ECM dendrite formation.”

This lack of awareness was a strong motivator for CELCORR, which turned to multiphysics simulation as a supplementary tool to help its partner organizations to better predict humidity-related issues at the design stage.

Modeling Moisture and Measuring Parameter Changes in PCBs

CELCORR believes the best way to identify and avoid electronic failures is to build more effective designs that better prevent corrosion from developing or can withstand a higher humidity load. Its research team applies its expertise in modeling to generate simulation apps that will help partner industries to evaluate safe designs for humidity robustness.

“We are at the intersection of materials science and the electronics industry. We work as a bridge between materials and electronics disciplines, using both kinds of language,” Dr. Anish Rao Lakkaraju, a postdoctoral researcher at CELCORR, explained.

To understand potential design issues, Ambat emphasized the importance of virtually breaking down systems to identify where problems may arise. “We need simulation software to analyze potential uses of designs and whether new designs are good or bad,” Ambat said.

Researchers at the Technical University of Denmark (DTU) are using simulation apps to predict corrosion and design electronics proactively to mitigate or withstand its effects.

Using the COMSOL Multiphysics software for investigation, the CELCORR research team together with other research partners (Aalborg University) built an example model with a simple PCB geometry that matched both its test circuit boards as well as the design of a device used by one of its partner companies. The team then added a water film layer on top to act as the relative humidity. From there, the team could introduce variation. “We change the layout, geometry, distance between electrodes, thickness of the water film, and conductivity of the water film depending on the conditions,” Ambat said.

Ambat and his team generate data on the effect of these variations and can identify which has the greatest impact on the device’s performance and whether any alterations can improve the device’s anticorrosion robustness. “We assume there is condensation forming on the electronic surfaces (Figure 2) and compute the electrochemical leak current for different design elements,” Ambat said. “The value of the computed electrochemical current between the parts will give us an indication of whether the PCB will be affected or not.”

Figure 2. A 10-µm water film condensation effect on an example PCB.CELCORR/DTU

Altering the design elements and solving the model equations again and again allows the team to better understand what makes a design effective. “Now, we are at the current form of the model, and we are quite happy with where the physics are at this point,” Lakkaraju said. This modeling, however, was just the first part of CELCORR’s overarching goal of illuminating the destructive potential of corrosion in electronics and the best ways to avoid it.

Using Simulation Apps to Test Real-World Designs

To open up and ease access to these models, CELCORR used the Application Builder in COMSOL Multiphysics to create simulation applications for the members of the industrial consortium. Built with a simple 3D circuit board geometry with two oppositely biased electrodes and a water layer to replicate corrosion-causing moisture, the apps provide a pared-back, straightforward interface where users can vary model inputs. “We focused on fundamental aspects,” Lakkaraju said. “We boiled down our partners’ overarching concerns to create two apps with very simple geometries and the simplistic stuff that can be varied over multiple parameters.”

The simple simulation apps shown in Figures 3 and 4 are designed to show companies how the distance between the electrodes and the thickness of the moisture layer affect the leak current through the water film depending on different parameters. By analyzing multiple design elements and parameters, users can determine the relative benefits of certain design elements on the humidity robustness. “The apps we have built have really helped because they give the electronics engineers a plug-and-play sort of approach,” Lakkaraju explained.

Figure 3. The UI of CELCORR’s standalone app showing the inputs that users can alter.CELCORR/DTU

“By using this app [Figure 3], companies have unlimited freedom to work with these sorts of variables,” Lakkaraju added. “This would be quite difficult to recreate in real life with physical design and testing, and the companies we work with are quite happy with the level of accuracy the app can provide.”

Figure 4. The UI of one of the simulation apps showing a streamline plot with inputs such as the cathode voltage and blockage length.CELCORR/DTU

Looking Forward: Complex, High-Voltage Modeling

Alongside its collaboration with the industry consortium, CELCORR is also working toward improving the world’s general understanding of corrosion’s impact on electronics. To do this, Ambat and his team are undertaking multiple projects, including actively adding greater complexity to their models. In a tertiary current distribution model they are building, the team is drilling down into each of the basic inputs used in a secondary current distribution model, zooming in to examine the effects of the set of even more detailed inputs each basic input comprises.

“The next point is to study what each of these detailed inputs does,” Lakkaraju said. In particular, the team is examining mass transport properties and the chemical reactions’ rate constants.

In addition to these ongoing studies, CELCORR is expanding the scope of its research to investigate corrosion in high-power, high-voltage systems. Thanks to a 2024 grant from the Grundfos Foundation, CELCORR was able to establish the Centre for Climate Robust Electronics Design (CRED). The center’s lab facilities and expertise are being developed to address the humidity-robustness requirements of today’s high-voltage and high-power electronic equipment. “Using CELCORR’s uniquely deep understanding of materials and corrosion, we are equipped to find the root cause and provide knowledge for environmentally robust designs,” said Ambat.

For all of its investigation, CELCORR continues to rely on the agility of the COMSOL Multiphysics software. As Lakkaraju explained, “It is really quite nice how a model can be adapted to a variety of combinations of materials, geometries, and parameters and how the software allows you to keep building on from there.”

Interconnects, the wires that string transistors together into circuits on microchips, have long been built from copper due to its high conductivity. However, as electronics continue to shrink, copper becomes a dramatically worse conductor. Now scientists find that a new class of materials containing exotic quasiparticles might one day help enable next-generation interconnects that become better conductors the thinner they get.

The problem that copper interconnects now face has to do with the mean free path of the metal, the average distance an electron can travel before it runs into a molecule. Once copper wires shrink beneath this limit—in copper’s case, 40 nanometers—their electrical conductivity drops dramatically because their electrons start experiencing more collisions.

Researchers are investigating other metals that show better conductivity at nanometer scales for use in interconnects. For instance, cobalt and ruthenium have electron mean free paths of 10 nm and 6 nm, respectively. This means interconnects made from these metals can get smaller than copper wires before running into the same conductivity problem. However, if they shrink far enough, they will have to deal with the same challenge.

In a new study, scientists instead investigated topological materials, which possess extraordinary properties based on the topology of their structures. The researchers synthesized nanowires made of one such material as a proof of concept.

“We do not need superpristine or high-quality samples or superlow temperatures or high vacuum to see the quantum effects,” says Judy Cha, a professor of materials science and engineering at Cornell University. “Our measurements were done at room temperature in low vacuum or in air. This to me is astonishing.”

Why Topology Could Uncover Next-Gen Interconnects

Topology is the branch of mathematics that investigates what aspects of shapes can survive deformation. For instance, an object shaped like a doughnut can get deformed into the shape of a mug, with the doughnut’s hole forming the hole in the cup’s handle, but it could not get pushed or pulled into a shape that lacked a hole without ripping the item apart.

Employing insights from topology, researchers first developed a kind of topological material called an electronic topological insulator in 2007. Electrons zipping along the edges or surfaces of these materials are “topologically protected” from the kind of scattering observed in standard conductors, meaning they strongly resist any disturbances that might hamper their flow, much as a doughnut might resist any change that would remove its hole.

However, while topological insulators are conductive on their surfaces, they remain insulating in their bulk. In contrast, different topological materials known as Weyl semimetals both are conductive in their bulk and possess topologically protected conductive states on their surfaces. This makes them “much more conducting than topological insulators,” says Cha.

Weyl semimetals get their special conductive properties from quasiparticle versions of Weyl fermions, theoretical subatomic particles that are massless and carry electric charge. (Quasiparticles are collective excitations of atoms within materials that behave as if they are particles in free space.)

These quasiparticles make the surfaces of Weyl semimetals more conductive. So, as wires of Weyl semimetals get thinner, and the ratio between their surface and their volume increases, the surface contribution to electrical conduction should also grow. This could theoretically give them an advantage over other materials in interconnects as they shrink.

Niobium Arsenide Nanowires Show Promise

In the new study, Cha and her colleagues synthesized nanowires of the Weyl semimetal niobium arsenide using a method known as thermomechanical nanomolding. This method allowed the researchers to make a single-crystal nanowire 2 to 3 micrometers long and as thin as 40 nm.

The scientists found the resistivity of niobium arsenide nanowires dropped with decreasing diameter. At room temperature, a 40-nm-wide nanowire displayed a resistivity about 70 percent lower than that of bulk single crystals. Their analyses suggest this improvement was due to surface conduction.

Although the 40-nm-wide niobium arsenide wires were more conductive than the same size cobalt or ruthenium wires, they did not prove more conductive than state-of-the-art 10-nm-wide copper interconnects. However, the researchers expect niobium arsenide nanowires about 12 nm in diameter to outperform such copper interconnects. At roughly that diameter or less, the surface contribution of these nanowires to their electrical conduction will exceed the bulk contribution, they say.

In addition, the nanowires proved stable in air and could safely carry a high amount of electrical current before they broke down. They also showed high thermal conductivity, which could help them prevent overheating if they were to serve as interconnects.

However, Cha notes that niobium arsenide may ultimately not prove a practical replacement for copper. “Arsenic is toxic,” she notes. In addition, the synthesis technique they used is not compatible with CMOS or industry back-end-of-line processing conditions.

Still, Cha says their proof-of-principle work shows Weyl semimetals may display a key advantage over conventional materials when it comes to scaling down, and that even imperfect nanowires of Weyl semimetals with many defects can show enhanced conduction. “Topological semimetals are compelling and realistic engineering materials for applications, rather than remaining as model systems for physicists in academia,” Cha says.

Topological semimetals besides niobium arsenide may also be promising. For instance, in June at the IEEE/JSAP VLSI Symposium in Honolulu, Samsung presented research on molybdenum phosphide, and IBM presented work on cobalt monosilicide. “Industry is paying attention,” Cha says.

The scientists detailed their findings online 16 July in the journal Science.

Atop a lab bench, Cornell Tech postdoctoral researcher Yifan He positions the lens of an optical receiver almost a meter away from an LED emitting a beam of red light. The computer monitor attached to the receiver takes a beat to refresh, then displays an array of squares that resemble a QR code.

When you hold your phone camera up to a QR code, light strikes the image sensor as only a first step to revealing the data hidden behind the black-and-white matrix. The receiver here is doing something different: directly altering its own memory using the photocurrents produced by the beamed array of light. And unlike the data behind a QR code, which might point to a simple web address, this optical code could convey the parameters of an AI model.

The new receiver design, presented last month at the IEEE/JSAP Symposium on VLSI Technology & Circuits in Honolulu, seeks to reduce the burden of increasing memory demands on AI systems. Shining data down onto processors could lower the energy typically required for data centers, self-driving cars, and even “edge” applications like AI-powered robots, researchers say.

“People are designing all sorts of different AI chips,” says Jae-sun Seo, an associate professor of electrical and computer engineering at Cornell Tech, in New York City. These processors don’t often have room for all the parameters that make up AI models, so the additional data is stored in dynamic RAM (DRAM). The electrical connections commonly used to move the data between the DRAM and the processor create cost and efficiency concerns when systems scale up. “That’s one of the major bottlenecks.”

Optical links move data at high bandwidth with less energy loss than metal wires, but today’s optical receivers undercut that advantage by relying on power-hungry analog circuits to convert light to electronic bits. The group’s new tech would instead receive rapid flashes of digital QR-code-like matrices so that chips can tweak model parameters without those analog circuits, enabling fully digital optical communication that would consume less energy.

“This is a really important problem,” says Dennis Sylvester, an IEEE Fellow who chairs the University of Michigan’s electrical and computer engineering department and was not involved in the work. “It’s got massive commercial implications. This solution is a clever way of dealing with it.”

Jae-sun Seo [left] and Yifan He have developed a receiver that can edit memory in response to QR-code-like arrays of light.Alex Music

How Light “Flips” Memory to Power AI

Processors have a bit of built-in static RAM (SRAM), but not enough to allow an AI model to run independently. While SRAM is the faster of the two memory options, DRAM can store more data in the same footprint.

In the new system, the DRAM sits with the transmitter, and the receiver is part of the processor’s SRAM. The transmitter beams the data to the array of SRAM cells, which in this case are modified to contain photodiodes. Light hitting each photodiode creates a current to flip binary values in the SRAM.

Creating a link between the light and receiver requires calibration, because you can’t expect them to be perfectly aligned or perpendicular to each other. So the chip references a data frame that has information about the expected position of each pixel of data and uses that frame to ensure it can receive the real data, He says. “Ideally the best way is to have direct, point-to-point space between the transmitter and the receiver,” Seo adds, “but even if it’s slightly tilted, we have this calibration circuit.”

For applications in real-world settings, the researchers say they will need to build an optical transmitter that can alter the light matrix millions of times per second, transferring gigabits per second. The transmitter that I saw in He and Seo’s lab is only a proof of concept, emitting a static 14-by-14-bit matrix through a metal mask over the light. The researchers say they are working with optics research groups to build a transmitter that is capable of rapidly changing the matrix.

The Future of Light-Based Memory Links

Michigan’s Sylvester says that the tech in its current form is likely far from commercialization because the individual photosensitive bit cells are larger than SRAM bit cells in conventional chips. Those larger cells mean the chip can fit less memory, a trade-off that he says could cancel out the added efficiency of the light-based approach.

Seo says that it’s part of the group’s ongoing efforts to shrink the bit cells, which can be achieved by optimizing the size of transistors and circuits and leveraging CMOS scaling.

Seo and He are looking at uses for the tech in robotics and other edge applications. One example is in AI-robot-powered warehouses and factories, which could use optical data transmission to save time and energy when updating the AI models in each robot. Additionally, microrobots, which are inherently memory-constrained due to their size, could one day benefit from the tech, though it would require a more size-conscious design.

“Edge AI is a big growth area, and in three, four, five years, you’re going to hear as much about that as you are with data centers, probably, as the intelligence migrates more and more into these devices that we have,” Sylvester says.

When you get a good night’s sleep, you aren’t just giving your brain a chance to rest. Sleep activates a system only discovered in 2012 that washes out brain waste. Called the glymphatic system, it’s comparable to the better-known lymphatic system that moves and filters fluids throughout your body. A healthy glymphatic system is linked to good cognitive function and could prevent neurodegenerative diseases like Alzheimer’s, but monitoring it during sleep has been practically impossible in humans, because today’s methods require noisy, confining MRIs and invasive spinal injections.

A new wearable device developed by researchers at Georgia Tech and Seoul National University (SNU) could offer a safer and more sleep-friendly alternative. The technology shines near-infrared light to detect brain water, a soup of the fluids that constantly flood your brain. The brain-water mixture contains cerebrospinal fluid (CSF), which is what the glymphatic system uses to flush out waste particles like plaques that block in-brain communication. Measuring total brain water could be a way to study how the glymphatic system moves CSF around to clean the brain, researchers say.

The patch, the design of which was published this month in Science Advances, is intended for ease of use. It’s the size of a Band-Aid and less than a centimeter thick. Its soft silicone body conforms to the user’s forehead, and it doesn’t require a wired connection during sleep. Plus, it can be recharged and used over multiple nights, capturing more long-term information than what traditional sleep studies and MRIs can.

“MRI is superexpensive, it’s not really accessible, and more importantly, you cannot sleep under MRI imaging,” says W. Hong Yeo, Peterson Professor in pediatric research at Georgia Tech. “With our device, we can naturally capture conventional sleep right at home.”

What brain water could say about sleep and the glymphatic system

The glymphatic system is essentially a network of tiny voids between veins, arteries, and cells that are flooded with CSF when brain cells relax. Sleeves called perivascular spaces, which surround blood vessels, deliver the fluid to the spaces between cells. Dr. Chang-Ho Yun, a professor of neurology at SNU’s Bundang Hospital, says that these intercellular spaces can expand by about 60 percent in sleeping mice, but observations of the change in humans remain indirect.

“The human brain is densely packed with cells,” Yun says. “During sleep, the alerting signal [noradrenaline] drops away, the cells shrink, and there’s room for cerebrospinal fluid to flow.”

The new device uses a simple light trick to try to detect CSF changes. If you’ve ever held a flashlight to your palm in a dark room, you’ve seen the beam cause your hand to glow red. That’s because shorter wavelengths of light, like green and blue, are absorbed in your tissue. Red light breaks through and scatters back.

The patch shines three different wavelengths of near-infrared light: two that are absorbed by blood-cell proteins called hemoglobins, which deliver oxygen to the brain, and one that is absorbed by water. What’s scattered back is picked up by the device’s photodetector. The pattern of absorption at each wavelength reveals how much blood and total brain water lie along the path of the light. Yun says that if total brain water rises while hemoglobin stays flat, the added water is not coming from blood, which could mean CSF is increasing and the glymphatic system is doing its job. This indirect measure is necessary because CSF does not reflect light all that differently from the other fluids in your brain.

“Although it is indirect evidence, it’s compatible with known theory and known facts demonstrated in animals and humans,” Yun says. In his previous research, he found evidence that suggested glymphatic activity lowers during the REM stage of sleep. The study associated with the new patch, which measured sleep in four people, showed brain-water measurements doing the same during the REM cycle. Still, he emphasizes that further research is necessary to determine if total brain-water changes truly signal glymphatic activity.

Lauren Hablitz, an assistant professor of translational neuromedicine at the University of Rochester, agrees that it’s hard to say whether the patch is actually monitoring the glymphatic system. Knowing for sure might even be impossible, she adds. “The brain is bathed in fluid, it sits in fluid, it floats in fluid,” she says. “Knowing whether it’s that pool of fluid or the perivascular space or the ventricles that’s changing is hard.”

But Hablitz, who was not involved in this project, is optimistic about how the new tech can be used, even if it isn’t ultimately measuring the glymphatic system. She says that sleep research is “heavily focused” on electroencephalograms, or EEGs, which use electrodes placed on the scalp to measure the brain’s electrical activity. Yet most people with sleep issues have normal EEG readings, she says.

“Maybe something like this patch, that can look at another aspect of the biology that isn’t just neuronal activity, can start saying something about what’s actually happening in sleep disruption,” she says.

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In the chill of a London spring night, under overcast skies, iconic Trafalgar Square opens around me. Admiral Nelson rises on his pedestal, the National Gallery rests behind, the church of St Martin-in-the-Fields sits nearby. From the 13th century, the site served as the Royal Mews for hawks and then horses. By 1844, it was a public space at the heart of one of the biggest cities in the world.

Despite the square’s presence through that grand sweep of history, it’s not why I’m here. My interest is far more specific: I want to find out what happens to spaces like this when artificial light, specifically from light-emitting diodes (LEDs), intrudes. My companion tonight is Simon Thorp, a local lighting designer, who crouches in the shadows near Nelson’s spire, light meter in hand. “Two lux,” he reports, “and it’s very comfortable here.” Two lux is 10 to 20 times the illuminance of a full moon. We can see each other clearly, and a nearby sign assures us that closed-circuit television (CCTV) is in operation for safety’s sake.

Trafalgar Square captures the relationship between lighting and darkness that exists in almost every city, suburb, small town, and village around the world. The lighting here is a mishmash of old technologies and new, of shadow and glare, the ornamental gas lamps fronting the National Gallery all but washed out by the LEDs inside modern versions of traditional “brass and glass” fixtures a few meters away—21st-century technology housed in 19th-century designs.

The ugly truth of artificial lighting today is that in parts of London, as in many cities around the world, lighting levels are excessive, with unshielded illumination blasting in all directions. And the irony is that too much light invites danger: It creates shadows, impedes our vision, and gives the illusion, without the reality, of safety. Thorp notes that modern CCTV cameras are “pretty great” even at low-light levels, while harsh light makes it hard for both human eyes and digital sensors to see.

“The more bad light we add, the more bad light we think we need,” says Thorp. “We can’t see because of the light we’ve added. And it makes areas that were perfectly okay seem darker.”

Among the costs of this excess, the most alarming may be its toll on human health (and that of other animals) by disrupting circadian rhythms, impeding the production of melatonin, and contributing to sleep disorders that are tied to every major modern disease. New research shows that increased exposure to blue light from LEDs is having “substantial biological impacts” such as suppression of the sleep hormone melatonin and an increased risk for obesity, certain cancers, and type 2 diabetes.

A panoramic view from the Eiffel Tower looks down the Pont d’Iéna and the Palais de Chaillot [in the center], with the imposing silhouette of the La Défense business district visible on the Parisian skyline.

Luigi Avantaggiato

I have come to London and Paris—which led the way in the expansion of public street lighting in the 19th century—because they embody both the current enormity of the problem as well as a future certain to be lit by trillions of chips: controllable, tunable, and energy-efficient LEDs.

Living with artificial light at night

The standard justification for nighttime illumination is public safety. Lighting experts’ term for the phenomenon is “artificial light at night.” While people won’t often admit it, the desire for light at night seems to stem from a primal fear of the dark. Darkness is where the bad guys hide. And if dark is bad and light is good, then more light can only be better.

This assumption has guided our use of nighttime light for hundreds of years. And yet, high-lumen output doesn’t necessarily correlate to a reduction in crime, research has found. In other words, if we relied on the data as much as we do our primal anxieties and paused those anxieties long enough to learn how light and darkness interact, our nights would almost certainly be lighted differently—especially now that we have the extraordinary technology that is the light-emitting diode.

A 19th-century gas lamp [white square] manufactured by William Sugg & Co. next to a pedestrian path in Trafalgar Square, along with the architectural floodlighting on the neoclassical facade of the National Gallery, showcase the interplay between modern and historic lighting systems.

Luigi Avantaggiato

The first visible red light-emitting diode was invented by Nick Holonyak in 1962, but LED lighting technology took several decades to develop, before exploding in recent years. Just a decade ago, LED streetlamps were rare. By 2019, more than half of U.S. streetlights were LEDs, and that number is predicted to top 90 percent by 2030. Similar uptake has occurred around the world, even in developing countries, where inexpensive Chinese-made LED fixtures are increasingly common.

This rapid global migration to LEDs represents a shift in the fundamental physics of how we illuminate our world. From oil lamps and candles to gas lamps, early examples of artificial light at night relied on a burning wick, an incredibly inefficient way to create light. An incandescent bulb is effectively a heater that happens to produce light as a by-product, so it squanders nearly all of its energy as heat.

By contrast, LEDs use semiconductors to convert electricity into light. Through this process of electroluminescence, LEDs use up to 90 percent less energy than incandescent bulbs do, which has enabled municipalities to realize an immediate energy savings of 50 percent or more. This fact alone has fueled the technology’s worldwide adoption.

But LEDs aren’t just more efficient and less expensive. The use of solid-state technology gives the lights an extraordinary life-span, often measured in decades rather than years. This significantly lowers the maintenance costs, as city workers spend far fewer hours replacing broken or burned-out lights. Even more striking, by manipulating the properties of the semiconductor material, engineers can dictate the precise color and intensity of the output, something that gives LEDs incredible versatility. For a lighting designer like Thorp, LEDs offer countless possibilities.

Digital control for smarter lighting

Wandering from Trafalgar Square along the edge of St. James’s Park, Thorp and I find ourselves near Westminster Bridge, one of nine city bridges that in 2021 were part of the Illuminated River project, meant to make the Thames more beautiful at night. Each bridge now features a new LED lighting scheme that moves and changes color and intensity to create a coordinated work of art. But Thorp is frustrated that the project did nothing to correct the often glary lighting on the riverbanks. “Why don’t you pay the money to correct all of this bad lighting instead of adding new lighting?” he says. LED technology, he points out, has the potential to fix that problem.

The Illuminated River artwork for Blackfriars Bridge uses a color scheme that closely complements the red pillar supports that remain from the original Blackfriars Railway Bridge.

Luigi Avantaggiato

In fact, this may be the most meaningful potential of LEDs: the ability for a community to control when, where, at what levels, and in which colors its lights shine. A public space like Trafalgar Square could be lit more brightly during rush hour, then dimmed as the night progresses, the lights not only connected to one another but to the surrounding streetlights and commercial lights. Anywhere in the world, LED streetlights could be programmed to rise and fall in brightness depending on the time of night or time of year. They could even be turned off during bird migrations, to reduce the number of birds that are disoriented by the lights and ultimately killed in collisions with reflective and illuminated windows.

Up to now, LED public lighting has largely not been part of any comprehensive plan to curtail and control nighttime illumination. Most LED installations have simply replaced older, inefficient “dumb” electric lighting with newer “dumb” LEDs and thus made light pollution worse. The main reason? Because LED lighting is cheaper, we tend to use more of it—a literally shining example of the Jevons paradox. Even as awareness of light pollution grows, we aren’t yet taking advantage of LED technology’s full potential.

The good news is that we could start tonight. At DarkSky International, the world’s foremost organization fighting light pollution, CEO and executive director Ruskin Hartley tells me the organization has five principles for responsible outdoor lighting: It should be useful, targeted, low level, controlled, and warm-colored. “They’re enabled because of the capabilities of LEDs,” Hartley says.

The technology to control LEDs will be part of the solution. In the olden days of the analog era, a streetlight was either on or off. To change a lighting schedule, you had to physically rewire a circuit. Today, the Digital Addressable Lighting Interface (DALI) protocol turns each luminaire into part of a network, with its own digital address and a driver that reports to a central server. With DALI, the lighting is managed through software rather than physical switches.

Unfortunately, most LED streetlights have been deployed without this technology because it costs more. But Paul Drosihn, general manager of the DALI Alliance, says that using such controls makes the LEDs much easier to maintain. Before the new digital protocol, it took an average of nearly three visits to identify, diagnose, and repair a defective luminaire. “Now it’s one,” Drosihn says. “Saving the cost of sending two guys on a cherry picker to replace those [lights] is immeasurable. What I just described to you is pretty much all the utilities need to know.”

The intricate cast-iron understructure of Westminster Bridge glows in vibrant green and teal light as part of the Illuminated River public art project, a color palette selected to echo the green benches of the nearby House of Commons.

Luigi Avantaggiato

What’s more, DALI allows the tuning of the lights’ spectrum so that they become warmer and less disruptive as the night progresses. Digitally connected, full-spectrum luminaires allow cities to transform the nocturnal experience—saving money, increasing health and safety, and creating a warmer and more appealing atmosphere at night.

This digital intelligence is equally transformative for the “bleed lighting” that spills from building interiors, Drosihn says. “You don’t think of night lighting as coming from inside buildings, but it does,” he says. “Particularly in the States, you drive through any major city and all the lights are on, on every floor of every high-rise, even if no one is home.”

Already, the use of digital controls for interior lighting has become commonplace in some European cities, Drosihn says. By integrating DALI with occupancy sensors and building-management systems that monitor HVAC, electrical systems, and security networks, a skyscraper can become a dynamic participant in the urban environment—dropping a floor’s interior lights to zero the moment the last person leaves. As a result, electronic controls combined with LEDs can act like a dimmer switch for a city’s entire skyline.

White light blights the night

With all the possibilities from LED technology, why are our nights too often lit with harsh and clinical light, casting glare and creating shadows, disrupting human and ecological health, erasing the stars from our skies? The answer starts with the color of LEDs. At first glance, an LED streetlight looks like a collection of small white bulbs, but it’s not. To produce a light we perceive as white, most manufacturers coat a blue semiconductor core with a yellow phosphor material that absorbs a portion of that high-energy blue light. The problem is that this “white” light is still heavily blue, which is exactly the color no species has evolved to expect at night.

And because blue light is the second most energetic part of the visible spectrum (violet is the most), it doesn’t just illuminate our streets and invade our homes. Blue light also scatters in the atmosphere more easily than any other color, which helps to create the hazy, illuminated fog known as sky glow over every city of any size.

“Cooler” colored LEDs in the 4,000- to 6,500-kelvin range offer the most lumens at the lowest cost, so most early adopters installed these blue-rich white lights. The good news is that LED technology has continued to advance, and a growing number of communities are choosing warmer-colored streetlights that have less blue. (Phoenix, for example, converted 100,000 streetlamps to 2,700 K LEDs in 2020.) And, of course, light pollution isn’t just a result of LEDs. Older lighting technology also adds to the glare—bright white metal-halide lights, especially—and cities are loath to replace something that isn’t yet broken.

But our main failure isn’t a technical one. It’s that we have yet to revise our thinking about lighting at night. We use LED technology just as we did the old sources of light. As a result, we have largely offset the gains that were promised in terms of reducing energy consumption and carbon emissions by making light pollution worse, and have so far let an incredible opportunity go unrealized.

Can the City of Light do it right?

Across the Channel in Paris, the failure to realize the potential of LEDs feels even more palpable. Unlike London, which suffered heavily from German bombs, the lovely 19th-century Paris that Baron Haussmann created largely escaped destruction in World War II. To nearly 50 million annual tourists, the beautiful uniformity of the architecture is instantly recognizable. But the City of Light’s nocturnal atmosphere is also part of the draw, and extensive attention has been given to relighting its buildings and monuments. When I wander into the Cour Carrée in the Louvre, for example, I’m stunned by rows of amber LEDs that together create a warm glow along the palace facades. When I see the Eiffel Tower, first from a distance walking along the Seine and then up close, I find myself staring as I would at a campfire, the structure’s metalwork amber-lit with more than 336 high-pressure sodium bulbs.

Still, the city’s night lighting is far from perfect. With millions of residents, thousands of stores and restaurants, and 300,000 streetlights, the city overall is among the world’s brightest. Even at the base of the Tower, bright white LED lamps illuminate the African émigrés selling cheap berets and Eiffel Tower trinkets. And the city has been replacing its old sodium streetlights with new LEDs, swapping the warm yellow tones for which the city has long been known for bright white lamps no one wants to look at.

Street vendors display souvenirs at the foot of the Eiffel Tower. Their merchandise is lit by harsh white LED systems, which starkly contrast with the warm golden sodium-vapor light illuminating the tower above.

Luigi Avantaggiato

Nonetheless, the potential is here. In 2019, France introduced a nationwide law to reduce levels of light pollution, setting rules about both public lighting (preventing light from being projected above the horizontal) and private lighting such as stores, which are required to turn off their exterior and shop window lights after 1 a.m. In addition, an increasing number of French communities dim or turn off municipal lights after midnight to save energy and reduce carbon emissions. Although light pollution worldwide continues to increase by nearly 10 percent per year, France has managed to reduce its overall level. Chloé Beaudet, a researcher at Université Paris-Saclay, documented local light-reduction measures and found people generally agreed with the notion of dimming or turning off the lights, mainly for energy savings and ecological concerns.

“What I find is that people living in urban areas, they accept this kind of policy,” she tells me. “They’re like, okay, I don’t really use public space at night as a pedestrian, so what’s the point of having lights on?” For her, a key takeaway is that one lighting level does not fit all areas. “I think there is really a need for policy that is differentiated according to the neighborhood.”

In another positive development, the country has been minimizing artificial light to create ecological corridors designed to protect nocturnal species such as birds, bats, and insects. These corridors are connected and dark, mitigating the disruption to the 30 percent of vertebrates and more than 60 percent of invertebrates that are nocturnal. Even for city dwellers, this trame noire (“dark infrastructure”) helps to raise awareness of why controlling light pollution is important for life on Earth. Nationwide laws to control light pollution, the ability to light different parts of a city differently, dark corridors to protect biodiversity—these are exactly the kind of changes made possible with LEDs.

The iconic I.M. Pei Pyramid glows softly at the center of the Cour Napoléon at the Louvre Museum, its warm LED illumination flowing through the geometric glass-and-metal structure with a symmetrical framing of the surrounding historic pavilions against the night sky.

Luigi Avantaggiato

That’s not all. Almost until 1920, astronomers at the Paris Observatory were still gazing at the Milky Way. That’s impossible nowadays, but it could happen again. Despite the bright white LED streetlights now lining so many Paris streets, networks of LEDs using controls could lower lighting levels enough each night, so that the Milky Way could once again be visible over the French capital. And in the process, Paris could become the City of Light in ways that would set an example for other parts of the world.

New lighting demands new thinking

“I think we should aspire to have cities that see the stars,” Simon Thorp says when I mention this view of Paris. “You just need everything to be coordinated.”

Nearing the end of our London walk, having turned from the river and back up toward the Strand, Thorp brings me down narrow Carting Lane behind the Savoy Hotel, to where a gas fixture tops a thick lamppost, an original from 1870. A small plaque reads, “The last remaining sewer gas destructor lamp in the city of Westminster.” Thorp explains that the thick pole hides a tube that allowed methane from the sewers to get burned off at the mantle. “An early example of renewable energy,” he jokes.

The fire-orange flame is pleasing to the eye. But even here, on a narrow lane with no vehicle traffic, in a touristy area of the city, the flame is overwhelmed by a nearby, unshielded LED security light. Thorp shakes his head. “It’s stunning that someone could put in a light like that and think, ‘Great, nice job.’”

Here is the crux of contemporary artificial lighting at night. We know how to light well, and LEDs give us the ability to do so. But while our technology is 21st century, too often our thinking about light and darkness, safety and security, is stuck in the past. We could be doing so much more with this technology than we are. We could relight our nights in ways that would not only reduce energy and maintenance costs but also bring a slew of benefits, including healthier nights for humans, safer skies for nocturnal creatures, and a restoration of the stars.

In 2026, the tale of these two cities and their artificial light at night is that of a brilliant technology that we’ve engineered but haven’t yet learned to master. In short, we have yet to change the way we think about artificial light at night and to use it more thoughtfully and carefully—as we might, as one hopes we will.

This article appears in the August 2026 print issue as “The Wrong Way To Light a City.”

Large Language Models (LLMs) demand immense amounts of memory, and the more people use them, the more memory is required. Memory makers responded by accelerating plans to build new memory fabs, with a focus on High Bandwidth Memory (HBM) and DRAM, the first of which is scheduled to start production in 2027. But the demand for memory may also provide an opportunity for new ideas to find footing.

One of these is a tricked-out version of the kind of memory that lives in an SD card or a thumb drive—High Bandwidth Flash (HBF). It essentially takes the ideas that made HBM successful—stacking multiple chips to increase capacity and bandwidth—and applies them to the NAND flash memory commonly used for data storage in SD cards, thumb drives, and smartphones, among many other devices.

“People ask, ‘How in the world does this make a grain of sense? Flash is enormously slow,’” says Jim Handy, general director at semiconductor market research firm Objective Analysis. He explains that while NAND flash is generally lacking in bandwidth, HBF will help alleviate that concern. “[Flash] is atrociously slow for writes, but for reads, it can be coaxed to go pretty fast. And High Bandwidth Flash is going to be coaxed to do that.”

What is High Bandwidth Flash?

NAND flash stores data as a trapped electric charge in arrays of floating gate transistors (FGTs), organized into blocks and pages rather than individually addressable bytes. It’s non-volatile, too, which means data persists without power.

These traits make flash a good choice for long-term storage. It can store more bytes in the same area than DRAM, and it doesn’t require power-hungry capacitors that need constant refreshing to hold their charge. But the mechanisms that make flash dense and non-volatile also make it slow to write to, as pushing charge into and out of an insulated gate takes longer than charging a capacitor.

The latest flash interface standard can support memory bandwidth up to 4.8 GB/s per die. That’s not bad for many situations, and NAND is widely used in high-performance long-term storage, such as solid state drives. However, DDR5 provides bandwidth up to 70.4 GB/s per DIMM (excluding overclocked memory), and HBM4E can reach up to 3.6 TB/s per stack—a roughly 750-fold bandwidth advantage for HBM4E over flash.

Hoshik Kim, senior vice president of memory systems research at SK Hynix, says HBF improves bandwidth with packaging techniques similar to HBM. “By applying advanced 3D packaging and vertical stacking techniques to NAND flash, HBF can deliver vastly higher bandwidth than standard NVMe [Non-Volatile Memory Express] storage,” he says. Much as HBM stacks DRAM, HBF stacks NAND flash dies to create a memory-dense chip.

HBF is at least a year away from shipping, but flash memory manufacturer Sandisk has published fact sheets for its anticipated first-generation product. The company expects HBF to stack up to 16 NAND flash chips for a total capacity of up to 512 GB per stack. It also projects memory read bandwidth up to 1.6 TB/s. Sandisk’s HBF roadmap also projects a second and third generation with expected read bandwidth of 2 TB/s and 3.2 TB/s, respectively.

What is the purpose of HBF?

Though HBF has the potential to deliver a lot more bandwidth than earlier versions of flash, you might’ve noticed a wrinkle. It’s still a lot slower than the HBM used in high-performance GPUs. Why, then, is HBF promising?

The answer lies in key differences between AI training (teaching an LLM to predict tokens) and AI inference (serving the finished model).

A model is trained by presenting it with input tokens, seeing what the model predicts, checking if that prediction was correct, and then changing weights based on the error with a step called backpropagation. While this process is simple in summary, it involves calculations across billions or trillions of model weights. That means training is heavy on both reading and writing data, which makes flash a poor fit.

However, AI inference is different. The model weights are frozen and effectively read-only, which means flash’s poor write bandwidth is no longer an obstacle. “In an inference environment, massive read-heavy data, such as the static multibillion parameter model weights or the precomputed KV cache, can be securely housed in the HBF tier,” Kim says. That would free up HBM to work as a “high-speed scratchpad.”

Handy says it’s a sensible way to target flash memory for inference workloads. “If you set that up right, you can get an awful lot of good performance out of that—that’s just basic caching. It’s one technology that I’m expecting to go places.”

What’s next for HBF?

Though it has potential, HBF is still early in development and likely several years away from broad deployment.

On 25 February 2026, Sandisk and SK Hynix held a kickoff event launching a joint effort to standardize HBF under a dedicated workstream within the Open Compute Project (OCP)—the same kind of open-industry body that governs many data center hardware specs. While work on the standard is ongoing, a timeline for publishing the standard has not been set.

It might seem odd for memory manufacturers—and for SK Hynix, specifically—to put forth HBF as a less expensive alternative to HBM. After all, HBM is a higher-margin product that is currently leading SK Hynix to record revenues.

However, Kim frames HBF as a complementary tool rather than a rival technology. “By alleviating the severe capacity bottlenecks of HBM without sacrificing data delivery speeds, HBF has the potential to reduce the number of individual accelerators required to run large-scale models,” he says. Kim expects this will improve energy efficiency and lower costs, making it possible for data centers to further scale their AI inference hardware.

This article appears in the Spectrum print issue as “High-Bandwidth Flash Could Sate AI’s Memory Appetite.”

GPUs and other big AI chips just can’t get enough memory. Today’s data center computers stack DRAM 12 dies high. But as memory makers try to build higher stacks to pack in more bits and bandwidth, experts worry this high bandwidth-memory (HBM) will trap enough heat to cook itself into oblivion. That will be especially true if GPU makers choose to start stacking HBM atop their already hot processors to boost bandwidth instead of placing them beside the processor.

Engineers around the world are working on an alternative: Instead of stacking the DRAM dies atop each other, why not stack them side by side? In that way they hope to turn a future towering inferno into a cube of cool silicon fins.

Last month at the IEEE VLSI Symposium, two research groups showed different paths to such a chip. One possible side-stacked chip, called V-Die, would deliver an 82 percent speed boost compared with today’s most advanced memory, HBM4, South Korean researchers predict. Engineers in Japan say their version, MOSAIC, should deliver twice the memory capacity of HBM4 without raising the peak temperature much more than 1℃.

HBM and its problems

Today’s HBM consists of multiple layers of silicon dies of DRAM stacked on another chip, called the base die. The base die delivers power to the stack and coordinates communications with the processor. Bits and power reach into the stack by vertical connections that pass through each die, called through-silicon vias (TSVs). The dies connect to each other and to the base die through microscopic bumps of solder that link to the TSVs.

A typical AI accelerator, such as the Nvidia B300, is flanked by eight HBM stacks that are each 12 dies high, delivering 36 gigabytes per stack. Each stack is placed on the same substrate as the GPU, so they can bridge the millimeters-wide gap via 2,048 lines that are micrometers wide. This arrangement, for HBM4, transmits 2,800 GB per second to and from the GPU.

But even that won’t be enough in the future. “The size of AI models is growing explosively,” Heesoo Yang, a student at Ulsan National Institute of Science and Technology working at Korea Advanced Institute of Science and Technology (KAIST), in South Korea, told engineers at the VLSI Symposium. “But memory capacity and bandwidth are struggling to keep up, creating a massive bottleneck.”

One of HBM’s most pressing problems is how hot they get. The material that fills the gaps between the dies is about 100 times as thermally resistant as the silicon substrate, keeping heat from flowing upward to where the processor-package’s heat sink can remove it. There are potential ways of mitigating the problem, but it’s likely to grow worse as chipmakers seek to add capacity by stacking more dies.

Another future problem is that as chipmakers seek taller stacks, trade-offs between storage capacity and bandwidth creep up, as Yang, a student in the laboratory of KAIST’s Jimin Kwon pointed out. Higher stacks need more TSVs to deliver the data, eating into the area of silicon needed to store it.

V-Die memory

Last month, Kwon’s team, in collaboration with Seongju Kim at Hanbat National University, in Daejeon, South Korea, presented its solution to HBM’s future ills. Called V-die, it will stack DRAM vertically and include microfluidic cooling channels between the dies to keep them at 45 ℃, which is quite cool relative to the typical 80 ℃-plus peak.

The dies themselves would be different, Yang explained. Without the need for vertical connections, there would be no TSVs, freeing up area for more memory cells. In addition, each die would have its own I/O systems, eliminating the need for a base die. These systems would sit all along the bottom edge of the die and connect to the silicon substrate on which the GPU sits, via links every 20 µm. Such an arrangement allows for four times as many connections as HBM4 and reduces the time it takes to read from memory by 37 percent, the team calculates, although some data does have to travel a few millimeters farther to reach the processor.

The team simulated how a 16-die stack would alter the performance of AI computers, such as one made up of Nvidia H100 GPUs. Tested using a workload representing a GPT3-size large language model, the V-die system delivered 540 tokens per second versus 296 for HBM4 with the same memory capacity. It also reduced latency (the time it takes to deliver the first token) by 32 percent, or about 24 milliseconds.

A prototype device, which will be used to validate thermal and electrical characteristics, is in the works.

Side-stacking connections

These DRAM schemes, sometimes called volumetric DRAM, are actually constructed first by adding one die atop another and then turning the whole stack on its side to connect it to the substrate or another chip. That could lead to some tricky integration problems, says James Myers, a program director at the Belgium-based microelectronics research center Imec. Myers’s team previously worked out solutions to the thermal problems of stacking DRAM on GPUs and is now looking at using vertical dies in that situation. “You have to get the thickness exactly right,” he says. Even if there’s only a few micrometers difference among the DRAM dies, it can add up to a problem connecting to the substrate. Put enough irregular dies in the stack and “you’ll miss the bond pads.”

A team from University of Tokyo, Tohoku University, and the Japanese national research institute Riken explained a novel way to ease this problem at the IEEE VLSI Symposium. Instead of directly electrically connecting the bottom of the dies to the substrate, the team tested an inductive coupling transceiver system. On one side of the memory die, the team formed oblong-shaped inductive coils, about 80 by 240 µm. They placed a corresponding set at a right angle on the substrate. Current through one coil induces a magnetic field in the other, transmitting a data signal. And because the coils don’t have to overlap exactly, there’s a lot of leeway in how precisely the memory sits on the substrate.

Power connections, which are fewer in number and take up more surface area, are placed on the sides of the memory cube, University of Tokyo doctoral student Yuki Mitarai said at the symposium.

MOSAIC, which is designed to attach to the top of a GPU, fits 98 dies per cube, delivering 294 GB of memory. While it doesn’t have a microfluidic cooling structure, the fact that heat can rise through the silicon fins themselves should keep such a structure to 81.3 ℃, near today’s typical 80 ℃ limit. What’s more, thinning the DRAM dies by two-thirds to 100 µm would allow a MOSAIC cube to integrate 294 dies in the same volume, reaching 882 GB, Mitarai said.

A new type of imaging sensor inspired by the functioning of the human brain can detect light and store data at the same time. What’s more, the device can forget the data it no longer needs, paving the way for future breakthroughs in robotic-vision efficiency.

Today’s digital cameras rely on complementary metal-oxide-semiconductors (CMOS) or charge coupled devices (CCDs), which convert photons into electrons. These devices, however, cannot store the images. The data have to be moved into memory and further for processing.

“Conventional camera sensors, which capture images, immediately forget them unless the information is transferred to a separate memory component,” says Larry Cheng, a professor of electrical engineering and computer science at Oregon State University. “Our device can see and remember it, and most importantly, gradually forget it. This kind of gradual forgetting is a key and very important feature of the device.”

Cheng and his colleagues described the device, a type of phototransistor, last month in the journal Advanced Functional Materials. He says that typical AI-driven image-recognition algorithms analyze captured video feed frame by frame to detect moving objects. Instead, the device developed by his team at Oregon State stores the recent history of light intensity that hits it. By doing so, the phototransistor flags changes and patterns of interest. The duration for which it remembers those changes can be modified based on specific needs. For example, a drone flying at 250 kilometers per hour needs only a short trail of changes, while a doorbell camera looking for strange people lingering around needs a longer sequence.

“The ability to tune the memory timescale is a key advantage of our approach, allowing the same sensor to be adapted for different AI vision tasks while improving speed and energy efficiency,” says Cheng.

He adds that the ability to do such basic processing directly on the sensor could pave the way to massive energy-demand reductions. Commercial cameras constantly shuffle data among sensors, storage devices, and processors making it relatively energy intensive to run image-recognition algorithms.

Experimental Oxide Phototransistor

The prototype device built by the researchers is a four- by four-pixel array, about the size of a USB stick. The top of the array is coated with a transparent light-absorbing layer of organic material that transforms the incoming light into electric charge.

Cheng explains that when photons hit the photoactive layer, they produce electrons and create holes. The electrons are transferred into the underlying transistor channel, which is made of indium gallium zinc oxide (IGZO). It’s the holes that provide the basis of the device’s memory function .

“The holes become trapped within isolated organic semiconductor aggregates because of energy barriers in the photoactive layer,” Cheng says. “These trapped holes continue to electrostatically modulate the [transistor] channel even after the light is turned off, allowing the device to retain a memory of recent illumination.”

The amount of charge gradually decays, but by applying voltage to the photoactive layer, the researchers could alter how long it lasts. A positive voltage, Cheng says, pushes the trapped holes further away from the transistor channel, reducing their effect and speeding up their decay. That results in faster forgetting. On the other hand, a negative voltage pulls the holes closer to the transistor channel and slows down the degradation process. As a result of such an intervention, the device retains the memory for hours or more, he says.

“This tunable memory enables the same device to adapt its temporal response to different applications, from tracking fast-changing events to storing longer-term visual information,” he says, adding that the memory feature of the organic photoactive layer was discovered by accident.

The researchers chose an IGZO transistor for its transparency to visible light, which means the transistor doesn’t contribute to light absorption.

“This decouples the electrical transport from the light-sensing function, which is handled by the organic photoactive memory layer,” says Cheng. IGZO is widely used in display technologies because charge travels quickly through it, yet transistors made using the material leak little current; additionally it is compatible with large-area fabrication. Together, the two materials enable each pixel to both detect light and retain a memory of recent illumination within a single device.

The way the device works, Cheng says, is inspired by the functioning of the human brain. The charge in the transistor acts like the neurotransmitter dopamine, which strengthens connectivity between synapses, the links between neurons, and thus the memories we keep.

“Our current work demonstrates the concept at the device level and with simple imaging demonstrations,” he says. “The next step is to scale the technology to larger pixel arrays and develop an integrated imaging prototype to showcase real-time temporal imaging and on-sensor processing. We hope to demonstrate these capabilities in the near future.”

Semiconductor companies and universities are trying to shorten their feedback loop to meet the challenges of the AI era. In recent years, National Yang-Ming Chiao Tung University in Taiwan; the University of California, Berkeley; Arizona State University; Virginia Tech; and others have been building closer links with industrial partners, as both sides seek to speed the turning of research into business and to inform the next round of research with fresh lessons from industry.

Now, the University of California, Los Angeles, and five major semiconductor companies announced in May a new US $125 million university-industry hub that takes that idea and runs with it.

Chip packages are growing larger and more complex as manufacturers scramble to keep up with the memory and processing demands of today’s frontier AI models. Frontier models undergo step-change updates every few months, compared to semiconductor parts, whose manufacturers typically update on an 18- to 48-month cycle, depending on the particular component. As a result, demand for AI-capable processors has outpaced production capacity, and prices for components at the chokepoints are spiking.

UCLA’s Semiconductor Hub includes partners at each stage of the semiconductor manufacturing process, spanning materials, architectural design, tooling, packaging, and fabrication. The work will address communications systems and AI inference at network edges—meaning in peripheral devices far from central servers.

Bridging University Research and Chip Fabs

The need for a stronger bridge from university to semiconductor fabs is clear. In February, Purdue University and Imec researchers wrote in Nature Reviews Electrical Engineering that the semiconductor industry was going to need a wider funnel of ideas to keep up with the complexities of 2D materials, enormous silicon wafers, and the tremendous demand from the AI industry. They called for more reliable, industry-ready research labs that would help transfer successful university prototypes into reliable, well-documented materials companies could build at larger scale. Universities should train and retain skilled technical workers at the interface of semiconductor research and commercialization so they can address industry needs, the authors wrote.

There is now so much research to do, spanning so many different specialties, at the bleeding edge of semiconductor innovation that it is the rare company that can afford to go alone, said Gary Dickerson, the president and CEO of Applied Materials, at the hub’s launch. “The companies that are doing the best in semiconductors are those that have been best at collaborating.”

With the UCLA hub, that collaboration now includes even more with academia. The UCLA hub will also adopt a flexible approach to problem-solving and career integration between academia and industry. The hub’s leadership will encourage participating faculty to pivot research projects on faster timescales than conventional federal funding allows, says Ah-Hyung “Alissa” Park, dean of the UCLA Samueli School of Engineering. Doctoral students, who will be co-advised by academic and industry supervisors, will also spend a year in industry internships in their fourth year.

The industry partners include Applied Materials, GlobalFoundries, Meta, Synopsys, and Broadcom, whose founder, Henry Samueli, spun off the company from his research at UCLA in 1991. In some ways, the hub represents a doubling-down on that and other related relationships. “Many of our faculty are already working with this hub,” says Park.

UCLA Semiconductor Hub Research Focus

The nearest parallel hubs in the U.S. are perhaps the Berkeley and Phoenix hubs, but they are each specialized in different stages of the semiconductor manufacturing process, and weighted toward industry. The UCLA program aims to address each phase of manufacturing, albeit from an earlier, blue-sky research stage. “Ours is very different because it is research-focused while collaborating with industry,” says Mona Jarrahi, a UCLA professor and the Semiconductor Hub’s faculty director.

These companies have been accustomed to selling products that emerged from lab work 10 or 20 years before and are now trying to speed up the commercialization timelines to suit an era of more advanced robotics and AI. “A lot of tech is now in commercialization in two to three years,” Park says.

If the UCLA Semiconductor Hub and similar university-industry bridges succeed, Ph.D. students of the future may see semiconductor projects they worked on reach commercial reality before they complete their doctorates.

This story was updated on 2 July 2026 to correct the mistaken statement that Samueli approached UCLA about founding the hub. Park proposed the idea to Samueli.

Today, you probably asked a question of a large language model, or accepted a connection suggestion on LinkedIn, or watched a recommended video on YouTube, or took a different route to work based on a traffic prediction from Google Maps. In other words, you probably used artificial intelligence. But what you might not know is how much energy that interaction consumed or why.

AI requires processing massive amounts of data, which is usually done in large data centers populated by thousands of GPUs capable of executing up to trillions of operations per second. But each of those GPUs achieves that by consuming as much as 1,000 watts apiece. For comparison, if you’ve got a newer smartphone, it probably uses less than 1 W. That kilowatt figure puts GPUs on the same level as vacuum cleaners, dishwashers, and stoves, but with the big difference that data-center processors are operating uninterrupted around the clock.

Fundamentally, a lot of this inefficiency is because GPUs are trying to simulate the workings of artificial neural networks using software and billions of transistors, which requires using energy to move massive amounts of data. What’s more, the simulated artificial neurons that make up these networks lack even a fraction of the complex computing behavior of the biological neurons that comprise the most energy-efficient computing system that we know, the human brain.

The brain is roughly one million times as energy efficient at many of the comparable tasks we set for AI. To try to approach these efficiencies, a radically different way of computing called neuromorphic engineering is seeking to build electronic components and circuits that act more like the brain’s neurons and the synapses that connect them.

Huge amounts of work have gone into making electronics operate more like biological neurons and synapses. Some research has focused on developing new, experimental devices, but they aren’t yet reliable enough to be used in large systems. Other efforts aim to implement neurons and synapses by interconnecting many complementary metal-oxide-semiconductor (CMOS) transistors—the workhorses of digital logic—to simulate a single neuron and synapse. But this approach requires so many transistors (and a few bulky capacitors) that it greatly limits the size of the system that can be constructed, making it unclear how such brain-inspired hardware could ever scale up and compete with state-of-the-art GPUs.

But all along there was an artificial neuron and a synapse—each a single device—hiding in plain sight. We found them last year. They were each made possible by an ordinary CMOS transistor—and not even a very good one at that. This is the story of their accidental discovery and their great promise for lowering the environmental footprint of AI.

Biological and artificial neurons

Modern digital electronics is based on producing and manipulating the ones and zeros of the binary code through the operation of metal-oxide-semiconductor field-effect transistors. MOSFETs have evolved in recent years, but their classic form consists of a piece of silicon that has been doped to contain an excess of either positive (p-type) or negative (n-type) charge carriers. (CMOS logic contains transistors of both types.) The device has two terminals connected to the silicon through regions highly doped with the opposite polarity of the rest of the silicon—the source and the drain. Another terminal, the gate, sits atop the silicon that separates the source from the drain. The gate itself doesn’t connect directly to this silicon, instead resting above a thin layer of insulating dielectric.

Notably, there is a fourth terminal that attaches to the bulk of the silicon; think of this bulk terminal as connecting to the underside of the chip. It doesn’t typically get much attention, but it’s very important to our story.

When voltage is applied at the gate and the bulk terminal is grounded, charge carriers of the same polarity as the source and drain are attracted to the channel region. In the case of an n-type source and drain, that will be electrons; for p-type it will be holes. The presence of these charges forms a conductive channel that reduces the resistance between the source and the drain by several orders of magnitude, and the device switches on. As the voltage at the gate increases, this physical phenomenon produces a current signal that, when plotted against the gate voltage, rises steadily. This response is ideal for logic gates, converters, multiplexers, memories, and other digital circuits. But it is not a good fit for mimicking the behavior of a neuron.

In real neural tissue, brain cells, called neurons, consist of a cell body, a long projection called an axon, and short branching projections called dendrites. The suite of behaviors and computing this collection of components is capable of is rich and broad, but the portion that artificial neural networks hope to copy is this: When the cell body’s voltage is perturbed enough to reach a particular threshold, a self-propagating pulse of voltage, called an action potential, shoots down the axon. The axon terminates in a synapse, an electrochemical connection between the axon and another neuron’s dendrites. The action potential will then temporarily boost the voltage of this next neuron, by an amount that depends on the strength of the synaptic connection. If enough action potentials reach these dendrites in a given time—from this neuron or from others that might also form synapses there—the cell body’s voltage will surpass the threshold and trigger its own action potential.

The MOSFET Neuron

The unusual action the authors discovered is understandable if you consider that a MOSFET contains a hidden bipolar-junction transistor.

TRANSISTOR BEHAVIOR

Under normal operation, with the bulk terminal grounded, increasing voltage at the drain leads to current that increases steadily. When the voltage decreases, current follows the same sloped path. Although some pairs of electrons and holes are created by current crashing into silicon atoms, these are swept away before they can accumulate.

NSRAM BEHAVIOR

Adding resistance to the bulk terminal means these extra holes pile up, increasing the bulk voltage relative to the source. Once that voltage reaches a certain value, the hidden transistor activates, causing current to spike. Current remains high until the drain voltage drops past a certain point.

To get closer to the behavior of real neurons, artificial neurons should produce a current spike when a critical voltage threshold is crossed and then quickly relax back to a resting state on their own. This spike needs to be sudden—nonlinear. It should also exhibit some hysteresis; that is, the activation and relaxation voltages should be different from each other to ensure that current flows only for a certain amount of time.

What’s wanted from an artificial synapse, the thing that connects two artificial neurons, is less complicated, but equally important. The main thing is that its conductance can be electronically adjustable. The device’s conductive states should increase and decrease in a linear pattern and remain stable over time.

No single MOSFET working under the standard operation mechanism can reproduce either of these neural properties. Instead, it’s been done by combining them into complex circuits. Until now, each neuron and each synapse has been implemented by interconnecting dozens and sometimes even hundreds of MOSFETs, which is highly inefficient in terms of area, performance, and cost. To limit the amount of space needed, chips can multiplex their signals, sending them to neurons and synapses serially, but such sequential processing introduces additional delays.

Despite these area-and-time penalties on tasks such as audio processing, computer vision, or health monitoring, state-of-the-art brain-inspired microchips have achieved power reductions up to a thousandfold compared with those of GPUs or CPUs on the same task. If we could create neurons and synapses from individual devices that are readily manufacturable instead, we might target more massive implementations while maintaining energy efficiency.

Reinventing the MOSFET for AI

Working in our laboratory in 2024, one of my students was measuring a memory circuit that consisted of one transistor and one memristor—a type of nonvolatile memory device first fabricated in 2008. The student’s memristor circuit was built from two-dimensional material atop a silicon microchip containing MOSFETs. The MOSFETs were created in a commercial foundry using fabrication technology called the 180-nanometer node, which was cutting-edge in the year 2000.

One day the student forgot to connect the bulk terminal of the transistor. What he observed was a sudden increase in current with high nonlinearity that self-relaxed when the voltage was ramped down (a phenomenon called a hysteresis loop). This was a very promising neuronlike behavior!

After a fruitless week of trying to think of an explanation for this behavior, I (Lanza) asked Pazos, then my postdoctoral fellow, to try to observe and control this phenomenon in chips without memristors. This time, we applied pulses of voltage—like the spikes a neuron would produce—instead of the ramped voltage that my student used when he first saw the peculiar behavior.

Pazos’s new data helped us understand what was going on. The key was that oft-ignored fourth, or bulk, terminal of a MOSFET. Under ordinary operation, many mobile charge carriers flitting through the channel collide with the silicon atoms, producing free pairs of electrons and holes—a process known as impact ionization. The electric field created by the potential difference between the source and the drain causes these new free electrons to drift toward the positively biased drain and the holes to move toward the bulk terminal, which is usually grounded, removing the charge without any drama.

However, when the bulk terminal of the transistor is floating—unconnected as it was in my student’s experiment—the holes produced by impact ionization cannot be driven to the ground. Instead, they accumulate in the bulk of the silicon, increasing its voltage. Then things start to get interesting.

It helps here to imagine a MOSFET as two different kinds of transistors occupying the same physical space—the intentionally constructed MOSFET and a hidden, bipolar junction transistor. A bipolar device transmits a current signal across two p-n junctions, in this case the interfaces between the source and the channel region and the channel and the drain. This signal is in proportion to a smaller current at a third terminal in between, called the base. In our experiment, that third terminal is the bulk.

To get current flowing through a bipolar transistor, you need a big enough potential difference between the base and one of the other terminals, so that current can get across the p-n junction. Let’s say this “threshold voltage” is 0.7 volts, although the real number depends on device geometry and silicon doping. In our device, that potential difference comes from those holes that were accumulating in the bulk, because it was not connected to ground. Once it reaches the threshold voltage, the device becomes sharply conductive, producing an abrupt increase of current. This sharp current increase eventually falls off once the drain voltage is lowered, because that lowering reduces the rate at which holes are generated in the bulk. The remaining excess holes recombine with stray electrons or leak away, and finally the bulk voltage falls. This cycle of hole accumulation, current spike, and hole removal gives rise to a hysteresis loop, very much like the electrical behavior of a biological neuron as it integrates ionic currents, fires a spike, and relaxes back to its resting voltage.

Initially, we observed this behavior only in a few transistors, and the relaxation time was very different for each of them. So, to try to control it better, we adjusted the resistance of the bulk terminal using a second MOSFET. Simply setting that resistance suddenly caused all the transistors to fire at the same voltage with hardly any variability. In other words, we found we could create perfect electronic neuron behavior in a single silicon transistor by controlling the bulk contact resistance. Setting the resistance can be done by doping the silicon during fabrication, but we think the two-transistor cell—where one acts as the bulk resistance—offers much greater versatility because it allows for electronic control.

We had to make sure the phenomenon would last, otherwise such a device would be useless. To our delight, every single one of the devices we tested worked over 10 million cycles. Not even one of them failed during our tests.

The MOSFET Synapse

To be honest, we were amazed. Dozens of research groups and companies all around the world have spent many millions of U.S. dollars over the past 20 years trying to emulate these neural behaviors using experimental memristor-like devices and other things, with limited success, mainly due to reliability and cost issues. We managed it in the cheapest and most industry-standard device: the MOSFET. This result was so shocking that we decided to confirm it using microchips from a different foundry. It was successful: All the behaviors could be reproduced, and perfect yield was achieved once again.

We were happy with the results and had started the process of filing for a patent and writing up our findings for the journal Nature, when our lab made another astonishing discovery: The same kind of MOSFET could act as a synapse, too!

Recall that in ordinary operation some electrons crash into silicon atoms to create pairs of electrons and holes. We noticed that at specific values of bulk resistance a significant amount of the charge from this impact ionization would get trapped in the gate dielectric. This trapped charge interferes with the flow of current through the MOSFET, effectively changing the device’s conductance. Importantly, this new conductance is stable and adjustable at will. It was then that we realized the MOSFET could also be used as an electronic synapse.

As it was in the neuron transistor, the bulk terminal was the key. A negative bulk-source voltage drives electrons into the dielectric, decreasing conductance. A positive one pushes holes in, increasing it.

From neuromorphic device to circuit to system

Here’s how the MOSFET synapse and the MOSFET neuron, together called a neurosynaptic random-access memory, or NSRAM, could work together to achieve a simple neural circuit: Say you had a circuit consisting of three synapse MOSFETs and a neuron MOSFET. The synapses have already been programmed as we’ve described, so that each has a different conductance. Spikes of voltage with different patterns and frequencies are applied to the gate of each of these transistors. What emerges from their drains are spikes of current with amplitudes modulated by the synapses conductance values.

The spikes converge at the drain of the neuron MOSFET. With each spike, impact ionization causes charge to build in the bulk of the silicon. Some of it will drain away, but if enough spikes arrive in a short enough period of time, the bulk voltage will reach a value at which the “hidden” transistor triggers a spike of current through the MOSFET. This current would then go on to become the input to other MOSFET synapses, and so on. The behavior is exactly the kind of integrate-and-fire action real neural circuits deliver.

The competitive advantage of our single-MOSFET electronic neurons and synapses is straightforward: We can produce with only one or two transistors the electronic signals that today require, at an industrial level, dozens and sometimes even hundreds of components. And moreover, unlike other emerging technologies, our solution is fully compatible with today’s silicon manufacturing lines and exhibits a yield of 100 percent in key figures of merit with near-zero variability.

Building functional circuits for brain-inspired computing and AI based on this technology is as exciting as it is laborious. It will require us to improve our computer models to resemble the behavior of both devices more accurately and to do so with computational efficiency. We must also perform accurate circuit- and system-level simulations to validate computing architectures, design peripheral circuitry to drive and convert signals, and undergo multiple fabrication rounds to optimize performance.

But all that will be worthwhile, because it could result in brain-inspired microchips for AI with better energy efficiencies than what we have now. These chips will first be a fit for smaller-scale, “edge-AI” tasks, such as bringing greater intelligence to battery-powered systems. But if we can scale up such chips, maybe in the long run they can compete with state-of-the-art GPUs.

As transistor sizes shrink to their atomic limits, computing demands are only growing. Sending chips to the third dimension is the future: Chips stacked on other chips can get more work done in the same footprint, saving time and energy. A 3D chipmaking technology called hybrid bonding is leading the charge in such efforts. Last month, two research teams used the tech to make hundreds of thousands more connections per millimeter than were previously possible, setting new records.

Presented at the IEEE Electronic Components and Technology Conference (ECTC) in Orlando, Fla., both results drastically reduced the bond pitch, the distances between the copper connections that bridge hybrid-bonded chips. The smaller the pitches, the more connections can fit in a package, and the more efficiently computing can get done.

“When we are talking about hybrid bonding at finer pitches, we can directly think about lowering the power consumption, having denser interconnects, and actually improving the communication between devices,” says Melissa Najem, a research engineer at the French microelectronics laboratory CEA-Leti. “This is actually extremely important to meet the rapidly growing demands for next generation semiconductor devices, such as for AI, for high performance computing, for high-bandwidth memory.”

Hybrid bonding places pads of copper and insulation on the faces of two or more chips, squishes them together, and adds heat so that the copper expands and joins, creating an electrical connection. The joining pads must be precisely aligned to within less than a micrometer for the process to work.

“A lot of applications are here just waiting for the improvement of die-to-wafer hybrid bonding” —Melissa Najem, CEA-Leti

The two ECTC records take different approaches to hybrid bonding. Belgium-based semiconductor research center Imec presented a record for hybrid bonding whole wafers of chips. This wafer-to-wafer (W2W) approach is useful for memory and logic applications, but it is less flexible for other uses as it requires uniformity of the wafers. In collaboration with chip-manufacturing-equipment maker EV Group, Imec got W2W pitches down to 200 nanometers from a previous low of 250 nm announced last year.

CEA-Leti’s record involves a die-to-wafer (D2W) approach, which places individual chips, also called dies, on a full wafer of chips (think adding pepperoni to a pizza). This method lets chipmakers mix and match the sizes and functionalities of the stacked chips. The researchers presented D2W pitches at 1 μm—yes, five times bulkier than the W2W milestone, but a 50 percent reduction from the last published record of 2 μm. A 1-μm pitch means a million connections per square millimeter, or four times as many as before.

Wafer-to-Wafer and Die-to-Wafer Hybrid Bonding

W2W hybrid bonding is the more straightforward method of the two: Connections require an alignment accuracy down to a minuscule 50 nm, but the uniformity of the silicon wafers makes the painstaking job a bit easier. Achieving smaller W2W pitches is mostly hung up on smoothing connection points as much as possible.

To flatten surfaces sufficiently for the 200-nm record, researchers improved a process called chemical mechanical polishing (CMP), says Imec program director of 3D system integration Zsolt Tokei. They combined this effort with improvements to wafer alignment and copper-pad design.

Srinidhi Ramamoorthy, a heterogeneous integration engineer at Applied Materials who was not involved in either breakthrough, notes that some research institutes have made wafers with W2W pitches below 200 nm, but that these records were not published alongside both electrical testing and reliability data. Without that information, she says, those numbers are “not the final pitch.”

For the D2W approach, the 1 μm record depended more on alignment accuracy than smoothness: Imagine having to drop a pepperoni on a pizza in a microscopically precise place, over and over. Najem says that CEA-Leti’s record was met by fine-turning the alignment process, alongside improved CMP.

The type of die CEA-Leti bonded to their wafer was a test vehicle, which records information to evaluate electrical connections. Najem says the test vehicle got data for multiple pitch levels, and while pitches above 1 μm had good electrical yields about 90 percent of the time, that number decreased to 22 percent for 1 μm.

Improving that yield is part of the next step for research, Najem says. “It’s important to have better devices, but it’s always better to know how efficiently they will be interconnected,” she says.

Hybrid Bonding’s Importance to Huawei

Blocked by U.S. export controls from using advanced chipmaking tools, Huawei is turning to 3D chip stacking to keep increasing transistor density. Last month, the company presented its own hybrid-bonding milestone at the IEEE International Symposium on Circuits and Systems in Shanghai. As part of a plan to catch up with global chipmakers, Huawei president He Tingbo said the company had implemented a hybrid-bonding pitch of 1.5 μm in its coming generation of Kirin processors. This could mark a significant step toward parity with global chipmakers, but the method Huawei used is unclear.

Experts are hesitant to speculate on how Huawei achieved the pitch, but they don’t venture into skepticism. “Connections can be realized in different ways,” Imec’s Tokei says. “It’s never that there is only one way to do things.”

The next steps for the global chip industry are clear: Get the current research milestones out of the lab and continue hitting new milestones. Gabriela Pereira, a senior semiconductor packaging technology and market analyst at Yole Group, says mass production pitches are still at 6–9 µm for D2W and 1–2 µm for W2W. She says the challenges that make research milestones difficult, such as alignment and smoothing, hold back mass production, because mass production requires speed and replicability.

Pereira adds that the industry may end up throwing more weight behind D2W over W2W tech, because it offers more flexible uses. For researchers like Najem, the sentiment is the same.

“A lot of applications are here just waiting for the improvement of die-to-wafer hybrid bonding,” Najem says.

Chipmakers agree that the transistor of the next decade will actually be two transistors stacked atop one another, packing in many more devices in the same area of silicon and leading to circuits that are as little as half the size of today’s. But their research efforts are beginning to show some important divergence in the details. Commercial introduction is likely six years away, so they are far from a final version, but research presented last week at IEEE VLSI Symposium in Honolulu and detailed today by IBM points toward two main paths.

Though companies have different names for it, in research this future device is commonly called the CFET, for complementary field-effect transistor. It takes the two types of transistor, the p-channel and n-channel field-effect transistor (PFET and NFET), that make up complementary metal-oxide semiconductor (CMOS) logic and stacks them instead of placing them side by side. Specifically, it stacks a type of transistor only recently commercially introduced called nanosheet or gate-all-around. This architecture itself contains a stack of nanometers-thick silicon sheets through which current flows. These are surrounded by a several-atoms-thin layer of insulation and a carefully concocted mix of metals collectively called the gate stack. The device is completed by caps of crystalline silicon at each end, the source and drain.

To construct CFETs, Intel, Samsung, and TSMC are pursuing a scheme called a monolithic process. Fundamentally that means they are building both the top and bottom device at the same time, one directly above the other. IBM, in contrast, is committed to a scheme that’s generally called a sequential process, because it builds a complete layer of transistors before constructing another layer above it. What’s more, IBM’s plans call for the transistor pair to be slightly staggered rather than directly in line as the monolithic process produces.

Chipmakers are expecting big gains from CFETs, especially IBM. The company, which does not manufacture its own chips but develops chipmaking processes for others, says its version of the technology, called Nanostack, will deliver as much as a 50 percent performance boost, 70 percent efficiency improvement, and 40 percent shrink of a computer chip’s memory compared to today’s 2-nanometer-node chips. Nanostack “is not just a one-time innovation,” says Huiming Bu, IBM Semiconductors vice president of global R&D. “It is a new transistor platform that enables so many innovations to come.”

Sequential Integration for CFETs

One of the biggest barriers that’s held back sequential processes is the scorching temperatures needed to make high-quality transistors. “The key trade-off is that the lower FET tiers must withstand the full thermal budget of the tiers above it,” said Nirmaan Shanker, a research scientist at IBM Research, at the VLSI Symposium.

This heat, which can reach in excess of 900 °C and last for hours, can ultimately reduce the amount of current a transistor can deliver and make it more difficult to control at what voltage it should switch on or off.

In earlier research, IBM demonstrated a way for NFETs to survive such a process. At the VLSI Symposium, Shanker explained how researchers did the same for PFETs.

There’s still work to be done to improve the process, but it points to an even more transistor-dense future. “In theory this process can be continued for additional FET tiers,” said Shanker. The team calculates that a chip with four tiers of transistors would shrink circuits by 40 percent versus a two-tiered chip.

IBM’s other innovation is to slightly offset the two tiers of transistors. Staggering the NFET and PFET instead of directly stacking them might seem like it would take up more space, but according to IBM it will really result in smaller logic circuits and better transistors.

One of the biggest issues with CFETs, generally, is managing to make all the needed connections to both transistors in a very confined vertical space, experts say. For example, the top transistor might need to connect to power, which comes from interconnects below the stack, and a data signal from above the stack might need to contact the bottom transistor. Needing to route these connections around the sides of the transistor stack puts a limit on how closely CFETs can sit.

Staggering solves some of these by allowing more direct connections. “The front side of each transistor and the backside of each transistor can be contacted independently,” says Bo. The staggered design is fundamental to delivering Nanostack’s 40 percent shrink of memory circuits, he says.

Monolithic Integration for CFETs

For all its advantages, sequential CFETs are not as straightforward as monolithic processes. “I think across the industry, the monolithic is the leading integration scheme,” says Myunghee Na, a CFET expert and vice president at Intel.

Monolithic schemes essentially take a somewhat taller stack of nanosheets and use the top set for one device and the bottom set for the other. The difficulty is modifying, separating, and squeezing in all the parts and connections, some of which are in the shadow of others. In solving these problems, chipmakers are experimenting with new kinds of connections and improving the performance of the devices.

Samsung reported the first three-nanosheet PFET and three-nanosheet NFET, but Intel and TSMC have been working with two-by-two structures. For Intel, it’s a compromise between the transistor being able to switch faster with more sheets and the stack being so tall that its structures lead to too much signal-sapping capacitance, eating up power, Jami Wiedemer, a device engineer at Intel, explained to engineers at the VLSI Symposium. But even that configuration “will likely change as the technology matures,” she said.

The companies are also modifying the electrical characteristics of the devices in other ways. Today, to serve applications that range from low-power mobile chips to high-clock-rate server CPUs, foundries offer versions of the same transistor that differ only in how much voltage is needed to turn them on or off. TSMC managed to make CFETs where those voltages could be set to three different levels for both the top and bottom device.

Intel, for its part, uses a different crystal orientation of silicon for the top and bottom transistor, because one orientation makes faster PFETs and the other makes faster NFETs. It’s done by growing the silicon for the two devices on separate wafers and then bonding the two wafers.

That process lends itself to a way of electrically isolating the top and bottom transistors that both Intel and TSMC use, forming a “middle dielectric isolation” layer from the insulating interface between the two wafers.

Samsung does it differently: Relying on an optimized crystal growth method, it starts with extra nanosheets between those nanosheets that will form the top and bottom devices. It then etches away the extras and fills in the gap with dielectric material.

Chipmakers are also using different methods to connect the top and bottom parts of the CFET. TSMC does this using a vertical connection along the side of the source and drain of the two devices. Intel’s “intraconnect” is formed completely within the CFET between the source and drain, and Samsung’s is built by cleaving through the source of the top transistor to link both devices to metal lines above them.

Expect chipmakers to try many more variations as they approach a commercially manufacturable CFET. “This is the ultimate architecture,” says Intel’s Na. It will take the whole industry, including semiconductor manufacturing equipment makers and electronic design-automation-software vendors, she says. “There is still a lot of work cut out for us, but it’s a really exciting time.”

Take a moment and try to imagine your life without the wireless advances of the past three decades.

Have you lost your luggage? What a shame AirTags have not been invented. The airline representative has promised to call with updates, so settle in for a long wait by the kitchen telephone, because there are no affordable cellphones. You’ll be stuck listening to whatever is on the radio while you wait, because there are no streaming services. That’s not even to speak of all the movie plots that would have been ruined.

This is just a tiny sliver of how wireless technology makes itself felt in your day-to-day existence. The effects it has had on supply chains, infrastructure, and how the economy runs have been world-altering.

None of it would be possible without the radio-frequency integrated circuits that allow all our devices to unobtrusively send and receive information.

Now imagine what the further evolution of this technology will bring: Wide-spread autonomous vehicles, quantum communications, 6G mobile service and satellite communications. Continued momentum will depend on newer and more advanced versions of today’s RF chips.

But there’s the rub. Whereas the design of most of the world’s computing chips has been standardized into its own science, RF design has remained stubbornly in the realm of art. A dark art, even, that is mastered only through years of experience. As any sorcerer will tell you, the dark arts keep their own schedule. And that schedule is impeding progress not just in RF chip design but in every other technology that depends on it.

About seven years ago, in the wake of AlphaGo’s victory over world Go champion Lee Sedol, my students at Princeton and I began to wonder: Could AI be taught this art as well? Recent successes suggest that, to a large extent, it can. Over the last few years, our group and other leaders in the field have started to develop machine-learning-driven algorithmic methods for designing RFICs. Some of the resulting chips look more like modern art than circuit layouts. Yet in many cases, the physical prototypes bested state-of-the art circuits in terms of performance. The real achievement, however, is that it took the AI orders of magnitude less time to conceive a working design than it would a human designer.

This is not about one or two RF chips. AI-enabled design could be the future of all RF design, and maybe much more.

The Dark Art of RFIC Design

So why do these chips all have to be crafted by hand? Why aren’t RFICs designed with an algorithmic synthesis process, much as CPUs and GPUs are?

The design of RFICs is an exercise in engineering across multiple physical domains. Maxwell’s equations, operating across different spatial and temporal scales, govern how electromagnetic fields interact with active and passive devices that must be carefully codesigned for the chip to function. Alongside these are the laws of thermodynamics, which determine how heat is generated and removed during operation, as well as the mechanics of thermal expansion and contraction that dictate how reliably the chip and its packaging survive temperature changes.

Simultaneously accounting for all the physical constraints these impose makes the design space almost impossibly large. Every decision involves complex priorities that often compete with one another, preventing the optimization of any of them.

To better understand the issue, let’s walk through the steps involved, after which you’ll better understand why a single new chip design takes years and tens to hundreds of millions of dollars.

Most of the area of radio-frequency integrated circuits is dominated by complex electromagnetic structures. Human-designed RFICs, like this broadband power amplifier [1], start with templates and follow a symmetric, understandable pattern. But freed from the constraints of human-designed templates and the need for humans to even understand the rationale of electromagnetic structures, power amplifier ICs [2–5] and low-noise amplifiers [6] can take on truly wild-looking yet efficient designs. SENGUPTA LAB

Let’s say you’re an engineer assigned to design a new 28-gigahertz power amplifier for a 5G-millimeter-wave handset. (This is the type of RFIC that boosts the 5G signals on your phone and transmits them to the antenna where they can be picked up by a distant base station). Where do you start?

RFIC design has some features in common with house building. Just as the blueprint for a house dictates the number of bedrooms and bathrooms to be built and the hallways connecting them, the blueprint for an RFIC—called the architecture—establishes the kinds of elements the RFIC needs to fulfill its intended function. Instead of rooms, the architecture includes, for example, the number of stages of amplification your power amplifier needs. Instead of hallways, it shows the paths that signals must take to get through those stages.

The blueprint for RFICs is actually mostly hallway; passive elements, like inductors and transmission lines, take up far more real estate than active elements like transistors.

Here’s why. As you have probably experienced yourself, a typical CPU’s transistors overheat when faced with operating frequencies of just a few gigahertz. The frequencies RFICs can operate at are higher by an order of magnitude—28 and 39 GHz for 5G signals, 26.5 to 40 GHz and even higher for satellite communications, and 77 GHz for automotive radar. Under this onslaught, a CPU’s transistors would fail.

RFIC transistors avoid this fate because these chips cleverly manage the signal’s energy with careful electromagnetic design. This takes the form of byzantine networks of metal elements that dominate the chip’s real estate. These structures are geometrically regular, often symmetrical, and so intricately constructed they sometimes resemble lacelike filigree. But while they may look decorative, they are essential to the chip’s functioning.

Electrically speaking, these “hallways” work more like the chip’s plumbing. Like plumbing, this extensive labyrinth of passives confines electromagnetic energy only to the places it should be traveling around the chip.

The major challenge in RFIC design is putting all these elements together to ensure they work, just as constructing a house from its blueprints demands exact specs for load-bearing beams, pipes, and external walls. On an RFIC, the architecture needs to be realized with physically fabricable transistors and passive components that are connected just so, to permit the signal to travel through the chip and be processed. The way these devices are connected locally is what we call the circuit’s topology.

The RFIC Design Process

To make that power amplifier, then, your first step is to identify a candidate circuit template: The combination of structures that will meet the goals of a particular architecture with a specific circuit topology. Over the years, researchers have eased your burden by developing reusable design templates for specific functions. For example, templates suggest how many amplification stages a circuit needs (because sometimes, combining the output of two smaller amplifiers will result in better bandwidth and efficiency than you would get from a single larger one). And they suggest what the general configuration of the passive structures should be. Today there is an extensive library of such templates.

However, these can’t simply be used off-the-shelf, because each comes with trade-offs. Some have better gain at the expense of stability; some better bandwidth at the expense of efficiency; still others are more energy efficient at the expense of output power, and so on. There is rarely a clear best choice.

To arrive at the “sweet spot” where all these different parameters are balanced into optimal harmony, designers will typically lay out several different versions of the circuit, using intuitions and methods they have picked up in their years of training.

The challenge is that the decision around the architecture, circuit topology, or the electromagnetic passives cannot be done separately. One decision influences the others. So, designing an RF circuit can often feel like trying to fit an oversized carpet into too small a room—press down one corner, and another pops up.

At microwave and millimeter-wave frequencies, even the smallest misstep is the difference between a chip that works and one that doesn’t, and any number of things can go wrong. For example, when an electromagnetic wave encounters a transistor—or any other component —the path it travels must be properly “matched” to what comes next. If it isn’t, some of the energy reflects backward instead of flowing forward. Imagine trying to connect a high-pressure fire hose directly to a narrow garden hose. Without the right adapter, water will splash backward at the junction. Very little will make it through. In electronics, this is called the impedance-matching problem.

To prevent those reflections, engineers design special transitions, essentially microscopic adapters, that smooth the handoff between components. On a chip, these adapters can be surprisingly intricate. They don’t just pass the signal along; they can also split it, combine it, or distribute it across multiple paths with carefully controlled timing and strength.

Once you’ve done the architecture, plumbing, and everything in between comes the moment of truth. Have all the choices you have navigated through the enormous design space resulted in an RFIC that meets its specifications? If the specifications are not met, you will have to go back, either redoing the topology or the entire architecture, and repeat the whole process. So get ready for months of time- and resource-heavy simulation and iteration. Perhaps you now see why, for decades, a core belief has persisted in the RFIC community: “RF design is an art.” It was said that only an experienced designer—with an artisanal understanding of how the pieces make up the whole—could master the subtleties of analog and RF design. Unfortunately, this entrenched notion has long held back algorithmic innovations in the field just when we need them most. Traditional, artisanal RFIC design is hitting its limits as the complexity of these systems inexorably grows.

AI for RFIC Design

While RFIC designers continued their battle against their “oversized carpet” problem, a series of interesting developments emerged in allied disciplines. Across a range of other previously intractable problems like protein folding and climate modeling, AI has been able to successfully navigate multidimensional complex spaces. This gave us the incentive to look deeper into AI for RF. After all, the combinatorial complexity of protein folding is not that different from the nature of the design space in our domain.

We were not the first to think of using artificial intelligence to speed up parts of RFIC design. Researchers had previously trained machine learning algorithms on circuit templates in the hope of speeding up the normal optimization processes. While this approach was undoubtedly faster than humans at optimizing templates, it still relied fundamentally on libraries of existing designs invented by humans.

We didn’t want that. We wanted to break free from the restrictions of prefabricated topologies. Because while a designer’s experience and hard-won heuristics are crucial to building a working design, they also place fundamental limits on it. Furthermore, such an approach would necessarily require simulation steps as part of the optimization cycle, and even the fastest simulations use a lot of computing resources. Worse still, in many advanced cases, such as for broadband designs, there are no existing templates.

But if we didn’t start with templates, where could we start?

The goal here was to allow algorithms to determine—entirely from scratch—every parameter for architecture, constituent circuits, and electromagnetic passives. This approach differs fundamentally from conventional optimization, which is limited to determining the parameters—like transistor dimensions and passive component geometries—that optimize structures originally devised by humans.

In our new approach, the architecture begins essentially from nothing and is progressively assembled through successive iterations. The system explores the design space by generating myriad candidate circuit combinations and mapping the resulting performance trade-offs as it navigates this landscape. Because the process is not biased by prior human design choices, it can produce completely novel circuit topologies that look markedly different from those created by human designers.

In some ways, the approach echoes AI systems such as AlphaGo Zero, which achieved superhuman performance not because it was trained on games played by humans but because it explored the rules by playing against itself. Similarly, our algorithm develops new circuit architectures by exploring and evaluating its own design strategies. In so doing, it learns to understand circuits, electromagnetics, and the close codesign they need to achieve the end-to-end design of RFIC.

Inverse Design for RFICs

To realize this capability, we proceeded in two stages. First, we developed a reinforcement-learning (RL) framework that determines the optimal system architecture, circuit topology, device parameters, and even the properties of the electromagnetic interfaces that connect different circuit elements. In this stage, the algorithm effectively defines how signals should propagate and interact across the system.

The algorithm trains very similarly to how a computer learns to play a game. If you let it play enough times, it can learn to play better by observing the relationship between the actions it took and the score it achieves. In a similar way, the RL agent here learns to design effective circuits by playing with a set of combinations, and over time, it can map the space between the circuit performance to its architecture, topology, and parameters. This training takes a few days to a week, but once trained, the agent can design circuits very quickly

The next step was to determine the physical structure of the IC’s electromagnetics—the plumbing—that can create the desired properties of the passive elements, which are characterized by a set of metrics called scattering parameters. These measure if a signal entering a component actually moves forward—or is reflecting backward, being wasted, as in our previous example with the fire hose and the garden hose.

Deriving the structure from the desired scattering parameters is an example of an approach called inverse design, which appears across many areas of engineering. In structural engineering, for example, one might collaborate with an architect on a physical goal—such as creating large interior spaces with high ceilings—and then determine the arrangement of arches or buttresses that can support it.

Generative AI for Electromagnetic Networks

But RF integrated crcuits pose a particular challenge for inverse design: The process must account simultaneously for circuit behavior and the electromagnetic responses of the interconnects and passive elements that link them together. But it has to figure that out without doing a lot of artisanal iterating.

So we replaced our RF circuit simulator with an AI-based emulator. This AI model can predict the behavior of electromagnetic fields going through any structure—even totally arbitrary two-dimensional shapes—without having to compute the underlying physics from scratch, as simulation tools do. It would predict the solution of Maxwell’s equations and tell you the scattering parameters for any structure you showed it, without actually doing the math. With such an AI in hand, what a time-consuming electromagnetic solver normally takes minutes or hours to accomplish is reduced to milliseconds.

We chose to build our emulator around a convolutional neural network—a machine learning model that has been remarkably successful for image processing. Such networks can extract spatial features from any structure, and it turns out that the image of a structure contains a lot of spatial information that can accurately predict its electromagnetic performance. Then we trained it on a vast number of random pixelated structures whose scattering parameters had been labeled.

Once we had our inverse-design RL and suitable AI emulator, we essentially had an end-to-end AI designer. So we asked it to design us a power amplifier.

Unconventional RF Architectures

In 2023, we published this proof of concept—a power amplifier targeting the millimeter-wave band, specifically spanning 30 to 100 GHz, which covers most of the relevant 5G and radar frequencies. The final design achieved the best combination of wide bandwidth, output power, and efficiency then reported for a silicon-based power amplifier—meaning it could amplify a large amount of data across a wide swath of frequencies—while maintaining record efficiency.

The structure of the IC’s electromagnetic pathways was unlike anything any human would ever consider. Since the AI is not trained on human designs, the layout that emerged looked more like an arbitrary pattern or perhaps a QR code than the regular symmetrical structures we are used to seeing.

One unexpected insight revealed by this prototype, and our research generally, is that there’s no evidence that the templates we’ve historically relied on are even close to optimal for modern design goals. It’s not that a human designer can never come up with a better design. But with the removal of the templates and the time to synthesize cycle upon cycle of optimized circuits, it is now clear that AI-driven synthesis could break traditional design barriers and push the limits of RFIC capabilities.

Our 5G amplifier had only one input port and one output port. Adding more inputs and outputs to a design is not straightforward. Every port electromagnetically couples to every other port, so the scattering parameters quickly add up. Two ports give you four scattering parameters. Four ports, 16 scattering parameters. The math gets ugly fast. Could our model keep up?

We next trained our model on larger classes of electromagnetic structures with many input and output ports. In 2024, we published work showing that multiport integrated circuits are no problem for these AI algorithms either. Where previously multiport electromagnetic simulation required days or weeks of toil, this model evolved new structures in minutes. Since then, a plethora of work in the space by research communities across the globe have demonstrated the power of inverse design in RFIC.

Combining the reinforcement learning framework with the inverse design, we now had the ability to create an RFIC from specifications all the way to a fabrication-ready layout. We’ve so far shown this is true for RFICs ranging from low-noise amplifiers to subterahertz and broadband power amplifiers. The hope is that this will work just as well for other circuits.

Making AI Designs Interpretable

Our goal was to make RFIC design better and easier, but we didn’t want to make it beyond human understanding. Chip testing and debugging is a long, arduous process, sometimes even more so than design. Engineers often prefer ICs to have interpretable structures, so that if a problem crops up, they can understand how the chip works well enough to debug it.

To create structures that are more interpretable, we turned to diffusion models, which you may know from their remarkable ability to generate realistic images from text prompts.

AI-driven synthesis could break traditional design barriers and push the limits of RFIC capabilities.

Imagine you go to your favorite image-generation engine and ask it to create a painting of the sky in the style of Picasso, Van Gogh, or Michelangelo. You will get images that capture the essence of their brushstrokes, their use of colors, and their framing. All are pictures of the sky nonetheless, but in different styles.

Electromagnetic design is similar in that multiple structures can have very similar electromagnetic responses. Instead of using text input, we used scattering parameters as our input, and the electromagnetic structure of an RFIC chip as our output. As part of the inputs to the diffusion model, we created a dial that sets the spatial frequency of the final structure. By turning the dial, a designer can direct the model to synthesize structures with low (classical-looking and interpretable), medium (mazelike structures), or high (pixelated or arbitrarily-shaped) spatial frequency.

From prompts to output, the entire process took about 6 minutes. With this diffusion model, algorithms can now both discover novel architectures and accelerate the creation of conventional, so-called classical ones.

All an RFIC designer needs to do is specify virtually any valid set of scattering parameters. As long as they are physically realizable under Maxwell’s equations, the model pops out a corresponding structure as if it were a vending machine.

The Future of AI-Driven RFIC Design

The results of our investigations have drawn the attention of the RF community. The traditional bottom-up design process is clearly beginning to reverse.

But there are still questions: How generalizable are these methods? Can they consistently deliver truly high performance? Can we get to a place where AI produces designs that maximize every conceivable trade-off, holistically optimizing every parameter to its most ideal physical state? We want to take this strategy beyond RFIC design and invent other kinds of circuits that are different from anything humans have ever done.

These are exciting and ambitious prospects, but we are not there yet. AI can hallucinate a design that creates bad circuits that don’t work. This means verification methods need to remain under human oversight. And, while hallucinations are rare, it would still be good to reduce their occurrence.

History suggests that meeting these dreams of the future will take much more data than we’ve been using. Before the creation of the ImageNet repository—a repository of 14 million varied, human-annotated images—image-recognition models didn’t function well in the real world. The datasets they had been trained on were too tiny to be effective. ImageNet’s massive amounts of training data ushered in a revolution that led to AI that can generalize and recognize images in the wild. The rest was history.

If the goal for RFIC and analog design is a universal foundational model—something that learns the governing laws of electromagnetics and circuit behavior—then we also need data.

The good news is that this data is plentiful. Around the world, countless engineers at companies and academic labs simulate nearly identical RF circuits and passive structures every day. The bad news is that it’s all locked away behind nondisclosure agreements.

Open ecosystems have propelled other areas, and we think the RFIC community should do the same. There had been some movement toward this. Natcast, the operator of the U.S. CHIPS and Science Act’s R&D program, would have bolstered shared infrastructure and innovation for the next generation of wireless, sensing, and defense technologies. Unfortunately, both the organization and the program it ran specifically for machine learning and RFICs have been closed.

But the momentum Natcast’s effort sparked hasn’t died out. Building on our early work, groups across the community have already demonstrated remarkable advances. AI-driven IC design is part of a much broader technological shift. From biology and materials science to automotive and aerospace engineering, AI is reshaping how complex systems are conceived and optimized. Deeper collaboration between AI researchers and chip designers will unlock the field’s full potential. It’s by no means a foregone conclusion, but if we get this right, this genie won’t stay in its bottle.

It’s little secret that Europe is dependent on foreign technology—particularly U.S. tech—for office software, cloud services, AI, and more. This may have been easy to accept just several years ago, but when the United States government now openly threatens European countries with military action, there is growing anxiety in Europe that technology dependency is a liability.

One 3 June, the European Commission, the European Union’s executive branch, introduced a sprawling package that seeks to shift the tech supply chain in Europe’s favor.

This Tech Sovereignty Package contains four parts. Two are proposed laws—the European Chips Act 2.0 and the Cloud and AI Development Act. The other two are broader strategies—one to promote open-source software and one to shore up the EU’s electric grid. Before the first two can become law, they must go through a long process involving the EU’s other two lawmaking bodies: the Parliament and the Council.

The Commission’s vision places European governments and crucial industry at the forefront of change, encouraging them to fund and buy European tech. Some analysts, however, are unconvinced the measures go far enough to change the status quo.

Part 1: Chips Act 2.0

As indicated in the name, the Chips Act 2.0 follows the EU’s original Chips Act, adopted in 2023 (and not to be confused with its similarly named U.S. counterpart.) The first European Chips Act encouraged investment in EU semiconductor production, aiming to reach a 20 percent share in the world market for “cutting-edge and sustainable” microchips by 2030. It supported pilot lines in areas like sub-2-nanometer chips and photonics, in addition to both large fabs and small startups.

Early results have been mixed—a 2025 audit found that the first Chips Act had created progress in areas like chip design and pilot lines, but deemed it “unlikely to be sufficient” to reach an “overly ambitious” target.

One criticism of the first Chips Act was that it did little to cultivate demand for European-made semiconductors. The Chips Act 2.0, then, includes demand-boosting measures that encourage governments and industry to use European chips, in addition to retaining its supply-side funding.

There are new supply-side elements, too. The Chips Act 2.0 allows the Commission to fund certain fabs as “strategic projects” and fast-track them through permitting. The Commission has proposed an open-access foundry to manufacture chips at 3-nm-process nodes or lower, which could start pilot production between 2030 and 2033.

If successful, European semiconductor manufacturers could take over the supply for industrial firms in automotive, defence, and advanced manufacturing. Today, these firms are especially vulnerable to global supply-chain disruptions.

At the same time, some analysts still question whether the Chips Act will create enough demand. “The Commission clearly recognizes this in the revision and devotes considerable attention to demand-side levers,” says Tillman Schenk, researcher at Bruegel, a Brussels-based think tank. “However, these instruments currently strike me as somewhat underdeveloped.”

Some analysts write that to raise demand, the EU must explicitly require, not merely encourage, governments to “buy European.”

Part 2: Cloud and AI Development Act

The accompanying Cloud and AI Development Act (CADA) focuses on cloud services and data centers. The EU trails both the U.S. and China in total data-center capacity, and European leaders say they need to close this cloud gap if both EU governments and industry are to make the most of cutting-edge AI.

Therefore, CADA calls for a tripling of EU data-center capacity by the early 2030s.

Michael Winterson, Secretary General of the European Data Centre Association, calls the goal “achievable in principle” and says that “demand alone could justify a tripling of capacity.” Achieving this goal will require dramatically speeding up data-center projects that today might get stuck in permitting or waiting in a queue for electrical supply, he says.

CADA stipulates that member states should designate particular projects and “acceleration zones” for fast-tracked approval. It also stipulates that, by 2030, data-center operators should be able to obtain the necessary permits and grid access—often a years-long process today—in 18 months.

But in Europe, there are some rather large elephants in the cloud. Today, four U.S. hyperscalers—AWS, Google Cloud, IBM Cloud, and Microsoft Azure—account for over two-thirds of EU cloud services. This troubles some Europeans because U.S. law authorizes U.S. authorities to compel U.S. firms to hand over data even if stored abroad.

To ensure that more sensitive European data stays within Europe, CADA lays out a sliding scale of four “assurance levels.” Higher levels require more EU-located data, infrastructure, staff, and supply chains. However, national authorities can choose assurance levels as they see fit, so the same application might use different levels in different countries.

Some analysts like EuroStack’s Stéfane Fermigier note that this leaves the door open for the assurance levels to be applied unevenly. American hyperscalers could locate data centers in the EU, claim sovereignty compliance, and avoid ceding ground to their smaller European counterparts.

Part 3: EU Energy System Road Map

The announcement of a threefold increase in the EU’s data-center capacity is unlikely to comfort the many Europeans who oppose their construction, citing concerns about their environmental footprints or their potential to strain the electrical grid. Partly in response, the EU’s tech sovereignty package includes a “strategic roadmap” for Europe’s electrical grids.

The Commission has proposed a rating system that would grade data centers based on their efficiency and environmental footprint, but this scheme has reportedly been delayed under pressure from data-center operators and some EU member states.

The road map includes support and research projects for smart grids and for AI models in the energy sector. It also plans to enable EU electric grids to more easily exchange data across borders.

Unlike the Chips Acts or CADA, the road map is not a proposed law. In many cases, its measures are research projects or promises to introduce future legislation by the end of 2027.

Part 4: Open Source Strategy

European public administrations spend an estimated €264 billion per year on proprietary IT, with 80 percent going to American companies. In the past several years some European bodies have made sporadic moves toward open-source alternatives, perhaps most notably the French civil service’s migration from Windows to Linux.

Now, the European Commission has unveiled an expensive strategy to promote open source in the public sector. In theory, open source could at once save on costs, phase out non-European software, and benefit European open-source developers.

The Commission’s plan stretches beyond office software and operating systems. It envisions public services partaking in a “vibrant” open-source ecosystem for everything from AI to RISC-V semiconductors to Web 4.0 architecture. It plans to fund open-source startups and developers in key sectors.

Although this strategy is not in itself a law, CADA includes some open-source measures, like a provision to “encourage” public-sector bodies to use open-source cloud and AI. In theory, this could establish a precedent for governments to choose “open source first.”

Jordan Maris, EU Policy Analyst for the Open Source Initiative, is optimistic about the package. He particularly believes it could be a boon for maintainers of core software. “They will likely receive recognition and opportunities for funding,” he says. “My guess is it will predominantly serve individual developers but some community-led projects could also benefit.”

Maris also says it can benefit developers of crucial enterprise software like Collabora Online, Euro-Office, and Nextcloud. Other open-source advocates, however, argue that the open-source measures in CADA do not go far enough. In particular, since CADA’s articles “encourage” public-sector bodies to prioritize open source rather than “require” it, the public sector may instead let inertia take its course.

This package is not final. The Chips Act 2.0 and CADA will now proceed through further European lawmaking, involving the European Council and European Parliament, a process that inevitably changes the content.

There’s also pressure from U.S. tech firms and some of the EU’s own member states to water down some of the requirements, as already happened with some of the open-source measures.

When the U.S. Navy’s fleet of F/A-18F Super Hornet fighter jets is headed for the scrap heap because an essential chip is unavailable, what do they do?

They turn to Ryan Hatcher, the CEO and founder of Phoenix Semiconductor. Hatcher repackages off-the-shelf semiconductors into devices that are virtually identical to the phased-out chips.

“You’re not going to park a US $100 million aircraft, whether it’s a 737 or an F-35, for a $1,000 chip, even if that chip originally cost five bucks,” Hatcher says. “We’re hooking up the supply of components you can get off the shelf today at volume, at low cost, with the demand for parts that are no longer available, but for which there’s tremendous marginal need.”

In the Navy’s case, they turned to Phoenix specifically for a replacement part needed to maintain the jet fighter’s bleed-air control unit that regulates cockpit air pressure and temperature.

Phoenix, founded in 2023 and based in Austin, Texas, connects chips on an interposer (the electrical bridge that connects chips within an electronic package) that the company designs into a package with a pin-out (the metal leads carrying signals from a chip to a printed circuit board) similar to the original component.

“When you drop that part into the socket, it looks identical, indistinguishable from the original,” Hatcher says. “There are no board updates. There are no software updates. There are no firmware updates. It just operates like the original.”

Solving Legacy Chip Obsolescence

Phoenix is aiming for the high-mix, low-volume demand that large chip manufacturers don’t want to touch. As more systems used in aerospace, healthcare, and industry face obsolescence because the legacy chips that run them are no longer available, Ryan sees a “long tail” of demand exceeding his ability to supply.

“There is demand for billions of dollars of legacy chips every year, and much of that demand literally doesn’t have a product in existence anymore,” says Jonathan Bronson, a managing partner at venture capital firm J2 Ventures. “In many of these cases, Phoenix is the only game in town.” Bronson became a board member for Phoenix in June 2025 after earlier investing in the company.

Leading chipmakers like Intel or Taiwan Semiconductor Manufacturing Company (TSMC) count on large production runs to maintain high capacity utilization, a key measure of profitability. A production run for one chip in a large fab can last up to three years. Retooling a production line for a new chip results in downtime and lower yields that hurt profit.

“No one’s going to pick up the phone for a couple hundred chips,” Hatcher says of big semiconductor foundries like Samsung, where he worked from 2013 to 2019. “The fundamental mismatch is that semiconductor companies go out of business if they have high mix, low volume. Defense companies, more generally, need a high mix of parts, but very low volumes.”

Phoenix and its 15-member team aim to bridge that mismatch, assembling prototypes in their Austin lab that they later outsource to companies like Micross, QP Technologies, or TTM Technologies for commercial production. In June, the company received an ISO 9001 certification, an internationally recognized standard for quality management systems published by the International Organization for Standardization.

To start, Hatcher likes to find low-power chips originally made for the Internet of Things (IoT) market in chip-scale packages that are nearly the same dimensions as the silicon inside.

“We take a collection of these and then put them onto an interposer, an MCM [multi-chip module],” Hatcher says. “The bottom, the pin-out, is like the original chip. One related challenge that we have faced is to source or fabricate legacy packaging like lead frames or CERDIP (ceramic dual in-line package) housings and adapt those packaging solutions for MCMs instead of single-chip die.”

Defense and Industrial Chip Demand

Defense applications make up the largest share of Phoenix’s business, which also includes medical technology, industrial applications, commercial aerospace, and oil and gas extraction. One customer makes audio-processing chips for stadium sound systems worth hundreds of thousands of dollars.

“All of these systems are not high volume, but super-high dollar value,” Hatcher says. “Those are our customers. Customers that are largely ignored by traditional OEMs [original equipment manufacturers]. For the OEMs like Texas Instruments or NXP, this obsolescence business is a constant pain in their butt because they’ve got these customers that have these long tails of demand. They’re good customers, but they’re annoying at the end, because [the OEMs] need to flip over to the next generation. We are working with the OEMs to essentially take over production of certain lines of products.”

Hatcher aims to invest in automation tools and facilities to expand production.

“At some point, we’re going to look to develop our own highly-optimized manufacturing flows for high-production [and] low-volume. Because even your Micross and TTMs, they’re not semiconductor fabs, but they still have pretty substantial switching costs to go from one product to the next, one board to the next.”

This story was updated on 17 June 2026 to correct the spelling of Micross.

This article appears in the August 2026 print issue as “Semiconductor Startup Builds Alternatives for Obsolete Chips.”

Uncle Sam wants you to solve big scientific and engineering bottlenecks outside the hallowed walls of academia. On 14 May, the U.S. National Science Foundation (NSF) issued a solicitation inviting what it calls “X-Labs,” or independent research organizations, to apply for a total of US $1.5 billion over 10 years. The structure of the X-labs solicitation is new for the United States government and closely matches an emerging private funding model for what are known as focused-research organizations (FROs), which various think tanks and philanthropies have proposed and tested during the last six years.

A focused-research organization is a team of scientists, engineers, and other technology developers that works on a well-defined problem with a target duration of three to seven years and on a budget in the tens of millions of dollars. Some examples have sought to build an ultrasound-based brain-computer interface, quantify marine CO₂ removal, and improve formal verification in mathematics. The funding for these FROs required a team approach to science larger and more agile than a typical academic lab but with a more academic appetite for scientific risk than a commercial venture might have. In some ways, they echo work done by the Defense Advance Research Projects Agency (DARPA), which is known for helping bridge high-risk research and early-stage commercialization of many technologies.

“The NSF’s X-Labs announcement is a welcome signal that the global research community is serious about finding new ways to fund ambitious, high-risk science,” says Pippy James, deputy CEO of the Advanced Research + Invention Agency (ARIA), a United Kingdom government funding body in London that uses a similar model to the X-Labs.

The NSF’s first two X-Lab research areas are scientific instrumentation for sensing and imaging and interconnects and integrated photonics for quantum systems, and the solicitation says the agency will announce additional topics within weeks.

The funding is structured in phases, with $1.5 million per project in the first year, then up to $50 million per project over the next two to three years for selected projects, with a third, more open-ended phase after that. That first-year funding is more than seven times as much as for the typical NSF project of around $200,000.

“Compared to incremental, project-based grants, larger institutional grants and longer-horizon grants let teams take on harder, more infrastructure-heavy problems with the agility to pivot as they learn,” says Jenn Gustetic, director of metascience and R&D policy at the Institute for Progress (IFP), a Washington, D.C. think tank that made a proposal last year for how the U.S. government could support more independent research organizations.

The NSF solicitation also requires applicants to demonstrate “substantial” independence from any non-X-Lab institutions such as a university or company, which the NSF defined in part to mean the ability to make decisions on research direction, partnerships, and staff in days rather than weeks. It would be difficult for a full-time researcher at a university to qualify, for example, which opens the door to industry researchers or academics willing to take extended leave.

What should new money for science look like?

“People have been kind of wanting to do [focused research organizations] in a fairly bipartisan way since 2020,” says Adam Marblestone, an early proponent who now directs Convergent Research, a Cambridge, Mass., nonprofit that has spent almost $400 million building a dozen FROs. Some larger goal-directed, rather than principal-investigator-centered, funding has existed for decades in other federal agencies in the form of the Advanced Research Projects Agencies for defense, intelligence, energy, and most recently health. ARPA program managers often took a more hands-on and flexible approach than typical three-year National Institutes of Health (NIH) or NSF grant managers could. On 2 June, the IFP published an Atlas of Innovation comparing many different research funding structures.

The NSF announcement comes against a backdrop of administration requests for dramatic cuts to the agency’s budget, though Congress has generally appropriated stable amounts. NSF has, however, not disbursed all its appropriated funding, because the Trump administration has been feuding with many universities, accusing them of discrimination, and suing them. Most recently, NSF stopped new funding for several prominent universities, Nature reported. MIT’s president in May said that the university has won 10 percent less federal money than the previous year.

The big-ticket nature of the X-labs might make administrators and principal investigators at those universities worry about whether it will impact their own funding. “I don’t think it’s a zero-sum game,” says Erica Goldman, director of policy entrepreneurship at the Federation of American Scientists, a Washington, D.C. science-policy think tank, “but the way the timing of the announcements have come out and the rhetoric out there make it very hard to see that.”

“NSF X-Labs is structured to complement the existing system, not displace it—adding an independent institutional type alongside universities, national labs, small businesses and corporate R&D,” the IFP’s Gustetic says. The X-Labs annual sticker price represents less than 2 percent of the agency’s overall budget of $8.75 billion in 2026.

The emerging field of metascience, which investigates how best to do science, has been debating how governments should build the proper pipelines for converting blue-sky research into returns for all taxpayers. Metascientists differ over how FROs should fit into the research system. Some argue that governments can’t expect to apply the vaunted DARPA model to everything. Others write that FROs are a great idea and that the federal government already has a version of them in the form of the Department of Energy’s National Labs, which have spun off science platforms such as the Human Genome Project and the Protein Data Bank.

NSF media affairs head Mike England told IEEE Spectrum that “X-labs creates space and provides funding for new institutions to achieve breakthroughs in scientific discovery, research, and translation, and ultimately helps create new platform technologies.” In addition, on 27 May NSF requested information for a new funding idea adjacent to X-Labs it calls Tech Accelerators. These would use NSF money and accelerator expertise to fund and guide “deep-tech” commercialization efforts in agriculture, materials, ocean, and scientific instrumentation.

Other elements of government are also exploring how to incorporate the FRO funding model. In December 2025, U.S. Representative Josh Harder (D-Calif.) introduced a bill that would apply the X-labs model to the NIH. England says that NSF is having conversations with other government agencies about the model and welcomes more agencies to explore it.

“We don’t have great evidence comparing how different funding mechanisms perform—individual project grants, milestone-based contracts, prize challenges, etc.” Gustetic says. “X-Labs is a chance to actually learn something about which institutional designs work for which kinds of problems.”

Universities will likely have to adapt to the new model. Mid-career academics may well want to take time away from their university homes to participate in an X-Lab or other FRO project, says Monica Dus, director of the Office of National Laboratories at the University of Michigan and a holder of NSF grants. Institutions will need to figure out how to cover teaching duties in their absence and how to assess commercial experience for tenure or other internal promotions. “Universities should adapt to make sure the research does really reach the people it is meant for,” she says.

Academics may also need to change their approach to succeed, Convergent’s Marblestone says. “When we go to academics at Convergent, it takes a few conversations to plan it, because they don’t always know how they’d manage $50 million and a professional engineering team. You really need a CEO.”

I have been an application-specific IC (ASIC) designer for almost three decades. Over that time, I’ve moved through the full academic trajectory, from graduate student to full professor; later, I transitioned to industry after an unsuccessful stint at entrepreneurship. When I made the switch to the private sector in 2019, I began focusing on a critically important aspect of the electronic industry: silicon intellectual property.

As much as 80 percent of the physical area in today’s most advanced chips is occupied by blocks that aren’t made for specific products or even designed by the consumer-facing companies that built them. Instead, chipmakers draw heavily on established silicon IP from companies like Arm, Cadence, Rambus, Synopsys, and the company I work for, Silicon Creations.

Throughout my career, I’ve designed chips for very different purposes, including enabling the research program in my academic lab and expanding the IP portfolio of my company. When I joined Silicon Creations, I had no idea how differently the industry approaches IC design and encountered a steep learning curve. Initially, it seemed that much of my two decades of academic research and training did not directly translate to the role. I had to learn new skills and adopt a new mindset.

Today, demand for ASICs is rapidly growing, driven by the need for specialized chips in the automotive sector, AI applications, and more. By one market estimate, the ASIC market is expected to grow from US $23.4 billion to $38.8 billion by 2033, and the semiconductor industry as a whole is projected to hit $1 trillion by 2030. The industry needs more chip designers—but if you’re coming from an academic background as I did, there are a few things you’ll need to know.

Different goals lead to different strategies

The differences between industry and academe begin with a divergence in purpose. In academia, my primary objective was to generate new knowledge: to propose a novel circuit technique, validate an unconventional architecture, or explore the limits of performance in a given domain. A successful chip is one that demonstrates a concept. In industry, it is not nearly enough to prove that something can work. The goal is to ensure that it works reliably, repeatedly, and at scale. Success is measured not by novelty but by whether the silicon meets specifications, yields as expected in production, and supports a competitive product delivered on schedule.

This leads to a stark contrast in risk tolerance. Academic designs often deliberately push into unproven territory, where even partial success can yield valuable insight. In industry, however, we systematically minimize risk. The cost of failure makes first-time silicon success a central requirement—especially at advanced technology nodes, where the lithography masks used to transfer circuit designs onto silicon wafers alone can cost tens of millions of dollars. As a result, industry design flows are built around eliminating uncertainty through conservative margins, extensive validation, and careful reuse of proven solutions.

“Academia explores the design space, asking what is possible, while industry exploits it, determining what is viable at scale.”

This paradigm has existed since the 1970s, when application-specific chip design was established. However, the gulf between academia and industry has expanded since the mid-2010s, when FinFET technology, a 3D architecture using vertical “fins” of silicon, was widely adopted in industry. System designs are also becoming increasingly modular with the advent of chiplets. This fundamentally altered the economics and complexity of ASIC development, with design costs rising by almost an order of magnitude. Initiatives like Taiwan Semiconductor Manufacturing Co.’s University FinFET Program and new government-funded chip-design hubs now let some well-resourced universities design for more advanced architectures, but the technology is still out of reach for many academics.

What the industry-academia split means in practice

Consider a startup developing an ASIC. Its engineering team may have deep expertise in a particular algorithm, sensor interface, or system architecture, the features that define its competitive advantage. But it is unlikely to possess world-class expertise in every supporting function. Developing each of these blocks internally would require significant time, capital, and specialized talent. Doing so could delay market entry beyond the startup’s viability.

Even large semiconductor companies face similar constraints. Advanced-node development demands intense focus. Allocating a team to redesign a standard interface block that has already been implemented elsewhere may be difficult to justify when differentiation lies at the system level, such as an inference chip’s ability to speed up neural network computations. The time it takes to move a new chip from conception to market and risk mitigation, not self-sufficiency, govern most decisions about in-house development versus outsourcing.

The economics of advanced IC manufacturing reinforce this reality. When the development cost of a leading-edge chip reaches hundreds of millions of dollars, minimizing risk becomes a central design imperative.

In this context, silicon IP emerged as a practical solution. Similar to how software developers rely on preexisting libraries rather than writing every function from scratch, ASIC designers license predesigned, preverified silicon blocks—such as processor cores, memory interfaces, and security engines—from highly specialized IP vendors. These blocks can then be integrated into larger, increasingly complex systems.

Design scope, verification, and time horizons

With the use of silicon IP, industry is able to widen the scope of its designs. Academic efforts tend to focus on block-level innovation: a new analog-to-digital converter architecture or an ultralow-noise amplifier, for instance. These designs typically abstract away many of the complexities of bringing a chip to market, such as packaging constraints, long-term reliability, and manufacturing yield.

In industry, the focus shifts to system-level integration. Modern systems on chips, or SoCs, incorporate dozens or even hundreds of functional blocks. Managing signal integrity, timing, firmware interaction, and system-level validation becomes as critical as the design of any individual block.

Verification philosophy also diverges sharply. In academia, the goal of verification is to demonstrate that the concept works under nominal conditions, which may not always reflect how it would perform in real applications. Even if only a fraction of fabricated chips from a multiproject wafer operates correctly, the design may still be considered a success if it validates the underlying idea.

At my academic lab for instance, we used to receive 40 chips from a TSMC prototyping service and started testing them in batches of five. If the first five or 10 chips proved functional, we had already collected more than enough data for a publication. If some of them failed, we weren’t required to mention this when publishing the results.

In industry, verification is exhaustive, critical, and often dominates the development schedule. Failures are measured in parts per million, and even rare anomalies are carefully analyzed and documented to identify root causes and prevent recurrence. When I started at Silicon Creations, I was surprised by the level of detail and scrutiny designs face.

Differences in time horizons and economic constraints reinforce each of these contrasts. Academic projects operate on flexible timelines aligned with research and funding cycles. If I missed a deadline, I just had to wait for the next cycle. Industry projects are driven by fixed product schedules and market windows, frequently targeting costly leading-edge nodes to achieve competitive performance, power, and area efficiency. Missing a deadline can negate the value of an entire design and may have major financial consequences along the entire supply chain.

In essence, academia explores the design space, asking what is possible, while industry exploits it, determining what is viable at scale. Both are indispensable, but they operate under fundamentally different definitions of success. As ASIC complexity continues to grow, understanding both perspectives will be essential for the next generation of engineers navigating the evolving semiconductor landscape.

This article appears in the June 2026 print issue.

A practical introduction to phase noise concepts, explaining how oscillator instability affects RF systems and how phase noise is measured, analyzed, and reported.

What Attendees will Learn

1. What phase noise is and why it matters — Learn how real-world oscillators differ from ideal ones, why short-term frequency instability arises, and why phase variations typically have a much greater impact than amplitude variations on system performance.
2. How phase noise degrades system performance — Understand the most common effects of excessive phase noise: spectral regrowth, reciprocal mixing, and constellation rotation in digital communications.
3. How phase noise is measured and reported — Explore the spectrum analyzer method and the cross-correlation technique, understand single sideband (SSB) phase noise plots and spot noise tables.
4. What advanced phase noise measurements look like in practice — Discover additional measurement types including integrated phase noise, additive (residual) phase noise, pulsed signal phase noise, and amplitude noise.

Chipmakers are struggling to shrink the amount of area a transistor takes up, so researchers are trying to build layers of devices on top of each other. However, many experimental 3D chips rely on exotic materials and perform poorly compared with regular silicon devices. But researchers at the University of Illinois Urbana-Champaign have found a new way to build 3D circuits from silicon. The secret is a process that lets them roll multiple layers of nanometers-thin silicon onto a wafer at relatively low temperatures.

Today’s 3D microchips, such as the AMD MI300 series, stack prefabricated layers on top of each other and connect them with the help of metal pillars known as through-silicon vias. However, the challenge of properly aligning the connections between these layers limits how many links can be made and therefore how useful 3D stacking can be.

By contrast, in monolithic 3D chips, layers of devices are fabricated directly on top of each other. This enables alignment of these layers with nanometer-scale precision, and with orders of magnitude denser connectivity than today’s 3D chips.

However, experimental monolithic 3D chips require transistors and other devices in the upper layers to be fabricated at 400 °C or less to preserve the wiring that connects their components together. Such 3D chips have been made using a variety of materials, but their performance and reliability all proved much worse than the metal-oxide-semiconductor field-effect transistors (MOSFETs) found in virtually all conventional microchips, erasing most of the gains offered by a monolithic 3D design.

Now scientists have created monolithic 3D chips from silicon at less than 200 ℃. “For years, people assumed monolithic 3D would require exotic new materials such as carbon nanotubes, metal-oxide semiconductors, or 2D semiconductors,“ says Qing Cao, an associate professor of materials science and engineering at the University of Illinois Urbana-Champaign. “Demonstrating that silicon can do the job means this technology can plug directly into existing manufacturing ecosystems, which dramatically accelerates its path toward real impact.”

Low-temperature junctionless transistors

Instead of the MOSFETs used in most chips, the new 3D chips rely on junctionless transistors. Regular MOSFETs are made using both n-type semiconductors, which are doped to contain an excess of electrons, and p-type semiconductors, which are doped to produce a deficit of electrons. Charges enter a transistor through its source terminal, travel down a channel, and exit out the drain terminal. In MOSFETs, if the the source and drain are made of p-type silicon, the channel will be made of n-type, and vice versa. The p-n junctions where these semiconductor types meet interrupt the flow of current. When a gate electrode applies voltage to the channel, current can flow across.

Each layer of a new kind of 3D contains so-called junctionless transistors. The bottom layer is made from silicon with excess mobile electrons, the top from silicon with excess holes. The transistors are linked together vertically to form complementary logic.Bao Lam, Yung Man Yu, et al.

In contrast, in junctionless transistors, the source, channel and drain are all completely either p-type or n-type, and so operate without p-n junctions. When a voltage is applied to the gates, they switch on, allowing current to flow. First proposed in 1925, they were not built until 2010 due to limits in fabrication technology; they require highly and uniformly doped channels at most about 10 nanometers thick. In MOSFETs, chipmakers use high heat to make sure dopants are located precisely where they are needed to be in the silicon crystal to create p-n junctions. Junctionless transistors don’t need these high temperatures.

“Junctionless devices also use a simpler process flow, which can reduce costs and improve yield,” Cao says.

The new 3D chips are made by laying down uniformly doped single-crystal silicon membranes each 10 nm or less thick using a wafer-scale roll-transfer-printing process. “Because the membranes are so thin and flexible, they conform to the underlying surface, avoiding the voids and warpage that often plague wafer bonding between rigid wafers,” Cao says.

That the nano-membranes can transfer onto surfaces that are not necessarily perfectly flat “is important because the current method typically used in industry requires sub-1-nanometer roughness for the surfaces to be bonded together and extremely flat—only a few microns of variations across the wafer,” says Veeresh Deshpande, an associate professor of electrical engineering at the Indian Institute of Technology Bombay, who did not participate in this study. “The proposed method simplifies the process complexity and allows stacking several tiers of transistors, both for advanced computing and memory like DRAM.”

Cao and his colleagues fabricated three levels of junctionless transistors on a 75-millimeter silicon wafer, with each tier composed of 625 transistors over a 1,600-square-mm area. From these transistors they constructed a variety of logic gates and circuits—including inverters, NAND and NOR gates, and static random access memory (SRAM) cells—using vertical connections between the layers that were aligned with sub-10-nm accuracy.

The researchers were able to form circuits made up of transistors distributed over all three layers of the 3D chips. That led to a six-transistor SRAM cell with a footprint as little as one-third the size of its 2D layout.

A transistor’s switching speed depends on its current density, and the junctionless transistors showed a current density that could exceed 650 milliamperes per micrometer, which is comparable to older commercial silicon MOSFETs. More advanced MOSFETs do show current densities exceeding 1,000 mA per micrometer, but Cao and his colleagues say that future engineering could further improve the performance of their devices.

“The key implication is that vertical stacking may not have to come with a severe transistor-performance penalty,” says Saptarshi Das, a professor of engineering science and mechanics at Pennsylvania State University, who did not take part in this research. “If scalable, this could open a practical path to denser, more energy-efficient chips with much shorter interconnects.”

Roll-transfer processes

The silicon wafers Cao’s team used are much smaller than the 300-mm ones most fabs use today. But transferring and stacking silicon membranes even across a 75-mm wafer without cracks, wrinkles, or defects “required a series of engineering innovations,” Cao says. These included adding surfactants during certain etching steps to reduce surface tension; adding polymer support layers for mechanical stability and surface protection; and adopting a roll-lamination process to apply uniform pressure during transfer.

“We began in 2019,” Cao says. “By 2024, we realized we had solved the fundamental barriers. The following year and a half was spent refining the process and demonstrating multilayered devices at wafer scale and 3D logic circuits.”

Beyond computing, integrating silicon with other materials in monolithic 3D devices may open up new applications “that were previously out of reach.” Cao says. “For example, vertically stacking different types of single-crystalline semiconductors could enable ultrasensitive X-ray-detector panels or compact multispectral imaging systems.”

A new 3D chip has three layers of silicon transistors separated by about 90 nanometers of dielectric.Bao Lam, Yung Man Yu, et al.

One challenge monolithic devices will face is yield. “When you stack devices vertically, the traditional assumption is that every transistor in every layer must work perfectly, which can reduce overall chip yield,” Cao says. “We are working with circuit designers on defect-tolerant architectures that can absorb imperfections with minimal area and power overhead.”

Another hurdle is the way these 3D chips increase power density, concentrating heat. “We are collaborating with circuit and architecture teams on solutions such as dynamic voltage and frequency scaling and AI-assisted on-chip power regulation to actively manage heat,” Cao says.

Cao suggests the new approach is initially only promising for research and low-volume prototyping applications. “Once the benefits of monolithic 3D integration are clearly established, we can work toward high-volume manufacturing,” Cao says. “We simply want to be realistic and avoid over-claiming before the technology has been validated in those settings with full cost analysis.”

The scientists now want to partner with semiconductor foundries to demonstrate and refine the technology in a manufacturing environment, Cao says. Ultimately, “because our approach is silicon based and compatible with foundry processes, it has a realistic path to adoption,” he notes. “It will be especially valuable for AI workloads that are increasingly limited by communication bottlenecks, which is directly addressed by this technology by bringing compute layers physically closer together.”

Open-source software is ubiquitous: Linux is the dominant operating system on servers and supercomputers worldwide; Wordpress powers over 40 percent of all websites, among other major projects. Open-source hardware has existed since the late 1990s, but it hasn’t seen nearly the same level of interest or adoption as its software-focused cousin.

Dominic Rizzo, CEO and founder of the startup zeroRISC, aims to change that. Today, the nonprofit global security standards consortium GlobalPlatform launched Pavona, where Rizzo will be a governing board chair. The goal of Pavona is to facilitate the adoption of open hardware into all kinds of applications, including tiny IoT devices and massive data centers, by making the elements modular, standardized, and trusted.

Pavona is a new open-hardware ecosystem. It provides a starting kit of hardware modules, coupled with reference designs, a set of software tools to streamline adoption in different types of chips, and software tooling to ease integration. It also has a governance structure aimed at lowering the barrier to entry for adding new open-hardware designs and collaborating on development.

“I think it’s foundational,” says Andrew “bunnie” Huang, hacker and founder of Baochip, which is a founding member of Pavona. “We are now at the point where we finally have enough of a nugget of something open that we can spread it around. The outcome of this experiment is going to determine the shape of how we interact with hardware and open source for a long time.”

How open-source hardware differs from open-source software

The main reason open-source hardware hasn’t seen as much of a boom as software is almost too obvious to name: hardware needs to be manufactured, and manufacturing costs money. “Hardware, when it’s built, requires atoms,” Huang says, “which requires logistics and payment.”

At bottom, manufacturing itself is closed source. Because of this, open-sourcing hardware is inherently layered: While the chip fabrication, physical design kit, and foundry process remain closed, the layers on top of that, such as the design verification, system architecture, instruction-set architecture, and firmware, may be open source.

The Pavona ecosystem isn’t meant to deepen the penetration of open source through the layers. Instead, it’s meant to take the available open-source layers and facilitate their adoption and repurposing into as broad an application set as possible. “A lot of the work we’re putting into Pavona has to do with the infrastructure and the architecture that connects all this stuff together,” Rizzo says, “so it becomes much more like Legos, so you can use it in one configuration for a small IoT device and in another configuration for some large data-center system-on-a-chip.”

Part of making the hardware components more modular is software. Rizzo and his team built what they call an architectural composition engine that serves as a wrapper around the hardware, allowing it to interact with different types of computing cores, be they ARM or RISC-V. This way, a company can integrate the open hardware into their existing architecture without changing the software stack.

Pavona begins with security chip OpenTitan

Pavona’s starting kit of open-hardware designs includes components of OpenTitan, a chip that provides a “hardware root-of-trust,” a chip-level source of security that serves as a foundation for all secure operations in a computer. They also include extensions of the OpenTitan design that incorporate efficient cryptography that’s safe against possible future attacks from a large-scale quantum computer.

According to OpenTitan’s proponents, security hardware benefits from openness more than other chips, because if anyone can inspect and verify the design, and there is an active community of people stress-testing the hardware, it can become more trustworthy, and therefore more secure. It also makes the process of proving compliance with various regulatory requirements more straightforward.

Rizzo is counting on three factors to drive adoption of these open-security chips. The first is the AI boom, which has caused a massive increase in demand for chips of all kinds, not only the GPUs but also less well-known components like networking cards, monitors, and more. The second is the regulatory push toward transitioning to postquantum security, which both the U.S. and European governments have legislated to happen by the end of 2030. And third is new regulatory requirements in the European Cyber Resilience Act, which adds new security verification and reporting requirements for products sold in the European market.

“I think those three things together are all driving people in this direction of using secure, open-source silicon,” Rizzo says.

Security hardware may be just the beginning. Pavona is designed to make it as easy as possible to pull in new hardware modules. One need not be a paying member of Pavona to contribute new designs. “We absolutely are rejecting gatekeeping,” Rizzo says.

To increase trust from both individual contributors and large companies, Rizzo and his team developed a governance structure based on large open-source projects from the software world, such as Yocto. Contributing-member companies get representation on Pavona’s governing board. However, an independent technical committee makes the high-level technical decisions. This separation of managerial and technical oversight is meant to increase trust and transparency. “People get very discouraged when they feel like, ‘Hey, I made a contribution, and then someone made a decision in a hallway somewhere and told us later.’ So this is more consensus based, it’s more discussion based. And so those discussions have to be open,” Rizzo says.

Frank Nagle, the Linux Foundation’s advising chief economist and a research scientist at MIT, says compliance with standards and transparent governance are the keys to adoption of open-source technologies. “Having that type of structure in place will hopefully give it a fighting chance and allow it to reach scale, without people being concerned that it’s controlled by any one company.”

Pavona’s architectural-composition engine allows hardware to interact with different types of computing cores, so a company can integrate open hardware into its existing architecture without changing the software stack.Dominic Rizzo

The open-hardware future

Nagle argues that an underappreciated benefit of open source is that it allows private companies to work together, collaborating on core technology while still competing on specialized implementations.

“My favorite example of this I heard from a car manufacturer,” Nagle says. “The seat in your car has a little button that slides your seat backward and forward. Nobody’s buying one car rather than another car because that little toggle is better. But if you didn’t have one of those in your car, then somebody might not buy your car.”

Many technologies fall into the same category as the car seat’s button—technologies that are necessary but not a differentiator of the product. Security chips are a great example: Every piece of hardware needs security; however, few have it as their main function. These are the parts that benefit from open source, Nagle explains.

Collaborating on such hardware may enable cost savings for chip manufacturers and their customers, making the AI boom more economically sustainable.

Perhaps even more important, open sourcing some hardware development can lower the barrier to entry for new people to enter the field. To aid in this quest, Pavona also provides multiple “getting started” guides, software emulation tools, and FPGA code that anyone can download onto a board and get up and running in under 10 minutes.

“I want to get more people involved,” says bunnie Huang. “Particularly young people, particularly new people. Because we need a more robust ecosystem, more new ideas to ensure that we have the ability to maintain these technologies we depend upon.”

Darwesh Singh thinks Nvidia has a weakness.

The last decade of Nvidia’s history was among the most consequential stories in technology ever. The company’s stock price has increased over 200-fold since 2016, and deployed Nvidia AI compute capacity has surged to 225 times greater than the first quarter of 2021, according to data tracked by Epoch AI.

Yet Nvidia may in some ways be a victim of its own success. Its dominance in AI has led to GPU designs that prioritize tensor units and low precision math. These decisions make sense for AI, but less so for some creative, scientific, and industrial work.

Singh’s five-year-old startup, Bolt Graphics, sees an opportunity to build a GPU specifically for these use cases. Jill Mueller, Bolt’s chief marketing officer, puts it bluntly. Nvidia has “a fundamental lack of understanding of their customer,” she says. “They just throw stuff at you, and there you go.”

Bolt aims for this potential weak spot with Zeus, a GPU that will be sold as both a PCIe (peripheral component interconnect express) card for desktop workstations and, for those who require more performance, a rack-mountable server containing four Zeus GPUs (for up to 96 per rack).

While Nvidia goes low-precision, Bolt goes high

Jacob Feldgoise, senior data research analyst at Georgetown University’s Center for Security and Emerging Technology, has also noticed a shift in Nvidia’s recent hardware.

“AI is sucking the computational units used for high-precision workloads out of that hardware,” he says. “If you look at Nvidia’s highest performance GPUs, generation to generation, a greater share of the hardware has been allocated to low-precision compute, as opposed to high-precision compute, which is generally needed for scientific computing.”

Precision refers to how many bits a GPU uses to represent each number. High-precision formats like FP64 (64-bit floating point) preserve more digits and a wider range, while FP16 and INT8 sacrifice precision for speed. Recently, Nvidia introduced a new 4-bit number format, NVFP4, to accelerate AI workloads, which generally tolerate low-precision math.

But some tasks require precision. Singh cited geographical information systems, such as Esri’s ArcGIS, as an example. When rendering the planet on a GPU, low-precision arithmetic applied to large coordinate values can introduce errors that cause objects to drift.

Because Zeus, unlike so many other GPUs, is not designed primarily for AI, its design makes FP64-native vector cores a focus and allocates a large share of silicon to them.

“[Nvidia and AMD] make a conscious trade-off to allocate more die space to matrix multiplication and tensor units and less towards fixed function hardware,” Singh says. ”We decided to allocate the die space a bit differently.”

Rasterization is out, path tracing is in

A focus on FP64 isn’t the only way Bolt differs from the norm. Zeus is also built to render graphics with path tracing instead of rasterization.

Rasterization is the traditional method of high-performance 3D rendering. It projects 3D triangles onto a pixel grid and uses mathematical abstractions to determine the correct color for each pixel. Path tracing instead does the equivalent of shooting rays from a camera to simulate how light should bounce and interact. It delivers more accurate lighting but is computationally expensive.

As with high-precision math, Bolt believes it can find an edge by placing more emphasis on path tracing than do today’s GPUs. Rasterization is supported by Zeus but significantly scaled back; Singh estimates that Zeus’s raster performance is about half that of a comparable Nvidia card.

Bolt’s fresh arrival to the GPU arena also allows the company to take a clean sheet approach unburdened by legacy support. This differs from Nvidia and AMD, which must integrate path tracing alongside rasterization in a way that can support numerous existing applications and application programming interfaces (APIs).

Bolt claims that a server rack with 28 Zeus GPUs will deliver real-time path traced performance equivalent to 280 Nvidia RTX 5090 GPUs. The aim is for this configuration of Zeus hardware to support real-time path tracing that simulates up to 20 “bounces”—a reflection or collision of the simulated light—at 4K resolution and 30 frames per second. This is a high degree of accuracy required for professional rendering workloads; for comparison, even the most graphically attractive path traced games simulate just a few bounces.

Can a startup really launch a new GPU?

There’s a logic to Bolt’s approach. Nvidia and AMD are focused on AI, but GPUs are still useful for many tasks besides AI. However, Bolt will need to overcome two key technical hurdles.

The first is production. Cutting-edge silicon production is in short supply, and leaders like Nvidia have most leading-edge production capacity tied up. The Zeus GPU will instead be fabricated on TSMC’s older N5 process node. Bolt is betting that an older process node will keep Zeus competitive with Nvidia on price.

Bolt may also find it challenging to convince users that an unproven GPU is a safe bet. Driver support for software is always a headache in the GPU arena—just ask Intel—and the use cases that might benefit Zeus’s high precision and path tracing will also require reliable drivers.

Bolt plans to address this by launching with support only for specific applications. “We know that PC gaming is a huge segment,” Singh says. “But our approach is we want to target professional, creative, and high-performance compute first.” The company is working with software companies including Blender, Autodesk, and SideFX.

Bolt announced the tape-out of the first Zeus test chips on 22 April 2026, and it is now focused on bringing the GPU to production by the fourth quarter of 2027.

This article appears in the July 2026 print issue as “Bolt Wants to Put the Graphics Back Into GPUs.”

Want to know what the next 10 years of Moore’s Law is going to look like? Maybe the next 15? The Belgium-based nanotech research institution Imec revealed its updated roadmap this week at its annual technology forum, ITF, and it points to a challenging road ahead for chip manufacturers.

The next evolution in CMOS transistors, the kind in almost all chips on the planet, will be the complementary field-effect transistor (CFET), and Imec predicts its commercial introduction will begin around 2033.

Imec's Roadmap

Imec’s new roadmap shows a change in the structure of transistors starting at the A7 node around 2033. Here’s a guide to reading the roadmap.

A7: What industry calls the “7 Angstrom” process node. It’s just a name; there’s not necessarily any structure in the transistor that is actually 7 Angstroms.

CPP: Contacted poly pitch is the shorthand for the distance in nanometers from one transistor to another.

Cell: Cell height is the smallest dimension of a logic cell in nanometers.

4.5T: The number of parallel interconnects (tracks) fitting within the smallest logic cell.

0.55NA EUV: EUV lithography using a higher numerical aperture (0.55), meaning it can print finer features than today’s 0.33NA machines.

MP: This is the minimum pitch, the distance from one line to another, that EUV can produce.

Further out, Imec expects another transition in transistor technology, this one driven more by power reduction than squeezing more devices onto a chip. In 2041, chipmakers may replace the main silicon part of the transistor, the channel region, with two-dimensional semiconductors. These are materials, such as molybdenum disulfide, that act as semiconductors even though they are only a single atomic layer thick.

Yes, 15 years is a very long time in an industry as fast moving as semiconductors. Imec’s projections extend so far out because of the role of its research in the semiconductor industry, says Paul Heremans, the organization’s chief technology officer. “Our research programs do de-risking of technology options,” he says. That is, they explore the costs and benefits of different choices with the aim of narrowing the field for chipmakers. “We have to be really well ahead of the time of the introduction of such technology into a real product, because after our de-risking work, there is still a lot of engineering and development work to get these technologies into production,” he says.

With de-risking as the goal, much of Imec’s focus right now is on what’s coming in 2033, and that’s the CFET.

So Many Choices for CFETs

The CFET is an attempt to build two transistors in the space of one. The CMOS logic that’s run computing for decades relies on two types of transistors—one called PMOS (p-channel metal-oxide semiconductor), the other NMOS (negative-channel metal-oxide semiconductor). They function so that the same input signal will cause one to switch on and the other to switch off, which helps foster relatively efficient operation. Today they are built in pairs side by side. CFETs would stack them on top of each other, which would be as good as halving the area of some circuits, according to proponents.

The likely path to the CFET builds both transistors at once, instead of one after another or building them on separate wafers and then somehow fusing them together. That starts by depositing multiple alternating layers of silicon and silicon-germanium onto a silicon wafer. After trenches and other features are carved through those layers, etchants that destroy silicon-germanium (but not silicon) are deployed to leave a set of suspended stack, nanometers-thick silicon ribbons. The top set of those ribbons, called nanosheets, become the PMOS transistor, and the bottom set becomes the NMOS, or vice versa.

RELATED: 3D-Stacked CMOS Takes Moore’s Law to New Heights

The world’s largest chipmakers—Intel, Samsung, and TSMC—are now working to make CFET-based chips manufacturable. Each of them have constructed prototype CFET chips. TSMC used its devices to build a super compact memory cell and a key test circuit called a ring oscillator, company engineers announced last December at the IEEE International Electron Devices Meeting. In June, at the IEEE VLSI Symposium, Samsung will detail a CFET that is simultaneously the smallest yet and made with the most layers of nanosheets (six in total).

RELATED: The Transistor of 2047: Expert Predictions

Nevertheless, how best to make CFETs is far from settled. “It is very clear that there are many versions still open,” Heremans says. For example, Imec has been developing new ways to better electrically separate the top and bottom transistor from each other, so they can work independently. The process that would make that possible is complicated. The silicon and silicon-germanium layers that will become the top transistor would be made on an entirely different silicon wafer. The two wafers are then bonded together in a way that leaves only the silicon and silicon-germanium layers from the top wafer attached to the bottom wafer. The process also leaves an extra layer of insulation between the material from the top wafer and the bottom wafer, providing the needed electrical isolation.

As difficult as that might seem, it could also help solve a mismatch in the speed of charge through PMOS and NMOS. Today’s chips use silicon wafers that are sliced along a crystal plane that favors conduction in NMOS. But if the PMOS layers are made on a separate wafer, that wafer could be cut to favor those devices. Intel is testing that scheme right now and will report the results of that work in June at the IEEE VLSI Symposium.

2D semiconductors in 15 years?

Imec expects CFETs to follow a similar evolution to other recent technology introductions, such as the FinFET (fin field-effect transistor) 15 years ago, and the nanosheet transistor, which is entering commercial products now. That is, an initial launch, then an effort to boost the density and performance, and finally a push to squeeze a bit more performance or power efficiency out of the dense version.

After that, probably around 2041, Imec expects industry to swap the silicon in CFETs for something new, such as one or more types of 2D semiconductors. Unlike with the move to CFETs, 2D semiconductors would mostly be about improving power consumption.

RELATED: 2D Transistors Could Come Sooner Than You Think

“The general goal of continuing the roadmap is, of course, to propose technologies that will increase the operation per watt that you can generate,” Heremans says. In advanced chips, a small reduction in voltage has an outsized effect on reducing power.

That’s where 2D could come in. 2D semiconductors are less than a nanometer thick, compared to the 3 nanometers of a future silicon nanosheet, Heremans points out. The transistor’s gate, which wraps around the channel region, could therefore use less voltage to control the flow of current through such a thin structure in comparison with the thicker silicon nanosheet. 2D CFETs could get a further efficiency boost if industry selects a semiconductor through which charge flows faster, Heremans suggests.

Interconnects, packaging, and CMOS 2.0

If CFETs arrive when Imec says they will, they’ll drop into an industry that’s already thinking in 3D. Intel has already moved power-delivering interconnects beneath the layer of silicon transistors on a chip, and with the CFET’s complicated connections, some data signals may have to move there as well.

Just as important, by 2033, chip companies will have more than a decade of experience stacking one chip atop another to increase the total amount of silicon in a processor. For example, in an AMD MI300 GPU, “compute tiles” made using the most advanced processes are stacked atop another die made using an older process that handles the GPU’s memory and communications.

The vertical connections in the AMD chip can be separated by as little as 9 micrometers. And that spacing is decreasing rapidly. “Today our most advanced wafer-to-wafer bonding technologies [in development] allow a pitch of about 200 nanometers,” Heremans says. “That means over 1 millimeter square, we’re talking about 25 million interconnects.”

RELATED: Hybrid Bonding Plays Starring Role in 3D Chips

That kind of density means that designers can start to build logic circuits in 3D dies,” Heremans says. Such an ability would lead to an evolution in chip design that Imec calls CMOS 2.0. In that scheme, not only can multiple chips made with different technologies be stacked together but individual chips can be made by fusing together layers of transistors, each optimized for a specific function such as memory density or driving current. “That gives you an enormous boost in what you can expect from this kind of fused chip,” he says.

This article appears in the July 2026 print issue as “The Next 15 Years of Moore’s Law.”

This sponsored article is brought to you by Applied Materials.

At pivotal moments in history, progress has required more than individual brilliance. The most consequential breakthroughs — such as those achieved under the Human Genome Project — required a new operating paradigm: Concentrate the world’s best talent around a single mission, establish a common platform, share critical infrastructure, and collapse feedback loops. When stakes are high and timelines are compressed, sequential and siloed innovation simply cannot keep pace.

Today’s AI era is creating an engineering race with similar demands. Every company is pushing to deliver higher-performance AI systems, faster. But performance is no longer defined by compute alone. AI workloads are increasingly dominated by the movement of data: In many cases, moving bits consumes as much — or more — energy than compute itself. As a result, reducing energy per bit can extend system‑level performance alongside gains in peak compute.

The path to energy‑efficient AI therefore runs through system‑level engineering, spanning three tightly interconnected domains:

• Logic, where performance per watt depends on efficient transistor switching, low‑loss power, and signal delivery through dense wiring stacks.
• Memory, where surging bandwidth and capacity demands expose the memory wall, with processor capability advancing faster than memory access.
• Advanced packaging, where 3D integration, chiplet architectures, and high‑density interconnects bring compute and memory closer together — enabling system designs monolithic scaling can no longer sustain.

These domains can no longer be optimized independently. Gains in logic efficiency stall without sufficient memory bandwidth. Advances in memory bandwidth fall short if packaging cannot deliver proximity within thermal and mechanical constraints. Packaging, in turn, is constrained by the precision of both front‑end device fabrication and back‑end integration processes.

In the angstrom era, the hardest problems arise at the boundaries — between compute and memory in the package, front‑end and back‑end integration, and the tightly coupled process steps needed for precise 3D fabrication. And it is precisely this boundary‑driven complexity where the traditional innovation model breaks down.

The Traditional R&D Workflow Is Too Slow for Angstrom‑Era AI

For decades, the semiconductor industry’s R&D model has resembled a relay race. Capabilities are developed in one part of the ecosystem, handed off downstream through integration and manufacturing, evaluated by chip and system designers, and only then fed back for the next iteration. That model worked when progress was dominated by relatively modular steps that could be scaled independently and simply dropped into the manufacturing flow.

But the AI timeline has upended these rules. At angstrom‑scale dimensions, the physics enforces inescapable coupling across the entire stack: materials choices shape integration schemes; integration defines design rules; design rules dictate power delivery; wiring sets thermal budgets; and thermals ultimately constrain packaging scaling. System architects simply cannot wait 10–15 years for each major semiconductor technology inflection to mature.

Representing a roughly $5 billion investment, EPIC is the largest commitment to advanced semiconductor equipment R&D in U.S. history.

A long‑term perspective is essential to align materials innovation with emerging device architectures — and to develop the tools and processes required to integrate both with manufacturable precision. At Applied Materials, together with our customers, we are charting a course across the next 3–4 generations, extending as far as 10 years down the roadmap.

The angstrom era demands that we break down silos and bring together the industry’s best minds — from leading companies to leading academic institutions. If the problem is coupled, the solution must be coupled. If the timeline is compressed, the learning loop must be compressed. It’s not enough to just innovate — we must innovate how we innovate.

EPIC: A Center and Platform for High‑Velocity Co‑Innovation

This is the challenge that Applied Materials EPIC Center is designed to solve.

Representing a roughly US $5 billion investment, EPIC is the largest commitment to advanced semiconductor equipment R&D in U.S. history. When it opens in 2026, it will deliver state‑of‑the‑art cleanroom capabilities built from the ground up to shorten the path from early‑stage research to full‑scale manufacturing. But the facilities are only one component of the model. EPIC is also a platform, an operating system for high-velocity co‑innovation that revolutionizes how ideas move from the lab to the fab.

EPIC is a platform, an operating system for high-velocity co‑innovation that revolutionizes how ideas move from the lab to the fab.Applied Materials

The EPIC model compresses the traditional workflow. Customer engineers work side‑by‑side with Applied technologists from day one — moving beyond isolated process optimization and downstream handoffs. Within a shared, secure environment, EPIC tightly integrates atomistic modeling, test vehicles, process development, validation, and metrology feedback. Constraints that once surfaced late in development are identified and addressed early.

The result is a potentially 2x faster path that benefits the entire ecosystem under one roof:

• Chipmakers gain earlier access to Applied’s R&D portfolio, faster learning cycles, and accelerated transfer of next‑generation technologies into high‑volume manufacturing.
• Ecosystem partners gain earlier access to advanced manufacturing technology and collaboration opportunities that expand what is possible through materials innovation.
• Academic institutions gain opportunities to strengthen the lab‑to‑fab pipeline and help develop future semiconductor talent.

Building on decades of co‑development, we are reinventing the innovation pipeline with our partners across logic, memory, and advanced packaging to deliver the next leap in energy‑efficient AI.

Accelerating Advanced Logic

Logic remains the engine of AI compute. In the angstrom era, however, system‑level gains are increasingly constrained by power and energy. Extending AI performance now depends on architectures that deliver more performance per watt — accelerating the move to 3D devices such as gate‑all‑around (GAA) transistors, which boost density within a compact footprint while preserving power efficiency.

These architectural shifts are unfolding at unprecedented scale, with the logic roadmap already extending beyond first‑generation GAA toward more advanced designs. One key example is GAA with backside power delivery, which relocates thick power lines to the backside of the wafer, reducing resistive losses and freeing front‑side routing for tighter logic cell integration. Another example brings adjacent GAA PMOS and NMOS transistors closer together while inserting a dielectric isolation wall between them to minimize electrical interference. Further out, complementary FETs (CFETs) push density scaling even more by stacking PMOS and NMOS devices directly atop one another.

While these architectures deliver compelling gains in performance per watt and logic density without relying solely on tighter lithography, they significantly raise integration complexity. Manufacturing a single GAA device today can involve more than 2,000 tightly interdependent process steps. At the same time, wiring stacks continue to grow taller and denser to connect these advanced logic devices. Modern leading‑edge GPUs now in development pack more than 300 billion transistors into an area little larger than a postage stamp, interconnected by over 2,000 miles of wiring.

At this level of complexity, the process steps used to create these precise 3D devices and wiring stacks cannot be optimized independently. Design and process must evolve in lockstep, and materials innovation and fabrication methods must advance alongside device architecture. EPIC’s co‑innovation model is designed to accelerate exactly this convergence — enabling logic compute to continue advancing the frontiers of AI at the pace the roadmap demands.

Powering the Memory Roadmap

At the same time, the AI computing era is fundamentally reshaping how data is generated, moved, and processed — making memory technologies, especially DRAM, central to delivering the energy‑efficient performance AI systems require. As models grow larger and more data‑hungry, the DRAM roadmap is shifting toward architectures that deliver higher density, greater bandwidth, and faster access per watt.

At the DRAM cell level, this shift is driving a transition from 6F² buried‑channel array transistors (BCAT) to more compact 4F² architectures, which orient the transistor vertically to boost density and reduce chip area. Looking beyond 4F², sustaining gains in performance per watt will require moving past what 2D scaling alone can deliver. The industry is therefore turning to 3D DRAM, stacking memory cells vertically to add capacity within a constrained footprint. As these structures grow taller and aspect ratios intensify, high-mobility materials engineering in three dimensions becomes increasingly critical to performance and reliability.

Beyond the memory cell array, another powerful lever for DRAM scaling is shrinking the peripheral circuitry, which includes logic transistors and interconnect wiring. One emerging approach places select periphery functions beneath the DRAM array by bonding two wafers — one optimized for the DRAM cells and the other for CMOS logic — using multiple wiring layers.

In parallel, DRAM performance is being extended by leveraging logic‑proven enhancers in the memory periphery. These include mobility boosters such as embedded silicon germanium and stress films, along with wiring upgrades like improved low‑k dielectrics and advanced copper interconnects. Memory manufacturers are also transitioning periphery transistors from planar devices to FinFET architectures, following the logic roadmap to further improve I/O speed. These valuable inflections are central to EPIC’s mission — where they can be co-developed and rapidly validated for next‑generation memory systems.

Driving System Scaling With Advanced Packaging

As data movement becomes the dominant energy cost in AI systems, advanced packaging has emerged as a critical lever for improving system‑level efficiency—shortening interconnect distances, increasing bandwidth density, and reducing the power required to move data between logic and memory.

High‑bandwidth memory (HBM) marks a major inflection along this path. By stacking DRAM dies — scaling to 16 layers and beyond — and placing memory much closer to the processor, HBM enables rapid access to ever‑larger working datasets. This delivers step‑function gains in both bandwidth and energy efficiency.

More broadly, the rise of 3D packages such as HBM underscores why advanced packaging is becoming central to the AI era. Packaging now addresses system‑level constraints that logic and memory device scaling alone can no longer overcome. It also enables a move away from monolithic systems‑on‑chip toward chiplet‑based architectures, as AI workloads increasingly demand flexible designs that combine logic, memory, and specialized accelerators optimized for specific tasks.

A vital technology powering this roadmap is hybrid bonding. With interconnect pitches approaching those of on‑chip wiring, conventional bumps and microbumps run into fundamental limits in density, power, and signal integrity. Hybrid bonding removes these barriers by allowing dramatically higher interconnect and I/O density, supporting a broad range of chiplet architectures — from memory stacking to tighter compute‑memory integration.

As bonded structures like HBM stacks grow larger and more complex, warpage control, die placement, stack alignment, and thermal management become first‑order challenges. EPIC tackles these and other high‑value advanced‑packaging challenges through early, parallel co‑innovation across materials, integration, and manufacturing.

Bringing It All Together

Across logic, memory, and advanced packaging, our industry faces an ambitious roadmap that promises significant gains in energy efficiency for AI systems. But realizing that potential demands breakthrough materials innovation at a time when feature sizes are shrinking, interfaces are multiplying, and process interdependencies are escalating. These challenges cannot be solved on 10–15‑year timelines under the traditional relay‑race model. We must break down silos, align earlier across the ecosystem, and parallelize learning to keep pace with AI’s demands.

In the AI era, progress will be defined by the speed at which lightbulb moments turn into manufacturing and commercialization reality. The only viable path forward is a new innovation model — and EPIC is how we are driving it.

This sponsored article is brought to you by Ampace.

As AI workloads grow to gigascale levels, the global data center industry has hit a hidden physical wall. The real bottleneck is no longer just the thermal limit of the chip or the capacity of the cooling system — it is the dynamic resilience of the power chain.

Modern AI computing clusters, driven by massive GPU clusters, generate high-frequency, abrupt, and synchronized spikey pulse loads. As rack densities soar beyond 100 kW, these fluctuations are amplified into a “power paradox”: while the digital logic of AI is moving faster than ever, the physical infrastructure supporting it remains tethered to legacy response capabilities.

The power usage of these gigascale sites and their drastic, high frequency, abrupt load surges from the AI GPU clusters can trigger transient voltage events and frequency instability, risking the entire local grid. The grid itself is not robust enough to support these loads. This leads to the infrastructure gap: The utility is not robust enough and traditional backup sources, such as diesel generators and gas turbines, simply cannot react to millisecond-level power spikes in output. This will often force operators into a cycle of costly infrastructure over sizing just to buffer the volatility.

AI infrastructure requires energy systems capable of instantaneous response while safeguarding continuity and reliability.

The industry has explored various mitigations — from rack-level BBUs to 800V DC architectures — yet the mature, high volume, traditional UPS system remains the most viable and scalable foundation for gigawatt-level facilities. Consequently, the UPS-integrated battery system has emerged as the critical “physical buffer” to neutralize these pulses at the source.

At Data Center World 2026 in Washington, D.C., Ampace led a pivotal technical dialogue with Eaton during the session “Powering Giga-scale AI.” Their exchange unveiled a fundamental paradigm shift: To bridge the AI power gap, energy storage must evolve from a passive insurance policy into an active, high-speed stabilizer. By aligning Ampace’s semi-solid-state battery innovation with Eaton’s proven system intelligence, we are moving beyond simple backup to solve the physical paradox of the AI era.

To move beyond simple backup and solve the physical paradox of the AI era, Ampace is aligning its semi-solid-state battery innovation with Eaton’s proven system intelligence.Ampace

The “Shock Absorber” physics: semi-solid chemistry for AI pulses

Conventional power systems were designed for steady-state loads, not the rapid heartbeat of a massive AI GPU cluster. When thousands of GPUs synchronize their computing cycles, they generate high-frequency, abrupt pulse loads that can lead to voltage sags, frequency oscillations, and potential interruptions of critical AI training.

Ampace’s PU Series semi-solid and low-electrolyte cells address this challenge by acting as high-speed “shock absorbers.” Leveraging ultra-low internal resistance (DCR) and high cycle capability, these batteries neutralize millisecond-level power spikes at the source, stabilizing the local power loop before disturbances propagate upstream to the grid or on-site generators. These high-rate cells enable 100 kW+ racks to maintain peak performance without transmitting instability across the power chain.

This capability aligns closely with Eaton’s matured UPS architectures, such as double-conversion topologies and advanced power electronics upgrades, which have long prioritized rapid load responsiveness and high system stability.

Together, these approaches embody a shared industry philosophy: AI infrastructure requires energy systems capable of instantaneous response while safeguarding continuity and reliability.

Ampace’s semi-solid state chemistry minimizes liquid electrolyte, greatly reducing the risk of leakage and thermal runaway under continuous AI high-load conditions.Ampace

Algorithmic intelligence: synchronizing energy and control

Hardware alone cannot solve the AI power paradox; the system also requires intelligent coordination between energy storage and power management. Sophisticated battery management systems (BMS) like Ampace’s high-precision design track state-of-charge (SOC) with high-speed sampling, even during rapid, shallow cycling typical in AI workloads.

Complementary algorithmic approaches in modern UPS platforms — such as ramp-rate control and average power management — effectively suppress sub-synchronous oscillations and optimize load smoothing. In large-scale AI training environments, where thousands of GPUs can trigger millisecond-level power pulses, these intelligent layers ensure that batteries buffer high-frequency fluctuations without compromising the mandatory emergency backup reserves.

By transforming energy storage from passive “standby insurance” into active, schedulable assets, the system simultaneously safeguards continuous AI training and maintains the long-term health of the data center infrastructure. In practical terms, this means that even during peak compute bursts, the infrastructure remains stable, training cycles continue uninterrupted, and operators avoid costly oversizing or grid stress.

Eaton’s dual-layer algorithms serve as a valuable benchmark in this space, demonstrating how advanced control logic can achieve similar objectives, reinforcing Ampace’s approach and philosophy within the broader data center power ecosystem.

Economic scalability: optimizing AI infrastructure efficiently

One of the largest costs in deploying AI infrastructure is “oversizing”: procuring transformers, generators, and UPS systems to handle brief peak spikes. This traditional approach inflates the Total Cost of Ownership (TCO) and leads to wasted capital on underutilized hardware.

Ampace’s turn-key cabinet design developed by its independent R&D is engineered for seamless compatibility with mature, high volume UPS systems. By leveraging Eaton’s double-conversion UPS topologies alongside intelligent ramp-rate and average power management algorithms, AI data centers can scale dynamically without requiring costly infrastructure redesigns. This approach allows the UPS and batteries to act as active load-shapers, smoothing AI-driven pulses while strictly maintaining mandatory emergency backup capacity.

By utilizing energy storage as an active, schedulable asset, operators can right-size their infrastructure, avoid unnecessary grid upgrades, and deploy gigascale AI clusters with unprecedented efficiency.

Safety First: Protecting AI Infrastructure While Enabling Innovation

In high-density AI facilities, safety is non-negotiable. Ampace’s semi-solid state chemistry minimizes liquid electrolyte, greatly reducing the risk of leakage and thermal runaway under continuous AI high-load conditions.

Ampace’s turn-key cabinet design developed by its independent R&D is engineered for seamless compatibility with mature, high volume UPS systems. Ampace

At the same time, Eaton’s UPS design emphasizes system-level energy scheduling that never sacrifices mandatory emergency backup reserves, ensuring thermal safety and uninterrupted operation.

This “safety-first” approach ensures that infrastructure can sustain aggressive performance targets without compromising the physical integrity of the facility. Coupled with over a decade of proven high-cycle life operation and design under shallow pulse conditions, these systems can extend operational lifespan, reduce replacement requirements, and provide operators with confidence that safety and reliability remain uncompromised as compute density continues to grow.

To remain the scalable backbone of AI data centers

As AI computing scales over the next two to three years, the industry will face stricter grid requirements and even more demanding pulse load characteristics. This evolution demands a forward-looking design philosophy that harmonizes UPS, battery, and grid compatibility.

Ampace views current low-electrolyte semi-solid technologies as the optimal transitional step toward a fully solid-state future — one that promises ultimate safety and performance.

Ampace remains committed to this long-term technological roadmap. We view current low-electrolyte semi-solid technologies as the optimal transitional step toward a fully solid-state future — one that promises ultimate safety and performance. Whether through rack-level BBU, integrated UPS systems, or containerized storage, the universal core of the AI era remains constant: high-speed response, long shallow-cycle life, and refined energy management.

By engaging in deep technical exchanges with Eaton and leading energy innovators, Ampace ensures that its solutions not only meet today’s AI pulse challenges but also harmonize with broader infrastructure strategies and shared industry best practices.

Ultimately, as traditional diesel generators gradually give way to diversified alternatives, the integrated UPS-plus-energy-storage system will become the fundamental infrastructure standard.

The dialogue has just begun. Ampace will continue to engage in strategic exchanges with global industrial automation leaders and digital energy pioneers, co-authoring the playbook for a safer, more efficient, and more resilient AI-ready world.