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In this project we are researching an increasingly popular trend -- stitching photos from standard digital cameras into 3D models. There is a lot of interesting work going on in this area. One you may have heard about is Microsoft's Photosynth, which is capable of searching the whole internet to find different people's photos of, say, the Roman Coliseum, and create a 3D model of it. Recent advances in computer visions algorithms to register and align 2D photos into a 3D space combined have made this possible, and more and more companies are creating tools based on this concept.

Our researchers at Intel Labs China are working to further advance this field. Why is Intel doing this? Two reasons, primarily. First, we need to understand emerging software algorithms in order to tune and adapt future Intel architectures to run them more efficiently and in a way that can be readily programmed. Second, because this lab is a center of expertise in computer vision research, and they have some ideas on how to make these algorithms run faster and with better visual results. Here's a demo of the work.

Why do we think this is an important capability? For one, in the labs we see the increasing popularity of online games like World of Warcraft and virtual worlds such as Second Life as the foreshadowing of a transition to a full 3D Internet. However, many barriers remain to making these experiences as appealing as, say, YouTube is today -- they need better graphics, more natural interfaces, and ways for people to create user-generated 3D content with the same facility that blogs are written and videos are edited.

Photo-based 3D content creation tools such as the one from Intel Labs China are one way to simplify content creation. Just snap some photos from different angles and you will be able to scan a real world object to put it into the real world. There are still some hurdles to overcome, such as reducing the polygon count (if you view the video you'll see the result is a very detailed mesh), animating the model, and neutralizing the real-world lighting present in the source photos. However, these appear to be tractable problems and a lot of institutions are working on them.

The result will be that, just as almost anyone can be a video editor today, almost anyone could become a 3D designer/animator in the future, using real world objects as a starting point and morphing them into cool avatars or simply pieces of 3D art. These tools are already becoming available for professional animators -- as they advance they will give these artists a new way of creating interesting, realistic visuals.

This is only one of the cool things happening in Intel Labs. I’ll blog about them regularly to share more new developments and how we think they could help to shape the future.

But, and that's what I found really interesting are the tech sessions which cover different topics being related to the parallel programming. There are dedicated sessions regarding this:

On Monday Tiberiu Covaci will talk about "Is the future of programming a parallel one?" He will find out which chip manufacturer drive the multicore market.

On Tuesday Tiberiu will have another session with the title "Why should you care about Multi-core programming". If you are familiar with all our blog posts I'm sure you can tell the answer right away!

Tiberiu is really a busy guy as on Wednesday he will climb the stage again and present "The Future of Parallel Programming". I'm sure this man is worth getting him interviewed after one of his sessions (or beforehand).

Thank god there are other presenters who are familiar with the parallel stuff. Like Anthony Howcroft who will talk on Wednesday about "Microsoft SQL Server Project Code Name "Madison". Madison is MPP which stands for Massively Parallel Processing. Got it?!

On Wednesday our dear old friend Steve has his session with the title "Parallel Computing for Managed Developers". This sounds like real fun.

So, if you wanna learn more about parallel computing at Microsoft Tech-Ed Europe 2009 you should go to Berlin next week - or watch this space for more parallel information yet to come!

Years ago I worked on a product called InfoCentral.  It was a wonderful database that gave as much power to the connections as the objects the connections were between.  You could manage your connections, including possibly multiple connections of different types between objects.  It gave you the ability to realistically map life’s complex realities into a software metaphor.  I really enjoyed that program and have been unable to find anything even close to its power in the years since.  Hopefully something like that can evolve from the successful roots of Facebook.

Currently there’s a way to avoid seeing news from specific people posted to your main page, but even that nice start needs to be improved.  Here are a couple of suggestions that would really help in connection management.

1.      Be able to prioritize, perhaps with as few as 3 levels you could group people into for news you would rather see first… priority level A, B and C.

2.      Be able to block anything having to do with, showing or related to specific individuals (without them knowing)

3.      Be able to “drop” someone from your relationships and yet have them continue to think its still there.  A stealth mode.  Someone you don’t want to offend but perhaps this relative posts updates a little too frequently for your tastes.

Small changes add up to big differences in what you see and experience when using social networking software.

If you are going to the event next week in Berlin then let me know about it. Maybe we can meet face to face and if there are enough of us perhaps even a gourp community meeting. This can be a good opportunity to meet the experts.

In any case, you are all welcome to join my session titled "Parallel Programming for Embedded". I will be presenting on Friday 10:45 - 12:00.

At the basis of this presentation is the fact that the hardware has always been parallel. This also caused the kernel drivers to live in a parallel environment, so even though embedded devices were late to adopt Multi-Core CPUs, the people who are working with the lower levels have always been working in parallel environments.

The session speaks of parallel systems in general side by side with embedded systems and infrastructure environemnts.

The goal of this session is to open the eyes and show the systems that have always been working in parallel and name the principles used with these systems.

You can read my previous blogs to learn more about this approach. For example these:

is dos the ideal parallel environment part iv

stateful programming a case study

Here are a few slides from this presentation.

Parallel Programming for Embedded TechEd 2009

USB Ping Pong

Hope to see you all there,
Asaf

The error consists in the fact that every parallel thread has its own seed and if no special initialization is carried out, rand() function will return the same value in all the threads. Most likely, this will not be the required result.

Note: seed is initial value given to the random sequence generator in order to obtain the first random number. If you assign seed a particular value, the numbers sequence will always repeat starting with this very number.

The following code example is given at the forum:

void initMatrix(int** m, int H, int W)
{
  #pragma omp parallel
  {
    #pragma omp for
    for (int i = 0; i < H; ++i)
      for (int j = 0; j < W; ++j)
         m[i][j] = rand()%15;
  }
}

The result of such code work is filling of matrix with repeating blocks of numbers. For example, a 10×10 matrix filled in in two threads can look as follows:

As we can see, the upper and the lower parts of the matrix filled in in two different threads are the same.

In order to avoid the same rand() function behavior, in your code, you should initialize random numbers generator in each parallel thread with various values. To do this, the combination of current time from the current thread number can be used.

The corrected code will look as follows:

void initMatrix(int** m, int H, int W)
{
  #pragma omp parallel
  {
    srand(int(time(NULL)) ^ omp_get_thread_num());
    #pragma omp for
    for (int i = 0; i < H; ++i)
      for (int j = 0; j < W; ++j)
        m[i][j] = rand()%15;
  }
}

You can use exceptions inside parallel regions. But they mustn't leave these parallel regions. Exceptions should be caught and processed inside a parallel region by using try/catch. If the exception leaves the parallel region it will cause fail and most surely program crash. Let's consider an example of incorrect code:

#pragma omp parallel for num_threads(4)
for(int i = 0; i < 4; i++)
{
  //...
  throw 1;
}

This code is incorrect as exceptions will leave the parallel region. To avoid this you should use other mechanisms for transferring information about error occurring. For example, the code may be rewritten as follows:

size_t errCount = 0;
#pragma omp parallel for num_threads(4) reduction(+: errCount)
for(int i = 0; i < 4; i++)
{
  try {
    //...
    throw 1;
  }
  catch (...)
  {
    ++errCount;
  }
}
if (errCount != 0)
  throw 1;

It looks a bit complicated but if you need to use exceptions inside parallel regions, there is no other way and you'll have to create a mechanism like this. But certainly, it's better to try to avoid exceptions.

There is some difficulty in that an exception may call not only your code in which you'll write throw. Exceptions can be generated in functions you use or memory allocating operators as well. Let's consider the following example which at first sight looks safe:

#pragma omp parallel for num_threads(4)
for(int i = 0; i < 4; i++)
{
  float *ptr = new float[10000];
  delete [] ptr;
}

This code can work safely for years and it can cause a program crash if at some moment 'new' operator cannot allocate the needed memory size. According to C++ standard new operator throws std::bad_alloc exception if it cannot allocate the needed memory size. This approach allows us not to check if the necessary memory size has been allocated as we do when using malloc function, and begin to work with it immediately. If memory is not allocated the program will proccess this situation in the necessary place. In case of a parallel region we need some additional work to correctly process the error of memory allocation inside the region itself. This is the corrected example:

#pragma omp parallel for num_threads(4) reduction(+: errCount)
for(int i = 0; i < 4; i++)
{
  try {
    float *ptr = new float[10000];
    delete [] ptr;
  }
  catch (std::bad_alloc &)
  {
    //process error
  }
}

I think you've already guessed that using functions inside parallel sections is also an unsafe and thankless task. Either you are sure that the functions don't generate exceptions or wrap them in try/catch. An unpleasant thing here is that if by the moment of writing parallel code the functions used in it haven't generated an exception, this can change later and you should be very careful.

Summarizing the information, we can say that exceptions are a thing which you should always keep in mind when developing a program using OpenMP. To simplify programmers' life we added three new diagnostic messages into VivaMP which will help you detect errors relating to using exceptions:

V1301. The 'throw' keyword cannot be used outside of a try..catch block in a parallel section

V1302. The 'new' operator cannot be used outside of a try..catch block in a parallel section.

V1303. The FOO function which throws an exception cannot be
used in a parallel section outside of a try..catch block.

V1301 diagnostic message indicates the error in the first example while V1302 diagnoses errors of calling 'new' operator outside the exception handler. V1303 is much more complicated. Now VivaMP will warn only about call of functions explicitly marked as throwing exceptions, i.e.:

void MyThrowFoo() throw(...) { }

Functions not marked with can also throw exceptions but they are not considered unsafe. This step is made deliberately to reduce the number of unnecessary warning messages. Otherwise any function call inside the parallel section not screened with try/catch will be unsafe. Although it is really so, it seems that there is little help from such a large number of diagnostic messages. But perhaps VivaMP analyzer will behave in this way in future in "pedantic mode". And in that case functions marked explicitly as not throwing exceptions will be considered safe:

void MyNotThrowFoo() throw() { }

The last thing I would like to say about exceptions in parallel regions is that you should be careful when using barriers. Let's consider the following example:

#pragma omp parallel num_threads (4)
{
  try {
     if (omp_get_thread_num ()  ==  0) {
       throw CException();
     }
     #pragma omp barrier
  }
  catch(CException &) {
  }
}

When an exception is generated one of the threads will "skip" barrier directive and after that a hang will occur. The other threads will eternally wait for the thread in which the exception occurred. Perhaps, in the next version of the analyzer search of the corresponding errors will be added, but at present there are some difficulties of technical character relating to this.

Additional resources:

• Blog. Michael Suess. Breaking Out of Loops in OpenMP.
• Blog. Michael Suess. Making Exceptions Work with OpenMP - Some Tiny Workarounds.
• Blog. Michael Suess. Exceptions in OpenMP and C++ - what's the state of affairs today?
• Wikipedia. Exception handling.

This time my attention was attracted by a message in RSDN "Alignment on 64-bit architectures" running as follows:

Today I have faced a problem in Linux. There is a data structure consisting of several fields: 64-bit double, 8 unsigned char and one 32-bit int. Altogether it is 20 bytes (8 + 8*1 + 4). On 32-bit systems sizeof is 20 bytes and everything is OK. But on the 64-bit Linux sizeof returns 24 bytes. That is, an alignment at the 64-bit border takes place.

After that the author dwells upon data compatibility and asks for advice how to pack data in the structure. But at the moment we are not interested in this. What we are interested in is that there is a new type of errors which can occur when porting applications on a 64-bit system.

It is clear and common that when sizes of fields in a structure change, the size of the structure itself changes too because of this. But this is a different case. The size of the fields remains the same but the size of the structure will change too due to different alignment rules. This behavior can lead to various errors, for example, incompatibility of the formats of the data being saved.

Linux systems are not supported by Viva64 yet, but I decided to find out if such an error can occur in Windows systems. For this purpose I took an example of the code printing types' sizes and alignment from the article "C++ data alignment and portability". I've modified it a bit for Visual Studio and got this program:

#include <iostream>
using namespace std;

template <typename T>
void print (char const* name)
{
  cerr << name
       << " sizeof = " << sizeof (T)
       << " alignof = " << __alignof (T)
       << endl;
}

int _tmain(int, _TCHAR *[])
{
  print<bool>        ("bool          ");
  print<wchar_t>     ("wchar_t       ");
  print<short>       ("short int     ");
  print<int>         ("int           ");
  print<long>        ("long int      ");
  print<long long>   ("long long int ");
  print<float>       ("float         ");
  print<double>      ("double        ");
  print<long double> ("long double   ");
  print<void*>       ("void*         ");
}

I compared the data I'd got with the data described in the article "C++ data alignment and portability" for GNU/Linux systems and now give them in Table 1.

Table 1. Types' sizes and alignment.

Let's study this table. Pay attention to the marked cells relating to long int and double. These types' sizes don't depend on the architecture's size and therefore don't change. Both on 32-bit and 64-bit systems their size is 8 byte. But alignment is different for 32-bit and 64-bit systems. It can cause change of the structure's size. When we implement Viva64 for Linux we'll take into consideration the possible errors relating to this.

In Windows systems, there are no such problems with alignment change. Pay attention that alignment of all the types doesn't change or changes together with the type's size. That is good - Windows developers have one potential problem off.

I thought that I would post this since one of my co-workers at Cadence will be gave a webinar on his experience parallelizing an existing application. The application and algorithms involved are really complex. It was especially interesting because it involves legacy code and also the development environment was Windows unlike many EDA applications which run on Linux/Unix. I really recommending watching.

Tom

October 27: John Schiavone, Cadence Design Systems: Real World Parallelism: Refactoring Legacy Code and Implementing Concurrency Cadence Allegro's complex Design Rules Checking (DCR) process is used to verify that designs meet constraint requirements. Development is currently underway to improve the performance of the DRC process using multithreading. View the design architecture and learn about the challenges faced in refactoring the legacy code, achieving platform independence, and performance verification.Link to John's Webinar

The activities put students in the place of procesor cores and had them perform tasks in parallel. These activities proved to be popular among many of the students at the camp, however, some of the more advanced students did express that they felt the exercsies could seem childish.

My personal observation is that these exercises laid an excellent foundation that was built upon later with actual computer lab activites using OpenMP and Threading Building Blocks.

The activities are best done in groups of 4 or 5 individuals but even two in a single group can.

Without further ado - here is my promised write up:

Thinking Parallel

These role playing activities are designed to get you start thinking in parallel. They will also expose you to some terminology & concepts that we will use throughout the rest of the boot-camp. Many of these exercises were inspired from Chapter two if James Reinders’ book “Intel Threading Building Blocks”.

Objectives
The objectives for the following five exercises are to:
1) Explore domain & task decomposition using a mailer example.
2) Learn about race conditions and two ways to mitigate them.
3) Learn what a critical section does
4) How a reduction can eliminate a race condition.

Activity 1 – Explore Domain Decomposition

In this activity, each member of your team or group will play the role of a processor core, or more accurately, the role of a thread executing code on a core. Your team will explore how to use domain decomposition to accomplish the job of folding, stuffing, sealing, addressing, stamping & mailing multiple envelopes.

Time Required
fifteen minutes

Objective
Use scrap paper, some empty envelopes, and a pencil to explore the concept of parallelism
through domain decomposition.

Materials
1) 16 envelopes per table of 4 to 5 “processors”
2) 32 colored post-it notes (16 to represent stamps, 16 to represent address labels)
3) Pens or pencils

Setup
1) Divvy up the 16 envelopes & colored post-its so that each process gets a roughly equal share
2) Each “processor” (think student) must read over and become familiar with the “code” or instructions she is to execute so that the “code” is committed to memory.
Here is your “code” of instructions – For Domain decomposition – each processor does the same task but uses different data (represented here by different addresses)
a) Fold scrap paper
b) Stuff paper into envelop
c) Pretend to seal envelope (so we can re-use them later)
d) Address an “address label” and fix it to the middle of the envelope
You may use these fictitious addresses if you cannot come up with 16 of your own:

e) Fix another post-it (representing a stamp) to the stamp area of the envelope
f) Place envelope in table area designated “the mail box”

Monitor Time for completion of mailer exercise
1) Have someone on the team write down the time just prior to saying go
2) Each “processor” should complete his assigned set of envelopes as quickly as possible.
3) Record the time to complete the assigned mailer job. Time: _____________________
4) Record any observations about the nature of the tasks you do – which ones take longest, which one are fast? Were any processors idle for periods of time?

Activity 2 – Explore Task Decomposition

In this activity, your team will explore how to use a task decomposition to accomplish the job of folding, stuffing, sealing, addressing, stamping & mailing multiple envelopes.

Time Required
fifteen minutes

Objective
Use scrap paper, some empty envelopes, and a pencil to explore the concept of parallelism
through task decomposition.

Materials
1) 16 envelopes per table of 4 to 5 “processors”
2) 32 colored post-it notes (16 to represent stamps, 16 to represent address labels)
3) Pens or pencils

Setup
1) Divvy up the 16 envelopes & colored post-its so that each process gets a roughly equal share
a) Each “processor” will agree with team ahead of time which task or tasks he/she is committed
to accomplishing. Perhaps, one processor is assigned the tasks of Folding, Stuffing, Pretend
Sealing all the envelopes.
b) Another processor, or perhaps even two, are assigned the task of addressing the envelopes
Use same addresses as before
c) Another processor is assigned the role of stamping and mailing the envelopes

Monitor Time for completion of mailer exercise
1) Have someone on the team write down the time just prior to saying go
2) Each “processor” should complete his assigned tasks as quickly as possible.
3) Record the time to complete the assigned mailer job. Time: _____________________
4) Record any observations about the nature of the tasks you do – which ones take longest, which one are fast? Were any processors idle for periods of time?

Activity 3 –Vector Addition exposes race conditions

In this activity, your team will explore how to use a domain decomposition to accomplish the job of (mis)adding a set of numbers which we will call a vector. The activity exposes the problem that occurs when writes to a shared memory variable are not protected by a synchronization construct.

Time Required
fifteen minutes

Objective
Use some index cards, and pencils to explore the concept of a race condition.

Materials
1) 16 numbered index cards.
2) One index card labeled “Shared Sum”
3) 16 extra index cards are labeled “local memory”
4) Pencils

Setup
1) The 16 numbered index cards represent a vector of length 16 elements. These are divvied up roughly equally among all 4 to 5 “processors”
2) One extra index card is labeled “Shared Sum” and has the value 0 written on it and is placed in the middle of the table accessible to all processors
3) Several extra index cards are labeled “local memory” and are given to each processor as a scratch pad to add number on.

Execution
1) This is a domain decomposition exercise, where each processor “reads” the value of the “shared sum” and writes a new value to this shared sum – ignoring all the other processors previously written values – this is called a race condition.
Each processor should do these steps as quickly as possible:
a) “read” the value of the “shared sum” and writes that number on your own scratch pad.
b) add one of your “vector” card’s values to the sum on your scratch pad.
c) Immediately cross off the current value on the “shared sum” card and write your own value on the card (probably stomping over someone else’s value).
d) Repeat steps 5a – 5c until you are out of index cards
2) Compare the final value written on the “shared sum” with the known total (46)
3) Did your team compute the correct grand total for the vector sum?

Activity 4 –Vector Addition fixed with critical section

In this activity, your team will explore how a critical section can be used to guarantee that access to a shared memory region are protected – in other words, that writes to a shared variable are done in an orderly and synchronized fashion. It will also expose the performance penalty that can be taken as a result of critical sections.

Time Required
Fifteen minutes

Objective
Use some index cards, a magic marker & pencils to explore the concept of a critical section

Materials
1) 16 numbered index cards (we call it our vector)
2) 1 index card labeled “Shared Sum”
3) 16 extra index cards are labeled “local memory”
4) Magic marker
5) Pencils

Setup
1) The 16 numbered index cards represent a vector of length 16 elements. These are divvied up roughly equally among all 4 to 5 “processors”
2) One extra index cards labeled “Shared Sum” and has the value 0 written on it and is placed in the middle of the table accessible to all processors.
3) Several extra index cards are labeled “local memory” and are given to each processor as a scratch pad to add number on.
4) A Magic maker, known as “critical section”, is placed on the table next to the “shared sum”

Execution
1) We are now trying to synchronize access to shared memory by implementing a critical section. Our goal is to get rid of the race condition we encountered earlier.
2) New rule: “Each processor can only use the magic marker, named critical section, to write values to the “shared sum” index card. And – No processor can do any computations without first acquiring the magic marker, called critical section. As soon as a processor writes a new value to “shared sum” the processor should expeditiously return the capped critical section to the middle of the table”.
3) Each processor should do these steps as quickly as possible:
a) Acquire the critical section! If you failed to acquire the critical section you must wait for the marker to be placed back in the middle of the table.
b) Immediately cross off the current value on the “shared sum” card
c) Add the value of one of your index cards to the “shared sum” use a scratch pad if needed
d) Write the new value for sum on the globally shared “shared sum” card
e) Return the cap to the marker
f) Return the marker to the middle of the table
g) Repeat steps 5a(i) – 5a(v) until you are out of index cards
4) Compare the final value written on the “shared sum” with the known total (46)
5) Did your team compute the correct grand total for the vector sum?
6) What did you observe about how much time you spent idling versus time spent writing or calculating?

Activity 5 – Vector Addition fixed with reduction

In this activity, your team will explore how a reduction (or a partial sums approach) can be used to guarantee that access to a shared memory region are protected – in other words, that writes to a shared variable are done in an orderly and synchronized fashion. It will also demonstrate the benefit of replacing a critical section with a reduction wherever possible.

Time Required
Fifteen minutes

Objective
Use some index cards, & pencils to explore the concept of a critical section

Materials
1) 16 numbered index cards (we call it our vector)
2) 1 index card labeled “Shared Sum”
3) 4 index card labeled “Partial Sum”
4) 16 extra index cards are labeled “local memory”
5) Pencils

Setup
1) The 16 numbered index cards represent a vector of length 16 elements. These are divvied up roughly equally among all 4 to 5 “processors”
2) One extra index cards labeled “Shared Sum” and has the value 0 written on it and is placed in the middle of the table accessible to all processors.
3) The remaining “Partial sum” cards are divvied up among the processors
4) Several extra index cards are labeled “local memory” and are given to each processor as a scratch pad to add number on.

Execution
We are now trying to synchronize access to shared memory by implementing a reduction – which amounts to a collection of partial sums computed by each processor, followed by a grand total computed by a master thread. Our goal is to get rid of the race condition we encountered earlier, and do the parallel tasks in a more efficient manner.

Every processor will add up his/her own partial sum that represents the total of all the vector
elements assigned to him/her.

One processor will also be named to execute the “master thread” that adds up all the partial sum cards to create a grand total , that the master thread writes this grand total to the “shared sum” card.

1) Each processor should:
a) Add the values from all their assigned vector cards
b) Write the value to a “partial Sum” card
c) Give the “Partial Sum” card to the Processor who will execute the master thread
2) The Master Thread only should:
a) Compute his own partial sum
b) Wait for all other partial sums to arrive
c) Compute the grand total for all partial sums
d) Write the grand total on the “Shared Sum” card

3) Did your team compute the correct grand total for the vector sum?
What did you observe about how much time you spent idling versus time spent writing or calculating?

4) How effective was the reduction strategy at computing the sum in parallel versus the other methods tried?

Review Questions

Question 1: Describe a race condition
Question 2: What does a critical section do?

Dawn: What do you like about working in Intel's Open Source Technology Center?

Eddie: Intel's Open Source Technology Center is a great place where I learned, grew up and contributed. The team here in China is young, open and skillful, and we all are in a very good atmosphere to help each other and work as a team. Each individual contribution is small, but we are proud of the whole team effort. That is the sole reason we received an Intel Achievement Award in 2006.

Dawn: How are you involved in performance tuning work for open source virtualization projects?

Eddie: I started my virtualization life in early 2004, and started working on open source virtualization projects, i.e. Xen, at the end of year. Performance is critical to the success of open source virtualization projects, but it was not that good at that time. I started the work with help from the team, accumulated all the expertise necessary and was able to improve it dramatically both in Xen and KVM.

Dawn: Can you tell us more about your efforts with SR-IOV Networking in the Xen project?

Eddie: SR-IOV, as part of Intel Virtualization Technology for Connectivity, is a significant product to improve I/O virtualization performance. It takes the advantage of Intel Virtualization Technology for directed I/O, i.e. VT-d, to reduce the intervention of hypervisor in I/O sharing. As a team, we implemented the SR-IOV support for open source virtualization and tuned the performance to achieve close to native performance.

Dawn: What do you do for fun when you aren't working at Intel?

Eddie: I like to spend time with my kid, playing chess or having fun together.

But this won't prevent us doing our job at the Microsoft event for four long days (at day five Tech-Ed has to get along without us). This means in particular:

• We will interview some of the most interesting people at the show with our video cam and blog this right away during Tech-Ed Europe 2009. This year we will try something really new: Instead of doing the live blogging in a dark and isolated chamber somewhere in one of these sad conference rooms I will sit right at the Intel stand within the Visual Studio Partner Zone and blog lively during the show. And with the help of a huge TV screen you can follow how I'm doing my job. This is nearly as good as watching a daily soap, isn't it?!

• There will be three 15 minute sessions which will be held by Intel colleagues. Their short presentations will take place at the huge show theatre. The main topic will be Intel Parallel Studio with all facets of parallel programming with native programming languages as C and C++. So you can learn how to optimize your serial coded application in order to make it as fast as possible on a multi-core system. BUT you will also learn that Parallel Studio can help developers to make their serial coded apps saver and more efficient.

In terms of code safety the Memory Checker (which is part of the Parallel Inspector) can identify critical and most likely memory leaks while running an application. This is something you'll hardly find with your known software engineering tools. Furthermore with Parallel Amplifier which belongs to Intel Parallel Studio too, it's also possible to raise the overall application performance by finding some critical bottlenecks and hotspots within the serial coded app. For example the tool identifies an often used loop which contains a huge bug and takes far too much time when being executed. As a result the application takes too much execution time than necessary. With the help of Parallel Amplifier you can eliminate that!

• Besides those parallel programming sessions you can stop by at Rami Radi's tech session. Rami will talk about how you as a developer can give "Your App a Triple Boost with Windows 7, Microsoft .NET Framework 4.0 and Intel Multi-Core". From what I've heard his session will be fully packed with interesting insights as "How to optimize .NET code with the help of Intel VTune Performance Analyzer". But no worries: You will find all these information on this dedicated TechEd09 blog. So don't forget to bookmark it and stop by later on.

Tim Duncan and Andy Schiestle this week released a new Remote Encryption Management video, showing you how to unclock remote clients. It also gives you more instruction about using the REM SDK itself.

We are helping to promote a new Intel Press book: Harnessing the UEFI Shell Moving the platform Beyond Dos. Read authors' descriptions of the features and capabilities of the shell for the UEFI. "UEFI is not an operating system per se, but is instead intended to be a set of defined interfaces between the system firmware (BIOS), Option ROMs, and operating systems."

Our Community Manager at Large program has started with our selection of Javier Andres Caceres Alvis who works as a Software Engineer for Aranda Software in Bucaramanga, Colombia. He will be attending our content meetings once per month and has already provided some excellent ideas for our community. An extremely astute developer who understands what our community is all about, Javier thinks we need to make "more noise" about Manageability in general and Intel® AMT™ in particular. Stay tuned to find out which of Javier's plans will be put into practice.

We recently featured a poll concerning language preference. The question was "How comfortable are you with the English Language?" Half of the responders said they were not English speakers but understand English well, 42% of respondents said they were native English speakers. Only eight percent stated that they were not English speakers and that English was difficult for them to understand. This is good news for the most part but eight percent stilll have challenges. Please write to me at kathy.a.farrel@intel.com with ideas on how to reach these folks. The Intel Software Network is working to address different languages and will add more over time.

Hey - did you know we're on Twitter? Follow ISNManage to get the latest on Manageability and our Community.

I will continue to morph our site as I receive more input and discover new areas to interest you!

Keep your cards and letters coming! :-) Tell me what you're thinking about - really. What else can we do to help you with your work?

Kathy

The event keynote will be delivered by Ernest Adams, the founder and first chairman of the International Game Developers' Association, who has authored various books on Game Design and often delivers sessions at GDC.

Many other companies seen as pioneers of gaming in India like FX Labs, Hyderabad, Dhruva Interactive, Bangalore, Indiagames, Mumbai, Immersive Games, Hyderabad, Ironcode Software and Interactive Media will be sharing their experiences and success stories.

Intel has been working closes with NASSCOM to energize the Indian Gaming Ecosystem and we kick started this effort with monthly webinars in June 2009. Since then we have conduct regular webinars for game developers with Industry experts and Intel Engineers on topics like Challenges of Cross Platform Game Development, Making 3D game production faster: Using scripting in 3D Studio Max, Crystal Ball Gazing into 3D Game Engine Technology and How to optimize games for PC graphics.

Continuing this association Udaysimha, Program Manager and Mark Kim, Engineering Manager, Intel Corporation will be sharing their experience and learning from the Korean and Asian markets. They will be delivering a session on Building a successful MMORPG - Technical decisions and best known methods.

Uday, Abarnaa and I will be at the Intel booth at the NAGFO Gaming and Animation Summit over the next two days and will bring you live updates. We are looking forward to spending two exciting days in Hyderabad, among Indian gaming stalwarts who will be driving the growth of the Indian gaming industry that is expected to reach USD830 million by 2012 growing at a CAGR of 53%, (according to the NASSCOM report). Stay tuned for more from the NAGFO Gaming and Animation Summit.

• Support for Windows 7 (32 and 64bit)
• Media Foundation samples
• Plugins: source code MFTs (Decode: H.264, MPEG-2, and VC-1) Encode: H.264
• Application (transcode/playback)
• Enchanced Video Pre-Processing
• Hardware accelerated re-sizing (scaling) and color conversion
• Simple frame rate conversion (1:2,1:3, 2:1,3:1)

If you'd like to provide feedback on this release in the Media SDK Forum - be sure and mention you're working with the 1.5 beta.

- Pitz