<?xml version="1.0" encoding="UTF-8"?>
<?xml-stylesheet type="text/xsl" media="screen" href="/~d/styles/rss2full.xsl"?><?xml-stylesheet type="text/css" media="screen" href="http://feeds.feedburner.com/~d/styles/itemcontent.css"?><rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:wfw="http://wellformedweb.org/CommentAPI/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:atom="http://www.w3.org/2005/Atom" xmlns:sy="http://purl.org/rss/1.0/modules/syndication/" xmlns:slash="http://purl.org/rss/1.0/modules/slash/" xmlns:feedburner="http://rssnamespace.org/feedburner/ext/1.0" version="2.0">

<channel>
	<title>Blogs</title>
	
	<link>http://software.intel.com/en-us/blogs</link>
	<description />
	<lastBuildDate>Fri, 10 Feb 2012 07:20:35 +0000</lastBuildDate>
	<language>en</language>
	<sy:updatePeriod>hourly</sy:updatePeriod>
	<sy:updateFrequency>1</sy:updateFrequency>
	<generator>http://wordpress.org/?v=3.1.3</generator>
		<atom10:link xmlns:atom10="http://www.w3.org/2005/Atom" rel="self" type="application/rss+xml" href="http://feeds.feedburner.com/IntelSoftwareNetworkBlog" /><feedburner:info uri="intelsoftwarenetworkblog" /><atom10:link xmlns:atom10="http://www.w3.org/2005/Atom" rel="hub" href="http://pubsubhubbub.appspot.com/" /><feedburner:emailServiceId>IntelSoftwareNetworkBlog</feedburner:emailServiceId><feedburner:feedburnerHostname>http://feedburner.google.com</feedburner:feedburnerHostname><item>
		<title>Jeff's Notebook: Best Known Methods for using Intel® AMT with client virtualization</title>
		<link>http://feedproxy.google.com/~r/IntelSoftwareNetworkBlog/~3/88s7xddz-dQ/</link>
		<comments>http://software.intel.com/en-us/blogs/2012/02/09/jeffs-notebook-best-known-methods-for-using-intel-amt-with-client-virtualization/#comments</comments>
		<pubDate>Fri, 10 Feb 2012 07:20:35 +0000</pubDate>
		<dc:creator>Jeff Kataoka (Intel)</dc:creator>
				<category><![CDATA[Intel SW Partner Program]]></category>
		<category><![CDATA[Manageability & Security]]></category>
		<category><![CDATA[AMT]]></category>
		<category><![CDATA[Intel vPro]]></category>
		<category><![CDATA[Manageability]]></category>
		<category><![CDATA[Virtualization]]></category>
		<category><![CDATA[vpro]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2012/02/09/jeffs-notebook-best-known-methods-for-using-intel-amt-with-client-virtualization/</guid>
		<description><![CDATA[Virtualization of PC's is being used more and more in many companies to help them to maximize their PC resources for a variety of application uses.  Some businesses are using virtualization with client PCs with Intel®vPro™  technology and Intel® Active Management Technology (Intel® AMT). Yet, there are some key differences you have to consider when using Intel [...]]]></description>
			<content:encoded><![CDATA[<p>Virtualization of PC's is being used more and more in many companies to help them to maximize their PC resources for a variety of application uses.  Some businesses are using virtualization with client PCs with Intel®vPro™  technology and Intel® Active Management Technology (Intel® AMT). Yet, there are some key differences you have to consider when using Intel Active Management Technology features on a virtualized client.  Whether you are an IT manager or even, a software consultant working with a major business client, it is important to know the differences and any other Best Known Methods to allow adjustments to the IT processes for managing virtualized clients with Intel Active Management Technology.  A recent white paper on the vPro Developer Community website describes the expected behavior and these Best Known Methods for IT managers.  <a href="http://software.intel.com/en-us/articles/intel-active-management-technology-on-virtualized-pcs/?cid=sw:Blog_BKM_AMT_Virtualization_JK15">Read the white paper to learn more.</p>
<p></a></p>
<div class="feedflare">
<a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=88s7xddz-dQ:y_MlnpcWUxA:yIl2AUoC8zA"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=yIl2AUoC8zA" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=88s7xddz-dQ:y_MlnpcWUxA:dnMXMwOfBR0"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=dnMXMwOfBR0" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=88s7xddz-dQ:y_MlnpcWUxA:V_sGLiPBpWU"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?i=88s7xddz-dQ:y_MlnpcWUxA:V_sGLiPBpWU" border="0"></img></a>
</div><img src="http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~4/88s7xddz-dQ" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://software.intel.com/en-us/blogs/2012/02/09/jeffs-notebook-best-known-methods-for-using-intel-amt-with-client-virtualization/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		<feedburner:origLink>http://software.intel.com/en-us/blogs/2012/02/09/jeffs-notebook-best-known-methods-for-using-intel-amt-with-client-virtualization/</feedburner:origLink></item>
		<item>
		<title>PVS-Studio: analyzing Doom 3 code</title>
		<link>http://feedproxy.google.com/~r/IntelSoftwareNetworkBlog/~3/YhPSSJ0t4Dk/</link>
		<comments>http://software.intel.com/en-us/blogs/2012/02/08/pvs-studio-analyzing-doom-3-code/#comments</comments>
		<pubDate>Wed, 08 Feb 2012 18:45:32 +0000</pubDate>
		<dc:creator>Andrey Karpov</dc:creator>
				<category><![CDATA[Game Development]]></category>
		<category><![CDATA[c plus plus]]></category>
		<category><![CDATA[doom 3]]></category>
		<category><![CDATA[Open Source]]></category>
		<category><![CDATA[PVS-Studio]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2012/02/08/pvs-studio-analyzing-doom-3-code/</guid>
		<description><![CDATA[The id Software company possesses a PVS-Studio license. However, we decided to test the source codes of Doom 3 that have been recently laid out on the Internet. The result is the following: we managed to find just few errors, but still they are there. I think it can be explained by the following fact. [...]]]></description>
			<content:encoded><![CDATA[<p><img src="http://www.viva64.com/external-pictures/habr91/image1.jpeg" alt="PVS-Studio VS Doom3"></p>
<p>The id Software company possesses a PVS-Studio license. However, we decided to test the source codes of Doom 3 that have been recently laid out on the Internet. The result is the following: we managed to find just few errors, but still they are there. I think it can be explained by the following fact.</p>
<p>A part of the Doom 3 code is still in use, and perhaps developers have fixed errors there. And another part of the code is obsolete and not used now. Most likely, the suspicious code fragments have been found in this very part.</p>
<p>For those who want to know more on the subject, in this article we cite code fragments the PVS-Studio analyzer gave warnings for. As usually, let me remind you that I will speak only on some of the warnings, while the other project fragments require us to know the program's structure, so I did not examine them.</p>
<p>The source code of Doom3 was published on <a href="http://www.viva64.com/go.php?url=757">GitHub</a> and official <a href="http://www.viva64.com/go.php?url=758">FTP</a> of the company under the GPL v3 license. I used the <a href="http://www.viva64.com/en/pvs-studio/">PVS-Studio</a> 4.39 analyzer for analysis.</p>
<h2>Fragment 1. Suspicious condition.</h2>
<pre>#define BIT( num ) ( 1 &lt;&lt; ( num ) )
const int BUTTON_ATTACK = BIT(0);
void idTarget_WaitForButton::Think( void ) {
  ...
  if ( player &amp;&amp;
      ( !player-&gt;oldButtons &amp; BUTTON_ATTACK ) &amp;&amp;
      ( player-&gt;usercmd.buttons &amp; BUTTON_ATTACK ) ) {
  ...
}</pre>
<p>PVS-Studio diagnostic message: V564 The '&amp;' operator is applied to bool type value. You've probably forgotten to include parentheses or intended to use the '&amp;&amp;' operator. Game target.cpp 257</p>
<p>Note the fragment "!player-&gt;oldButtons &amp; BUTTON_ATTACK". The developers intended to check here that the least significant bit is equal to 0. But the <a href="http://www.viva64.com/en/t/0064/">priority</a> of the '!' operator is higher than that of the '&amp;' operator. It means that the condition works according to the following algorithm:</p>
<pre>(!player-&gt;oldButtons) &amp; 1</pre>
<p>It turns out that the condition is true only when all the bits equal zero. This is the correct code:</p>
<pre>if ( player &amp;&amp;
    ( ! ( player-&gt;oldButtons &amp; BUTTON_ATTACK ) ) &amp;&amp;
    ( player-&gt;usercmd.buttons &amp; BUTTON_ATTACK ) ) {</pre>
<h2>Fragment 2. Suspicious loop.</h2>
<pre>void idSurface_Polytope::FromPlanes(...)
{
  ...
  for ( j = 0; j &lt; w.GetNumPoints(); j++ ) {
    for ( k = 0; k &lt; verts.Num(); j++ ) {
      if ( verts[k].xyz.Compare(w[j].ToVec3(),
                                POLYTOPE_VERTEX_EPSILON ) ) {
        break;
      }
    }
    ...
  }
  ...
}</pre>
<p>PVS-Studio diagnostic message: V533 It is likely that a wrong variable is being incremented inside the 'for' operator. Consider reviewing 'j'. idLib surface_polytope.cpp 65</p>
<p>The nested loop increments the 'j' variable instead of 'k'. The 'k' variable is not incremented at all. Results of such a loop cannot be predicted. This is the correct code:</p>
<pre>for ( k = 0; k &lt; verts.Num(); k++ ) {</pre>
<h2>Fragment 3. One more suspicious loop.</h2>
<pre>bool idMatX::IsOrthonormal( const float epsilon ) const {
  ...
  for ( int i = 0; i &lt; numRows; i++ ) {
    ...
    for ( i = 1; i &lt; numRows; i++ ) {
      ...
    }
    if ( idMath::Fabs( sum ) &gt; epsilon ) {
      return false;
    }
  }
  return true;
}</pre>
<p>PVS-Studio diagnostic message: V535 The variable 'i' is being used for this loop and for the outer loop. idLib matrix.cpp 3128</p>
<p>One and the same variable is used to arrange both the outer loop and the nested loop. The both loops have the same loop end condition: i &lt; numRows. It turns out that the outer loop always performs only one iteration. To fix the code you may use another variable in the nested loop.</p>
<h2>Fragment 4. Undefined behavior.</h2>
<pre>int idFileSystemLocal::ListOSFiles(...)
{
  ...
  dir_cache_index = (++dir_cache_index) % MAX_CACHED_DIRS;
  ...
}</pre>
<p>PVS-Studio diagnostic message: V567 Undefined behavior. The 'dir_cache_index' variable is modified while being used twice between sequence points. TypeInfo filesystem.cpp 1877</p>
<p>The "dir_cache_index" variable is changed twice in one <a href="http://www.viva64.com/en/t/0065/">sequence point</a>. It does not matter that the prefix increment is used and, theoretically, nothing prevents the compiler from creating the following code:</p>
<pre>A = dir_cache_index;
A = A + 1;
B = A % MAX_CACHED_DIRS;
dir_cache_index = B;
dir_cache_index = A;</pre>
<p>Of course, the expression is most likely calculated as it should be. But you cannot be absolutely sure because the result is determined by the type and version of the compiler as well as optimization settings. This is the correct code:</p>
<pre>dir_cache_index = (dir_cache_index + 1) % MAX_CACHED_DIRS;</pre>
<h2>Fragment 5. Suspicious array clearing.</h2>
<pre>void idMegaTexture::GenerateMegaMipMaps() {
  ...
  byte *newBlock = (byte *)_alloca( tileSize );
  ...
  memset( newBlock, 0, sizeof( newBlock ) );
  ...
}</pre>
<p>PVS-Studio diagnostic message: V579 The memset function receives the pointer and its size as arguments. It is possibly a mistake. Inspect the third argument. DoomDLL megatexture.cpp 542</p>
<p>Only part of the 'newBlock' array is filled with nulls. Most likely, it is an incorrect situation. It seems to me that this fragment looked like this earlier:</p>
<pre>byte newBlock[ CONST_ARRAY_SIZE ];
...
memset( newBlock, 0, sizeof( newBlock ) );</pre>
<p>Then the requirements changed and the size of the 'newBlock' array started to change too, but the programmers forgot about the function clearing it. This is the correct code:</p>
<pre>memset( newBlock, 0, tileSize );</pre>
<h2>Fragment 6. One more instance of suspicious array clearing.</h2>
<pre>void Sys_GetCurrentMemoryStatus( sysMemoryStats_t &amp;stats ) {
  ...
  memset( &amp;statex, sizeof( statex ), 0 );
  ...
}</pre>
<p>PVS-Studio diagnostic message: V575 The 'memset' function processes '0' elements. Inspect the third argument. DoomDLL win_shared.cpp 177</p>
<p>Arguments are mixed up when calling the 'memset' function. The function clears 0 bytes. By the way, this error is rather widely-spread. I came across it in many projects.</p>
<p>This is the correct function call:</p>
<pre>memset( &amp;statex, 0, sizeof( statex ) );</pre>
<h2>Fragment 7. Hello, Copy-Paste.</h2>
<pre>void idAASFileLocal::DeleteClusters( void ) {
  ...
  memset( &amp;portal, 0, sizeof( portal ) );
  portals.Append( portal );

  memset( &amp;cluster, 0, sizeof( portal ) );
  clusters.Append( cluster );
}</pre>
<p>PVS-Studio diagnostic message: V512 A call of the 'memset' function will lead to underflow of the buffer '&amp; cluster'. DoomDLL aasfile.cpp 1312</p>
<p>Note the similarity between the two upper and the two lower code lines. The last two lines must have been written through Copy-Paste. This is the thing that caused the error here. The programmer forgot to replace the word 'portal' with the word 'cluster' in one place. As a result, only a part of the structure is cleared. This is the correct code:</p>
<pre>memset( &amp;cluster, 0, sizeof( cluster ) );</pre>
<p>There were some other incompletely cleared arrays in the code, but they are not of much interest.</p>
<h2>Fragment 8. Suspicious pointer handling.</h2>
<pre>void idBrushBSP::FloodThroughPortals_r(idBrushBSPNode *node, ...)
{
  ...
  if ( node-&gt;occupied ) {
    common-&gt;Error( "FloodThroughPortals_r: node already occupied\n" );
  }
  if ( !node ) {
    common-&gt;Error( "FloodThroughPortals_r: NULL node\n" );
  }
  ...
}</pre>
<p>PVS-Studio diagnostic message: V595 The 'node' pointer was utilized before it was verified against nullptr. Check lines: 1421, 1424. DoomDLL brushbsp.cpp 1421</p>
<p>The 'node' pointer is dereferenced first: node-&gt;occupied. And then it is suddenly checked if it is not equal to NULL. This is a very suspicious code. I do not know how to fix it because I do not know the logic of the function operation. Perhaps it is just enough to write it that way:</p>
<pre>if ( node &amp;&amp; node-&gt;occupied ) {</pre>
<h2>Fragment 9. Suspicious string format.</h2>
<pre>struct gameVersion_s {
  gameVersion_s( void )
  {
    sprintf(string, "%s.%d%s %s %s",
            ENGINE_VERSION, BUILD_NUMBER, BUILD_DEBUG,
            BUILD_STRING, __DATE__, __TIME__ );
  }
  char string[256];
} gameVersion;</pre>
<p>PVS-Studio diagnostic message: V576 Incorrect format. A different number of actual arguments is expected while calling 'sprintf' function. Expected: 7. Present: 8. Game syscvar.cpp 54</p>
<p>What is suspicious about this is that the '__TIME__' argument is not used in any way.</p>
<h2>Fragment 10. Confusing code.</h2>
<p>There are several code fragments which seem to work properly but look strange. I will cite only one example of this code.</p>
<pre>static bool R_ClipLineToLight(..., const idPlane frustum[4], ...)
{
  ...
  for ( j = 0 ; j &lt; 6 ; j++ ) {
    d1 = frustum[j].Distance( p1 );
    d2 = frustum[j].Distance( p2 );
    ...
  }
  ...
}</pre>
<p>As a tip, the programmer has written that the 'frustum' array consists of 4 items. But there are 6 items being processed. If you look at the 'R_ClipLineToLight' call, the array there consists of 6 items. That is, everything must work as intended but the code makes you feel uneasy about it.</p>
<p>What other errors and defects are concerned, you can see them launching the PVS-Studio analyzer. By the way, taking the opportunity, I want to give my best regards to John Carmack and tell him that we will soon fix the flaw that does not allow the id Software company to use PVS-Studio at full.</p>
<p>This flaw is the analyzer's low operation speed. Taking into account the large size of the source code the company deals with, this is a crucial limitation. In PVS-Studio 4.50 that will be released in this year, you will be able to use Clang as a preprocessor instead of the Visual C++ preprocessor. This will provide a significant speed-up of project analysis. For example, the Doom 3 source codes are checked within 26 minutes when using the Visual C++ preprocessor. With the Clang preprocessor, it will be 16 minutes. Well, this example is not very good because the analysis speed boost will be much more significant for most other projects.</p>
<p>But for now you will have to use the Visual C++ preprocessor by default - Clang still has some issues of incompatibility and defects concerning the Windows-platform. So, only 80% of projects are checked successfully with the new preprocessor.</p>
<div class="feedflare">
<a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=YhPSSJ0t4Dk:1F5yZ9P-vyU:yIl2AUoC8zA"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=yIl2AUoC8zA" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=YhPSSJ0t4Dk:1F5yZ9P-vyU:dnMXMwOfBR0"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=dnMXMwOfBR0" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=YhPSSJ0t4Dk:1F5yZ9P-vyU:V_sGLiPBpWU"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?i=YhPSSJ0t4Dk:1F5yZ9P-vyU:V_sGLiPBpWU" border="0"></img></a>
</div><img src="http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~4/YhPSSJ0t4Dk" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://software.intel.com/en-us/blogs/2012/02/08/pvs-studio-analyzing-doom-3-code/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		<feedburner:origLink>http://software.intel.com/en-us/blogs/2012/02/08/pvs-studio-analyzing-doom-3-code/</feedburner:origLink></item>
		<item>
		<title>Myths about static analysis. The third myth - dynamic analysis is better than static analysis.</title>
		<link>http://feedproxy.google.com/~r/IntelSoftwareNetworkBlog/~3/v-VqpXahWuY/</link>
		<comments>http://software.intel.com/en-us/blogs/2012/02/08/myths-about-static-analysis-the-third-myth-dynamic-analysis-is-better-than-static-analysis/#comments</comments>
		<pubDate>Wed, 08 Feb 2012 18:45:26 +0000</pubDate>
		<dc:creator>Andrey Karpov</dc:creator>
				<category><![CDATA[Parallel Programming]]></category>
		<category><![CDATA[bugs]]></category>
		<category><![CDATA[C++]]></category>
		<category><![CDATA[Static code analysis]]></category>
		<category><![CDATA[static code analyzer]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2012/02/08/myths-about-static-analysis-the-third-myth-dynamic-analysis-is-better-than-static-analysis/</guid>
		<description><![CDATA[While communicating with people on forums, I noticed there are a few lasting misconceptions concerning the static analysis methodology. I decided to write a series of brief articles where I want to show you the real state of things. The third myth is: "Dynamic analysis performed by tools like valgrind for C/C++ is much better [...]]]></description>
			<content:encoded><![CDATA[<p>While communicating with people on forums, I noticed there are a few lasting misconceptions concerning the static analysis methodology. I decided to write a series of brief articles where I want to show you the real state of things. </p>
<p>The third myth is: "Dynamic analysis performed by tools like valgrind for C/C++ is much better than static code analysis".</p>
<p>The statement is rather strange. Dynamic and static analyses are just two different methodologies which supplement each other. Programmers seem to understand it, but I hear it again and again that dynamic analysis is better than static analysis.</p>
<p>Let me list advantages of static code analysis.</p>
<h2>Diagnostics of all the branches in a program</h2>
<p>Dynamic analysis in practice cannot cover all the branches of a program. After these words, fans of valgrind tell me that one should create appropriate tests. They are right in theory. But anyone who tried to create them understands how complicated and long it is. In practice, even good tests cover not more than 80% of program code.</p>
<p>It is especially noticeable in code fragments handling non-standard/emergency situations. If you take an old project and check it with a static analyzer, most errors will be detected in these very places. The reason is that even if the project is old, these fragments stay almost untested. Here is a brief example to show you what I mean (FCE Ultra project):</p>
<pre>fp = fopen(name,"wb");
int x = 0;
if (!fp)
  int x = 1;</pre>
<p>The 'x' flag will not be equal to one if the file wasn't opened. It is because of such errors that something goes wrong in programs: they crash or generate meaningless messages instead of adequate error messages.</p>
<h2>Scalability</h2>
<p>To be able to check large projects through dynamic methods regularly, you have to create a special infrastructure. You need special tests. You need to launch several instances of an application in parallel with different input data.</p>
<p>Static analysis is scaled several times easier. Usually you need only a multi-core computer to run a tool performing static analysis.</p>
<h2>Analysis at a higher level</h2>
<p>One of the advantages of dynamic analysis is that it knows what function and with what arguments is being called. Consequently, it can check if the call is correct. Static analysis can't know it and can't check arguments' values in most cases. This is a disadvantage of this method. But static analysis performs analysis at a higher level than dynamic analysis. This feature allows a static analyzer to detect issues which are correct from the viewpoint of dynamic analysis. Here is a simple example (ReactOS project):</p>
<pre>void Mapdesc::identify( REAL dest[MAXCOORDS][MAXCOORDS] )
{
  memset( dest, 0, sizeof( dest ) );
  for( int i=0; i != hcoords; i++ )
    dest[i][i] = 1.0;
}</pre>
<p>Everything is good here from the viewpoint of dynamic analysis, while static analysis gives the <a href="http://www.viva64.com/en/d/0100/">alarm</a> because it is very suspicious that the number of bytes being cleared in an array coincides with the number of bytes the pointer consists of.</p>
<p>Here you are another example from the Clang project:</p>
<pre>MapTy PerPtrTopDown;
MapTy PerPtrBottomUp;
void clearBottomUpPointers() {
  PerPtrTopDown.clear();
}
void clearTopDownPointers() {
  PerPtrTopDown.clear();
}</pre>
<p>Is there anything here dynamic analysis may find suspicious? Nothing. But a static analyzer can suspect there is something wrong. The error is this: inside clearBottomUpPointers() there must be this code: "PerPtrBottomUp.clear();".</p>
<div class="feedflare">
<a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=v-VqpXahWuY:BiKAjkbhBws:yIl2AUoC8zA"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=yIl2AUoC8zA" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=v-VqpXahWuY:BiKAjkbhBws:dnMXMwOfBR0"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=dnMXMwOfBR0" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=v-VqpXahWuY:BiKAjkbhBws:V_sGLiPBpWU"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?i=v-VqpXahWuY:BiKAjkbhBws:V_sGLiPBpWU" border="0"></img></a>
</div><img src="http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~4/v-VqpXahWuY" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://software.intel.com/en-us/blogs/2012/02/08/myths-about-static-analysis-the-third-myth-dynamic-analysis-is-better-than-static-analysis/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		<feedburner:origLink>http://software.intel.com/en-us/blogs/2012/02/08/myths-about-static-analysis-the-third-myth-dynamic-analysis-is-better-than-static-analysis/</feedburner:origLink></item>
		<item>
		<title>Myths about static analysis. The fourth myth - programmers want to add their own rules into a static analyzer.</title>
		<link>http://feedproxy.google.com/~r/IntelSoftwareNetworkBlog/~3/7L1q19DGMYM/</link>
		<comments>http://software.intel.com/en-us/blogs/2012/02/08/myths-about-static-analysis-the-fourth-myth-programmers-want-to-add-their-own-rules-into-a-static-analyzer/#comments</comments>
		<pubDate>Wed, 08 Feb 2012 18:45:17 +0000</pubDate>
		<dc:creator>Andrey Karpov</dc:creator>
				<category><![CDATA[Parallel Programming]]></category>
		<category><![CDATA[Static code analysis]]></category>
		<category><![CDATA[static code analyzer]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2012/02/08/myths-about-static-analysis-the-fourth-myth-programmers-want-to-add-their-own-rules-into-a-static-analyzer/</guid>
		<description><![CDATA[While communicating with people on forums, I noticed there are a few lasting misconceptions concerning the static analysis methodology. I decided to write a series of brief articles where I want to show you the real state of things. The fourth myth is: "A static analyzer must enable users to add user-made rules. Programmers want [...]]]></description>
			<content:encoded><![CDATA[<p>While communicating with people on forums, I noticed there are a few lasting misconceptions concerning the static analysis methodology. I decided to write a series of brief articles where I want to show you the real state of things. </p>
<p>The fourth myth is: "A static analyzer must enable users to add user-made rules. Programmers want to add their own rules."</p>
<p>No, they don't. They actually want to solve some tasks of searching for particular language constructs. It is not the same thing as creating diagnostic rules.</p>
<p>I have always answered that implementation of own rules is not the thing programmers actually want. And I never saw any other alternative than implementing diagnostic rules by the analyzer's developers at the request of programmers (<a href="http://www.viva64.com/en/b/0110/">an article on the subject</a>). I have had a fruitful conversation with Dmitry Petunin recently. He is the director of an Intel department of compiler testing and software verification tool development. He enlarged my understanding of this subject and voiced the idea I had been pondering over but failed to give the final formulation of.</p>
<p>Dmitry confirmed my belief that programmers wouldn't write diagnostic rules. The reason is very simple - it is very hard. Some static analysis tools enable users to extend the rule set. But it is done rather as a pure formality or for convenience of the tool's developers themselves. You need to know the subject very deeply to be able to develop new diagnostic rules. If an enthusiast without skill starts creating them, they will be of little use.</p>
<p>My understanding of the issue was over at this point. Dmitry, being more skilled than I, helped me learn more. In brief, this is how the situation looks.</p>
<p>Indeed, programmers want to be able to search for some particular patterns/errors in their code. They really need it. For example, someone needs to find all the explicit conversions of the int type to float. This task cannot be solved by such tools as grep, since it is unknown what type the FOO() function will return in a "float(P-&gt;FOO())" -like construct. At this moment the programmer comes to the idea that he/she can implement search of such constructs by adding his/her own check into the static analyzer.</p>
<p>This is where the key point lies. The programmer does not need to create his/her analysis rules. He/she needs to solve a particular issue. What he/she wants is a very small task from the viewpoint of static analysis mechanisms. It is like using a car to light cigarettes with its cigarette lighter.</p>
<p>That's why both Dmitry and I don't support the idea of providing users with API to handle the analyzer. It is an extremely difficult task from the viewpoint of development. Besides, people will hardly use more than 1% of it. So, it's irrational. It is easier and cheaper for a developer to implement users' wishes than create a complex API for add-ons or a special language of rule description.</p>
<p>The readers may say: "then make only 1% of the functionality in API available, and everyone will be happy". Yes, right. But look where the emphasis has moved: from developing own rules we have come to the idea that we just need a tool similar to grep but possessing some additional information about program code.</p>
<p>There is no such a tool yet. If you want to solve some task, write to me, and we will try to implement it in the PVS-Studio analyzer. For example, we have recently implemented several requests on searching for explicit type conversions: <a href="http://www.viva64.com/en/d/0199/">V2003</a>, <a href="http://www.viva64.com/en/d/0200/">V2004</a>, <a href="http://www.viva64.com/en/d/0201/">V2005</a>. It is much easier for us to implement such wishes than create and maintain an open interface. It's also easier for users themselves.</p>
<p>By the way, such a tool might appear some time later within the scope of Intel C++. Dmitry Petunin said they had discussed a probability of creating a grep-like tool possessing knowledge about code structure and variable types. But it was discussed just in theory. I don't know whether or not they really intend to create this tool.</p>
<div class="feedflare">
<a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=7L1q19DGMYM:iR_AhcaevV0:yIl2AUoC8zA"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=yIl2AUoC8zA" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=7L1q19DGMYM:iR_AhcaevV0:dnMXMwOfBR0"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=dnMXMwOfBR0" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=7L1q19DGMYM:iR_AhcaevV0:V_sGLiPBpWU"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?i=7L1q19DGMYM:iR_AhcaevV0:V_sGLiPBpWU" border="0"></img></a>
</div><img src="http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~4/7L1q19DGMYM" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://software.intel.com/en-us/blogs/2012/02/08/myths-about-static-analysis-the-fourth-myth-programmers-want-to-add-their-own-rules-into-a-static-analyzer/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		<feedburner:origLink>http://software.intel.com/en-us/blogs/2012/02/08/myths-about-static-analysis-the-fourth-myth-programmers-want-to-add-their-own-rules-into-a-static-analyzer/</feedburner:origLink></item>
		<item>
		<title>Myths about static analysis. The fifth myth - a small test program is enough to evaluate a tool.</title>
		<link>http://feedproxy.google.com/~r/IntelSoftwareNetworkBlog/~3/STjnFpgLfC0/</link>
		<comments>http://software.intel.com/en-us/blogs/2012/02/08/myths-about-static-analysis-the-fifth-myth-a-small-test-program-is-enough-to-evaluate-a-tool/#comments</comments>
		<pubDate>Wed, 08 Feb 2012 18:44:58 +0000</pubDate>
		<dc:creator>Andrey Karpov</dc:creator>
				<category><![CDATA[Parallel Programming]]></category>
		<category><![CDATA[Static code analysis]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2012/02/08/myths-about-static-analysis-the-fifth-myth-a-small-test-program-is-enough-to-evaluate-a-tool/</guid>
		<description><![CDATA[While communicating with people on forums, I noticed there are a few lasting misconceptions concerning the static analysis methodology. I decided to write a series of brief articles where I want to show you the real state of things. The fifth myth: "You can easily evaluate capabilities of a static analyzer on a small test [...]]]></description>
			<content:encoded><![CDATA[<p>While communicating with people on forums, I noticed there are a few lasting misconceptions concerning the static analysis methodology. I decided to write a series of brief articles where I want to show you the real state of things.</p>
<p>The fifth myth: "You can easily evaluate capabilities of a static analyzer on a small test code".</p>
<p>This is how this statement looks in discussions on forums (this is a collective image):</p>
<p><i>I've written a special program, its size is 100 code lines. But the analyzer doesn't generate anything although all the warning levels are enabled. This [tool of yours] / [static analysis] in general is just rubbish.</i></p>
<p>It is not the static analysis methodology which is rubbish, but this approach to evaluating the usability of a particular tool. The incorrectness of this kind of tool studying consists of two aspects:</p>
<p>1.</p>
<p>Programmers think they don't make simple mistakes. This phenomenon was discussed in <a href="http://www.viva64.com/en/b/0116/">Myth 2</a>. So they try to feed an analyzer with a tricky sample and feel happy secretly when the analyzer can't find the error. This game is interesting yet senseless.</p>
<p>You should understand that most errors are simple as hell, and static analyzers detect them very well. The paradox is that it's much more difficult to invent a simple mistake than a complicated one. Here you are an example. Can you ever guess to write a sample like this?</p>
<pre>int threadcounts[] = { 1, kNumThreads };
for (size_t i = 0;
     i &lt; sizeof(threadcounts) / sizeof(threadcounts); i++) {</pre>
<p>I doubt. I cannot imagine one can make such a silly mistake and write "sizeof(threadcounts) / sizeof(threadcounts)". So, such an example will never be created on purpose. By the way, this fragment is taken not from a student's lab work, but from the Chromium project. It is diagnosed by the PVS-Studio analyzer very easily, of course.</p>
<p>2.</p>
<p>Written samples are of random character, and they are few. So you may get very different results depending on chance. You may invent 5 errors that will be successfully found by one analyzer and not found by another analyzer. Or you may create a program with five errors, and two analyzers will give opposite results for it. The sampling for such an investigation is too small. To be able to compare and study tools with at least somewhat reliable results, you must write a program text with at least 500 different errors. An investigation based on 5-10 errors is not reliable.</p>
<p>Moreover, programmers expect to see diagnostic messages on errors of some particular type and forget about the rest. For example, almost all the programmers write one and the same sample with a memory release defect:</p>
<pre>void Foo()
{
  int *a = (int *)malloc(X);
  int *b = (int *)malloc(Y);
  //...
  free(a);
}</pre>
<p>Some analyzers detect this error, the others don't. For instance, PVS-Studio does not diagnose memory leaks currently. But it can find the following stuff:</p>
<pre>static int rr_cmp(uchar *a,uchar *b)
{
  if (a[0] != b[0])
    return (int) a[0] - (int) b[0];
  if (a[1] != b[1])
    return (int) a[1] - (int) b[1];
  if (a[2] != b[2])
    return (int) a[2] - (int) b[2];
  if (a[3] != b[3])
    return (int) a[3] - (int) b[3];
  if (a[4] != b[4])
    return (int) a[4] - (int) b[4];
  if (a[5] != b[5])
    return (int) a[1] - (int) b[5];
  if (a[6] != b[6])
    return (int) a[6] - (int) b[6];
  return (int) a[7] - (int) b[7];
}</pre>
<p>There must be "return (int) a[5] - (int) b[5];" instead of "return (int) a[1] - (int) b[5];".</p>
<p>Why does nobody write such examples? Note that PVS-Studio has found this error in the MySQL project.</p>
<p>The conclusion is, adequate investigation or comparison of tools can be carried out only with real projects. You take project A, test it with PC-Lint / Visual C++ / PVS-Studio / C++Test, study all the messages attentively, draw up a table of results (how many and which errors each analyzer has found). This is the only real investigation and comparison. For example: "<a href="http://www.viva64.com/en/a/0073/">Comparing the general static analysis in Visual Studio 2010 and PVS-Studio by examples of errors detected in five open source projects</a> ".</p>
<div class="feedflare">
<a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=STjnFpgLfC0:OUlwQknj1OY:yIl2AUoC8zA"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=yIl2AUoC8zA" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=STjnFpgLfC0:OUlwQknj1OY:dnMXMwOfBR0"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=dnMXMwOfBR0" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=STjnFpgLfC0:OUlwQknj1OY:V_sGLiPBpWU"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?i=STjnFpgLfC0:OUlwQknj1OY:V_sGLiPBpWU" border="0"></img></a>
</div><img src="http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~4/STjnFpgLfC0" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://software.intel.com/en-us/blogs/2012/02/08/myths-about-static-analysis-the-fifth-myth-a-small-test-program-is-enough-to-evaluate-a-tool/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		<feedburner:origLink>http://software.intel.com/en-us/blogs/2012/02/08/myths-about-static-analysis-the-fifth-myth-a-small-test-program-is-enough-to-evaluate-a-tool/</feedburner:origLink></item>
		<item>
		<title>The way to becoming an Intel Black Belt Software Developer</title>
		<link>http://feedproxy.google.com/~r/IntelSoftwareNetworkBlog/~3/d4tiRp82pUs/</link>
		<comments>http://software.intel.com/en-us/blogs/2012/02/08/the-way-to-becoming-an-intel-black-belt-software-developer/#comments</comments>
		<pubDate>Wed, 08 Feb 2012 18:44:18 +0000</pubDate>
		<dc:creator>Andrey Karpov</dc:creator>
				<category><![CDATA[Site News & Announcements]]></category>
		<category><![CDATA[black belt]]></category>
		<category><![CDATA[Intel Black Belt Software Developer]]></category>
		<category><![CDATA[Intel Software Netwirk]]></category>
		<category><![CDATA[Intel® Software Network 2.0]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2012/02/08/the-way-to-becoming-an-intel-black-belt-software-developer/</guid>
		<description><![CDATA[The Intel company holds a lot of specialist training programs, carries out programming contests, invites people to meetings and free conferences. Unfortunately, we often miss such events, and one gets upset on knowing that he/she did not participate in an already finished event. By the way, participating in Intel contests often ends with a participant [...]]]></description>
			<content:encoded><![CDATA[<p>The Intel company holds a lot of specialist training programs, carries out programming contests, invites people to meetings and free conferences. Unfortunately, we often miss such events, and one gets upset on knowing that he/she did not participate in an already finished event. By the way, participating in Intel contests often ends with a participant being employed by Intel. I have witnessed it a couple of times. A person comes to a meeting to get his/her prize, the next year you see him wearing the "Intel worker" badge himself/herself. So, mind this. :)</p>
<p>However, you don't necessarily need to fight for the first prize in competitions to attract Intel's attention; there are other interesting and useful ways too. For example, you can become a participant of the Intel Software Network (ISN) community and automatically become a participant in the "Black Belt Software Developer" contest. It is this program that I wanted to tell you about.</p>
<p><a href="http://software.intel.com/en-us/" target="_blank">Intel Software Network</a> is a community of software developers. It includes blogs and articles by the community members or Intel company's employees, forums, announcements of new events, contests and so on. What is important and interesting is that you can ask questions directly of Intel workers in forums or in article comments. Or you may give answers yourself, publish interesting content, etc., i.e. be an active and useful community member. It is this what Intel takes into account when selecting candidates to nominate for the "Intel Black Belt Software Developer" award.</p>
<p>This is how the Intel site defines a person deserving to bear this title:</p>
<p><i>This is a title for community members who demonstrate outstanding expertise on Intel technologies and enrich our communities by regularly sharing their knowledge and expertise, providing help &amp; support in the discussion forums, submitting content such as articles and participating in the communities. It is recognition of the community leadership and contribution by these members.</i></p>
<p>While you are on your way to perfection, you will be given belts of different colors. To learn more about this program, its conditions and advantages see the following posts:</p>
<ul>
<li><a href="http://software.intel.com/en-us/articles/blackbelt/" target="_blank">Intel® Black Belt Software Developer</a>; </li>
<li><a href="http://software.intel.com/en-us/articles/intel-brown-belt-software-developer-and-intel-green-belt-software-developer-faqs/" target="_blank">Intel Brown Belt Software Developer and Intel Green Belt Software Developer - FAQs</a>;</li>
<li><a href="http://software.intel.com/en-us/articles/intel-black-belt-software-developers-faqs/?wapkw=(Black+Belt+Software)" target="_blank">Intel® Black Belt Software Developers - FAQs</a>;</li>
<li><a href="http://software.intel.com/en-us/articles/intel-black-belt-software-developer-terms-and-conditions/?wapkw=(Black+Belt+Software)" target="_blank">Intel® Black Belt Software Developer Terms and Conditions</a>.</li>
</ul>
<p>And what myself is concerned, I'm writing this post from joy and gratitude. The reason is that I have been given the Intel Black Belt Software Developer title. I was very pleased to receive congratulations at the ISN-meeting and get a wonderful high-performance laptop as a prize.</p>
<p><a href="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2011/12/image1.png"><img src="http://software.intel.com/en-us/blogs/wordpress/wp-content/uploads/2011/12/image1.png" align="left" width="200" height="280" class="size-full wp-image-43729" /></a></p>
<p>The prize is a Sony VAIO Intel Core i7-based laptop with 4 cores, 6 Gbytes of memory, a Blu-ray driver and other bonuses. There are other presents besides this one and even more advantages provided by the title. For example, I've become a user of the Intel Parallel Studio XE 2011 software.</p>
<p>What do you need to get appreciated? Nothing extraordinary. You should be an active community member, write articles and keep in touch with people. I, for instance, even did not think about and reckon for the Black Belt title. To be honest, I was more concerned with the discussions of <a href="http://www.viva64.com/en/a/0077/">PVS-Studio</a>. That's why it was very unexpectedly and pleasant to get the award for interesting articles and contribution into the ISN community's life.</p>
<p>Thanks to everyone. I will try to continue pleasing my readers with interesting posts and unicorns.</p>
<div class="feedflare">
<a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=d4tiRp82pUs:ErUPYrTP8N4:yIl2AUoC8zA"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=yIl2AUoC8zA" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=d4tiRp82pUs:ErUPYrTP8N4:dnMXMwOfBR0"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=dnMXMwOfBR0" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=d4tiRp82pUs:ErUPYrTP8N4:V_sGLiPBpWU"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?i=d4tiRp82pUs:ErUPYrTP8N4:V_sGLiPBpWU" border="0"></img></a>
</div><img src="http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~4/d4tiRp82pUs" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://software.intel.com/en-us/blogs/2012/02/08/the-way-to-becoming-an-intel-black-belt-software-developer/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		<feedburner:origLink>http://software.intel.com/en-us/blogs/2012/02/08/the-way-to-becoming-an-intel-black-belt-software-developer/</feedburner:origLink></item>
		<item>
		<title>Intel Tool Helps SW Developers Develop More Secure Applications</title>
		<link>http://feedproxy.google.com/~r/IntelSoftwareNetworkBlog/~3/-AvYvw2Uh_s/</link>
		<comments>http://software.intel.com/en-us/blogs/2012/02/07/intel-tool-helps-sw-developers-develop-more-secure-applications/#comments</comments>
		<pubDate>Tue, 07 Feb 2012 23:27:40 +0000</pubDate>
		<dc:creator>Robert Chesebrough (Intel)</dc:creator>
				<category><![CDATA[Manageability & Security]]></category>
		<category><![CDATA[Software Tools]]></category>
		<category><![CDATA[Buffer Overflow]]></category>
		<category><![CDATA[Buffer Overrun]]></category>
		<category><![CDATA[Build Security In]]></category>
		<category><![CDATA[C++]]></category>
		<category><![CDATA[Common Weakness Evaluation]]></category>
		<category><![CDATA[Intel Compiler]]></category>
		<category><![CDATA[Intel® vPro™]]></category>
		<category><![CDATA[Mitigate Secure Bugs]]></category>
		<category><![CDATA[OS Command Injection]]></category>
		<category><![CDATA[owasp top 10]]></category>
		<category><![CDATA[scanf]]></category>
		<category><![CDATA[security]]></category>
		<category><![CDATA[security layer]]></category>
		<category><![CDATA[server]]></category>
		<category><![CDATA[sprintf]]></category>
		<category><![CDATA[static security analysis]]></category>
		<category><![CDATA[Ultrabook]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2012/02/07/intel-tool-helps-sw-developers-develop-more-secure-applications/</guid>
		<description><![CDATA[Developers are urged to find these kinds of bugs using tools such as Intel Static Security Analysis, and then make it a practice to validate all inputs and replace unsafe functions (strcpy, strncpy, strcat, and gets, among others)  with safe counterparts.  To learn more about steps you can take as a developer to reduce your exposure to security attacks go to the Department of Homeland Security's Build Security In website or visit the Common Weakness Evaluation site.
]]></description>
			<content:encoded><![CDATA[<p>There has been a steady occurrence of security breaches at prestigious companies over the last weeks, months and years.  These breaches are becoming far too frequent and, as the folks at Amazon and Zappos know, expensive.</p>
<p>A wide variety of ways exist for addressing these kinds of security challenges and Intel offers technologies to assist in the battle.  For probably the most sane and scalable way of addressing security issues, at least for enterprise applications, I would recommend that you jump over to Blake Dournaee's (Intel) blogs <a href="http://software.intel.com/en-us/blogs/2010/11/09/using-a-service-gateway-to-protect-against-the-owasp-top-10/">"Using a Service Gateway to Protect against the OWASP Top 10</a>" and "<a href="http://software.intel.com/en-us/blogs/2011/02/10/how-about-a-security-layer/">How about a Security Layer?"</a>.  The idea of a Security Layer on a Service Gateway is truly the most comprehensive way to tackle these kinds security issues. </p>
<p>Never-the-less, some enterprise shops may be unwilling to re-architect their legacy systems using the security layer approach and some developers are targeting client applications.  What tools and techniques can these developers use to mitigate security bugs?  For those developers I offer the following:</p>
<p> I had a chat with Julian Horn, who is Intel's architect on the compiler team for the Static Security Analysis (SSA) tool.  SSA comes as part of the Intel compiler (C/C++/Fortran) and is available for Linux* and Windows*.  SSA identifies various coding errors such as memory and resource leaks, pointer and array errors, incorrect use of OpenMP* directives, and incorrect use of Cilk Plus language features.  SSA also identifies security errors such as buffer overflows and boundary violations, use of uninitialized variables and objects, incorrect usage of pointers and dynamically allocated memory, dangerous use of unchecked input, arithmetic overflow and divide by zero, and misuse of string, memory, and formatting library routines.</p>
<p>I was curious what kind of security flaws that SSA could find. Specifically, I wanted to know if it could help developers to mitigate any of the most dangerous software errors as identified by the <a href="http://cwe.mitre.org/top25/index.html#CWE-798">Common Weakness Enumeration</a> (CWE) community sponsored by Mitre.</p>
<p>After an email exchange with Julian, and pouring over the descriptions of the top twenty-five security bugs as reported by CWE, I determined that the Intel SSA could help to mitigate at least two of the top five errors listed.  Coming in at error number two is "OS Command Injection", and at number three was "Classic Buffer Overflow". How can SSA mitigate these errors?</p>
<p><strong>Identification and Mitigation of CWE Top Error #2 (OS Command Injection)</strong><strong><br />
</strong>OS Command Injection is an error type that really should be checked on both server and client side applications.  The essence of this error, or potential attack, is that, sometimes, your application is a bridge linking an outsider to the internals of your operating system. If your application simply passes un-trusted inputs to be fed into a command string that you pass to a system call, then your application can inadvertently wreak all kinds of havoc on the system. <em>The recommended mitigation step is to validate all inputs to your application</em>.</p>
<p>A simple minded BAD example, in "C", might be issuing a system call to delete a file that a user types in.</p>
<p><em>          // user inputs a filename to be deleted<br />
</em><em>          scanf (“%s”, str);                        // buffer overflow</em><em><br />
<em>          sprintf (cmd, "del %s", str);   // another buffer overflow</em><br />
<em>          system(cmd);                             // OS command injection, due to not validating the input</em></em></p>
<p>What happens if the user types into the input *.* rather than a normal filename?  Since the input has not been validated and was passed right to the OS<ins datetime="2012-02-06T09:55" cite="mailto:C%20Breshears">,</ins> then clearly deletions unintended by the developer would occur. </p>
<p>Analyzing your code for un-validated input is known as <em>taint analysis – tainted input means un-validated input</em>.  CWE recommends doing a taint analysis to identify where in your code you are not validating input, and then take steps to remove the taint.</p>
<p>Intel's Static Security Analysis tool uses a taint analysis algorithm to detect whether or not an unknown input has been compared against another value.  There are various rules under which taintedness is propagated from one variable to another.  One rule is that when a value is <em>compared </em>against another value this removes the taint.  If an untested value is used in a “dangerous” context, then you get an error reported by SSA.</p>
<p>The logic here is that a <em>comparison </em>is considered sufficient to sanitize the value.  The example below demonstrates the idea of tainted variable, x.  When x is used blindly with no comparisons done on it to check it validity, SSA flags this value as tainted:</p>
<p><em>          x = input;</em><br />
<em>          a[x] = 0;   // SSA identifies use of tainted value x</em></p>
<p>The example below uses a comparison operator to check the input value x, so it is considered untainted now by SSA:</p>
<p><em>          x = input;</em><br />
<em>          ok = (x &lt; 10);     // comparison un-taints the value x</em><br />
<em>          if (ok) a[x] = 0;</em></p>
<p>This "good" example might still have some issues with it, the checking is not extensive, but at least the developer went to some effort to validate the input.</p>
<p>The key take away here is to use tools to find un-validated inputs and then add the necessary validation around each of these inputs.</p>
<p><strong>Identification and Mitigation of CWE Top Error #3 (Classic Buffer Overflow)</strong><strong><br />
</strong>Michael Howard &amp; David LeBlanc, in their book <em>Writing Secure Code</em>, 2nd edition, identify the buffer overflow (AKA buffer overrun) as public enemy number one.  The Common Weakness Enumeration list is kinder, listing this issue as the number three most dangerous error.  It is well known that certain <a href="http://tldp.org/HOWTO/Secure-Programs-HOWTO/dangers-c.html">"C" functions are unsafe</a> because they are vulnerable to buffer overflow attacks. These functions should be replaced with <a href="http://msdn.microsoft.com/en-us/library/bb288454.aspx">safe counterparts</a> : <em>strcpy</em>, <em>strncpy</em>, <em>strcat</em>, and <em>gets</em>, among others. </p>
<p>The buffer overflow terminology comes from the idea that if you continue to pour water into a finite sized container, the container will eventually overflow. In computer terms, the analogy means that copying too much text into a finite sized array<span style="text-decoration: line-through;"><del datetime="2012-02-06T10:10" cite="mailto:C%20Breshears">,</del></span> will cause the extra text in the buffer to spill over into areas of memory that the developer did not intend.  These areas of memory get corrupted with the excess text and malicious coders use this to exploit your application and potentially run malicious code within the confines of your application's process. I found the following buffer overflow example insightful, though I didn't want to copy it here in its entirety and will simply link<ins datetime="2012-02-06T10:10" cite="mailto:C%20Breshears"> </ins>to it instead.  It demonstrates how an overflow attack can occur and is found on an <a href="http://blogs.msdn.com/b/roberthorvick/archive/2004/01/16/59460.aspx">MSDN blog by Robert Horvick</a>.</p>
<p>Other strains of buffer overflow can occur in some types of formatted input.  The biggest issue here is when the "%s" input format is used. This format specifier is generally regarded as unsafe. In the <a href="http://software.intel.com/sites/products/evaluation-guides/docs/intelparallelstudio-evaluationguide-ssa.pdf">Intel Parallel Studio XE evaluation guide on Static Security Analysis (SSA)</a>, there is a nice example of SSA detecting a buffer overflow in a <em>fscanf</em> function. In this case, SSA indicates that it found an "unsafe format specifier<ins datetime="2012-02-06T10:22" cite="mailto:C%20Breshears">,</ins>" which is essentially a condition that can lead to buffer overflow.  The code snippet from this guide is as follows:</p>
<p>          // example that would allow buffer overflow  <br />
<em>          char data[255];</em><em><br />
<em>          fscanf(dfile, "%s", data);</em></em><br />
<em>          if (strcmp(data, string) != 0) {</em><br />
<em>                fprintf(stderr, "parse: Expected %s, got %s \n", string, data);<br />
          }</em></p>
<p>The call to <em>fscanf </em>uses an input descriptor string with a “%s” format specifier. This reads input characters up to the next newline and stores the data in the array “data”. There is no guarantee that the number of characters read will not overflow the bounds of the array, so this statement could corrupt memory.  SSA reported this as an error and the developer should follow up by making code changes using an alternative format specifier such as the "%255s"  to limit the number of characters read in.  The corrected code should be something like this:</p>
<p><em>          // example that corrects the undesired  buffer overflow  condition<br />
</em><em>          char data[255];</em><em><br />
<em>          fscanf(dfile, "%255s", data);</em></em><br />
<em>          if (strcmp(data, string) != 0) {</em><br />
<em>                fprintf(stderr, "parse: Expected %s, got %s \n", string, data);</em><em></em></p>
<p>For similar tips on how to protect your code through defensive programming, read this article by McGraw &amp; Viega, <em><a href="http://www.ibm.com/developerworks/library/s-buffer-defend.html">Make your software behave: Preventing buffer overflows</a>.</em></p>
<p>The key take away here, in addition to validating all  inputs, is to find unsafe “C” functions and format specifiers, and replace them with safe alternatives .</p>
<p><strong>What should a developer do?</strong><br />
The security bugs discussed above are two of the most dangerous and prevalent according to CWE.  These bugs affect client applications that are run on laptops, desktops, ultrabooks, as well as enterprise applications on web servers, application servers, database servers and more.  Developers are urged to find these kinds of bugs using tools such as <a href="http://software.intel.com/sites/products/evaluation-guides/docs/intelparallelstudio-evaluationguide-ssa.pdf">Intel Static Security Analysis</a>, and then make it a practice to validate all inputs and to replace unsafe functions (<em>strcpy</em>, <em>strncpy</em>, <em>strcat</em>, and <em>gets</em>, among others)  with <a href="http://msdn.microsoft.com/en-us/library/bb288454.aspx">safe counterparts</a>.  To learn more about steps you can take as a developer to reduce your exposure to security attacks go to the Department of Homeland Security's <a href="https://buildsecurityin.us-cert.gov/bsi-rules/home/g1/816-BSI.html">Build Security In</a> website or visit the <a href="http://cwe.mitre.org/top25/index.html#CWE-798">Common Weakness Evaluation</a> site.</p>
<p>Oh, and did I mention that enterprise developers  should  jump over to Blake Dournaee's (Intel) blogs <a href="http://software.intel.com/en-us/blogs/2010/11/09/using-a-service-gateway-to-protect-against-the-owasp-top-10/">"Using a Service Gateway to Protect against the OWASP Top 10</a>" and "<a href="http://software.intel.com/en-us/blogs/2011/02/10/how-about-a-security-layer/">How about a Security Layer?"</a> to learn an even better way to secure your systems?</p>
<p>For more complete information about compiler optimizations, see our <a href="http://software.intel.com/en-us/articles/optimization-notice/">Optimization Notice</a>.</p>
<div class="feedflare">
<a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=-AvYvw2Uh_s:fybmAk2zr8A:yIl2AUoC8zA"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=yIl2AUoC8zA" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=-AvYvw2Uh_s:fybmAk2zr8A:dnMXMwOfBR0"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=dnMXMwOfBR0" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=-AvYvw2Uh_s:fybmAk2zr8A:V_sGLiPBpWU"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?i=-AvYvw2Uh_s:fybmAk2zr8A:V_sGLiPBpWU" border="0"></img></a>
</div><img src="http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~4/-AvYvw2Uh_s" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://software.intel.com/en-us/blogs/2012/02/07/intel-tool-helps-sw-developers-develop-more-secure-applications/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		<feedburner:origLink>http://software.intel.com/en-us/blogs/2012/02/07/intel-tool-helps-sw-developers-develop-more-secure-applications/</feedburner:origLink></item>
		<item>
		<title>Show 17 - Intel AppUp Show At CES 2012</title>
		<link>http://feedproxy.google.com/~r/IntelSoftwareNetworkBlog/~3/VtbGL8TZWKY/show-17-intel-appup-show-ces-2012</link>
		<comments>http://appdeveloper.intel.com/en-us/blog/2012/02/07/show-17-intel-appup-show-ces-2012#comments</comments>
		<pubDate>Tue, 07 Feb 2012 23:01:50 +0000</pubDate>
		<dc:creator>AppUp Show</dc:creator>
				<category><![CDATA[Intel® AppUp Developer Program]]></category>
		<category><![CDATA[blog]]></category>
		<category><![CDATA[Intel® Atom™]]></category>

		<guid isPermaLink="false">http://appdeveloper.intel.com/en-us/blog/2012/02/07/show-17-intel-appup-show-ces-2012</guid>
		<description><![CDATA[


Bob Duffy &#38; Gunjan Rawal host this extra-long episode of the AppUp show and cover some of the cool technologies, demos and announcements from Intel while at CES 2012. In this on location episode you will get a CES keynote wrap-up, overview of Ultrab...]]></description>
			<content:encoded><![CDATA[<p>
<object id="flashObj" width="640" height="360" classid="clsid:D27CDB6E-AE6D-11cf-96B8-444553540000" codebase="http://download.macromedia.com/pub/shockwave/cabs/flash/swflash.cab#version=9,0,47,0"><param name="movie" value="http://c.brightcove.com/services/viewer/federated_f9?isVid=1" /><param name="bgcolor" value="#FFFFFF" /><param name="flashVars" value="videoId=1439100082001&playerID=741496470001&playerKey=AQ~~,AAAArH1stHk~,LuRqJUw7MaeYQkat5frTpWWPINh71g7p&domain=embed&dynamicStreaming=true" /><param name="base" value="http://admin.brightcove.com" /><param name="seamlesstabbing" value="false" /><param name="allowFullScreen" value="true" /><param name="swLiveConnect" value="true" /><param name="allowScriptAccess" value="always" /><embed src="http://c.brightcove.com/services/viewer/federated_f9?isVid=1" bgcolor="#FFFFFF" flashVars="videoId=1439100082001&playerID=741496470001&playerKey=AQ~~,AAAArH1stHk~,LuRqJUw7MaeYQkat5frTpWWPINh71g7p&domain=embed&dynamicStreaming=true" base="http://admin.brightcove.com" name="flashObj" width="640" height="360" seamlesstabbing="false" type="application/x-shockwave-flash" allowFullScreen="true" swLiveConnect="true" allowScriptAccess="always" pluginspage="http://www.macromedia.com/shockwave/download/index.cgi?P1_Prod_Version=ShockwaveFlash"></embed></object>
</p>
<p>Bob Duffy & Gunjan Rawal host this extra-long episode of the AppUp show and cover some of the cool technologies, demos and announcements from Intel while at CES 2012. In this on location episode you will get a CES keynote wrap-up, overview of Ultrabooks, a sneak peak at the new Intel powered smartphone, reaction and insight from tech bloggers, and a demo of the Ultrabook optimized MixMan Spin Control app, now available on the Intel AppUp center. So enjoy this 25 minute AppUp slice of CES 2012
</p>
<p><a href="http://appdeveloper.intel.com/en-us/blog/2012/02/07/show-17-intel-appup-show-ces-2012" >read more</a></p><div class="feedflare">
<a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=VtbGL8TZWKY:iW4Czuhpaog:yIl2AUoC8zA"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=yIl2AUoC8zA" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=VtbGL8TZWKY:iW4Czuhpaog:dnMXMwOfBR0"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=dnMXMwOfBR0" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=VtbGL8TZWKY:iW4Czuhpaog:V_sGLiPBpWU"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?i=VtbGL8TZWKY:iW4Czuhpaog:V_sGLiPBpWU" border="0"></img></a>
</div><img src="http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~4/VtbGL8TZWKY" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://software.intel.com/en-us/blogs/2012/02/07/show-17-intel-appup-show-at-ces-2012/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		<feedburner:origLink>http://appdeveloper.intel.com/en-us/blog/2012/02/07/show-17-intel-appup-show-ces-2012</feedburner:origLink></item>
		<item>
		<title>Coarse-grained locks and Transactional Synchronization explained</title>
		<link>http://feedproxy.google.com/~r/IntelSoftwareNetworkBlog/~3/CRMtn-LmMJU/</link>
		<comments>http://software.intel.com/en-us/blogs/2012/02/07/coarse-grained-locks-and-transactional-synchronization-explained/#comments</comments>
		<pubDate>Tue, 07 Feb 2012 22:55:02 +0000</pubDate>
		<dc:creator>James Reinders (Intel)</dc:creator>
				<category><![CDATA[Parallel Programming]]></category>
		<category><![CDATA[Software Tools]]></category>
		<category><![CDATA[Haswell]]></category>
		<category><![CDATA[HLE]]></category>
		<category><![CDATA[RTM]]></category>
		<category><![CDATA[transactional memory]]></category>
		<category><![CDATA[TSX]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2012/02/07/coarse-grained-locks-and-transactional-synchronization-explained/</guid>
		<description><![CDATA[Coarse-grained locks, and the importance of transactions, are key concepts that motivate why Intel Transactional Synchronization Extensions (TSX) is useful.  I’ll do my best to explain them in this blog. In my blog “Transactional Synchronization in Haswell,” I describe new instructions (Intel TSX) that will improve the performance of coarse-grained locks.  Understanding coarse-grained locks and [...]]]></description>
			<content:encoded><![CDATA[<p>Coarse-grained locks, and the importance of transactions, are key concepts that motivate why Intel Transactional Synchronization Extensions (TSX) is useful.  I’ll do my best to explain them in this blog.</p>
<p>In my blog “<a href="../../../../2012/02/07/transactional-synchronization-in-haswell">Transactional Synchronization in Haswell</a>,” I describe new instructions (Intel TSX) that will improve the performance of coarse-grained locks.  Understanding coarse-grained locks and the concept of transactions are both key to understanding why Intel TSX matters.</p>
<p>Intel TSX may enhance performance of mutual exclusion other than simple coarse-grained locks, but I will focus on coarse-grained locking because it is common and Intel TSX allows highly concurrent accesses using only a simple locking mechanism.</p>
<p><strong>An example</strong></p>
<p>To motivate by illustration, let’s consider a simple hash table. Hash tables are used to map a <em>key</em> to a <em>key</em> and <em>value</em> pair in linear time. Two key operations are add (insert) and lookup (retrieve). Resizing and deletion are two additional operations of general interest also, but I will leave them for another time.</p>
<p>Designing a highly concurrent hash table is a non-trivial task, and there are many approaches to allow high levels of concurrency.  All these approach add complexity to the program, and often to the data structures themselves.</p>
<p>The simplest approach is a <em>single lock</em> approach. In such an approach, every operation on the hash table starts by obtaining the lock for the table and concludes by releasing the lock. While the lock is held for the operation, no other task on the system can obtain the lock and therefore no hash table operation is allowed to proceed.</p>
<p>Considering Figure 1, no concurrent operations are allowed, so each of the five operations shown would occur one at a time.</p>
<div style="text-align: center;"><img src="../../../../wordpress/wp-content/uploads/2012/01/Slide1.png" alt="" width="77%" /></p>
<p><strong>Figure 1: Five hash table operations requested</strong></div>
<p><strong>Solutions</strong></p>
<p>A common solution is to break the hash table into smaller regions, and have locks that apply to regions. While this can reduce contention, it still can create needless delays and it definitely complicates the coding and the data structure.</p>
<p>Such an approach is a prime example of taking a <strong>coarse-grained lock</strong> (a single lock for the entire hash table) and working to make it a finer grained lock (multiple locks for smaller table sections). Coarse-grained locks are easier to use, easier to understand and easier to debug.  The only disadvantage is that they tend to impede performance in a multithreaded environment. Multicore processors are increasing the likelihood of this being a problem, and help motivate new hardware assistance so that programming has a chance to stay simple more often than without assistance.</p>
<p><strong>Transactional Synchronization (Intel TSX) as a solution</strong></p>
<p><strong> </strong></p>
<p>What would be ideal, is to use the single lock (coarse-grained locking) because it is easy and not very error prone, but still have the performance of a fine-grained implementation. In our Figure 1 example, only one operation conflicts with another. This example does have more conflicts that would be expected in a real world example.</p>
<p>Considering this example, three of the operations have no collision with the other operation so the use of HLE (part of Intel TSX) on the single lock will completely elide the lock. In other words, the performance is very close to the performance of the code if no locking or unlocking code was present. The key however is that the operations are protected by the Intel TSX hardware, which has silently ensured that the protection intended by the lock is indeed assured.</p>
<p>The two operations that map to the same hash table entry will need to be staggered. This will occur even if we are unlucky enough to have them happen at the same time. In such a case, the Intel TSX will detect that the lock was indeed needed and some locking overhead will be incurred. What would actually happen in such a case, is that the colliding tasks will proceed into the protected code until the processor detects the conflict. As such a point, both updates will abort their protected code (also called the transaction). The most common solution then is to have each task proceed but actually enforce the lock on the second try. This means that one task will win, and delay the other, until the operation is complete. The precise decision on how to handle the collision is either up to the processor implementation with HLE, or the programmer with RTM. The processor implementation for HLE will also be fairly simple and conservative, in order to preserve the semantics of the original lock and hence compatibility with processors that lack Intel TSX.</p>
<p><strong>Summary</strong></p>
<p>For a hash map, Intel TSX allows for the right things to occur without losing the protection that the locks need to give. Intel TSX ensures the same results as the coarse-grained lock guarantees, but allows unrelated operations to proceed without delays that the coarse-grained locks would have caused. For more information on Transactional Synchronization, see my blog on <a href="http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell/">Intel TSX</a>.</p>
<p>Please check out the <a href="http://software.intel.com/en-us/avx/ ">specification</a> and stay tuned for information about supporting tools from Intel and others in the coming months.</p>
<div class="feedflare">
<a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=CRMtn-LmMJU:Itck-WJLNqQ:yIl2AUoC8zA"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=yIl2AUoC8zA" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=CRMtn-LmMJU:Itck-WJLNqQ:dnMXMwOfBR0"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=dnMXMwOfBR0" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=CRMtn-LmMJU:Itck-WJLNqQ:V_sGLiPBpWU"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?i=CRMtn-LmMJU:Itck-WJLNqQ:V_sGLiPBpWU" border="0"></img></a>
</div><img src="http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~4/CRMtn-LmMJU" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://software.intel.com/en-us/blogs/2012/02/07/coarse-grained-locks-and-transactional-synchronization-explained/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		<feedburner:origLink>http://software.intel.com/en-us/blogs/2012/02/07/coarse-grained-locks-and-transactional-synchronization-explained/</feedburner:origLink></item>
		<item>
		<title>Transactional Synchronization in Haswell</title>
		<link>http://feedproxy.google.com/~r/IntelSoftwareNetworkBlog/~3/PKmzaeR5Lq0/</link>
		<comments>http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell/#comments</comments>
		<pubDate>Tue, 07 Feb 2012 22:54:33 +0000</pubDate>
		<dc:creator>James Reinders (Intel)</dc:creator>
				<category><![CDATA[Parallel Programming]]></category>
		<category><![CDATA[Software Tools]]></category>
		<category><![CDATA[Haswell]]></category>
		<category><![CDATA[HLE]]></category>
		<category><![CDATA[RTM]]></category>
		<category><![CDATA[transactional memory]]></category>
		<category><![CDATA[TSX]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell/</guid>
		<description><![CDATA[We have released details of Intel® Transactional Synchronization Extensions (TSX) for the future multicore processor code-named “Haswell”. The updated specification (Intel® Architecture Instruction Set Extensions Programming Reference) can be downloaded. In this blog, I’ll introduce Intel TSX and provide a little background. Please refer to The Transactional Synchronization Extensions Chapter (Chapter 8) in the manual [...]]]></description>
			<content:encoded><![CDATA[<p>We have released details of Intel® Transactional Synchronization Extensions (TSX) for the future multicore processor code-named “Haswell”. The updated specification (Intel® Architecture Instruction Set Extensions Programming Reference) can be <a href="http://software.intel.com/en-us/avx">downloaded</a>.</p>
<p>In this blog, I’ll introduce Intel TSX and provide a little background. Please refer to The Transactional Synchronization Extensions Chapter (Chapter 8) in the <a href="http://software.intel.com/en-us/avx/">manual </a> for additional information. These new synchronization extensions (Intel TSX) are useful in shared-memory multithreaded applications that employ lock-based synchronization mechanisms.</p>
<p>In a nutshell, Intel TSX provides a set of instruction set extensions that allow programmers to specify regions of code for transactional synchronization. Programmers can use these extensions to achieve the performance of fine-grain locking while actually programming using coarse-grain locks. I have written a simple illustrative example in my blog “<a href="http://software.intel.com/en-us/blogs/2012/02/07/coarse-grained-locks-and-transactional-synchronization-explained/">Coarse-grained locks and Transactional Synchronization explained</a>.”</p>
<p>Locks are a low-level programming construct (close to the hardware), so any discussion of Intel TSX will be low level too. How Intel TSX might affect higher-level programming methods, or enable new programming models, is beyond the scope of my blog but I will briefly comment on it at the end of this blog.</p>
<p><strong>Why is this useful? </strong></p>
<p>With transactional synchronization, the hardware can determine dynamically whether threads need to serialize through lock-protected critical sections, and perform serialization only when required. This lets the processor expose and exploit concurrency that would otherwise be hidden due to dynamically unnecessary synchronization.</p>
<p>At the lowest level with Intel TSX, programmer-specified code regions (also referred to as transactional regions) are executed transactionally. If the transactional execution completes successfully, then all memory operations performed within the transactional region will appear to have occurred instantaneously when viewed from other logical processors. A processor makes architectural updates performed within the region visible to other logical processors only on a successful commit, a process referred to as an atomic commit.</p>
<p>These extensions can help achieve the performance of fine-grain locking while using coarser grain locks. These extensions can also allow locks around critical sections while avoiding unnecessary serializations. If multiple threads execute critical sections protected by the same lock but they do not perform any conflicting operations on each other’s data, then the threads can execute concurrently and without serialization. Even though the software uses lock acquisition operations on a common lock, the hardware is allowed to recognize this, <a href="http://www.merriam-webster.com/dictionary/elide">elide</a> the lock, and execute the critical sections on the two threads without requiring any communication through the lock if such communication was dynamically unnecessary.</p>
<p><strong>Intel TSX Interfaces</strong></p>
<p>Intel TSX provides two software interfaces. The first, called Hardware Lock Elision (HLE) is a legacy compatible instruction set extension (comprised of the XACQUIRE and XRELEASE prefixes) that are used to specify transactional regions. HLE is compatible with the conventional lock-based programming model. Software written using the HLE hints can run on both legacy hardware without TSX and new hardware with TSX. The second, called Restricted Transactional Memory (RTM) is a new instruction set interface (comprised of the XBEGIN, XEND, and XABORT instructions) that allows programmers to define transactional regions in a more flexible manner than is possible with HLE. Unlike the HLE extensions, but just like most new instruction set extensions, the RTM instructions will generate an undefined instruction exception (#UD) on older processors that do not support RTM. RTM also requires the programmer to provide an alternate code path for when the transactional execution is not successful.</p>
<p>In summary: “Intel Transactional Synchronization Extensions (Intel TSX) comes in two flavors: HLE and RTM. Hardware Lock Elision (HLE) is legacy compatible. Restricted Transactional Memory (RTM) offers flexibility but requires the programmer to provide an alternative code path for when transactional execution is not successful.”</p>
<p>The <a href="http://software.intel.com/en-us/avx/">specification</a> describes these extensions in detail and outlines various programming considerations to get the most out of them.</p>
<p><strong>Intel TSX Applicability</strong></p>
<p>Intel TSX targets a certain class of shared-memory multi-threaded applications; specifically multi-threaded applications that actively share data. Intel TSX is about allowing programs to achieve fine-grain lock performance without requiring the complexity of reasoning about fine-grain locking.</p>
<p>However, if there is high <em>data</em> contention the algorithm would need to change in order to have an opportunity for high scalability. There are no magic bullets that can solve the problem, since true high data contention implies that the algorithm is effectively serialized.</p>
<p><strong>Transactional Programming?</strong></p>
<p>How Intel TSX might affect higher-level programming methods, or enable new programming models, is beyond the scope of my blog. Several experimental compiler implementations, not related specifically to Intel TSX, are available including <a href="http://gcc.gnu.org/wiki/TransactionalMemory">gcc 4.7</a> which will have an experimental implementation. We can expect languages standards committees will be reviewing proposals on how to add transactional models at a language level (Intel has supported the creation of the <a href="https://sites.google.com/site/tmforcplusplus/C%2B%2BTransactionalConstructs-1.1.pdf">Draft Specification of Transaction Language Constructs for C++</a>). Intel TSX may enable a more efficient implementation of some transactional models than without Intel TSX. Much work remains to focus on real-world examples of usages and applications to develop and refine future usage. Good luck to all involved!</p>
<p>While Intel TSX may enable efficient implementations of new programming models, it does not require a new programming model and does not propose a new programming model. Intel TSX provides hardware-supported transactional-execution extensions to ease the development and improve the performance of existing programming models.</p>
<p><strong>Summary</strong></p>
<p><strong> </strong></p>
<p>Intel TSX provides extensions that allow programmers to specify regions of code for transactional execution. Programmers can use these extensions to achieve higher performance with lesser effort, for example achieve fine-grain locking performance while programming with coarser-grain locks. This is a big help and therefore big news for programmers.</p>
<p>Please check out the <a href="http://software.intel.com/en-us/avx/">specification</a> and stay tuned for information about supporting tools from Intel and others in the coming months.</p>
<div class="feedflare">
<a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=PKmzaeR5Lq0:H1qgCHrAO5Q:yIl2AUoC8zA"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=yIl2AUoC8zA" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=PKmzaeR5Lq0:H1qgCHrAO5Q:dnMXMwOfBR0"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=dnMXMwOfBR0" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=PKmzaeR5Lq0:H1qgCHrAO5Q:V_sGLiPBpWU"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?i=PKmzaeR5Lq0:H1qgCHrAO5Q:V_sGLiPBpWU" border="0"></img></a>
</div><img src="http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~4/PKmzaeR5Lq0" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		<feedburner:origLink>http://software.intel.com/en-us/blogs/2012/02/07/transactional-synchronization-in-haswell/</feedburner:origLink></item>
		<item>
		<title>Sweet 16?</title>
		<link>http://feedproxy.google.com/~r/IntelSoftwareNetworkBlog/~3/Jqh-4TEVnrs/</link>
		<comments>http://software.intel.com/en-us/blogs/2012/02/06/sweet-16/#comments</comments>
		<pubDate>Mon, 06 Feb 2012 21:59:29 +0000</pubDate>
		<dc:creator>Clay Breshears (Intel)</dc:creator>
				<category><![CDATA[Parallel Programming]]></category>
		<category><![CDATA[Power Efficiency]]></category>

		<guid isPermaLink="false">http://software.intel.com/en-us/blogs/2012/02/06/sweet-16/</guid>
		<description><![CDATA[Have we already hit the maximum number of cores that can be put in our processors? Or have the needs of the user and developer communities been served at sixteen cores?]]></description>
			<content:encoded><![CDATA[<p>I just saw the article "<a title="AMD calls end to core growth on server chips" href="http://news.techworld.com/data-centre/3334884/amd-calls-end-ot-core-growth-on-server-chips/">AMD calls end to core growth on server chips</a>" at Techworld.com. The gist of the article is that AMD has decided to produce server chips with no more than 16 cores. There were some interesting future directions outlined and hinted at by the end of the article, too.</p>
<p>What seemed most disturbing to me was the limit on the number of cores being self-inflicted. Surely we can't have reached the maximum number of cores that are possible to squeeze onto a chip? The whole "right turn" idea to add cores rather than try to cool processors reaching rocket engine temperatures was less than 10 years ago. I'm not sure where the physics starts to overshadow Moore's Law, but I thought I'd  heard that a few more generations of smaller wire sizes in processor dies were still possible. So why not push more and more cores into the same package?</p>
<p>It might be that the average server application (and, perhaps even more so, consumer applications) can't scale well beyond some fixed number of cores. How many cores does it take to type and post a tweet or update your Facebook status or to watch a streaming video? Would any of those tasks be faster or somehow enhanced if there were twice the number of cores available?</p>
<p>If we stop increasing the core counts in the next 5 years, how will new chips keep fulfilling the ever-growing hunger for more performance by consumers? Maybe it won't be about faster and faster application exeuction, but more about less energy consumption while maintaining a level of performance. I guess at some point we'll stop being concerned about Gigahertz or core counts because all processors will be able to do many of the same tasks in about the same amount of time.</p>
<p>I do know that power consumption is going to be a major driving design force as HPC moves closer toward Exascale platforms.  Thus, if the THX-1138 processor draws power twice as fast as the CFM602 processor, I would be more likely to build my system equipped with the former.</p>
<div class="feedflare">
<a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=Jqh-4TEVnrs:khQk4WqrqvQ:yIl2AUoC8zA"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=yIl2AUoC8zA" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=Jqh-4TEVnrs:khQk4WqrqvQ:dnMXMwOfBR0"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=dnMXMwOfBR0" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=Jqh-4TEVnrs:khQk4WqrqvQ:V_sGLiPBpWU"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?i=Jqh-4TEVnrs:khQk4WqrqvQ:V_sGLiPBpWU" border="0"></img></a>
</div><img src="http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~4/Jqh-4TEVnrs" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://software.intel.com/en-us/blogs/2012/02/06/sweet-16/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		<feedburner:origLink>http://software.intel.com/en-us/blogs/2012/02/06/sweet-16/</feedburner:origLink></item>
		<item>
		<title>Loading local XML files with JavaScript</title>
		<link>http://feedproxy.google.com/~r/IntelSoftwareNetworkBlog/~3/_Rj6beng99k/loading-local-xml-files-javascript</link>
		<comments>http://appdeveloper.intel.com/en-us/blog/2012/02/06/loading-local-xml-files-javascript#comments</comments>
		<pubDate>Mon, 06 Feb 2012 16:07:56 +0000</pubDate>
		<dc:creator>Sulamita Garcia</dc:creator>
				<category><![CDATA[Intel® AppUp Developer Program]]></category>
		<category><![CDATA[cross-platform]]></category>
		<category><![CDATA[html5]]></category>
		<category><![CDATA[Intel® Atom™]]></category>
		<category><![CDATA[Support]]></category>

		<guid isPermaLink="false">http://appdeveloper.intel.com/en-us/blog/2012/02/06/loading-local-xml-files-javascript</guid>
		<description><![CDATA[I’m developing a test application that is helping me to understand much better the new possibilities of HTML5. I have been using maps, queries and quite a lot of CSS to make it more pleasant. I will write about them later, but for now I would like to...]]></description>
			<content:encoded><![CDATA[<p><span style="font-size: small;">I’m developing a test application that is helping me to understand much better the new possibilities of HTML5. I have been using maps, queries and quite a lot of CSS to make it more pleasant. I will write about them later, but for now I would like to focus on one issue I found myself dealing with, and may be other developers with the same issue.</span></p><p><a href="http://appdeveloper.intel.com/en-us/blog/2012/02/06/loading-local-xml-files-javascript" >read more</a></p><div class="feedflare">
<a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=_Rj6beng99k:W4hvwY9WFiI:yIl2AUoC8zA"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=yIl2AUoC8zA" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=_Rj6beng99k:W4hvwY9WFiI:dnMXMwOfBR0"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=dnMXMwOfBR0" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=_Rj6beng99k:W4hvwY9WFiI:V_sGLiPBpWU"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?i=_Rj6beng99k:W4hvwY9WFiI:V_sGLiPBpWU" border="0"></img></a>
</div><img src="http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~4/_Rj6beng99k" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://software.intel.com/en-us/blogs/2012/02/06/loading-local-xml-files-with-javascript/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		<feedburner:origLink>http://appdeveloper.intel.com/en-us/blog/2012/02/06/loading-local-xml-files-javascript</feedburner:origLink></item>
		<item>
		<title>Hack your way to an Ultrabook at Angel Hack 2 (SF &amp; Boston)</title>
		<link>http://feedproxy.google.com/~r/IntelSoftwareNetworkBlog/~3/BL1KPLk0PVg/hack-your-way-ultrabook-angel-hack-2-sf-boston</link>
		<comments>http://appdeveloper.intel.com/en-us/blog/2012/02/03/hack-your-way-ultrabook-angel-hack-2-sf-boston#comments</comments>
		<pubDate>Fri, 03 Feb 2012 22:57:02 +0000</pubDate>
		<dc:creator>Gina M Bovara</dc:creator>
				<category><![CDATA[Intel® AppUp Developer Program]]></category>
		<category><![CDATA[Intel® Atom™]]></category>

		<guid isPermaLink="false">http://appdeveloper.intel.com/en-us/blog/2012/02/03/hack-your-way-ultrabook-angel-hack-2-sf-boston</guid>
		<description><![CDATA[Think you've got what it takes to code an Intel AppUp app in 30 hours?  For those that are up to the challenge, check out the AngelHack 2 hackathon happening in San Francisco and Boston, March 3-5, 2012.  read more]]></description>
			<content:encoded><![CDATA[<img src="http://www.solidliquiddesigns.com/images/angelhack.jpg" border="0" width="350" /><br /><br />Think you've got what it takes to code an Intel AppUp app in 30 hours?  For those that are up to the challenge, check out the <a href="http://www.angelhack.com" >AngelHack 2 hackathon</a> happening in San Francisco and Boston, March 3-5, 2012.  <br /><p><a href="http://appdeveloper.intel.com/en-us/blog/2012/02/03/hack-your-way-ultrabook-angel-hack-2-sf-boston" >read more</a></p><div class="feedflare">
<a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=BL1KPLk0PVg:8luC6X2r3_s:yIl2AUoC8zA"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=yIl2AUoC8zA" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=BL1KPLk0PVg:8luC6X2r3_s:dnMXMwOfBR0"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=dnMXMwOfBR0" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=BL1KPLk0PVg:8luC6X2r3_s:V_sGLiPBpWU"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?i=BL1KPLk0PVg:8luC6X2r3_s:V_sGLiPBpWU" border="0"></img></a>
</div><img src="http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~4/BL1KPLk0PVg" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://software.intel.com/en-us/blogs/2012/02/03/hack-your-way-to-an-ultrabook-at-angel-hack-2-sf-amp-boston/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		<feedburner:origLink>http://appdeveloper.intel.com/en-us/blog/2012/02/03/hack-your-way-ultrabook-angel-hack-2-sf-boston</feedburner:origLink></item>
		<item>
		<title>Show 16 – SkypeUp with Black Belt Developer Blue Innovations</title>
		<link>http://feedproxy.google.com/~r/IntelSoftwareNetworkBlog/~3/e8cvlBKi_wk/show-16-skypeup-black-belt-developer-blue-innovations</link>
		<comments>http://appdeveloper.intel.com/en-us/blog/2012/02/02/show-16-skypeup-black-belt-developer-blue-innovations#comments</comments>
		<pubDate>Thu, 02 Feb 2012 23:24:08 +0000</pubDate>
		<dc:creator>AppUp Show</dc:creator>
				<category><![CDATA[Intel® AppUp Developer Program]]></category>
		<category><![CDATA[blog]]></category>
		<category><![CDATA[cross-platform]]></category>
		<category><![CDATA[Intel® Atom™]]></category>

		<guid isPermaLink="false">http://appdeveloper.intel.com/en-us/blog/2012/02/02/show-16-skypeup-black-belt-developer-blue-innovations</guid>
		<description><![CDATA[

read more]]></description>
			<content:encoded><![CDATA[<p>
<iframe width="560" height="315" src="http://www.youtube.com/embed/XSLBZSlQFc8" frameborder="0" allowfullscreen></iframe>
</p><p><a href="http://appdeveloper.intel.com/en-us/blog/2012/02/02/show-16-skypeup-black-belt-developer-blue-innovations" >read more</a></p><div class="feedflare">
<a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=e8cvlBKi_wk:ZCn3DmK6_Ak:yIl2AUoC8zA"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=yIl2AUoC8zA" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=e8cvlBKi_wk:ZCn3DmK6_Ak:dnMXMwOfBR0"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=dnMXMwOfBR0" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=e8cvlBKi_wk:ZCn3DmK6_Ak:V_sGLiPBpWU"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?i=e8cvlBKi_wk:ZCn3DmK6_Ak:V_sGLiPBpWU" border="0"></img></a>
</div><img src="http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~4/e8cvlBKi_wk" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://software.intel.com/en-us/blogs/2012/02/02/show-16-skypeup-with-black-belt-developer-blue-innovations/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		<feedburner:origLink>http://appdeveloper.intel.com/en-us/blog/2012/02/02/show-16-skypeup-black-belt-developer-blue-innovations</feedburner:origLink></item>
		<item>
		<title>Intel AppUp at the Game Developers Conference, March 5-9</title>
		<link>http://feedproxy.google.com/~r/IntelSoftwareNetworkBlog/~3/B9TBTS5ZrdI/intel-appup-game-developers-conference-march-5-9</link>
		<comments>http://appdeveloper.intel.com/en-us/blog/2012/02/01/intel-appup-game-developers-conference-march-5-9#comments</comments>
		<pubDate>Wed, 01 Feb 2012 16:27:40 +0000</pubDate>
		<dc:creator>Gina M Bovara</dc:creator>
				<category><![CDATA[Game Development]]></category>
		<category><![CDATA[Intel® AppUp Developer Program]]></category>
		<category><![CDATA[cross-platform]]></category>
		<category><![CDATA[Intel® Atom™]]></category>

		<guid isPermaLink="false">http://appdeveloper.intel.com/en-us/blog/2012/02/01/intel-appup-game-developers-conference-march-5-9</guid>
		<description><![CDATA[It's that time of year, again - we can't wait to see you all at the 25th annual Game Developers Conference in San Francisco, March 5-9, 2012!

The Intel AppUp developer program team will be at the event in full force and we'll be looking to meet you an...]]></description>
			<content:encoded><![CDATA[<img src="http://software.intel.com/file/40372/" width="300" /><br /><br />It's that time of year, again - we can't wait to see you all at the 25th annual <a href="http://www.gdconf.com/" >Game Developers Conference</a> in San Francisco, March 5-9, 2012!<br /><br />

The Intel AppUp developer program team will be at the event in full force and we'll be looking to meet you and hear about your apps!  Some of our activities at the show include:<br /><p><a href="http://appdeveloper.intel.com/en-us/blog/2012/02/01/intel-appup-game-developers-conference-march-5-9" >read more</a></p><div class="feedflare">
<a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=B9TBTS5ZrdI:FEHVnmyVq3E:yIl2AUoC8zA"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=yIl2AUoC8zA" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=B9TBTS5ZrdI:FEHVnmyVq3E:dnMXMwOfBR0"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?d=dnMXMwOfBR0" border="0"></img></a> <a href="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?a=B9TBTS5ZrdI:FEHVnmyVq3E:V_sGLiPBpWU"><img src="http://feeds.feedburner.com/~ff/IntelSoftwareNetworkBlog?i=B9TBTS5ZrdI:FEHVnmyVq3E:V_sGLiPBpWU" border="0"></img></a>
</div><img src="http://feeds.feedburner.com/~r/IntelSoftwareNetworkBlog/~4/B9TBTS5ZrdI" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://software.intel.com/en-us/blogs/2012/02/01/intel-appup-at-the-game-developers-conference-march-5-9/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		<feedburner:origLink>http://appdeveloper.intel.com/en-us/blog/2012/02/01/intel-appup-game-developers-conference-march-5-9</feedburner:origLink></item>
	</channel>
</rss>

