MAGMA Flow Concepts

Import the RTL Design

2010-09-21T10:53:00.000-07:00

Import the RTL Design

Step - 1: Now import your RTL code in a sequence of top module file is followed by the rest of the design files. For purpose of clear explanation here we are using a standard AES design. It is designed using verilog and whose topmodule name is "aes_cipher_top". AES design contains the following verilog files.

aes_cipher_top.v (Top Module)
aes_sbox.v
aes_rcon.v
aes_key_expand_128.v

Step - 2: "import rtl" reads the RTL files. To analyze RTL code use "-analyze" at the end. "-analyze" is optional command.

mantle[0]:> import rtl aes_cipher_top.v aes_sbox.v aes_rcon.v aes_key_expand_128.v

mantle[0]:>import rtl aes_cipher_top.v aes_sbox.v aes_rcon.v aes_key_expand_128.v
MSG-10   While running 'import rtl aes_cipher_top.v aes_sbox.v aes_rcon.v
         aes_key_expand_128.v':
RTL-3    Building model aes_cipher_top(aes_cipher_top)
RTL-3    Building model aes_key_expand_128(aes_key_expand_128)
RTL-3    Building model aes_sbox(aes_sbox)
RTL-3    Building model aes_rcon(aes_rcon)
/work/aes_cipher_top/aes_cipher_top

Step - 3: "set m" set the variable for the top level Design. In this design the top level model is "/work/aes_cipher_top/aes_cipher_top". The top level model path is displayed at the end of the report of the "import rtl" command.

mantle[0]:>set m /work/aes_cipher_top/aes_cipher_top

mantle[4]:>set m /work/aes_cipher_top/aes_cipher_top
/work/aes_cipher_top/aes_cipher_top

Step - 4: "fix rtl" performs RTL optimizations.

mantle[5]:> fix rtl $m

mantle[5]:> fix rtl $m ################### Starting Standard fix rtl #################### MSG-10 While running 'run rtl expression /work/aes_cipher_top/aes_cipher_top': EXP-4 Labeling datapath cells EXP-5 Grouping datapath cells into expression models EXP-6 Flattening expressions for expression models EXP-7 Resource sharing over flat expressions EXP-8 Generating DPF for expression models CMD-8 cputime 0.4 minutes, walltime 0.4 minutes, process memory 133.4 MB, peak memory 144.4 MB, command "run rtl implement /work/aes_cipher_top/aes_cipher_top" MSG-10 While running 'export verilog equation /work/aes_cipher_top/aes_cipher_top snap/aes_cipher_top%fix-rtl-final%vereqn.veq': WRI-2 Writing file snap/aes_cipher_top%fix-rtl-final%vereqn.veq. MSG-10 While running 'export volcano snap/aes_cipher_top%fix-rtl-final.volcano': LAVA-26 Writing library /cl013lv LAVA-26 Writing library /work LAVA-26 Writing library /macro_lib LAVA-900 Successfully froze lava into volcano snap/aes_cipher_top%fix-rtl-final.volcano: 1 seconds, 1 on cpu. LAVA-248 Volcano file size: 55.8 MByte, data compression was not used. LAVA-251 Data throughput 44.352 MB/s (1.26 s elapsed) ################### Finished Standard fix rtl #################### CMD-8 cputime 0.4 minutes, walltime 0.4 minutes, process memory 133.4 MB, peak memory 144.4 MB, command "fix rtl /work/aes_cipher_top/aes_cipher_top"

Step - 5: "fix netlist" performs the logical optimizations.

mantle[5]:> fix netlist $m $l

Step - 6: "export verilog netlist" saves the verilog netlist file to specified file name for example "filename_netlist.v". The proper usage of export command is shown below.

mantle[6]:> export verilog netlist $m aes_cipher_top_netlist.v

mantle[6]:>export verilog netlist $m aes_cipher_top_netlist.v

MSG-10   While running 'export verilog netlist /work/aes_cipher_top/aes_cipher_top

         aes_cipher_top_netlist.v':

WRI-2    Writing file aes_cipher_top_netlist.v.

Note: The Netlist to GDSII flow will start from next point. You can import any netlist file to the magma flow.

Step - 7: "run bind logical" will bind the unbound cells to the target library.

mantle[7]:> run bind logical $m $l

mantle[7]:>run bind logical $m $l

MSG-10   While running 'run bind logical /work/aes_cipher_top/aes_cipher_top /cl013lv':

BND-3    Binding model /work/aes_cipher_top/aes_cipher_top to library /cl013lv

BND-4    All cells bound in model /work/aes_cipher_top/aes_cipher_top

Step - 8: "report model" Checks the model for basic netlist and floorplan integrity (for example, cell overlap and dangling input pins, etc.,).

mantle[8]:> report model $m

mantle[8]:>report model $m

MSG-10   While running 'report model /work/aes_cipher_top/aes_cipher_top':

CK-5 Collecting data on model aes_cipher_top .....

------------------- M O D E L  S T A T I S T I C S ------------------

Generated for user temp on host vlsi2             on Thu Mar  1 13:30:20 2007

Model: /work/aes_cipher_top/aes_cipher_top

Cell Statistics                - count -    - area -         - legend -

  Super cells:                      12402      0.174mm2         (s)

  Bound cells:                         24      (without layout data)

  Constant cells:                     524

  Total cells:                      12950      0.174mm2

Net Statistics

  Number of signal nets:         13815

  Number of power/clock nets:        0

  Number of cell pins:           50077

  Average pins per signal net:    3.70       (maximum = 1668)

Dangling Pin Statistics

  Dangling cell pins:              276       (0 dangling input pins)

  Dangling model pins:              14

  Estimated signal wire length:   7.653       meter

CK-16    Use 'check model /work/aes_cipher_top/aes_cipher_top' to check its sanity.

---------------------------------------------------------------------

force timing clock {/work/aes_cipher_top/aes_cipher_top/mpin:clk}

NEXT---->>>>>Import Design Constraints

The Magma RTL to GDSII using command prompt- Part 1

2010-09-20T03:57:00.000-07:00

The detailed flow is explained in the three stages as follows:

Stage 1: Invoking Mantle, Import RTL Design and Imoport Design Constraints

Invoking Mantle

Step - 1: Create a directory where you want put all your magma synthesis documents. In this example, aes is the working directory.

bash-2.05b$ mkdir aes

This will create a directory called "aes" . Copy your all RTL Code in to the created directory. Then go to the directory to invoke the magma tool.

bash-2.05b$ cd aes

Step - 2: Invoke the mantle using the path "/magma/2004_12_29.0014/linux24_x86_64/bin/mantle". Mantle is the command prompt of the Magma Blast Fusion Tool.

bash-2.05b$ /magma/2004_12_29.0014/linux24_x86_64/bin/mantle

MEM-4 WARNING: Unusually large stacksize of 17592186044416.0MB reserved by

user's shell resource limits. This may inhibit utilization of all

available system memory resources. Recommended is 8000k

mantle version 4.1.57-linux24_x86_64 (compiled Dec 28 2004 23:43:34)

LIC-1 Setting default license file to

'/magma/2004_12_29.0014/common/license'.

LIC-12 The following features have been checked out: BLAST_VIEW BLAST_WRAP

BLAST_SPEED BLAST_BUILDER BLAST_PLAN BLAST_RTL BLAST_LOGIC BLAST_SI

BLAST_RAIL

OSD-100 Running /magma/2004_12_29.0014/linux24_x86_64/bin/mantle on host

"vlsi2" with pid 30575 for user "temp" started on Thu Mar 01

01:18:55 PM IST 2007 in directory /home/temp/noors/aes

mantle[1]>

Note: If you have any problem in opening the mantle please contact to CS623 TAs. If you come across any error stating Error UI-39 in invoking the tool ask System Administrator to run "nscd" demon. If you come across any license related problems, then use "export LM_LICENSE_FILE=2700@10.6.5.27" at your command prompt. Still if you have any problem please contact System Administrator.

Directory Structure Generated by Magma

Files generated by Magma: You can also review the contents of two automatically-generated directories. The logfiles directory contains logs of the sessions you run, and the snap directory contains volcanos and reports of design statistics that reflect the design at the end of each part of the flow.

Logfiles Directory: When you start the tool, a file called mantle.log is created. This file is usually the most useful file in the logfiles directory. It contains a full record of your latest session. With each new session you start, the file is renamed to mantle#.log (# is a number) and the mantle.log file is overwritten with the latest information. In the tool, to find where the file has been saved, use the query logfile command.

Snap Directory: The snap directory is created locally in the directory where you have started the tool. This directory stores snapshot volcanos and status reports that show design statistics during the flow. Use a text editor to review the snapshot reports or use a snapshot volcano to rerun the flow from a specific step. There are several config, query and report commands related to snap, which are identified in the man pages.

Step - 3: To invoke the Graphical User Interface (GUI) use the following command.

mantle[1]> ui start

The above command will opens the GUI based work space of the Magma Blast Fusion.

Importing the Library Volcano

To use the provided design library, import the library and technology rules together in the form of a Volcano. A Volcano is a Magma database that stores design information.

Step - 4: Import the library using the following command where all the logic cells are stored. (Please verify the library path with course TA). In this example we are using the Magma 130nm library cell for synthesis. Import volcano command reads the data model from a disk.

mantle[0]:> import volcano /magma/cl013lv.volcano

mantle[0]:>import volcano /magma/cl013lv.volcano

MSG-10 While running 'import volcano /magma/cl013lv.volcano':

LAVA-333 This volcano erupted Tue Jan 21 12:42:38 2003 EST for user jwalston (Joe Walston)

(v14c1)

LAVA-24 'import volcano' importing global config settings from volcano, existing settings

maybe overwritten

LAVA-27 Reading library /cl013lv

LAVA-874 All cells were bound as a result of this 'import volcano'.

LAVA-902 Melted back from volcano '/magma/cl013lv.volcano' ( 2 seconds elapsed of which

2 on CPU).

LAVA-249 Volcano file size: 34.6 MByte (57.1 MB data, Compression = 1.65x)

LAVA-251 Data throughput 21.631 MB/s (2.64 s elapsed)

"Set l " set the variable for library name. The library name that we are using is cl013lv.

mantle[0]:>set l /cl013l

mantle[0]:>set l /cl013lv /cl013lv

Next ---->>>>Import the RTL Design

Sample Verilog File

2010-09-20T03:31:00.000-07:00

/////////////////////////////////////////////////////////////////////
////                                                             ////
////  AES Cipher Top Level                                       ////
////                                                             ////
////                                                             ////
////  Author: Rudolf Usselmann                                   ////
////          rudi@asics.ws                                      ////
////                                                             ////
////                                                             ////
////  Downloaded from: http://www.opencores.org/cores/aes_core/  ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann                    ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws                       ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////

//  CVS Log
//
//  $Id: aes_cipher_top.v,v 1.1 2002/11/09 11:22:48 rudi Exp $
//
//  $Date: 2002/11/09 11:22:48 $
//  $Revision: 1.1 $
//  $Author: rudi $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: aes_cipher_top.v,v $
//               Revision 1.1  2002/11/09 11:22:48  rudi
//               Initial revision
//
//
//
//
//
//


module aes_cipher_top(clk, rst, ld, done, key, text_in, text_out );
input  clk, rst;
input  ld;
output  done;
input [127:0] key;
input [127:0] text_in;
output [127:0] text_out;

////////////////////////////////////////////////////////////////////
//
// Local Wires
//

wire [31:0] w0, w1, w2, w3;
reg [127:0] text_in_r;
reg [127:0] text_out;
reg [7:0] sa00, sa01, sa02, sa03;
reg [7:0] sa10, sa11, sa12, sa13;
reg [7:0] sa20, sa21, sa22, sa23;
reg [7:0] sa30, sa31, sa32, sa33;
wire [7:0] sa00_next, sa01_next, sa02_next, sa03_next;
wire [7:0] sa10_next, sa11_next, sa12_next, sa13_next;
wire [7:0] sa20_next, sa21_next, sa22_next, sa23_next;
wire [7:0] sa30_next, sa31_next, sa32_next, sa33_next;
wire [7:0] sa00_sub, sa01_sub, sa02_sub, sa03_sub;
wire [7:0] sa10_sub, sa11_sub, sa12_sub, sa13_sub;
wire [7:0] sa20_sub, sa21_sub, sa22_sub, sa23_sub;
wire [7:0] sa30_sub, sa31_sub, sa32_sub, sa33_sub;
wire [7:0] sa00_sr, sa01_sr, sa02_sr, sa03_sr;
wire [7:0] sa10_sr, sa11_sr, sa12_sr, sa13_sr;
wire [7:0] sa20_sr, sa21_sr, sa22_sr, sa23_sr;
wire [7:0] sa30_sr, sa31_sr, sa32_sr, sa33_sr;
wire [7:0] sa00_mc, sa01_mc, sa02_mc, sa03_mc;
wire [7:0] sa10_mc, sa11_mc, sa12_mc, sa13_mc;
wire [7:0] sa20_mc, sa21_mc, sa22_mc, sa23_mc;
wire [7:0] sa30_mc, sa31_mc, sa32_mc, sa33_mc;
reg  done, ld_r;
reg [3:0] dcnt;

////////////////////////////////////////////////////////////////////
//
// Misc Logic
//

always @(posedge clk)
 if(!rst) dcnt &lt;= 4'h0;
 else
 if(ld)  dcnt &lt;= 4'hb;
 else
 if(|dcnt) dcnt &lt;= dcnt - 4'h1;

always @(posedge clk) done &lt;=  !(|dcnt[3:1]) &amp; dcnt[0] &amp; !ld;
always @(posedge clk) if(ld) text_in_r &lt;=  text_in;
always @(posedge clk) ld_r &lt;=  ld;

////////////////////////////////////////////////////////////////////
//
// Initial Permutation (AddRoundKey)
//

always @(posedge clk) sa33 &lt;=  ld_r ? text_in_r[007:000] ^ w3[07:00] : sa33_next;
always @(posedge clk) sa23 &lt;=  ld_r ? text_in_r[015:008] ^ w3[15:08] : sa23_next;
always @(posedge clk) sa13 &lt;=  ld_r ? text_in_r[023:016] ^ w3[23:16] : sa13_next;
always @(posedge clk) sa03 &lt;=  ld_r ? text_in_r[031:024] ^ w3[31:24] : sa03_next;
always @(posedge clk) sa32 &lt;=  ld_r ? text_in_r[039:032] ^ w2[07:00] : sa32_next;
always @(posedge clk) sa22 &lt;=  ld_r ? text_in_r[047:040] ^ w2[15:08] : sa22_next;
always @(posedge clk) sa12 &lt;=  ld_r ? text_in_r[055:048] ^ w2[23:16] : sa12_next;
always @(posedge clk) sa02 &lt;=  ld_r ? text_in_r[063:056] ^ w2[31:24] : sa02_next;
always @(posedge clk) sa31 &lt;=  ld_r ? text_in_r[071:064] ^ w1[07:00] : sa31_next;
always @(posedge clk) sa21 &lt;=  ld_r ? text_in_r[079:072] ^ w1[15:08] : sa21_next;
always @(posedge clk) sa11 &lt;=  ld_r ? text_in_r[087:080] ^ w1[23:16] : sa11_next;
always @(posedge clk) sa01 &lt;=  ld_r ? text_in_r[095:088] ^ w1[31:24] : sa01_next;
always @(posedge clk) sa30 &lt;=  ld_r ? text_in_r[103:096] ^ w0[07:00] : sa30_next;
always @(posedge clk) sa20 &lt;=  ld_r ? text_in_r[111:104] ^ w0[15:08] : sa20_next;
always @(posedge clk) sa10 &lt;=  ld_r ? text_in_r[119:112] ^ w0[23:16] : sa10_next;
always @(posedge clk) sa00 &lt;=  ld_r ? text_in_r[127:120] ^ w0[31:24] : sa00_next;

////////////////////////////////////////////////////////////////////
//
// Round Permutations
//

assign sa00_sr = sa00_sub;
assign sa01_sr = sa01_sub;
assign sa02_sr = sa02_sub;
assign sa03_sr = sa03_sub;
assign sa10_sr = sa11_sub;
assign sa11_sr = sa12_sub;
assign sa12_sr = sa13_sub;
assign sa13_sr = sa10_sub;
assign sa20_sr = sa22_sub;
assign sa21_sr = sa23_sub;
assign sa22_sr = sa20_sub;
assign sa23_sr = sa21_sub;
assign sa30_sr = sa33_sub;
assign sa31_sr = sa30_sub;
assign sa32_sr = sa31_sub;
assign sa33_sr = sa32_sub;
assign {sa00_mc, sa10_mc, sa20_mc, sa30_mc}  = mix_col(sa00_sr,sa10_sr,sa20_sr,sa30_sr);
assign {sa01_mc, sa11_mc, sa21_mc, sa31_mc}  = mix_col(sa01_sr,sa11_sr,sa21_sr,sa31_sr);
assign {sa02_mc, sa12_mc, sa22_mc, sa32_mc}  = mix_col(sa02_sr,sa12_sr,sa22_sr,sa32_sr);
assign {sa03_mc, sa13_mc, sa23_mc, sa33_mc}  = mix_col(sa03_sr,sa13_sr,sa23_sr,sa33_sr);
assign sa00_next = sa00_mc ^ w0[31:24];
assign sa01_next = sa01_mc ^ w1[31:24];
assign sa02_next = sa02_mc ^ w2[31:24];
assign sa03_next = sa03_mc ^ w3[31:24];
assign sa10_next = sa10_mc ^ w0[23:16];
assign sa11_next = sa11_mc ^ w1[23:16];
assign sa12_next = sa12_mc ^ w2[23:16];
assign sa13_next = sa13_mc ^ w3[23:16];
assign sa20_next = sa20_mc ^ w0[15:08];
assign sa21_next = sa21_mc ^ w1[15:08];
assign sa22_next = sa22_mc ^ w2[15:08];
assign sa23_next = sa23_mc ^ w3[15:08];
assign sa30_next = sa30_mc ^ w0[07:00];
assign sa31_next = sa31_mc ^ w1[07:00];
assign sa32_next = sa32_mc ^ w2[07:00];
assign sa33_next = sa33_mc ^ w3[07:00];

////////////////////////////////////////////////////////////////////
//
// Final text output
//

always @(posedge clk) text_out[127:120] &lt;=  sa00_sr ^ w0[31:24];
always @(posedge clk) text_out[095:088] &lt;=  sa01_sr ^ w1[31:24];
always @(posedge clk) text_out[063:056] &lt;=  sa02_sr ^ w2[31:24];
always @(posedge clk) text_out[031:024] &lt;=  sa03_sr ^ w3[31:24];
always @(posedge clk) text_out[119:112] &lt;=  sa10_sr ^ w0[23:16];
always @(posedge clk) text_out[087:080] &lt;=  sa11_sr ^ w1[23:16];
always @(posedge clk) text_out[055:048] &lt;=  sa12_sr ^ w2[23:16];
always @(posedge clk) text_out[023:016] &lt;=  sa13_sr ^ w3[23:16];
always @(posedge clk) text_out[111:104] &lt;=  sa20_sr ^ w0[15:08];
always @(posedge clk) text_out[079:072] &lt;=  sa21_sr ^ w1[15:08];
always @(posedge clk) text_out[047:040] &lt;=  sa22_sr ^ w2[15:08];
always @(posedge clk) text_out[015:008] &lt;=  sa23_sr ^ w3[15:08];
always @(posedge clk) text_out[103:096] &lt;=  sa30_sr ^ w0[07:00];
always @(posedge clk) text_out[071:064] &lt;=  sa31_sr ^ w1[07:00];
always @(posedge clk) text_out[039:032] &lt;=  sa32_sr ^ w2[07:00];
always @(posedge clk) text_out[007:000] &lt;=  sa33_sr ^ w3[07:00];

////////////////////////////////////////////////////////////////////
//
// Generic Functions
//

function [31:0] mix_col;
input [7:0] s0,s1,s2,s3;
reg [7:0] s0_o,s1_o,s2_o,s3_o;
begin
mix_col[31:24]=xtime(s0)^xtime(s1)^s1^s2^s3;
mix_col[23:16]=s0^xtime(s1)^xtime(s2)^s2^s3;
mix_col[15:08]=s0^s1^xtime(s2)^xtime(s3)^s3;
mix_col[07:00]=xtime(s0)^s0^s1^s2^xtime(s3);
end
endfunction

function [7:0] xtime;
input [7:0] b; xtime={b[6:0],1'b0}^(8'h1b&amp;{8{b[7]}});
endfunction

////////////////////////////////////////////////////////////////////
//
// Modules
//

aes_key_expand_128 u0(
 .clk(  clk ),
 .kld(  ld ),
 .key(  key ),
 .wo_0(  w0 ),
 .wo_1(  w1 ),
 .wo_2(  w2 ),
 .wo_3(  w3 ));

aes_sbox us00( .a( sa00 ), .d( sa00_sub ));
aes_sbox us01( .a( sa01 ), .d( sa01_sub ));
aes_sbox us02( .a( sa02 ), .d( sa02_sub ));
aes_sbox us03( .a( sa03 ), .d( sa03_sub ));
aes_sbox us10( .a( sa10 ), .d( sa10_sub ));
aes_sbox us11( .a( sa11 ), .d( sa11_sub ));
aes_sbox us12( .a( sa12 ), .d( sa12_sub ));
aes_sbox us13( .a( sa13 ), .d( sa13_sub ));
aes_sbox us20( .a( sa20 ), .d( sa20_sub ));
aes_sbox us21( .a( sa21 ), .d( sa21_sub ));
aes_sbox us22( .a( sa22 ), .d( sa22_sub ));
aes_sbox us23( .a( sa23 ), .d( sa23_sub ));
aes_sbox us30( .a( sa30 ), .d( sa30_sub ));
aes_sbox us31( .a( sa31 ), .d( sa31_sub ));
aes_sbox us32( .a( sa32 ), .d( sa32_sub ));
aes_sbox us33( .a( sa33 ), .d( sa33_sub ));

endmodule

Magma ASIC Design Script

2010-09-20T01:55:00.000-07:00

#########################################
# Magma ASIC Design Script
#########################################

import volcano /magma/cl013lv.volcano
set l /cl013lv

###########################################
#     Import RTL Design
###########################################
import rtl aes_cipher_top.v aes_sbox.v aes_rcon.v aes_key_expand_128.v
set m /work/aes_cipher_top/aes_cipher_top
fix rtl $m
fix netlist $m $l
export verilog netlist $m aes_cipher_top_netlist.v
run bind logical $m $l
report model $m

#############################################
#     Import Design Constraints
#############################################
force timing clock {/work/aes_cipher_top/aes_cipher_top/mpin:clk} 1000n -waveform {-rise 5n -fall 10n}
report force timing $m
force wire model constant $m
report timing summary $m
check timing $m
data flatten $m
run gate sweep $m

#############################################
#     Logic Optimization
#############################################
fix time $m $l
report timing summary $m
report model $m
run bind logical $m $l

##############################################
#     Floor Planning
##############################################
run bind physical $m $l
run prepare lib $l
clear readonly /cl013lv
force plan net VDD $m -port VDD -usage
force plan net VSS $m -port VSS -usage ground
force plan chip $m -width 400u -height 400u -left_clearance 2.6u -right_clearance 2.6u -top_clearance 2.6u -bottom_clearance 2.6u
run plan create chip $m
run floorplan apply $m
run plan create pin $m
run place global $m
export volcano aes_floorplan.volcano

#################################################
#     GUI Power Plan
# Power plan can be done using the GUI
#     Power Rings
#     Power Mesh
#     Power Rails
#################################################
check route drc $m -power_only
run route power2 post_route_refine $m
check route drc $m
#################################################
#     Physical Optimization
#################################################
fix cell $m $l
fix opt global $m $l
report model $m
report timing summary $m
run gate size $m -effort high
run place timing $m
run place detail $m
################################################
#     CLOCK DESIGN
################################################
fix clock $m $l -effort medium
report timing path $m -clock_path_detail all
report timing path $m
report clock skew $m
report timing summary $m
run gate sweep $m -hier
report timing summary $m
run place timing $m -step 10
run place detail $m -eco
report timing summary $m
report model $m
################################################
#     Detailed Routing
################################################
fix wire $m $l
check route drc $m
run route refine $m
run route final -incremental $m -effort high
check route antenna $m
run route antenna $m
export volcano aes_final.volcano

Note: Reference-IIT MADRAS MAGMA Tutorial