Step 1: Open terminal and type

ifconfing

and note down the IP address.

Step 2: Then type:

python -m SimpleHTTPServer

Step 3: Open the web browser on your phone and enter the IP address and the port (Eg: 192.168.0.3:8000)

You can now browse your files on your phone and if you have MX video player, you can stream too.

P.S – You need to be connected to the same WiFi network.

A vulnerability has been discovered in Oracle Java, which can be exploited by malicious people to compromise a user’s system.

The vulnerability is caused due to an error in how the “setSecurityManager()” function can be called, which can be exploited by an applet to set its own privileges to e.g. allow downloading and executing arbitrary programs.

Successful exploitation allows execution of arbitrary code.

NOTE: This is currently being actively exploited in targeted attacks.

The vulnerability is confirmed in version 7 update 6 build 1.7.0_06-b24. Other versions may also be affected.

A critical flaw in java has been discovered by FireEye. This flaw is ALREADY being used in the wild. Just by you visiting a malicious page,  the attacker can gain access to your computer remotely.

In short, even if you have up-to-date system and have java installed, you can get hacked! If you had to fill up a CAPTCHA to enter this site, chances are, your system is already compromised. (Not necessarily by this java vulnerability.) You should update your antivirus and run a scan.

Metasploitians, rejoice! The exploit is already landed in metasploit. Updated and give it a try.

Anyway, here’s how to disable java and be safe. The instructions can’t get simpler than this. If you did not understand, High Five. On your face!

To just disable the browser plugins:

Firefox

Chrome

Just type “chrome://plugins” or “about:plugins” in the address bar. Find java from the list and click disable. If you have multiple users in chrome, you will have to do it for each user.

Internet Explorer

You deserve to get hacked! You make a web designer’s life so difficult. Go, Download Chrome or Firefox.

To disable java from windows 7:

1. Go to Start > Control Panel > Programs

2. Select Java

3. Select Java > View…

4. Uncheck both the check-boxes

Linux

Find Sun Java 6/7 Plugin Control Panel under others or search for ‘java’ in the menu. Then in the ‘Java Control Panel’ > Java > View > Uncheck all.

Mac

I do not own a mac, so here’s a link: http://stikine.wordpress.com/2012/04/05/2549j48b/

And… you’re safe. Almost.

AirDroid

AirDroid is a fast, free app that lets you wirelessly manage your Android from your favorite browser.

>>Video<<

Smart App Protector

Protect your installed applications using a password or pattern!

Instant Heart Rate

Turns your phone into a heart rate monitor. Quick and accurate.

Alarm Clock Extreme

Most reliable and highest rated alarm clock and timer for Android!

Do you have problems turning off your alarm clock only to fall back asleep? Wake up gently and avoid accidentally disabling your alarm with Alarm Clock Xtreme. This alarm clock and timer includes features that prevent excessive snoozing and get you out of bed.

Memory Trainer

Begin training your spatial and working memory! Improve focus and concentration!

Chrome 2 Phone

Send links, maps, phone numbers, & more from your Chrome browser to your phone!

Also Available: Phone 2 Chrome

AndroZip

AndroZip File Manager helps you copy, delete, move, search, and organize your files, music, pictures, and folders just like you would do on your PC.

FlashLight

Flashlight + LED Light. Brightest. Fastest. Simplest. Your own Tiny Flashlight.

Samsung Apps

Samsung’s App Discovery & Recommendation Engine. Get a few premium apps like CamScanner for FREE!

BitTorrent

Find torrents and download them directly to your smart phone or tablet – all with this handy BitTorrent app from the team that invented the BitTorrent protocol over a decade ago. Subscribe to RSS feeds, play content and more. The first generation of this powerful new app is designed to be easy-to-use, super-fast, and make your Android device so much more fun.

RealCalc

RealCalc Scientific Calculator

Android’s #1 Scientific Calculator. A fully featured scientific calculator which looks and operates like the real thing.

Android Lost

>>Download<<

Lost your android? We will help you find it. See http://www.androidlost.com

Remotely control your Android phone from the internet or by SMS.

IVONA Voice

The most natural, accurate and responsive voice. You will hear the difference!

Any.DO

Any.DO helps you remember everything you have to do. It’s free, simple & fun.

Evernote

Evernote turns your Android device into an extension of your brain.

Google Drive

Keep everything. Share anything.

Alternatives: Box, DropBox

Cam Scanner HD

CamScanner HD turns your tablet into a scanner.

PhotoFunia

Put your face on a billboard, a stamp, or in a Warhol-like work of pop-art. Become the Mona Lisa or a bodybuilder. You get over 150 scenes to play with. You’re not cutting and pasting; instead, the app “finds” the face in your photo and integrates it with the scene of your choice.

Pixlr-O-Matic

You can add fun retro effects to your photos in a snap and transform your photos into cool looking vintage images. Editing is as easy as one, two, three with Pixlr-o-matic to add effects, overlays and borders. So many options to choose from, there are more than 5,000,000 possible finishes to make your photos look spectacular!

Adobe Photoshop Touch [Tablet]

Transform images with core Photoshop features in an app designed for tablets.

Combine images, apply professional effects, share results with friends and family through sites like Facebook, and more – all from the convenience of your tablet.

>>For Mobile Users<<

CameraZoomFX

The Best Camera App for Android! Seriously!

MX Player

Plays almost All video formats and tons of features!

UStream

Go live and watch live video on your phone or tablet – anytime, anywhere!

Broadcast live and watch live video on your phone or tablet – anytime, anywhere!

AutoDesk SketchBook

Autodesk® SketchBook® Express for Android is a fun and intuitive drawing application, optimized for use on Honeycomb tablet devices. Get a taste of the professional-grade paint and drawing tools available in the award-winning SketchBook Pro.

>>For Mobile Users<<

SideReel

Find, Track, and Watch your favorite TV shows with the SideReel Android app!

Songify

Songify turns speech into music automatically!

Just speak into your Android device, and Songify will magically turn your speech into a song. Join the over 9 million people worldwide addicted to Songify!

SoundHound

What’s that song? Identify it FAST with SoundHound.

Unlimited music recognition! Featuring the world’s fastest, most accurate music identification, exclusive singing search, and now: free unlimited LiveLyrics for over 1 million of your favorite songs.

FourSquare

foursquare helps you and your friends make the most of where you are.

Join the over 20 million people who are already on foursquare. Download the free app now!

Google Body [Tablet]

Google Body is a detailed 3D model of the human body. You can view different anatomical layers, zoom in, and navigate to parts that interest you. Click to identify anatomy, or search for muscles, organs, bones and more.

Bobsled

Bobsled Calling gives you UNLIMITED FREE CALLING to all your friends and family – talk to any of your Facebook friends and make free calls to any phone in US, Canada, and Puerto Rico.

>>For Mobile Users<<

cSIP Simple

CSipSimple – High quality OpenSource SIP

OpenSource (GPL) project for SIP on Android.

Viber

Viber – Be Free to Communicate. Call and text anyone, anywhere.

Viber lets everyone in the world connect. Freely. More than 40 million Viber users call, text, send photos and locations with each other worldwide – for free.

WhatsApp

Get WhatsApp Messenger and say goodbye to SMS!

WhatsApp Messenger is a smartphone messenger available for Android, BlackBerry, iPhone, Windows Phone and Nokia phones. WhatsApp uses your 3G or WiFi (when available) to message with friends and family. Switch from SMS to WhatsApp to send and receive messages, pictures, audio notes, and video messages. First year FREE!

Google Voice

Make cheap international calls with your Google number. Send free text messages. Place calls and send text messages showing your Google number. Listen to voicemail and read transcripts.

Google Currents

Beautiful, free, favorite publications for your phone and tablet.

Google Currents delivers beautiful magazine-like editions to your tablet and smartphone for high speed and offline reading.

StumbleUpon

StumbleUpon is the easiest way to discover new and interesting things from across the Web. Simply tap the “Stumble!” button, or swipe your device’s screen to discover photos, videos, web pages and more, recommended by people sharing your Interests.

Feedly

Feedly. Your personalized magazine.

A fast and stylish way to read and share the content of your favorite websites. Feed your mind. Anytime. Anywhere

Opera Mini [Highly Recommended!]

Opera’s fastest mobile browser that can save you money on data. Totally free.

Try the world’s fastest Android browser!

Asphalt 6

Race the world. Feel the adrenaline.

Feel the thrill of arcade racing like never before in the newest adrenaline-pumping game of the Asphalt series

Fifa 12

Experience the action of your favorite sport like never before! Watch matches come to life with vibrant graphics and ultra-realistic animations.

Apparatus

Build a complex machine to perform a simple task.

Apparatus is a game about setting up simple mechanical structures to
move one or several marbles to the goal.

MineCraft

Imagine it, build it. Create worlds on the go with Minecraft – Pocket Edition

This is the demo of Minecraft – Pocket Edition. Minecraft – Pocket Edition allows you to build on the go. Use blocks to create masterpieces as you travel, hangout with friends, sit at the park, the possibilities are endless. Move beyond the limits of your computer and play Minecraft everywhere you go.

NinJump

In this fast paced ninja climbing game, your goal is to rise as high as you can while avoiding killer squirrels, angry birds, enemy ninjas, throwing stars and exploding bombs. With a simple tap you can jump from one wall to the other, knocking obstacles from the air as you do. Take down three enemies of the same kind to trigger mega-jump bonuses. Collect shields to plow through your opponents with. Just watch out for ledges and other ninjas because they will knock you off and send you to your doom!

Tank Heros

The follow-up to the hit puzzle action game Tank Hero has finally arrived! Charge your lasers and get ready to take the fight to new battlegrounds that will challenge you like never before.

Angry Birds Space

Does it need and introduction? Get it FREE on Samsung app store.

ShadowGun

SHADOWGUN puts you into the role of John Slade, the galaxy’s most infamous bounty hunter. Your mission: hunt down Dr. Edgar Simon, maniacal genius and leader of his own mutant army. Infiltrate Dr. Simon’s mountain fortress and fight his personal guard of cyborgs, battle droids, and genetically enhanced humanoids. Using state-of-the-art weaponry, ships, and the assistance of S.A.R.A.—Slade’s personal android assistant—SHADOWGUN combines intense tactical combat with 3rd person action.

Temple Run

You’ve stolen the cursed idol from the temple, and now you have to run for your life to escape the Evil Demon Monkeys nipping at your heels. Test your reflexes as you race down ancient temple walls and along sheer cliffs. Swipe to turn, jump and slide to avoid obstacles, collect coins and buy power ups, unlock new characters, and see how far you can run!

Cut The Rope

Cut the Rope, catch a star, and feed Om Nom candy in this award-winning game!

A mysterious package has arrived, and the little monster inside has only one request… CANDY! Cut the ropes, release candy into Om Nom’s mouth, collect shiny gold stars, and unlock new levels.

FruitNinja

Fruit Ninja is a juicy action game with squishy, splatty and satisfying fruit carnage! Become the ultimate bringer of sweet, tasty destruction with every slash.

2 Player Reactor

Challenge your friends (or enemies) to a battle of reflexes, wits and knowledge! Great as a bar game, ice breaker or to decide who has to do the dishes!

>>4 Player Version<<

Multi Worm

Multi Worm is multi-touch multiplayer game for up to 4 players on one device! If you enjoy playing snake on old Nokia phones, you can’t miss this game!

MultiPonk

One finger to control your paddle. Give your ball smooth effects and thwart the traps to win the game !

Google unveals a new product this week – Consumer Surveys.

Here’s how it’s going to work:
1. Businesses create small quick surveys.
2. You include Google Consumer Survey JavaScript Code into your Website. Probably Wrap it around the content.
3. The Visitor will need to answer the survey to access the content.
4. Neat! A Win-Win-Win situation.

I think it’d be great for premium content and downloads section.

Waiting for my account to be approved

Useful Links:

Home Page: http://www.google.com/insights/consumersurveys
Registration Link: https://services.google.com/fb/forms/surveysforpublishers/

UPDATE: I got a reply from Google saying, it’s not available in just India yet. Guess I’ll have to wait a little while longer.

According to the original plan offered, for Rs. 500/month I get 1 Mbps upto 5GB and there after 256 kbps unlimited + 100 airtel-to-airtel calls free. I think it was a limited time offer, i’m not sure. Anyway, I exhaust the 5GB in like 3 days and max upto 21 days. And thereafter I find 256kbps unbearable! Especially, if you want to watch tutorials on YouTube.
But now, the plan seems to be revised. It’s been 2 months now, the 5GB cap has been extended to 25GB. Hurray! Now, that’s what i call a sensible plan! When will all the other Tel Co’s learn?

This i think is the BEST BROADBAND PLAN right now.

P.S. -It may however be a glitch like the last time when we were getting 2Mbps unlimited WITHOUT a cap!

To make a High Definition Time Lapse video all you need is a phone [Preferably android] with a 2MP camera and access to a computer. That’s right, You can create a HD video with just 2MP camera. If you have that, Read along for the complete tutorial.

Here are a few i made:

You’ll need these softwares:

• Any App that can take photographs after a set interval. I used CameraZOOM for android.
  Other apps: LapseIt. If you know some other, leave a comment below.
• Download AVIDeMux.
• [optional] Bulk Rename Utility.
• [optional] Adobe Photoshop.

What is Time Lapse Photography?
It is a technique of capturing at a lower frame rate and displaying it at a higher frame rate. In simple words, you are speeding up the time.

Before you begin:

• Calculate the amount of time required for the event. You may just observe and note once.
• Then decide the duration of the video. I prefer 20~30 seconds.
• Most Video sharing sites prefer 30fps. So, You’ll need to set your timer to roughly at
  time = [Whole Event]/[Preferred Duration*30]
• Turn off all the auto modes. Set the white balance yourself.
• Take snapshots of the target and decide the best position and settings.
• Place your cam on a sturdy place and start the app.
  I used a tripod from a small telescope i had lying around and hacked it to hold the phone.

Once you are done taking pictures:

Download all your photos onto your PC.
Sometimes, for some weird reasons, your photos might not be in order. To rename them, i used the Bulk Rename Utility.

If you need to Add a few touches to the photos, You can use the Batch Automate Option in photoshop.
To do this:

Open the first image in photoshop.

You then need to create an action: (Window > Actions)

Give your Action a name and press record. From now on, all your activity on photoshop will be recorded in this action.

After you’ve applied your effects, Resize the image to 1920×1080 px.

Then select Save As and save the photo as jpg in a folder. [NOTE: DO NOT create a folder or rename the file in the save as dialogue box. Create the folder from the File Browser.]

Then Click close. [Before stopping the recording of the action]

Now, Stop the action recording.

Now it’s time to apply the effect to the rest of the heap of photos. Select Batch  from File > Automate > Batch.

Choose the recorded action in the previous step as action.

Choose the Source as the folder where all your images are stored and Destination as the folder you created to save the photoshop images.

And check the ‘Override actions “Save As” commands‘ and press OK.

Photoshop will now apply the effects in the action to each image in the source folder and save in the destination folder.

Now, to stitch the photos to gether, we’ll use AVIDeMux.

YouTube prefers 30fps in H.264, MPEG-2 or MPEG-4 format.

In AVIDeMux, Just open the first image and it’ll load the rest of the sequence.
Select MPEG-4 AVC from the video drop down and AVI from format drop down.

Then save the video from file > save video.

DONE!

You may now upload it to Vimeo, YouTube and Facebook and share with your friends.

Also, Leave the links in the comments below. I’d love to see your Magic

DOWNLOAD: 7th SEM EC VLSI Lab Programs & Layouts | SIZE:7.04 MB

Part A

1. Inverter

Verilog Code:

module inv(a,v);
input a;
output v;
assign v=~a;
endmodule 

TestBench Code:

`timescale 1ns/1ns
module inv2(input a, output y);
assign y=(~a);
endmodule

`timescale 1ns/1ns
module inv_tb;
reg a;
wire y;
or2 out(.a(a), .y(y));
initial
begin
a=0;
#100;

a=1;
#100;

end
endmodule

PEX NetList Code:

X1 A V GND VDD inverter
.lib /home/software/FOUNDRY/adk3_0/technology/ic/models/ami05.mod

.connect gnd 0
v1 vdd gnd dc 5v
v2 A gnd pulse(0v 5v 0 5ns 5ns 20ns 50ns)

.tran 1n 1u
.plot v(A) v(V)
.end

2. OR Gate

Verilog Code:

module orgate(a,b,x);
input a,b;
output x;
assign x=a|b;
endmodule

TestBench Code:

TEST BENCH CODE FOR INVERTER

`timescale 1ns/1ns
module or2(input a, input b, output y);
assign y=(a|b);
endmodule

`timescale 1ns/1ns
module or_tb;
reg a,b;
wire y;
or2 out(.a(a), .b(b), .y(y));
initial
begin
a=0;
b=0;
#100;

a=1;
b=0;
#100;

a=0;
b=1;
#100;

a=1;
b=1;
#100;
end
endmodule

PEX NetList Code:

X1 I2 I1 O1 GND VDD or_gate
.lib /home/software/FOUNDRY/adk3_0/technology/ic/models/ami05.mod

.connect GND 0
v1 VDD GND dc 5v
v2 I2 GND pulse(0v 5v 0 5ns 5ns 40ns 80ns)
v3 I1 GND pulse(0v 5v 0 5ns 5ns 20ns 60ns)

.tran 1n 1u
.plot v(I2) v(I1) v(O1)
.end

3. NAND Gate

Verilog Code:

module nandgate(a,b,x);
input a,b;
output x;
assign x=~(a&b);
endmodule

TestBench Code:

`timescale 1ns/1ns
module nand2(input a, input b, output y);
assign y=~(a&b);
endmodule

`timescale 1ns/1ns
module my_tb;
reg a,b;
wire y;
nand2 out(.a(a), .b(b), .y(y));
initial
begin
a=0;
b=0;
#100;

a=1;
b=0;
#100;

a=0;
b=1;
#100;

a=1;
b=1;
#100;
end
endmodule

PEX NetList Code:

X1 I2 I1 O1 GND VDD nand
.lib /home/software/FOUNDRY/adk3_0/technology/ic/models/ami05.mod

.connect GND 0
v1 VDD GND dc 5v
v2 I2 GND pulse(0v 5v 0 5ns 5ns 40ns 80ns)
v3 I1 GND pulse(0v 5v 0 5ns 5ns 20ns 60ns)

.tran 1n 1u
.plot v(I2) v(I1) v(O1)
.end

4. D-FlipFlop

Verilog Code:

module mydff(d,clk,q,qb);
input d,clk;

output q,qb;
reg q,qb;
always@(posedge clk)
begin
        case(d)
        1'd0:q=0;
        1'd1:q=1;
        endcase
qb=~q;
end
endmodule

TestBench Code:

`timescale 1ns/1ns
module dff1(d,clk,q,qb);
input d,clk;
output q, qb;
reg q,qb;

always@(posedge(clk))
begin
if(d==0)
q=0;
else
q=1;
qb=~q;
end 
endmodule

`timescale 1ns/1ns
module dff1_tb;
reg a,b;
wire y,yb;
dff1 out(.d(a),.clk(b),.q(y),.qb(yb));
initial
begin
a=0;
b=0;
#100;

b=1;
#100;

a=1;
b=0;
#100;

b=1;
#100;
end
endmodule

PEX NetList Code:

X1 D CLK QB Q GND VDD mydff
.lib /home/software/FOUNDRY/adk3_0/technology/ic/models/ami05.mod

.connect GND 0
v1 VDD GND dc 5v
v2 CLk GND pulse(0v 5v 0 5ns 5ns 20ns 50ns)
v3 D GND pulse(0v 5v 0 5ns 5ns 100ns 200ns)
.tran 1n 1u
.plot v(D) v(CLK) v(Q) v(QB)
.end

5. T-FlipFlop

Verilog Code:

module mytff(t,q,qb,clk);
input   t,clk;
output q,qb;
reg q,qb;
initial q=0;

always@(posedge clk)
begin
        if (t==1)
        begin
                q=~q;
              end
      else
        begin
      q=q;                
        end
        qb=~q;      
    end
endmodule

TestBench Code:

`timescale 1ns/1ns
module tff (t,clk,q,qb);
input t,clk;
output q,qb;
reg q, qb;
initial
begin
q=0;
q=1;
end

always@(posedge (clk))
begin
if(t==0)
q=q;
else
q=qb;
qb=~q;
end
endmodule

`timescale 1ns/1ns
module tff_tb;
reg a,b;
wire y,yb;
tff out(.t(a), .clk(b),.q(y),.qb(yb));
initial
begin
a=0;
b=0;
#100;

b=1;
#100;

a=1;
b=0;
#100;

b=1;
#100;
end 
endmodule

PEX NetList Code:

X1 T CLK Q QB GND VDD mytff
.lib /home/software/FOUNDRY/adk3_0/technology/ic/models/ami05.mod

.connect GND 0
v1 VDD GND dc 5v
v2 T GND pulse(0v 5v 0 0ns 0ns 100ns 200ns)
v3 CLK GND pulse(0v 5v 0 0ns 0ns 50ns 100ns)

.tran 1n 1u
.plot v(T) v(CLK) v(Q) v(QB)
.end

6. JK-FlipFlop

Verilog Code:

module myjkff(jk,clk,q,qb);
output q,qb;
input[1:0] jk;
input clk;
reg q,qb;

always @(posedge clk)
begin
      
                case(jk)
                        2'd1:q=0;
                        2'd2:q=1;
                        2'd3:q=~q;
                        2'd0:q=q;
                  endcase
          
         
          qb=~q;
     end
   endmodule

TestBench Code:

`timescale 1ns/1ns
module jkff(j,k,clk,q,qb);
input j,k, clk;
output q, qb;
reg q,qb;
initial
begin
q=0;
qb=1;
end

always@ (posedge (clk))
begin
if(j==0 && k==0)
     q=0;
else if(j==0 && j==1)
     q=0;
else if (j==1 && k==0)
     q=1;
else q=qb;
     qb=~q;
end 
endmodule

`timescale 1ns/1ns
module jkff_tb;
reg a,b,c;
wire y,yb;
jkff out (.j(a), .k(c),.clk(b), .q(y), .qb(yb));
initial
begin
c=0;
a=0;
b=0;
#100;

b=1;
#100;

a=1;
b=0;
#100;

b=1;
#100;

c=1;
a=0;
b=0;
#100;

a=0;
b=1;
#100;

a=1;
#100;

b=1;
#100;
end
endmodule

PEX NetList Code:

X1 JK[0] Q JK[1] QB CLK GND VDD myjkff
.lib /home/software/FOUNDRY/adk3_0/technology/ic/models/ami05.mod

.connect GND 0
v1 VDD GND dc 5v
v2 JK[0] GND pulse(0v 5v 0 0ns 0ns 100ns 200ns)
v3 JK[1] GND pulse(0v 5v 0 0ns 0ns 50ns 100ns)
v3 CLK GND pulse(0v 5v 0 0ns 0ns 25ns 50ns)

.tran 1n 1u
.plot v(JK[0]) v(JK[1]) v(CLK) v(Q) v(QB)
.end

7. Full Adder

Verilog Code:

module fa(a,b,c,s,c1);
input a,b,c;
output s,c1;
assign s=a^b^c;
assign c1=a&b|(b&c)|(c&a);
endmodule

TestBench Code:

`timescale 1ns/1ns
module fulladd2(input a, input b, input c, output c1, output s);
assign c1=a&b|(b&c)|(c&a);
assign s=a^b^c;
endmodule

`timescale 1ns/1ns
module fulladd_tb;
reg a,b,c;
wire c1,s;
fulladd2 out(.a(a), .b(b), .c(c), .c1(c1), .s(s)) ;
initial
	begin
	a=0;
	b=0;
	c=0;
	#100;

	a=1;
	b=0;
	c=1;
	#100;

	a=0;
	b=1;
	c=0;
	#100;

	a=1;
	b=1;
	c=1;
	#100;

	a=1;
	b=1;
	c=0;
	#100;
	end
endmodule

PEX NetList Code:

X1 A C C1 B S GND VDD fa
.lib /home/software/FOUNDRY/adk3_0/technology/ic/models/ami05.mod

.connect GND 0
v1 VDD GND dc 5v
v2 A GND dc 5v
v3 B GND dc 5v
v4 C GND dc 0v

.tran 1n .5u
.plot v(A) v(B) v(C) v(C1) v(S)
.end

8. Counter

Verilog Code:

module bincount(clk,clr,q);
input clk,clr;
output[3:0] q;
reg[3:0] q;
initial q=4'b0000;

always @(posedge clk)

begin
  if (clr == 0)
    begin
      case(q)
        
        4'b0000 : q=4'b0001;
        4'b0001 : q=4'b0010;
        4'b0010 : q=4'b0011;
        4'b0011 : q=4'b0100; 
        4'b0100 : q=4'b0101;
        4'b0101 : q=4'b0110; 
        4'b0110 : q=4'b0111; 
        4'b0111 : q=4'b1001; 
        4'b1001 : q=4'b1010;
        4'b1010 : q=4'b1011;
        4'b1011 : q=4'b1100;
        4'b1100 : q=4'b1101;
        4'b1101 : q=4'b1110;
        4'b1110 : q=4'b1111;
      endcase
    end
  else
      q=4'b0000;
      
    end
  endmodule

TestBench Code:

`timescale 1ns/1ns
module count4(clk,clr,q);
input clk,clr;
output[3:0]q;
reg[3:0]q=0000;
always@(posedge(clk))
begin
	if(clr==0)
	begin
		q=q+4'd1;
		end
		else
		q=0000;
	end
endmodule

`timescale 1ns/1ns
module count4_tb;
reg a,b;
wire[3:0]y;
count4 out(.clr(a),.clk(b),.q(y));
initial
	begin
	a=0;
	while(1)
		begin
		b=0;
		#100;
		b=1;
		#100;
		end
	end 
endmodule

PEX NetList Code:

X1 Q[0] CLR CLK Q[3] Q[1] Q[2] GND VDD bincount 
.lib /home/software/FOUNDRY/adk3_0/technology/ic/models/ami05.mod

.connect GND 0
v1 VDD GND dc 5v
v2 CLR GND dc 0v
v3 CLK GND pulse(0v 5v 0 0ns 0ns 20ns 50ns)

.tran 1n 1u
.plot v(CLR) v(CLK) v(Q[0]) v(Q[1]) v(Q[2]) v(Q[3])
.end

Part B

[Spice NetList code]

1. Inverter

.subckt inv VDD VSS IN1 OUT1
M1 OUT1 IN1 VDD VDD p w=3.0u l=0.6u
M2 OUT1 IN1 VSS VSS n w=1.5u l=0.6u
.ends inv

X1 VDD VSS IN1 OUT1 inv
.lib /home/software/FOUNDRY/adk3_0/technology/ic/models/ami05.mod
.connect VSS 0
V1 VDD VSS dc 5V
V2 IN1 VSS pulse(0V 5V 0 5ns 5ns 25ns 50ns)
.tran 1n 1u 
.plot V(IN1) V(OUT1)
.end

2. NOR Gate

.subckt nor VDD VSS A B OUT
M1 1 A VDD VDD p w=3.0u l=0.6u
M2 OUT B 1 VDD p w=3.0u l=0.6u
M3 OUT A VSS VSS n w=1.5u l=0.6u
M4 OUT B VSS VSS n w=1.5u l=0.6u
.ends nor

X1 VDD VSS A B OUT nor
.lib /home/software/FOUNDRY/adk3_0/technology/ic/models/ami05.mod
.connect VSS 0
V1 VDD VSS dc 5v
V2 A VSS pulse(0v 5v 0ns 5ns 5ns 25ns 50ns)
V3 B VSS pulse(0v 5v 0ns 5ns 5ns 50ns 100ns)
.tran 1n 1u
.plot v(A) v(B) v(OUT)
.end

3. NAND Gate

.subckt nand VSS VDD A B OUT
M1 OUT A VDD VDD p w=3u l=0.6u
M2 OUT B VDD VDD p w=3u l=0.6u
M3 OUT A 1 VSS n w=1.5u l=0.6u
M4 1 B VSS VSS n w=1.5u l=0.6u

.ends nand

X1 VSS VDD A B OUT nand
.lib /home/software/FOUNDRY/adk3_0/technology/ic/models/ami05.mod
.connect VSS 0
V1 VDD VSS dc 5V
V2 A VSS pulse(0V 5V 0 5ns 5ns 20ns 50ns)
V3 B VSS pulse(0V 5V 0 5ns 5ns 40ns 80ns)
.tran 1n 1u
.plot V(A) V(B) V(OUT)
.end

4. Common Source

.subckt csa VDD VSS IN1 OUT1
M1 OUT1 OUT1 VDD VDD p w=3.0u l=0.6u
M2 OUT1 IN1 VSS VSS n w=1.5u l=0.6u
.ends csa

X1 VDD VSS IN1 OUT1 csa
.lib /home/software/FOUNDRY/adk3_0/technology/ic/models/ami05.mod
.connect VSS 0V
V1 VDD VSS dc 5V
V2 IN1 VSS dc 0V
.dc V2 0 5V 0.1V
.plot V(IN1) V(OUT1)
.end

5. OpAmp

.subckt opamp VDD VSS IN1 IN2 5 OUT
M1 1 IN1 3 3 n w=1.5u l=0.6u
M2 2 IN2 3 3 n w=1.5u l=0.6u
M3 1 1 VDD VDD p w=3.0u l=0.6u
M4 2 1 VDD VDD p w=1.5u l=0.6u
M5 3 5 VSS VSS n w=1.5u l=0.6u
M6 VDD 2 OUT OUT n w=1.5u l=0.6u
M7 OUT 5 VSS VSS n w=1.5u l=0.6u
M8 5 5 VSS VSS n w=1.5u l=0.6u
cc 2 OUT 3pf
.ends opamp

X1 VDD VSS IN1 IN2 5 OUT opamp
.lib /home/software/FOUNDRY/adk3_0/technology/ic/models/ami05.mod
V1 VDD 0 dc 2.5V
V2 VSS 0 dc -2.5V
i1 VDD 5 30ua
V3 IN1 0 dc 0V
V4 IN2 0 dc 0V
.dc V4 -2.5V 2.5V 0.1V
.plot V(OUT) V(IN2)
.end

1. First, Let’s see what’s a netbook?

Netbooks are just SMALL and INEXPENSIVE laptops and are most often LESS POWERFUL. But MORE often give a longer battery life. And they are super LIGHT.

2. What can i do on a netbook?

If all you do is browse the internet, make presentations, write programs, read books, listen to songs and watch videos and you want to carry it everywhere, definitely go for a netbook.  But mind you, it wont be as snappy as a laptop. You’d rather NOT use CAD applications, Photoshop, VirtualBox, and heavy applications. You’ll die of frustration. You’ll notice lags when you turn your 3D CAD models, drag or add effects on Photoshop. But they do work. I personally use SolidWorks, FireWorks, Photoshop, VMWare and many more.

And yes, you can install linux on it. In fact any operating system. Even chromium.

Even with the shortcoming, its a perfect productivity gadget.

3. The one that i bought, How’s it?

I LOVE IT! I bought a ASUS 1015 PEM  from flipkart.com and here are the details:

It comes with Dual Core intel atom n550 1.6 GHz processor. Don’t be fooled by the numbers, though. The 1.6GHz atom doesn’t perform the same as any other processor at 1.6 GHz. But if you happen to buy one, make sure you buy a dualcore. Helps big time while multitasking.

Although it has an Intel GMA 3150 Dynamic Video Memory Technology 4.0, i haven’t even been able to play 720p quiet well.

It came with 1 GB of DDR3 (1333MHz SODIMM) RAM but I’ve upgraded mine to 2 GB. Unless you plan to use the above heavy applications, you wont need to upgrade.

The 320 GB SATA HDD (5,400 rpm) if more than sufficient for the stuff you’ll be using your netbook.

The 1024 x 600 ( WSVGA ) 10″ screen may be a little hard to adjust in the beginning. It is comfortable to read books. but, not as much if you are designing or building CAD models. And did i mention its a Non-Glossy. You can work outdoors with no reflections at all!

It uses WiFi – b/g/n and Bluetooth 3.0 and supports upto 24 MBPS between devices on wifi. It wouldn’t be called a ‘netbook’ if it didn’t have wifi, right?

It’s blessed with Windows 7 starter. Unlike most other users out ther, i’m in favor of the starter. And i recommend against replacing it with XP or Ultimate. The starter has been stripped down of all the unnecessary services which would otherwise use up all the little resource your netbook has. Ubuntu and backtrack run great. If you are new to linux, you might want to try Mint.

With so many great features the 0.3 MP webcam disappoints me. You might consider buying an external webcam.

I bought the one with 48WHr 6-cell battery and gives me upto 5hrs of browsing and videos. There’s also an option to buy a 63WHrs version of the battery that’ll give you an extra 2 hours. Note that you’ll need the ASUS SuperHybridEngine installed on Win7 to get more from your battery. For linux alternative, try Jupiter.

The  Chiclet style keyboard is a 90% of the normal size keyboards. Although, i didn’t like the placement of the PgUp/PgDn buttons.

It has a multi-touch touchpad. And it supports gestures like two-finger scrolling and one/two/three finger tapping. But the buttons are quiet harder than the other models out there.

The Speakers are useless! They aren’t loud nor are they clear. If you turn up the volume above 90%, they start crying.

It supports BIOS caching and boots up a little faster. I bought a MattBlack model which frees me from the smudges. The form factor is slightly thicker than the other ones i’ve seen.  But, its good enough. I weighs just over 1 kg (2.76 lbs) and is easy to carry around. You can even hold it in your hand as you work.

I bought it for ? 17,000 and i’m very happy with my purchase.

If you plan to buy one, you may check out some of the models here.

[I'll upload the complete tutorial in some time.]

Thanks to Manjunath Kalkutagi for submitting the programs.

DOWNLOAD: HDL Lab programs - VTU - ALL | SIZE:37 KB

1. Write HDL code to realize all the logic gates
Verilog:

module allgates(i1,i2,o1,o2,o3,o4,o5,o6,o7);
    input i1,i2;
    output o1,o2,o3,o4,o5,o6,o7;
    assign o1=i1 &i2;
    assign o2= i1|i2;
    assign o3=~(i1 & i2);
    assign o4=~(i1 | i2);
    assign o5= i1 ^ i2;
    assign o6= ~(i1 ^ i2);
    assign o7= ~i1;
endmodule

VHDL:

module allgates(i1,i2,o1,o2,o3,o4,o5,o6,o7);
    input i1,i2;
    output o1,o2,o3,o4,o5,o6,o7;
    assign o1=i1 &i2;
    assign o2= i1|i2;
    assign o3=~(i1 & i2);
    assign o4=~(i1 | i2);
    assign o5= i1 ^ i2;
    assign o6= ~(i1 ^ i2);
    assign o7= ~i1;
endmodule

2. Write a HDL program for the following combinational designs:
a] 2 to 4 Decoder
Verilog:

//Behavioral
module dec2to4_df(ebar,a,y);
    input ebar;
    input[1:0]a;
    output[3:0]y;
    reg y;
    always@(a,ebar)
    begin
        if(ebar==0)
        begin
            case(a)
                2'd0:y=4'd1;
                2'd1:y=4'd2;
                2'd2:y=4'd4;
                2'd3:y=4'd8;
            endcase
        end
        else
        y=4'd0;
    end
endmodule

//Dataflow
module dec2to4_df(ebar,a,y);
    input ebar;
    input[1:0]a;
    output[3:0]y;
    assign y[0]=(~a[1])&(~a[0])& ebar;
    assign y[1]=(~a[1]) & (a[0]) & ebar;
    assign y[2]=(a[1])&(~a[0])& ebar;
    assign y[3]=(a[1]) &(a[0]) & ebar;
endmodule

//Structural
module dec2to4_structural(ebar,a,y);
    input ebar;
    input[1:0]a;
    output[3:0]y;
    wire[3:1] abar; /*abar- not a*/
    not(ebar,e);
    not(abar(0),a(0));
    not(abar(1),a(1));
    and(y(0),e,abar(1),abar(0));
    and(y(1),e,abar(1),a(0));
    and(y(2),e,a(1),abar(0));
    and(y(3),e,a(1),a(0));
endmodule

VHDL:

//Behavioral
library ieee;
    use ieee.std_logic_1164.all;
    entity dec2to4 is
        port(a: in std_logic_vector(1 downto 0);
             ebar:in std_logic;
             y:out std_logic_vector(3 downto 0));
end dec2to4;
architecture dec2to4_behave of dec2to4 is
    begin
        process(ebar,a)
            begin
                if(ebar='0')then
                    case a is
                        when"00"=>yyyynull;
                    end case;
                    else y                end if;
            end process;
        end  dec2to4_behave;

//Dataflow
library ieee;
    use ieee.std_logic_1164.all;
    entity dec2to4 is
        port(a: in std_logic_vector(1 downto 0);
             ebar:in std_logic;
             y:out std_logic_vector(3 downto 0));
end dec2to4;
architecture dec2to4_df of dec2to4 is
begin
     y(0)     y(1)     y(2)     y(3) end dec2to4_df;

//Structural
library ieee;
    use ieee.std_logic_1164.all;
    entity dec2to4 is
        port(a: in std_logic_vector(1 downto 0);
             ebar:in std_logic;
             y:out std_logic_vector(3 downto 0));
end dec2to4;
architecture dec2to4_struct of dec2to4 is
    component not1
        port(x:in std_logic; xbar:out std_logic);
        end component;
        component and3ip
            port(p,q,r:in std_logic; s:out std_logic);
            end component;
            signal e,abar1,abar0:std_logic;
            begin
                n1:not1 port map(ebar,e);
                n2:not1 port map(a(0),abar0);
                n3:not1 port map(a(1),abar1);
                a0:and3ip port map(e,abar1,abar0,y(0));
                a1:and3ip port map(e,abar1,a(0),y(1));
                a2:and3ip port map(e,a(1),abar0,y(2));
                a3:and3ip port map(e,a(1),a(0),y(3));
            end dec2to4_struct;

 library ieee;
    use ieee.std_logic_1164.all;
    entity not1 is
        port(x:in std_logic;xbar:out std_logic);
        end not1;
        architecture notgate of not1 is
            begin
                xbar            end notgate;

  library ieee;
    use ieee.std_logic_1164.all;
    entity and3ip is
    port(p,q,r:in std_logic;s:out std_logic);
end and3ip;
architecture andgate of and3ip is
begin
send andgate;

b] 8 to 3 Encoder

//Behavoral
module npenc8to3(a,y);
    input[7:0] a;
    output[2:0]y;
    reg[2:0]y;
    always@(a)
    begin
        case(a)
            8'd1:y=3'd0;
            8'd2:y=3'd1;
            8'd4:y=3'd2;
            8'd8:y=3'd3;
            8'd16:y=3'd4;
            8'd32:y=3'd5;
            8'd64:y=3'd6;
            8'd128:y=3'd7;
            default:$display("not a valid input");
    endcase
end
endmodule

//Dataflow
module npenc8to3(a,y);
    input[7:0] a;
    output[2:0]y;
    assign y[0]=a[1]|a[3]|a[5]|a[7];
    assign y[1]=a[2]|a[3]|a[6]|a[7];
    assign y[2]=a[4]|a[5]|a[6]|a[7];
endmodule

//Structural
module npenc8to3(a,y);
    input[7:0] a;
    output[2:0]y;
    or(y[0],a[1],a[3],a[5],a[7]);
    or(y[1],a[2],a[3],a[6],a[7]);
    or(y[0],a[4],a[5],a[6],a[7]);
endmodule

VHDL:

//Behavoral
library ieee;
    use ieee.std_logic_1164.all;
    entity npenc8to3 is
        port(a:in std_logic_vector(7 downto 0);ebar:in std_logic;
            y:out std_logic_vector(2 downto 0));
        end npenc8to3;
        architecture npenc8to3_behave of npenc8to3 is
            begin
                process(ebar,a)
                    begin
                        if ebar='0' then

                            case a is
                                when "00000001"=>yyyyyyyyreport"not a valid input"severity note;
                            end case;
                            else y                        end if;
                    end process;
                end  npenc8to3_behave ;

<strong>//Dataflow</strong>
library ieee;
    use ieee.std_logic_1164.all;
    entity npenc8to3 is
        port(a:in std_logic_vector(7 downto 0);
            y:out std_logic_vector(2 downto 0));
        end npenc8to3;
        architecture npenc8to3_df of npenc8to3 is
            begin
                y(0)                y(1)                y(2)            end npenc8to3_df;

//Structural
library ieee;
    use ieee.std_logic_1164.all;
    entity npenc8to3 is
        port(a:in std_logic_vector(7 downto 0);
            y:out std_logic_vector(2 downto 0));
        end npenc8to3;
        architecture npenc8to3_struct of npenc8to3 is
            component or4ip
                port(p,q,r,s:in std_logic;
                     t:out std_logic);
                 end component;
                 begin
                     or1:or4ip port map(a(1),a(3),a(5),a(7),y(0));
                     or2:or4ip port map(a(2),a(3),a(6),a(7),y(1));
                     or3:or4ip port map(a(4),a(5),a(6),a(7),y(2));
                 end npenc8to3_struct;
                 library ieee;
                     use ieee.std_logic_1164.all;
                     entity or4ip is
                         port(p,q,r,s:in std_logic;t:out std_logic);
                         end or4ip;
                         architecture orgate of or4ip is
                             begin
                                 t                             end orgate;

c] 8 to 1 Multiplexer
Verilog:

//Behavoral
module mux8x1 (a,e,s,y);
    input[7:0]a;
    input[2:0]s;
    input e;
    output y;
    reg y;
    always@(a,e,s)
    begin
    if(e==1)
    begin
        case(s)
            3'd0:y=a[0];
            3'd1:y=a[1];
            3'd2:y=a[2];
            3'd3:y=a[3];
            3'd4:y=a[4];
            3'd5:y=a[5];
            3'd6:y=a[6];
            3'd7:y=a[7];
    endcase
end
else
y=1'bz;
end
endmodule

//Dataflow
module mux8x1 (a,s,y);
    input[7:0]a;
    input[2:0]s;
    output y;
    assign y=(a[0]&(~(s[2]))&(~(s[1]))&(~(s[0])))|
             (a[1]&(~(s[2]))&(~(s[1]))&(s[0]))|
             (a[2]&(~(s[2]))&(s[1])&(~(s[0])))|
             (a[3]&(~(s[2]))&(s[1])&(~(s[0])))|
             (a[4]&(s[2])&(~(s[1]))&(~(s[0])))|
             (a[5]&(s[2])&(~(s[1]))&(s[0]))|
             (a[6]&(s[2])&(s[1])&(~(s[0])))|
             (a[7]&(s[2])&(s[1])&(s[0]));
     endmodule
//Structural
module mux8x1 (a,s,y);
    input[7:0]a;
    input[2:0]s;
    output y;
    wire n0,n1,n2,a0,a1,a2,aa3,a4,a5,a6,a7;
    not(n0,s[0]);
    not(n1,s[1]);
    not(n2,s[2]);
    and(a0,n2,n1,n0,a[0]);
    and(a1,n2,n1,s[0],a[1]);
    and(a2,n2,s[1],n0,a[2]);
    and(a3,n2,s[1],s[0],a[3]);
    and(a4,s[2],n1,n0,a[4]);
    and(a5,s[2],n1,s[0],a[5]);
    and(a6,s[2],s[1],n0,a[6]);
    and(a7,s[2],s[1],s[0],a[7]);
    or(y,a0,a1,a2,a3,a4,a5,a6,a7);
endmodule

VHDL:

//Behavoral
library ieee;
    use ieee.std_logic_1164.all;
    entity mux is
        port(i:in std_logic_vector(7 downto 0);
            s:in std_logic_vector(2 downto 0);
            y:out std_logic);
        end mux;
        architecture mux_bh of mux is
            begin
                process(i,s)
                    variable temp:std_logic;
                    begin
                        case(s) is
                            when "000"=>temp:=i(0);
                            when "001"=>temp:=i(1);
                            when "010"=>temp:=i(2);
                            when "011"=>temp:=i(3);
                            when "100"=>temp:=i(4);
                            when "101"=>temp:=i(5);
                            when "110"=>temp:=i(6);
                            when "111"=>temp:=i(7);
                            when others=>temp:='z';
                        end case;
                        y                    end process;
                end mux_bh;

//Dataflow
library ieee;
    use ieee.std_logic_1164.all;
    entity mux8x1 is
        port(a:in std_logic_vector(7 downto 0);
            s:in std_logic_vector(2 downto 0);
            y:out std_logic);
        end mux8x1;
        architecture mux8x1_df of mux8x1 is
            begin
                y                    (a(1) and(not(s(2))) and(not(s(1))) and s(0)) or
                    (a(2) and(not(s(2))) and s(1)and s(0)) or
                    (a(4) and s(2) and(not(s(1))) and(not(s(0)))) or
                    (a(5) and s(2) and (not(s(1))) and s(0)) or
                    (a(6) and s(2) and s(1) and(not(s(0)))) or
                    (a(4) and s(2) and s(1) and s(0));
                end mux8x1_df;

//Structural
library ieee;
    use ieee.std_logic_1164.all;
    entity mux8x1 is
        port(a:in std_logic_vector(7 downto 0);
            s:in std_logic_vector(2 downto 0);
            y:out std_logic);
        end mux8x1;
        architecture mux8x1_strt of mux8x1 is
            component not1
                port(x:in std_logic;xbar:out std_logic);
                end component;
                component and4ip
                    port(p,q,r,s:in std_logic; t:out std_logic);
                    end component;
                    component or8ip
                        port(p0,p1,p2,p3,p4,p5,p6,p7:in std_logic;q:out std_logic);
                        end component;
                        signal s2bar,s1bar,s0bar,y0,y1,y2,y3,y4,y5,y6,y7:std_logic;
                        begin
                            n1:not1 port map(s(2),s2bar);
                            n2:not1 port map(s(1),s1bar);
                            n3:not1 port map(s(0),s0bar);
                            a0:and4ip port map(s2bar,s1bar,s0bar,a(0),y0);
                            a1:and4ip port map(s2bar,s1bar,s(0),a(1),y1);
                            a2:and4ip port map(s2bar,s(1),s0bar,a(2),y2);
                            a3:and4ip port map(s2bar,s(1),s(0),a(3),y3);
                            a4:and4ip port map(s(2),s1bar,s(0),a(5),y5);
                            a5:and4ip port map(s(2),s1bar,s0bar,a(4),y4);
                            a6:and4ip port map(s(2),s(1),s0bar,a(6),y6);
                            a7:and4ip port map(s(2),s(1),s(0),a(7),y7);
                            or8:or8ip port map(y0,y1,y2,y3,y4,y5,y6,y7,y);
                        end mux8x1_strt;
                        library ieee;
                            use ieee.std_logic_1164.all;
                            entity not1 is
                                port(x:in std_logic;xbar:out std_logic);
                                end not1;
                                architecture notgate of not1 is
                                    begin
                                        xbar                                    end notgate;
                                     library ieee;
                            use ieee.std_logic_1164.all;
                            entity and4ip is
                                port(p,q,r,s:in std_logic;t:out std_logic);
                                end and4ip;
                                architecture andgate of and4ip is
                                    begin
                                        t                                    end andgate;
                                     library ieee;
                            use ieee.std_logic_1164.all;
                            entity or8ip is
                                port(p0,p1,p2,p3,p4,p5,p6,p7:in std_logic; q:out std_logic);
                                end or8ip;
                                architecture orgate of or8ip is
                                    begin
                                        q                                    end orgate;

d] 4 Bit binary to gray converter
Verilog:

//Behavoral
module bin2gray(b,g);
    input[3:0]b;
    output[3:0]g;
    reg g;
    always@(b)
    begin
        case(b)
            4'd0:g=4'd0;
            4'd1:g=4'd1;
            4'd2:g=4'd3;
            4'd3:g=4'd2;
            4'd4:g=4'd6;
            4'd5:g=4'd7;
            4'd6:g=4'd5;
            4'd7:g=4'd4;
            4'd8:g=4'd12;
            4'd9:g=4'd13;
            4'd10:g=4'd15;
            4'd11:g=4'd14;
            4'd12:g=4'd10;
            4'd13:g=4'd11;
            4'd14:g=4'd9;
            4'd15:g=4'd8;
    endcase
end
endmodule

//Dataflow
module bin2gray(b,g);
    input[3:0]b;
    output[3:0]g;
    assign g[3]=b[3];
    assign g[2]=b[3] ^b[2];
    assign g[1]=b[2] ^ b[1];
    assign g[0]=b[1] ^b[0];
endmodule

//Structural
module bin2gray(b,g);
    input[3:0]b;
    output[3:0]g;
    xor(g[3],b[3],'0');
    xor(g[2],b[3],b[2]);
    xor(g[1],b[2],b[1]);
    xor(g[0],b[1],b[0]);
endmodule

VHDL:

//Behavoral
library ieee;
    use ieee.std_logic_1164.all;
    entity bin2gray is
        port(b:in std_logic_vector(3 downto 0);
             g:out std_logic_vector(3 downto 0));
         end bin2gray;
         architecture bin2gray_behave of bin2gray is
             begin
                 process(b)
                     begin
                         case(b) is
                             when "0000"=>ggggggggggggggggnull;
                                 end case;
                             end process;
                         end bin2gray_behave;

//Dataflow
library ieee;
    use ieee.std_logic_1164.all;
    entity bin2gray is
        port(b:in std_logic_vector(3 downto 0);
             g:out std_logic_vector(3 downto 0));
         end bin2gray;
         architecture bin2gray_df of bin2gray is
             begin
                 g(3)                 g(2)                 g(1)                 g(0)             end bin2gray_df;
//Structural
library ieee;
    use ieee.std_logic_1164.all;
    entity bin2gray is
        port(b:in std_logic_vector(3 downto 0);
             g:out std_logic_vector(3 downto 0));
         end bin2gray;
         architecture bin2gray_strt of bin2gray is
             component xor2
                 port(p,q:in std_logic; r:out std_logic);
                 end component;
                 begin
                     x3:xor2 port map(b(3),'0',g(3));
                     x2:xor2 port map(b(3),b(2),g(2));
                     x1:xor2 port map(b(2),b(1),g(1));
                     x0:xor2 port map(b(1),b(0),g(0));
                 end bin2gray_strt;
                 library ieee;
    use ieee.std_logic_1164.all;
                 entity xor2 is
                     port(p,q:in std_logic;r:out std_logic);
                     end xor2;
                     architecture xorgate of xor2 is
                         begin
                             r                         end xorgate;

e] 1 to 4 DeMux
Verilog:

//behavioral
module demux1x4(a,e,s,y);
    input s,e;
    input[1:0]a;
    output[3:0]y;
    reg y;
    always@(a,e,s)
    begin
    if(e==1)
    begin
        case(s)
            2'd0:y=a;
            2'd1:y=a;
            2'd2:y=a;
            2'd3:y=a;
    endcase
end
end
endmodule

//DataFlow
module demux1x4(a,s,y);
    input a;
    input[1:0]s;
    output[3:0]y;
    assign y[0]=a&(~s[1])&(~s[0]);
    assign y[1]=a&(~s[1])&(s[0]);
    assign y[2]=a&s[1] &(~s[0]);
    assign y[0]=a &s[1] &s[0];
endmodule

//Structural
module demux1x4(a,s,y);
    input a;
    input[1:0]s;
    output[3:0]y;
    wire n0,n1;
    not(n0,s[0]);
    and(y[0],n1,n0,a);
    and(y[0],n1,s[0],a);
    and(y[2],s[1],n0,a);
    and(y[3],s[1],s[0],a);
endmodule

VHDL:

//behavioral
library ieee;
    use ieee.std_logic_1164.all;
    entity demux1x4 is
        port(a:in std_logic;
            s:in std_logic_vector(1 downto 0);
            y:out std_logic_vector(3 downto 0));
        end demux1x4;
        architecture demux1x4_beh of demux1x4 is
            begin
                process(a,s)
                    begin
                        case s is
                            when "00"=>y(0)y(1)y(2)y(3)null;
                        end case;
                    end process;
                end demux1x4_beh;

//DataFlow
library ieee;
    use ieee.std_logic_1164.all;
    entity demux1x4 is
        port(a:in std_logic;
            s:in std_logic_vector(1 downto 0);
            y:out std_logic_vector(3 downto 0));
        end demux1x4;
        architecture demux1x4_df of demux1x4 is
            begin
                y(0)                y(1)                y(2)                y(3)            end demux1x4_df;

//Structural
library ieee;
    use ieee.std_logic_1164.all;
    entity demux1x4 is
        port(a:in std_logic;
            s:in std_logic_vector(1 downto 0);
            y:out std_logic_vector(3 downto 0));
        end demux1x4;
        architecture demux1x4_strt of demux1x4 is
             component not1
          port(x:in std_logic;xbar:out std_logic);
          end component;
          component and3ip
              port(p,q,r:in std_logic;s:out std_logic);
              end component;
              signal s0bar,s1bar:std_logic;
              begin
                  n1:not1 port map(s(0),s0bar);
                  n2:not1 port map(s(1),s1bar);
                  a0:and3ip port map(s1bar,s0bar,a,y(0));
                  a1:and3ip port map(s1bar,s(0),a,y(1));
                  a2:and3ip port map(s(1),s0bar,a,y(2));
                  a3:and3ip port map(s(1),s(0),a,y(3));
              end demux1x4_strt;
               library ieee;
                      use ieee.std_logic_1164.all;
                      entity not1 is
                          port(x:in std_logic;xbar:out std_logic);
                          end not1;
                          architecture notgate of not1 is
                              begin
                                  xbar              end notgate;
              library ieee;
                      use ieee.std_logic_1164.all;
                              entity and3ip is
                                  port(p,q,r:in std_logic;s:out std_logic);
                                  end and3ip;
                                  architecture andgate of and3ip is
                                      begin
                                      s                                      end andgate;

3. Write a HDL code to describe the functions of a Full Adder Using three modeling styles.
Verilog:

//Behavoral
module fa_beh(xyz,sum,carry);
    input[2:0]xyz;
    output sum ,carry;
    reg sum,carry;
    always@(xyz)
    begin
        case(xyz)
            3'd0:begin
                sum=0; carry=0;
            end
            3'd1:begin
                sum=1; carry=0;
           end
            3'd2:begin
                sum=1; carry=0;
           end
            3'd3:begin
                sum=0; carry=1;
           end
            3'd4:begin
                sum=1; carry=0;
           end
            3'd5:begin
                sum=0; carry=1;
           end
            3'd6:begin
                sum=0; carry=1;
           end
            3'd7:begin
                sum=1; carry=1;
           end
   endcase
   end
   endmodule

//Dataflow
module fa_data_flow(x,y,cin,sum,carry);
    input x,y,cin;
    output sum,carry;
    wire s1,s2,s3;
    assign s1=y^cin;
    assign s2=y & cin;
    assign sum=x^s1;
    assign s3=x &s1;
    assign carry=s2|s3;
endmodule

//Structural
module fa_strt(x,y,cin,sum,carry);
    input x,y,cin;
    output sum,carry;
   half_add h1(s1,s2,y,cin);
   half_add h2(sum,s3,s1,x);
   or(carry,s2,s3);
   endmodule
   module half_add(o1,o2,i1,i2);
   input i1,i2;
   output o1,o2;
   xor(o1,i1,i2);
   and(o2,i1,i2);
   endmodule

VHDL:

//Behavoral
library ieee;
    use ieee.std_logic_1164.all;
    entity fa_beh is
        port(xyz:in std_logic_vector(2 downto 0);
            sum, carry:out std_logic);
        end fa_beh;
        architecture behave of fa_beh is
            begin
                process(xyz)
                    variable temp1,temp2:std_logic;
                    begin
                        case xyz is
                            when "000"=>temp1:'0'; temp2:='0';
                            when "001"=>temp1:'1'; temp2:='0';
                            when "010"=>temp1:'1'; temp2:='0';
                            when "011"=>temp1:'0'; temp2:='1';
                            when "100"=>temp1:'1'; temp2:='0';
                            when "101"=>temp1:'0'; temp2:='1';
                            when "110"=>temp1:'0'; temp2:='1';
                            when "111"=>temp1:'1'; temp2:='1';
                                when others=>null;
                                end case;
                                sum                                carry                            end process;
                        end behave;

//Dataflow
library ieee;
    use ieee.std_logic_1164.all;
    entity fa is
        port(a,b,cin:in std_logic;
            s,cout:out std_logic);
        end fa;
        architecture fa_df of fa is
            begin
                s                cout            end fa_df;

//Structural
library ieee;
    use ieee.std_logic_1164.all;
    entity fa_strt is
        port(x,y,cin:in std_logic_vector(2 downto 0);
            sum, carry:out std_logic);
        end fa_strt;
        architecture  strt of fa_strt is
            component half_adder
            port(i1,i2:in std_logic;o1,o2:out std_logic);
            end component;
            for all:half_adder use entity work.bind22(half_add);
            for all:or2 use entity work.bind2(or_gate);
            signal s1,s2,s3;std_logic;
            begin
                h1:half_adder port map(y,cin,s1,s2);
                h2:half_adder port map(x,s1,sum,s3);
                or1:or2 port map(s2,s3,carry);
            end strt;
            library ieee;
                use ieee.std_logic_1164.all
                entity bind2 is
                    port(i1,i2:in std_logic;
                        o1:out std_logic);
                    end bind2;
                    architecture or_gate of bind2 is
                        begin
                            o1                        end or_gate;
                        library ieee;
                            use ieee.std_logic_1164.all;
                             entity bind22 is
                    port(i1,i2:in std_logic;
                        o1,o2:out std_logic);
                    end bind22;
                    architecture half_add of bind22 is
                        begin
                            o1                            o2                        end half_add;

4. Write a model for 32 bit ALU
Verilog:

module alu32(a,b,opcode,enable,o1);
    input[31:0]a,b;
    input[2:0]opcode;
    input enable;
    output[63:32]o1;
    reg[63:0]o1;
    always@(a,b,opcode,enable)
    begin
        if(enable==1)
        begin
            case(opcode)
                3'd0:begin
                    o1[31:0]=a+b;
                    o1[63:32]=32'd0;
                end
                 3'd1:begin
                    o1[31:0]=a-b;
                    o1[63:32]=32'd0;
                end
                 3'd2:begin
                    o1=a*b;
                end
                 3'd3:begin
                    o1[31:0]=~a;
                    o1[63:32]=32'd0;
                end
                 3'd4:begin
                    o1[31:0]=a&b;
                    o1[63:32]=32'd0;
                end
                 3'd5:begin
                    o1[31:0]=a|b;
                    o1[63:32]=32'd0;
                end
                 3'd6:begin
                    o1[31:0]=~(a&b);
                    o1[63:32]=32'd0;
                end
                 3'd7:begin
                    o1[31:0]=a^b;
                    o1[63:32]=32'd0;
                end
        endcase
    end
    else
    $display("alu disabled");
end
endmodule

VHDL:

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;
    entity alu32 is
        port(a,b:in std_logic_vector(31 downto 0);
             opcode:in std_logic_vector(2 downto 0);
             enable:in std_logic;
             output:out std_logic_vector(63 downto 0));
         end alu32;
         architecture behavioral of alu32 is
             begin
                 process(enable,opcode,a,b)
                     begin
                         if(enable='1')then
                             case opcode is
                                 when"000"=>output(31 downto 0)output(31 downto 0)                                     output(63 downto 32)'0');
                                     when"010"=>outputoutput(31 downto 0)                                        output(63 downto 32)'0');
                                         when"100"=>output(31 downto 0)                                        output(63 downto 32)'0');
                                         when"101"=>output(31 downto 0)                                        output(63 downto 32)'0');
                                         when"110"=>output(31 downto 0)                                        output(63 downto 32)'0');
                                         when"111"=>output(31 downto 0)                                        output(63 downto 32)'0');
                                        when others=>null;
                                        end case;
                                        else
                                        report"alu disabled";
                                    end if;
                                end process;
                            end behavioral;

5. FlipFlops
a]D flip-flop
Verilog:

module dff(d,clk,q,qb);
    input d,clk;
    output q,qb;
    reg temp;
    always@(posedge clk)
    begin
        temp=d;
    end
    assign q=temp;
    assign qb=~temp;
endmodule

VHDL:

library ieee;
    use ieee.std_logic_1164.all;
    entity dff is
        port(d,clk:in std_logic;q,qb:out std_logic);
        end dff;
        architecture dff of dff is
            signal temp:std_logic;
            begin
                process(clk)
                    begin
                        if(clk='1' and clk'event)then
                            temp                        end if;
                    end process;
                    q                end dff;

b]JK FlipFlop
Verilog:

module jkff(jk,clk,q,qb);
    input[1:0]jk;
    input clk;
    output q,qb;
    reg q,qb;
    always@(posedge clk)
    begin
        case(jk)
            2'd0:q=q;
            2'd1:q=0;
            2'd2:q=1;
            2'd3:q=~q;
    endcase
    qb=~q;
end
endmodule

VHDL:

library ieee;
    use ieee.std_logic_1164.all;
    entity jk_ff is
        port(jk:in std_logic_vector(1 downto 0);
             clk:in std_logic;
             q,qbar:out std_logic);
         end jk_ff;
         architecture jkarch of jk_ff is
             begin
                 process(clk)
                     variable temp:std_logic;
                     begin
                         if rising_edge(clk) then
                             case(jk) is
                                 when "01"=>temp:='0';
                                  when "10"=>temp:='1';
                                   when "11"=>temp:=not (temp);
                                       when others=>null;
                                       end case;
                                       q                                       qbar                                   end if;
                               end process;
                           end jkarch;

c]SR FlipFlop
Verilog:

module srff(sr,clk,q,qb);
    input[1:0]sr;
    input clk;
    output q,qb;
    reg q,qb;
    always@(posedge clk)
    begin
        case(sr)
            2'b00:begin q=q;qb=~q;end
            2'b01:begin q=0;qb=1;end
            2'b10:begin q=1;qb=0;end
            2'b11:begin q=1;qb=1;end
            default:begin q=q;qb=qb;end
    endcase
end
endmodule

VHDL:

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;
    entity sr_ff is
        port(sr:in bit_vector(1 downto 0);
             clk:in std_logic;
             q,qbar:out std_logic);
         end sr_ff;
         architecture sracrh of sr_ff is
             signal clk_div:std_logic_vector(12 downto 0):=(others=>'0');
             signal use_clk:std_logic;
             begin
                 p1:process(clk)
                 begin
                     if rising_edge(clk)then
                         clk_div                     end if;
                 end process p1;
                 use_clkqqqqnull;
                             end case;
                         end if;
                         end process;
                     end sracrh;

d]T FlipFlop
Verilog:

module tff(t,clk,q,qb);
    input clk,t;
    output q,qb;
    reg temp;
    always@(posedge clk)
    begin
        temp=~temp;
    end
    assign q=temp;
    assign qb=~temp;
endmodule

VHDL:

library ieee;
    use ieee.std_logic_1164.all;
    entity tff is
        port(t:in std_logic;
             clk:in std_logic;
             q,qb:out std_logic);
         end tff;
         architecture tff of tff is
             begin
                 process(clk)
                     variable temp:std_logic:='0';
                     begin
                         if(clk='1' and clk'event)then
                             temp:=not(temp);
                         end if;
                         q                         qb                     end process;
                 end tff;

6. n-Bit Counter
VHDL:

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;
    entity counter is
        generic(n:integer:=4);
        port(clk,reset:in std_logic;count:out std_logic_vector(n-1 downto 0));
        end counter;
        architecture counter_behave of counter is
            signal clk_div:std_logic_vector(22 downto 0):=(others=>'0');
            signal use_clk:std_logic;
            signal q:std_logic_vector(n-1 downto 0 ):=(others =>'0');
            begin
                p1:process(clk)
                begin
                    if rising_edge(clk) then
                        clk_div                    end if;
                end process p1;
                use_clk                p2:process(use_clk,reset)
                begin
                    if reset='1' then q'0');
                    elsif falling_edge(use_clk) then
                    q            end if;
        end process p2;
                count            end counter_behave;

7]BCD Counter
VHDL:

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;
    entity counter is
        port(clk,reset:in std_logic;
             count:out std_logic_vector(3 downto 0));
         end counter;
         architecture counter_behave of counter is
            signal clk_div:std_logic_vector(22 downto 0):=(others=>'0');
            signal use_clk:std_logic;
            signal q:std_logic_vector(3 downto 0 ):=(others =>'0');
            begin
                p1:process(clk)
                begin
                    if rising_edge(clk) then
                        clk_div                    end if;
                end process p1;
                use_clk                p2:process(use_clk,reset)
                begin
                    if falling_edge(use_clk)then
                        if reset='1' then q'0'); --synchronous reset
                        else q                    end if;
                    if q="1010" then q                end if;
            end process p2;
            count        end counter_behave;

7. Stepper Motor
a] Half Step
VHDL:

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;
    entity step_motorhs is
        port(clk,rst,dir:in std_logic;
             bit_ptrn:out std_logic_vector(3 downto 0));
         end step_motorhs;
         architecture behavioral of step_motorhs is
             type state_type is(hs0,hs1,hs2,hs3,hs4,hs5,hs6,hs7);
             signal state_hs:state_type;
             signal div_clk:std_logic_vector(12 downto 0):=(others=>'0');
             signal speed:std_logic;
             begin
                      p1:process(clk,rst)
                begin
                    if (rst='1') then
                        div_clk'0');
                        elsif(clk'event and clk='1')then
                            div_clk                    end if;
                end process p1;
                speed                            div_clk                    end if;
                end process p1;
                speed                            count                        end if;
                    end process;
                    dac_clk                    dac_in                    process(dac_clk,rst)
                        begin
                            if rst='1' then
                                sine_count                                elsif
                                dac_clk='1' and dac_clk'event then
                                if(sine_count=79)then
                                    sine_count                                    else
                                    sine_count                                end if;
                                end if;
                            end process;
                                with sine_count select
                                sine_out                                            "10000000" when 0,
                                           "10000000" when 0,
                                           "10000000" when 0,
                                           "10000000" when 0,
                                           "10000000" when 0,
                                           "10000000" when 0,
                                           v
                                           v
                                           "10000000" when 0,
                                           v
                                           "10000000" when 0,
                                           v
                                           "10000000" when 0,
                                           "10000000" when 0,
                                           "10000000" when 0,
                                           "10000000" when 0,
                                           "10000000" when 0,
                                           "10000000" when 0,
                                           "10000000" when 0,
                                           "10000000" when 0,
                                           "10000000" when 0,
                                           "10000000" when 0,
                                           "10000000" when 0,
                                           "10000000" when 0,
                                          "10000000" when 0,
                                          "10000000" when 0,
                                         "10000000" when 0,
                                         "10000000" when 0,
                                         "10000000" when 0,
                                         "10000000" when 0,
                                         "10000000" when 0,
                                         "10000000" when 0,
                                         "10000000" when 0,

b]Square Wave
VHDL:

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;
    entity dac1 is
        port(clk,rst:in std_logic;
            dac_in:out std_logic_vector(7 downto 0));
        end dac1;
        architecture dac_arch of dac1 is
               signal count:std_logic_vector(4 downto 0);
            signal dac_clk:std_logic;
            signal square_count:integer range 0 to 255;
            signal delay_count:integer range 0 to 255;
            begin
                process(clk,rst)
                    begin
                        if rst='1' then
                            count'0');
                            elsif
                            clk='1' and clk'event then
                            count                        end if;
                    end process;
                    dac_clk                    dac_in                    square_count126 else 0;
                    process(dac_clk,rst)
                        begin
                            if rst='1' then
                                delay_count                                elsif
                                dac_clk='1' and dac_clk'event then
                                delay_count                            end if;
                        end process;
                    end dac_arch;

c]Ramp
VHDL:

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;
    entity dac3 is
        port(clk,rst:in std_logic;
            dac_in:out std_logic_vector(7 downto 0));
        end dac3;
        architecture dac_arch of dac3 is
               signal count:std_logic_vector(4 downto 0);
            signal dac_clk:std_logic;
            signal ramp_count:integer range 0 to 255;
            begin
                process(clk,rst)
                    begin
                        if rst='1' then
                            count'0');
                            elsif
                            clk='1' and clk'event then
                            count                        end if;
                    end process;
                    dac_clk                    dac_in                    process(dac_clk,rst)
                        begin
                            if rst='1' then
                                ramp_count                                elsif
                                dac_clk='1' and dac_clk'event then
                                ramp_count                            end if;
                        end process;
                    end dac_arch;

d]Triangular Wave
VHDL:

library ieee;
    use ieee.std_logic_1164.all;
    use ieee.std_logic_unsigned.all;
    use ieee.std_logic_arith.all;
    entity dac4 is
        port(clk,rst:in std_logic;
            dac_in:out std_logic_vector(7 downto 0));
        end dac4;
        architecture dac_arch of dac4 is
            signal count:std_logic_vector(4 downto 0);
            signal dac_clk:std_logic;
            signal trang_count:integer range 0 to 255;
            signal ud:std_logic;
            begin
                process(clk,rst)
                    begin
                        if rst='1' then
                            count'0');
                            elsif
                            clk='1' and clk'event then
                            count                        end if;
                    end process;
                    dac_clk                    dac_in                    process(dac_clk,rst)
                        begin
                            if rst='1' then
                                trang_count                                elsif
                                dac_clk='1' and dac_clk'event then
                                if(ud='0') then
                                    trang_count                                    else
                                    trang_count                                end if;
                            end if;
                        end process;
                        process(dac_clk,rst)
                            begin
                                if rst='1' then
                                    ud                                    elsif
                                    dac_clk='1' and dac_clk'event then
                                    if(trang_count=254)then
                                        ud                                        elsif(trang_count=1)then
                                            ud                                        end if;
                                    end if;
                                end process;
                            end dac_arch;