MCQs on Electrical Subjects

MCQs on Switchgear and Protection

2022-11-26T22:40:00.000-08:00

Power System MCQs

1. For an arcing fault where the arc resistance is significant, an impedance or admittance relay will____.

a. The reach will depend on the arcing resistance and may under reach or over reach

b. The reach of relay is unaffected

c. Under reach

d. Over reach

2. Kick fuses are used across relay coils to prevent relay operation during______.

a. Bolted faults

b. Line to ground faults

c. Inrush current of transformers when they are energized

d. Heavy external faults

3. There is a problem of high transient over voltages while interrupting______.

a. Capacitive currents

b. Inductive currents

c. Heavy short circuit current

d. (a) or (c)

4. The most suitable circuit breaker for voltages above 220 kV is_______.

a. Oil CB

b. Air blast CB

c. SF₆ CB

d. Vacuum CB

5. Pilot relaying schemes are used for protection of______.

a. Instrument transformers

b. Transmission lines

c. Transformers

d. Bus bars

6. High synchronous reactance is preferred in the present day alternators because one can have______.

a. High voltage regulation with load

b. Reduced transient currents

c. Reduced harmonic currents

d. Reduced sub-transient currents

7. Current chopping is due to_____.

a. Interruption of unity power factor loads

b. Interruption of low inductive currents

c. Interruption of bolted faults

d. Interruption of heavy capacitive currents

8. The relay most likely to maloperate during power swing is______.

a. Reactance relay

b. Mho relay

c. Impedance relay

d. Both (a) and (c)

9. For protection of short lines against ground faults where arc resistance is comparable to the impedance of the line, the preferred relay is______.

a. Overcurrent relay

b. Admittance relay

c. Reactance relay

d. Impedance relay

10. Current chopping is minimum in case of_______.

a. ABCB

b. SF₆ CB

c. Oil CB

d. Vacuum CB

11. Reactor switching is done with____.

a. Minimum oil circuit breaker

b. SF₆ circuit breaker

c. Vacuum circuit breaker

d. Air blast circuit breaker

Load-Flow Study MCQs

2022-11-19T04:34:00.005-08:00

Power System MCQs

1. The slack bus has to be a______.

a. No constraint

b. QV bus

c. PQ bus

d. PV bus

2. Providing synchronous condensers at load bus will control_________.

a. P at bus

b. Q

c. p.f

d. (b) and (c)

3. Generally in load flow solutions the load is modelled as a______.

a. Dynamically varying load

b. Constant current load

c. Constant power load

d. Constant impedance load

4. At a slack bus_________.

a. V is unknown

b. Q is unknown

c. P is known

d. δ is unknown

5. In FDLF method, the Jacobian matrix is_______.

a. A null matrix

b. Is a constant and need to be computed only once

c. To be updated at every iteration

d. To be updated one in a few iterations

6. The time taken for each iteration in NR method compared to GS method is________.

a. Depend upon the size of the power system

b. Less

c. Equal

d. More

7. Ybus matrix is a________.

a. Unity matrix

b. Full matrix

c. Sparse matrix

d. Null matrix

8. The model used for transmission lines in load flow studies is________.

a. T-model

b. π model

c. Long-line model

d. Short-line model

9. In solution of load flow equations, if slack bus is changed______.

a. Choice of slack bus has no effect on solution of load flow equations

b. Complex voltages do not change, however line losses are affected

c. Only complex voltages will change, losses will be same

d. Complex voltages and losses will change

10. In N-R and G-S method of load flow study, the variables are respectively expressed in________.

a. Rectangular co-ordinates only

b. Polar co-ordinate only

c. polar co-ordinate and rectangular co-ordinates

d. Rectangular co-ordinates and polar co-ordinates

Fault Analysis MCQs

2022-11-11T22:40:00.000-08:00

Power System MCQs

1. When all the three phases are short-circuited, it gives rise to_____.

a. Zero fault current

b. Symmetrical fault current

c. Asymmetrical fault current

d. Both (b) and (c)

2. The zero sequence reactance will be more than the positive sequence reactance, if the equipment is:________.

a. Generator

b. Transformer

c. Transmission line

d. Both (b) and (c)

3. The sequence networks for three-phase faults are connected in______.

a. Series

b. Parallel

c. Series opposition

d. None of the above

4. The base impedance and base voltage for a given power system are 10 ohm and 400 V respectively. The base kVA and the base current will be respectively_____.

a. 4 kVA and 400 A

b. 16 kVA and 40 A

c. 4 kVA and 16 A

d. 16000 kVA and 40 A

5. In a line to ground fault on a system, the fault current is 1500 A. The zero sequence current is_____.

a. 500 A

b. 750 A

c. 0 A

d. 1500 A

6. In a practical sequence, currents were measured during a fault:________.

a. LLG fault

b. L-G fault

c. Both (a) and (b)

d. 3-ф fault

7. Symmetrical faults can be analysed using______.

a. Thevenin's theorem on per phase basis

b. Bus admittance matrix

c. Symmetrical components

d. Both (a) and (b)

8. In short circuit studies of a large power system network______.

a. Both series resistances of lines and load currents are neglected

b. Both series resistances of the lines and load currents are taken into consideration

c. The series resistances of lines are considered, while load currents are neglected

d. The series resistances of lines are neglected, while load currents are not neglected

9. Consider the following statements:

1. The positive and negative sequence components of voltage in a balanced 3-ф system are zero and only zero sequence component is present

2. The zero sequence current flows only where neutral return path is available

3. For a line to line fault, the sequence networks are connected in series

Which of the above statement(s) is/are true?

a. 2 only

b. 1 and 2 only

c. 2 and 3 only

d. 1 and 3 only

10. A three-phase transformer having zero-sequence impedance of Z₀ and neutral grounded with impedance Zₙ has the zero-sequence network as shown in the below figure.

The connections of its windings are____.

a. Star-delta

b. Star-star

c. Delta-star with neutral grounded

d. Star-star with neutrals grounded

Generating Power Stations MCQs

2022-11-04T23:22:00.000-07:00

Power System MCQs

1. A hydrograph indicates______.

a. The average run-off during the period

b. The maximum and minimum run-off during the period

c. The discharge at any time during the period under consideration

d. All of the above

2. Which is the conventional source of energy?

a. Wind

b. Geothermal

c. Radio-active substances

d. Solar

3. The power output from a hydro-electric power plant doesn't depend on ______.

a. System efficiency

b. Type of turbine

c. Head

d. Discharge

4. A station operates with a load factor and plant capacity factor of 0.75, with a maximum demand of 100 MW. The reserve capacity is______.

a. 133.33 MW

b. 0 MW

c. 75 MW

d. 100 MW

5. The area under daily load curve gives_______.

a. Energy generated to supply peak load

b. Energy generated per day

c. Energy generated during off-peak hours

d. Energy generated during peak hours

6. Within the boiler, the steam has highest temperature in_______.

a. Water drum

b. Water walls

c. Water tubes

d. Superheater

7. In which part of the thermal power plant, the steam pressure is less than that of atmosphere?

a. Condenser

b. Superheater

c. Turbine

d. Boiler

8. In a nuclear reactor, chain reaction is controlled by_____.

a. Brass rods

b. Graphite rods

c. Cadmium rods

d. Iron rods

9. In a nuclear power station using boiling water reactor, water is used as_________.

a. Neither moderator nor coolant

b. Both moderator and coolant

c. A coolant but not as a moderator

d. A moderator but not as a coolant

10. Electrostatic precipitator is installed between__________.

a. Boiler furnace and economiser

b. Economiser and air preheater

c. Air preheater and induced fan

d. Induced fan and chimney

11. The efficiency of a nuclear power plant is less than that of a conventional fuel fired thermal plant because of__________.

a. Low pressure and temperature conditions

b. Higher pressure conditions

c. Higher temperature conditions

d. Less injection of heat in the condenser

12. A generating station which has a high investment cost and low operating cost is usually operated as a________.

a. Medium load station

b. Base load station

c. Peak load station

d. None of the above

13. The surge tank is a component of a_______.

a. Hydro PP

b. Pumped storage PP

c. Nuclear PP

d. Thermal PP

14. The choice of number and size of units in a station are governed by best compromise between_______.

a. Plant load factor and use factor

b. Plant capacity factor and plant-use factor

c. A plant load factor and capacity factor

d. None of the above

15. A peak load station___________.

a. Can have a operating cost high

b. Should have a low capital cost

c. Should have a low operating cost

d. Both (b) and (a)

16. The modern trend in electric power generation is__________.

a. To have a large size thermal plants located near coal fields

b. To have a large size thermal plants near load center's

c. To have a large number of small size thermal plants located at different places

d. None of the above

17. In a steam power plant heat from the flue gases is recovered in__________.

a. A desuper heater

b. Economiser and air preheater

c. A chimney

d. A condenser

18. A plant having maximum demand more than the installed capacity will have utilization factor________.

a. More than 100%

b. Equal to 100%

c. Less than 100%

d. None of the above

19 . If capacity factor = load factor, then

a. Utilization factor is equal to one

b. Utilization factor is non-zero

c. Utilization factor is zero

d. None of the above

20. When compared to a thermal plant, the operating cost and capital cost of a hydro-electric plant are respectively__________.

a. Both low

b. Both high

c. Low and high

d. High and low

21. It is necessary to heat water before feeding it back to the boiler as because of this_________.

a. Some other impurities carried by steam and condensate due to corrosion in boiler and condenser are precipitated outside the boiler

b. Thermal stresses due to cold water entering the boiler drum are avoided

c. The dissolved oxygen and carbon dioxide which would otherwise corrode boiler are removed in the feed water heater

d. All of the above

Distribution Systems, Cables & Insulators

2022-10-28T23:31:00.000-07:00

Power System MCQs

1. The insulation resistance of a cable of 10 km length is 1 MΩ. The resistance for a length of 40 km is______.

a. Can't be determined

b. 0.25 MΩ

c. 4 MΩ

d. 1 MΩ

2. Sheath losses can be eliminated by________.

a. Cross bonding

b. Transposing cable along with cross bonding

c. Transposing cables only

d. None are effective

3. Armouring protect cables against_______.

a. Stray magnetic fields

b. Mechanical damage

c. Capacitance leakage

d. Earth fault

4. Which of the following distribution systems is the most economical?

a. Three phase, 3-wire AC system

b. Three phase, 4-wire AC system

c. DC system

d. Single phase AC system

5. For high voltage transmission lines, conductors are suspended from towers so as to_____.

a. Reduce clearance from ground

b. Take care of increase in length

c. Reduce wind and snow effect

d. Increase clearance from ground

6. The function of steel wire in an ACSR conductor is to______.

a. Reduce inductance

b. Provide additional mechanical strength

c. Take care of surges

d. Compensate for skin effect

7. The string efficiency of insulators can be increased by_______.

a. Changing orientation of strings

b. Correct grading of insulators of various capacitances

c. Increasing the number of strings

d. Reducing the number of strings

8. The insulating materials most commonly used in a cable is_______.

a. VIR

b. PVC

c. Impregnated paper

d. All of the above

9. If the frequency of a transmission system is changed from 50 Hz to 1000Hz, the string efficiency will_______.

a. May increase or decease

b. Remains unchanged

c. Decrease

d. Increase

10. The insulation thickness on the conductor in cables depends upon________.

a. Current

b. Reactive power

c. Power factor

d. Voltage

11. Which of the following distribution system is the simplest and have lowest installation cost?

a. Ring main system

b. Radial system

c. Inter connected system

d. None of the above

12. The dielectric loss in a cable is not a function of________.

a. Radius of the conductor

b. Square of the voltage

c. Frequency of supply

d. Capacitance of the cable

13. Which of the following is not a characteristic of a ring main distributor?

a. Greater reliability

b. More power loss

c. Greater voltage regulation

d. Better flexibility

14. For an existing AC transmission line, the string efficiency is 80%, if DC voltage is supplied for the same set up, the string efficiency will be_______.

a. 100%

b. 90%

c. 80%

d. < 80%

15. In a three unit insulator string, voltage across the lowest unit is 17.5 kV and string efficiency is 84.28%. The total voltage across the string will be equal to______.

a. 442.5 kV

b. 88.25 kV

c. 44.25 kV

d. 8.825 kV

Compensation Techniques, Voltage Profile Control and Load Frequency Control MCQs

2022-10-22T07:07:00.006-07:00

Power System MCQs

1. Series capacitive compensation on EHV transmission lines is used to________.

a. Improve the stability of the system

b. Reduce the voltage profile

c. Improve the protection of line

d. Reduce the line loading

2. Phase modifier is normally installed in the case of_____.

a. For all length lines

b. Long length lines

c. Medium length lines

d. Short transmission line

3. For the stable operation of interconnected system, the passive element that can be used as an interconnecting element is_______.

a. Reactor

b. Capacitor

c. Resistor

d. Any of these

4. For a synchronous phase modifier, the load angle is______.

a. 0°

b. 30°

c. 25°

d. None of these

5. A synchronous phase modifier supplies_____.

a. Inductive reactive power only

b. Both lagging and leading reactive power

c. Both active and reactive power

d. None of the above

6. Series capacitors on transmission line are of little use when_____.

a. The load VAR requirement is fluctuating

b. The load VAR requirement is large

c. The load VAR requirement is small

d. None of the above

7. Full load compensator in a line requires_______.

a. Series capacitors

b. Shunt capacitors

c. Transformers

d. Shunt reactors

8. Use of additional shunt capacitor can be made for increasing the capability of line as it________.

a. Reduces surge impedance Z₀

b. Increase α

c. Increase phase shift ß

d. All of the above

9. Shunt capacitance in an EHV line is restored to_______.

a. Improve the voltage

b. Reduce fault level

c. Improve the stability

d. None of the above

10. For a synchronous generator connected to a power station, increase in excitation will_______.

a. Increase active power generation

b. Decrease active power generation

c. Increase reactive power generation

d. Decrease reactive power generation

11. A power system needs injection of VARs at_______.

a. Full load

b. Both peak and off-peak load

c. Peak load

d. off-peak load

12. Shunt capacitors in a substation_____.

a. Deliver active power

b. Consume active power

c. Deliver lagging VARs

d. Consume lagging VARs

13. During load shedding______.

a. System power factor is changed

b. System loads are switched off

c. System frequency is reduced

d. System voltage is reduced

14. Flow of active power through a line in a power system may be controlled by______.

a. Synchronous phase modifier

b. Phase shifting transformer

c. Tap changing transformer

d. Any of the above

15. Which of the following is not a sub-component of load-frequency controller?

a. Hydraulic amplifier

b. Exciter

c. Linkage mechanism

d. Speed changer

16. Whenever there is a change in frequency of the system due to a change in the load demand, the component of the load frequency controller which senses this change in load is______.

a. Speed governer

b. Linkage mechanism

c. Hydraulic amplifier

d. Speed changer

17. When the speed governer fails to sense any variation/change in the load demand, the resulting load frequency control is termed as______.

a. Free governer operation

b. Integral controller operation

c. Proportional controller operation

d. None of the above

MCQs on Semiconductor Memories

2022-10-14T23:02:00.000-07:00

Digital Electronics MCQs

1. EPROM contents can be erased by exposing it to______.

a. Infrared rays

b. Ultraviolet rays

c. Intense heat radiations

d. Burst of microwaves

2. Which of the following memory is volatile?

a. RAM

b. PROM

c. EPROM

d. ROM

3. The access time of ROM using bipolar transitions is about______.

a. 1 sec

b. 1 nsec

c. 1 μsec

d. 1 msec

4. In a RAM, information can be stored_______.

a. By the manufacturer, only once

b. By the user, number of times

c. By the manufacturer, number of times

d. By the user, only once

5. The process of entering data into a ROM is called______.

a. Burning in the ROM

b. Programming the ROM

c. Charging the ROM

d. None of the above

6. How many address bits are required to represent a 32 k memory?

a. 14 bits

b. 12 bits

c. 16 bits

d. 10 bits

7. Which of the following memory require refreshing?

a. SRAM

b. DRAM

c. EPROM

d. ROM

8. Which of the following memory system can not be accessed randomly?

a. Magnetic tape

b. DRAM

c. EPROM

d. ROM

9. The information in ROM is stored______.

a. By the user once and only once

b. By the user any number of times

c. By the user using the ultraviolet rays

d. By the manufacturer during fabrication of the device

10. In a virtual memory system, the address used by the programmer belongs to_______.

a. Physical address

b. Memory space

c. Main memory address

d. Address space

11. A circuit in which connections to both AND and OR arrays can be programmed is called______.

a. PAL

b. RAM

c. ROM

d. PLA

12. Dynamic RAM consumes _____ power and is____ than the static RAM.

a. less, slower

b. less, faster

c. more, faster

d. more, slower

13. Cache memory works on the principle of______.

a. Locality of reference and memory

b. Locality of data

c. Locality of reference

d. Locality of memory

14. Memory interfacing technique is used to address the memory modules in order to have_____.

a. Reduced complexity in mapping hardware

b. Higher average utilization

c. Faster access to a block of data

d. Both (b) and (c)

15. When a ROM is designed to convert a binary word to a Gray code, the number of input bits to the ROM is____ the number of output bits of the ROM.

a. Not related to

b. Less than

c. Equal to

d. Greater than

16. Which of the following memories stores the most number of bits?

a. A 5 M x 8 memory

b. A 1 M x 16 memory

c. A 1 M x 12 memory

d. A 5 M x 4 memory

17. The total capacity of a ROM with 1024 rows and 4 columns is______.

a. 512

b. 256

c. 1024

d. 4096

18. The number of bits required to address a 4 k memory is_______.

a. 14

b. 13

c. 12

d. 11

A/D (Analog to Digital) and D/A (Digital to Analog) converters MCQs

2022-10-14T22:07:00.000-07:00

Digital Electronics MCQs

1. The speed of conversion is maximum in_______.

a. Parallel-comparator A/D converter

b. Counter ramp A/D converter

c. Successive-approximation A/D converter

d. Dual-slope A/D converter

2. The A/D converter whose conversion time is independent of the number of bits is______.

a. Successive approximation type

b. Dual slope type

c. Flash type

d. Counter type

3. In successive-approximation A/D converter, offset voltage equal to 1/2 LSB is added to the D/A converter's output. This is done to_____.

a. Improve the speed of operation

b. Increase the range of input voltage that can be converted

c. Increase the number of bits at the voltage

d. Reduce the maximum quantization error

4. A weighted resistor digital to analog converter using n-bits required a total of_______.

a. n+1 precision resistors

b. n precision resistors

c. n-1 precision resistors

d. 2n precision resistors

5. The number of compensators required for 12-bit flash type ADC is_____.

a. 2512

b. 3095

c. 4095

d. 4000

6. A clock rate of one megahertz operating 12-stage counter of a counter-type ADC would need a maximum conversion time of approximately_______.

a. 3.2 ms

b, 7.1 ms

c. 8 ms

d. 4.1 ms

7. Which of the following is not true in the circuit for digital-to-analog voltage converter?

a. A resistor network

b. A resonant circuit

c. A reference voltage

d. Some logic circuitry

8. In a D/A converter made with binary weighted resistors, it is difficult to maintain high accuracy as the number of bits increases, because_____.

a. The finite gain of the opamp increases inaccuracies

b. The LSB resistance consume too much current, and power

c. Obtaining stable, precise resistors with a large spread in their values is very difficult

d. As the resistance values of the most significant bits become larger, the circuit takes a very long time to settle

9. An ADC has a total conversion time of 200 micro seconds. What is the highest frequency that its analog input should be allowed to contains?

a. 10 kHz

b. 7.5 kHz

c. 2.5 kHz

d. 5 kHz

10. Which of the following ADC do not use a DAC?

a. SAR type ADC

b. Ramp type ADC

c. Dual slope type ADC

d. Both (a) and (c)

11. An ADC is used to convert signals in the range of 1 kHz to 50 kHz. The maximum conversion time would be equal to_____.

a. 10 μs

b. 20 μs

c. 5 μs

d. 15 μs

12. The full scale input voltage of an ADC is 10 V. The resolution required is 5 mV. The minimum number of bits required for ADC is______.

a. 6

b. 10

c. 11

d. 12

13. The output voltage range of a 12-bit DAC is 0 to 10 V. The integer number of 516 causes an analog output of______.

a. 1.26 V

b. 0.516 V

c. 4.17 V

d. 2.88 V

MCQs on Logic Families

2022-10-01T01:58:00.000-07:00

Digital Electronics MCQs

1. When an n-p-n transistor is used to make an inverter for positive logic, the transistor is forced into saturation when the input is high, because______.

a. Saturated transistors have a high voltage gain

b. The high base current in saturation leads to a smaller turn off time

c. The output voltage(Vce) in saturation is very close to zero

d. The large stored charge in the base, in saturation, ensures a fast turn-off

2. Compared to a passive pull-up (resistor) output stage, the active pull-up (totem-pole) output stage has______.

a. Longer delays and higher power consumption

b. Shorter delays and higher power consumption

c. Shorter delays and lower power consumption

d. Longer delays and lower power consumption

3. In today's world, the almost exclusive logic family used for making digital circuits is______.

a. TTL

b. CMOS

c. RTL

d. NMOS

4. The logic family which belongs to non-saturated logic is_____.

a. ECL

b. CMOS

c. TTL

d. NMOS

5. Emitter-coupled logic (ECL) is the fastest bipolar transistor logic because______.

a. It uses differential inputs

b. It has no p-n-p transistors

c. It uses a circuit configuration that prevents the transistors from going into saturation

d. It uses current, rather than voltages, as the output variables

6. The digital logic family which has minimum power dissipation is_____.

a. CMOS

b. DTL

c. TTL

d. RTL

7. Which of the following is the fastest logic?

a. TTL

b. ECL

c. LSI

d. CMOS

8. The digital logic family which has the lowest propagation delay time among all the logic family members is____.

a. PMOS

b. TTL

c. CMOS

d. None of these

9. In digital ICs, Schottky transistors are preferred over normal transistors because of their______.

a. Higher propagation delay

b. Higher fan out

c. Lower propagation delay

d. Lower power dissipation

10. Which TTL logic gate is used for wired ANDing?

a. Totem pole

b. Tristate output

c. Open collector output

d. ECL gates

11. CMOS circuits are extensively used for ON-chip computers, mainly because of their extremely______.

a. Low power consumption

b. Large packing density

c. Low cost

d. High noise immunity

12. CMOS logic has the property of_____.

a. Increased capacitance and delay

b. Low static power dissipation

c. High noise margin

d. Decreased area

13. The problem of "current hogging" is associated with______.

a. CMOS gates

b. ECL gates

c. DCTL gates

d. DTL gates

MCQs on Counters

2022-09-26T08:25:00.000-07:00

Digital Electronics MCQs

1. How many flip-flops are required for Mod-16 counter?

a. 5

b. 3

c. 6

d. 4

2. A ring counter consisting of five flip-flops will have______.

a. 10 states

b. 5 states

c. infinite states

d. 32 states

3. If the input to T-flip flop is 100 Hz signal, the final output of the three T-flip flops in cascade is______.

a. 12.5 Hz

b. 500 Hz

c. 1000 Hz

d. 333 Hz

4. A 4-bit synchronous counter uses flip-flops with propagation delay times of 20 ms each. The maximum possible time required for change of state will be____.

a. 10 ns

b. 30 ns

c. 20 ns

d. 60 ns

5. How many flip-flops are required to construct a decade counter?

a. 4

b. 2

c. 10

d. 3

6. If the clock input applied to a cascaded Mod-6 and Mod-4 counter is 48kHz, the output of the cascaded arrangement would be_____.

a. 12 kHz

b. 8 kHz

c. 4.8 kHz

d. 2 kHz

7. For what minimum value of propagation delay in each FF will a 10-bit ripple counter skip a count when it is clocked at 10 MHz?

a. 100ns

b. 5 ns

c. 10 ns

d. None of these

8. A binary ripple counter is required to count up to 16,383₁₀ . If the clock frequency is 8192MHz, what is the frequency at the output of the MSB?

a. 500 kHz

b. 150 kHz

c. 225 kHz

d. 625 kHz

9. A 25 : 1 ripple counter is required. If 4 flip-flops are available on a chip, how many chips are needed?

a. 3

b. 1

c. 2

d. 25

10. Minimum number of J-K flip-flops needed to construct a BCD counter is______.

a. 5

b. 4

c. 3

d. 2

11. The decoding error of the counter can be avoided by______.

a. Increasing propagation delay of flip-flops used in the counter

b. Using very fast logic

c. Using the strobe signal

d. Reducing the propagation delay of flip-flops used in the counter

12. A switch tailoring counter is made by using a single D-flip-flop. The resulting circuit is a______.

a. SR flip-flop

b. JK flip-flop

c. D flip-flop

d. T flip-flop

MCQs on Registers

2022-09-10T01:58:00.003-07:00

Digital Electronics MCQs

1. Data can be changed from spacial code to temporal code and vice-versa by using_____.

a. Combinational circuits

b. A/D counters

c. Shift registers

d. Counters

2. Shifting a register content to left by one bit position is equivalent to______.

a. Addition by two

b. Multiplication by two

c. Subtraction by two

d. Division by two

3. The content of a 4-bit register is initially 1101. The register is shifted 2 times to the right, with the serial input being 1011101. The content of the register after each shift operations are respectively

a. 1101 and 1011

b. 0001 and 1000

c. 1001 and 1001

d. 1110 and 0111

4. How long will it take to shift and 8-bit number into and 8-bit serial -in parallel-out shift register if the clock is set at 10 MHz?

a. 700 ns

b. 0 ns

c. 800 ns

d. 100 ns

5. The flip flop used in shift registers are generally______.

a. T flip-flop

b. D flip flop

c. J-K flip-flop

d. S-R flip-flop

6. Data can be changed from spacial code to temporal code spacial by using_____.

a. Timers

b. SIPO shift resisters

c. PISO shift resistors

d. ADCs and DACs

Sequential Logic Circuits MCQs

2022-09-05T01:55:00.000-07:00

Digital Electronics MCQs

1. For which of following flip-flops, the output is clearly defined for all combinations of to inputs?

a. D flip-flop

b. J-K flip-flop

c. R-S flip-flop

d. None of these

2. What J-K input condition will always set Q+ upon the occurrence of the active clock transition?

a. J = 1, K = 0

b. J = 1, K = 1

c. J = 0, K = 1

d. J = 0, K = 0

3. In a J-K flip-flop, toggle means___.

a. Change the output to the opposite state

b. Set Q = 1 and Q(bar) = 0

c. Set Q = 0 and Q(bar) = 1

d. No change in the input

4. The output of S-R flip-flop when S = 1, R = 0 is______.

a. High impedance

b. No change

c. High

d. Low

5. Assertion(A): An unlocked flip-flop is called a latch.

Reason(R): A latch is constructed using two cross-coupled NAND gates or NOR gates.

a. A is false but R is true

b. A is true but R is false

c. Both A ad R are true but R is not the correct explanation of A

d. Both A and R are true but R is the correct explanation of A

6. Race around condition always arise in a______.

a. Digital circuit

b. Synchronous circuit

c. Asynchronous circuit

d. Combinational circuit

7. A T-flip-flop can be made from a J-K flip-flop by using______.

a. An OR gate

b. A AND gate

c. An XOR gate

d, None of these

8. The J-K master-slave flip-flop is different from the S-R flip-flop (Both made with NAND gates)

in that, it has_____.

a. A much shorter delay

b. A valid output when both inputs are 1

c. No need of a clock

d. No race around condition

9. In a clocked S_R flip-flop made with NAND gates, the input combination S = 1, R = 1, is not permitted because it leads to_____.

a. The output becoming available before the clock goes low

b. An unpredictable output when the inputs become zero

c. Both the outputs being zero simultaneously

d. A race around condition

Combinational Logic Circuits MCQs

2022-08-28T08:20:00.003-07:00

Digital Electronics MCQs

1. Consider the following statements:

When a MUX is used to implement a logic function, the logic variables are applied to the MUX's data inputs.
The circuit for a DEMUX is basically the same as that for a decoder.

Of these:

a. Both statements are false

b. Statement-1 is false while statement-2 is correct

c. Both the statements are correct

d. Statement-1 is correct while 2 is false

2. The logic function F(A, B, C) = Σ (1, 3, 5, 6) can be implemented using:

a. One 4x1 MUX

b. One 4x1 MUX and an OR gate

c. One 4x1 MUX and a AND gate

d. One 4x1 MUX and a NOT gate

3. A certain multiplexer can switch one of 32 data inputs to its output. The number of control inputs in this multiplexer is_____.

a. 8

b. 5

c. 16

d. 32

4. Assertion(A): The multiplexer can be viewed as a function generator.

Reason(R): The multiplexer acts like a digitally controlled multi-position switch.

a. A is false but R is true

b. A is true but R is false

c. Both A and R are true, but R is not the correct explanation of A

d. Both A and R are true, and R is the correct explanation of A

5. A multiplexer has______.

a. One data output and number of select inputs

b. One data output and number of data inputs

c. One data output, a number of data inputs, and number of select inputs

d. One data input and number of data outputs

6. A multiplexer can be used as______.

a. 7-segement LED driver

b. Counter

c. Logic element

d. Flip-flop

7. To add two 4-bit numbers using a parallel adder circuit, we require_____.

a. 8-half adders

b. Neither (a) nor(b)

c. Either (a) or (b)

d. 4-full adders and 1-OR gate

8. The correction to be applied in decimal adder to the generated sum is____.

a. 01010

b. 01101

c. 00110

d. 00101

9. The gates required to build a half adder are:

a. EX-OR gate and OR gate

b. EX-OR gate and NOR gate

c. EX-OR gate and AND gate

d. Four NAND gate

10. The code where all successive numbers differ from their preceding number by a single bit is_____.

a. BCD code

b. Gray code

c. Excess-3 code

d. Binary code

11. A device which changes from serial data to parallel data is_______.

a. FLIP-FLOP

b. COUNTER

c. MULTIPLEXER

d. DEMULTIPLEXER

12. A device which converts BCD to Seven Segment is called_____.

a. Encoder

b. Decoder

c. Demultiplexer

d. Multiplexer

13. When the set of input data to an even parity generator is 0111, the output will be_____.

a. Depends on the previous input

b. 1

c. 0

d. Undefined

14. Compared to a parallel adder, a serial adder is______.

a. Faster, and requires more hardware

b. Slower, and Requires more hardware

c. Faster, and requires less hardware

d. Slower, and requires less hardware

15. In a 2-bit half adder, the sum and the carry bits are obtained, respectively, by the______.

a. NAND and OR gate

b. NAND and NOR gate

c. NOr and EXCLUSIVE-OR gates

d. EXCLUSIVE-OR and AND gate

16. A 16-to-1 multiplexer can be used to______.

a. Convert a 4-bit serial input to a parallel output

b. Convert a 4-bit parallel input to a serial output

c. Convert a 16-bit serial input to a parallel output

d. Convert a 16-bit parallel input to a serial output

Logic Gates & Switching Circuits MCQs

2022-08-20T02:29:00.000-07:00

Digital Electronics MCQs

1. Which of the following logic gate follow both commutative and associative law?

a. AND gate

b. NAND gate

c. NOR gate

d. None of these

2. The minimum number of NOR gates requires to implement the expression f(A, B, C) = πM(0, 1, 2, 3, 4, 7) is______.

a. 6

b. 7

c. 4

d. 5

3. The number of two input NAND gate required to implement an OR gate and an EX-NOR gate are respectively______.

a. 2 and 4

b. 3 and 5

c. 3 and 4

d. 2 and 5

4. If one of the input to an EX-NOR gate is fixed to logic '1', then the output of this gate will be______.

a. Logic '1'

b. Same as input

c. Logic '0'

d. Complement of its input

5. An AND gate______.

a. Gives high output only when all inputs are low

b. Is equivalent to a series switching circuit

c. Implements logic addition

d. Is equivalent to a parallel switching circuit

6. An XOR gate produces output 1 only when two inputs are____.

a. Equal

b. Low

c. High

d. Different

7. A logic gate is an electronic circuit which______.

a. Performs arithmetic and logic functions

b. Operates on binary algebra

c. Alternates between 0 and 1 values

d. Allows flow of electrons only in one direction

8. The output of a logic gate is '0' when both its inputs are different. The gate is_____.

a. Either an EX-NOR or NOR gate

b. Either an EX-OR or NOR gate

c. Either an EX-NOR or NAND gate

d. Either an EX-OR or NAND gate

9. A circuit has three inputs and one output. The output is 1 if at least two of the three input variables are 1, otherwise it is zero. The minimum number of basic gates required to implement the output(Y) are_____.

a. 8

b. 7

c. 4

d. 3

10. In the truth table of an N-input OR gate, in the column for the output of the gate,______.

a. The number of times a zero occurs is a complex function of N

b. The output is zero if any one of the input is zero

c. The number of zeros is always 1

d. The number of zeros is equal to N

11. Assertion (A): When a number of variables are to be X-NORed, a number of two-input X-NOR

gates can be used.

Reason (R): Three or more variable X-NOR gates will make the circuit costly.

a. A is false but R is true

b. A is true but R is false

c. Both A and R true but R is not the correct explanation of A

d. Both A and R are true and R is the correct explanation of A

Boolean Algebra and minimization techiniques MCQs

2022-08-12T22:39:00.003-07:00

Digital Electronics MCQs

1. The only function of NOT gate is to ______.

a. Invert an input signal

b. Act as a universal gate

c. Stop a signal

d. None of these

2. Negative logic in a logic circuit is one in which______.

a. Logic 0 voltage level is higher than logic 1 voltage level

b. Logic 0 voltage level is lower than logic 1 voltage level

c. Logic 0 and 1 are represented by zero and positive voltages respectively

d. Logic 0 and 1 are represented by the negative and zero voltages respectively

3. Which of the following Boolean expression is not true?

a. A . A = A

b. A + A bar = 1

c. A + 1 = A

d. A .A bar = 0

4. The POS form of expression is suitable for circuit using______.

a. NAND

b. AND

c. XOR

d. NOR

5. Which of the following is/are the correct reason for using Gray code in k-maps?

a. Gray code provides cell values that differ in only one bit in adjacent cells

b. Gray code is efficient than binary code

c. No other code is available

d. All of the above

6. When eight adjacent 1's are grouped horizontally or vertically, the group so found is called_____.

a. Octet

b. Quad

c. Pair

d. Hex

7. For 4 number of variables, maximum possible self dual expressions are______.

a. 256

b. 16

c. 65536

d. None of these

8. The minimized output equation of the k-map shown below has.

K-map table

a. 9 minterms

b. 6 minterms

c. 7 minterms

d. 5 minterms

Basics of Digital Electronics MCQs

2022-08-08T02:10:00.000-07:00

Digital Electronics MCQs

1. The decimal equivalent of (101111.1101)₂ is_______.

a. 51.6328

b. 47.8125

c. 38.6254

d. 52.6789

2. The range of numbers that can be represented using 6-bits in signed binary number representation is________.

a. -31 to +32

b. -32 to +32

c. -32 to +31

d. -31 to +31

3. The 7-bit even parity Hamming code of the binary bits 0101 is______.

a. 0 0 1 0 1 0 0

b. 0 1 0 0 1 0 1

c. 1 0 1 0 0 1 0

d. 1 1 0 1 1 0 1

4. The ASCII code is a_______.

a. Alphanumeric code

b. Cyclic code

c. Weighted code

d. Reflective code

5. Which of the following 4-bit binary pairs does not forms a Gray code pair?

a. 0101, 0100

b. 1110, 1010

c. 1010, 1001

d. 1100,1101

6. Which of the following code is correct regard of excess-3 code ?

a. It is a BCD code

b. It is a self-complementing code

c. It is an unweighted code

d. All of the above

7. Multiplication of two binary numbers A and B is 11011. If A = 011, then B is_____.

a. 0101

b. 1011

c. 1100

d. 1001

8. Which of the following statement is not correct, in regard to the "GRAY CODE"?

a. It is a unit distance code

b. It is a reflective code

c. It is a BCD code

d. It is a cyclic code

9. The ASCII is an input code which is a_____.

a. Seven bit code

b. Eight bit code

c. Two bit code

d. Four bit code

10. The number of bits required to represent an eight digit decimal number BCD is_____.

a. 24

b. 8

c. 16

d. 32

11. An example of self complementing code is______.

a. 8421 code

b. XS-3 code

c. Gray code

d. 7421 code

12. When signed numbers are used in binary arithmetic, then which one of the following notations would have unique representation for zero?

a. 9's complement

b. 2's complement

c. 1's complement

d. Sign magnitude

13. Addition of all gray code to convert decimal(0-9) into gray code is______.

a. 53

b. 69

c. 108

d. 129

14. The binary number, 110011 is to be converted to gray code. The number of gates and type required are________.

a. 5, XOR

b. 6, XOR

c. 6, XNOR

d. 6, AND

15. Three Boolean operators are______.

a. NOR, NAND, NOT

b. NOT, NAND, OR

c. NOR, OR, NOT

d. NOT, OR, AND

MCQs on Power Electronics Part-2

2022-07-29T22:45:00.000-07:00

Power Electronics

1. At reduced voltage and reduced frequency in ac drives:

Current gets reduced
pf is improved under maximum torque conditions
The maximum torque is reduced
The maximum torque occurs at a higher value of slip

Choose the correct code from the given options:

a. 1,2,3 and 4

b. 2 and 4

c. 1 and 3

d. 2,3 and 4

2. At lower speeds of a motor or at higher firing angle, power factor of the system is______.

a. Unaffected

b. Deteriorated

c. Improved

d. May improve or deteriorate

3. For an ac voltage controller fed induction motor drive negotiating a load whose torque requirement does not vary with speed_____.

a. The fundamental component of current drawn from the supply decreases as speed is reduced

b. The fundamental component of current drawn from supply is independent of speed

c. The fundamental component of current drawn from the supply increases as speed is reduced

d. None of the above

4. Which of the following option is not correct about an ac drive compared to a dc drive?

a. AC drives are less expensive

b. Power converters for AC drives generate harmonic in the supply system and load circuit

c. AC motors are lighter in weight

d. Power converters for AC drives are simple

5. A delta-connected induction motor being fed by a 3-phase ac to dc inverter and operated in constant v/f control mode requires during starting a _____.

a. Auto-transformer starter

b. DOL starter

c. star-delta starter

d. None of the above

6. As SCR circuit supplies power to a dc motor. The armature current of the motor will be ______.

a. Exponential rise and decay

b. Sinusoidal

c. Constant

d. None of the above

7. In ac motor control, the ratio of voltage-to-frequency is maintained at constant value______.

a. To maximise the current drawn from the supply to provide torque

b. To provide maximum pull-out torque

c. To make maximum use of magnetic circuits

d. To make minimum use of magnetic circuits

8. The phase controlled rectifiers used in speed control of dc motors converts fixed ac supply voltage into______ output voltage.

a. variable dc

b. Variable ac

c. Full rectified dc

d. variable frequency ac

9. The speed of dc motor can be controlled by using.

a. Thyristors

b. Diodes

c. Transistors

d. Either diodes or thyristors

10. In converter control of induction motor's speed control, a d.c. link is use. This is to_____.

a. Trigger the thyristor of the inverter

b. Vary the slip

c. Provide necessary d.c. voltage to inverter

d. Provide a constant peak flux density to the air-gap and core insulation

11. In cycloconverters speed control of an induction motor, cycloconverter frequency_____.

a. Is always less and about one-third of supply frequency

b. Can be higher or lower than supply frequency

c. Is higher than the supply frequency

d. Is equal to that of supply frequency

12. A fully controlled thyristor bridge drives a d.c. motor. The system is capable of_____.

a. Only motoring in forward direction, no braking

b. Motoring in forward direction and braking in reverse direction

c. Only motoring in both directions, no braking

d. Motoring and braking in both directions

13. UPS find application in ______.

a. Electric traction

b. Computer power supply

c. Battery powered vehicle

d. HVDC

14. SMPS are superior to linear power supplies in respect of______.

a. Efficiency and regulation

b. Noise and cost

c. Size and efficiency

d. Regulation and noise

15. Consider the following statements :

Switched mode power supplies are preferred over the continuous types, because these are:

Suitable for low power circuits
More efficient
Suitable for use in both ac and dc
Suitable for high-power circuits

of these, the correct statements are:

a. 2 and 3

b. 1 and 2

c. 1 and 3

d. 2 and 4

MCQs on Cycloconverters

2022-07-23T00:00:00.000-07:00

Power Electronics

1. Assertion (A): A cycloconverter essentially a dual converter but so operated as to produce an alternating output voltage.

Reason (R): Each SCR in a cycloconverter works as a phase-controlled converter with a varying firing angle.

a. A is false but R is true

b. A is true but R is false

c. Both A and R are true but R is not the correct explanation of A

d. Both A and R are true and R is the correct explanation of A

2. A cycloconverter requires_____.

a. Natural commutation in step-down mode and forced commutation in step-up mode

b. Forced commutation in step-down mode and natural commutation in step up mode

c. Forced commutation in both step-up and step-down mode

d. Natural commutation in both step-up and step-down mode

3. The number of thyristors required for single-phase to single-phase cycloconverter of the mid-point type and for three-phase 3-pulse type cycloconverter are respectively____.

a. 4 and 36

b. 4 and 18

c. 8 and 18

d. 4 and 6

4. The controlled rectifier used in which application_______.

a. Solar cells

b. Magnet Power supply

c. High power ac drive

d. Ceiling fan drive

5. Cycloconverter used in which application_______.

a. Solar cells

b. Magnet Power supply

c. High power ac drive

d. Ceiling fan drive

6. Inverter used in which application________.

a. Solar cells

b. Magnet Power supply

c. High power ac drive

d. Ceiling fan drive

7. Voltage controller used in which application_______.

a. Solar cells

b. Magnet Power supply

c. High power ac drive

d. Ceiling fan drive

8. Compared to a cycloconverter, a d.c link converter______.

a. Requires natural commutation

b. Is suitable for low frequencies only

c. Has high input power factor if diode rectifier is used

d. All of the above

9. A cycloconverter power electronic equipment is a______.

a. Device which converts dc to ac

b. Device which converts ac to dc

c. frequency converter which has no intermediate dc state

d. None of the above

10. An intergroup reactor is used in a single-phase cycloconverter circuit to______.

a. Limit di/dt in the semiconductor switch

b. Limit circulating current

c. Reduce voltage ripples

d. Reduce current ripples

MCQs on Microcontrollers Part-9

2022-07-15T21:54:00.001-07:00

Microprocessor and Microcontrollers

1. A ROM is used to store the table for multiplication of two 8-bit unsigned integers______.

a. 64 K x 8

b. 4 K x 16

c. 64 K x 16

d. 256 K x 16

2. An advantage of memory interfacing is that_____.

a. A non-volatile memory is obtained

b. The cost of the memory is reduced

c. Effective speed of the memory is increased

d. A larger memory is obtained

3. The highest address in a 48 K memory, in hexadecimal system, is:______.

a. FFFF H

b. FEEE H

c. CDEF H

d. BFFF H

4. In an 8-bit microcomputer having 8 K bytes of RAM memory, the length of SP will be:______.

a. 13

b. 11

c. 8

d. 5

5. A typical cell, for dynamic RAM, can be implemented by using how many MOS transistors?

a. Two

b. Five

c. One

d. Six

6. A microprocessor has 24 address lines and 32 data lines. If it uses 10 bits of opcode, the size of its memory buffer register is:______.

a. 14 bits

b. 32 bits

c. 24 bits

d. 22 bits

7. The addressing mode in which the machine language instruction itself includes the data is called______.

a. Indirect

b. Indexed

c. Immediate

d. Direct

8. What is the addressing mode used in the instruction PUSH D_____.

a. Register indirect

b. Register

c. Direct

d. Immediate

9. Which of the following instruction does not use the stack?

a. JMP

b. CALL

c. RET

d. None of these

10. An instruction cycle is a time in which, a hard-wired controller completes four functions. The correct sequence of these functions is______.

a. Execute-decode-fetch-update

b. Fetch-update-decode-execute

c. Fetch-decode-update-execute

d. Decode-execute-fetch-update

11. What is the effect of DAD H instruction?

a. To shift each bit one position to the left

b. To shift each bit one position to the right

c. To shift each bit one position to the left with a zero inserted in LSB position

d. To shift each bit one position to the right with a zero inserted in MSB position

12. Which of the following instruction will alter the contents of accumulator?

a. ORA A

b. CPI 3A H

c. CMP C

d. ANI 5C H

13. Which of the following 8085 instruction does not affect the flags?

a. ORA C

b. INR A

c. INX B

d. DCR A

14. Which of the 8085 instructions uses the stack?

a. MOV

b. RET

c. JMP

d. DCR A

15. The advantage of immediate addressing is______.

a. To allow both positive and negative operands

b. Not to fetch operand from memory

c. To execute the instruction immediately

d. To decode the operand easily

MCQs on Microcontrollers Part-8

2022-07-08T23:21:00.000-07:00

Microprocessor and Microcontrollers

1. The number of control and status signals in 8085 microprocessor are respectively______.

a. 2 and 4

b. 2 each

c. 3 and 2

d. 2 and 3

2. If the status lines S₁ and S₀ is High, then 8085 microprocessor is performing:

a. Opcode fetch operation

b. HOLD operation

c. Half operation

d. None of the above

3. Which of the following option is not correct about the various flags in 8085 microprocessor?

a. The carry flag is set if the ALU operation result generates a carry

b. The parity flag is set if the result has odd parity

c. The zero-flag is set if the ALU operation result is zero

d. The sign-flag is set to zero, if the most significant bit of the result of an arithmetic or logic operation is zero

4. Pesudo-instructions are basically______.

a. Instructions that are treated like comments

b. False instructions

c. Instructions that are ignored by the microprocessor

d. Assembler directives

5. Which microprocessor pins are used to request and acknowledge a DMA transfer?

a. reset and ready

b. HOLD and HLDA

c. reset and ready

d. ready and wait

6. The first modern computer was called____.

a. INTEL

b. ENIAC

c. FLOW-MATIC

d. UNIVAC-I

7. NMI input is_______.

a. Edge sensitive

b. Level sensitive

c. Neither edge nor level sensitive

d. Both edge and level sensitive

8. What is the direction of control bus?

a. Unidirectional into μP

b. Bidirectional

c. Unidirectional out of μP

d. Mixed direction i.e. some line into μP and some others out of μP

9. Every processor must necessarily have_____.

a. Control bus

b. Data bus and address bus

c. Data bus

d. Address bus, data bus and control bus

10. The number of address lines required to address 8 K bytes of memory is_____.

a. 15

b. 16

c. 13

d. 14

11. The number of memory chips of size 1 K x 4-biits required to build a memory bank of size 16 K x 8 bits is_______.

a. 8

b. 32

c. 64

d. 16

12. The I/O devices in 8085 microprocessor can be used in :_____.

a. Memory mapped I/O only

b. I/O mapped I/O only

c. Memory mapped I/O or I/O mapped I/O

d. None of the above

13. The maximum number of memory and I/O devices that can be addressed in a 8085 microprocessor based system is_____.

a. Infinite

b. 2⁸

c. 2¹⁶

d. 2⁸ + 2¹⁶

14. The capacity of a memory chip is 8192 bits, and it has 2048 rows. Then the organization of the chip is_____.

a. bit organized

b. nibble organized

c. byte organized

d. word organized

15. The size of the memory, a microprocessor can access is determined by the number of_____lines the microprocessor.

a. Address

b. Status

c. Control

d. Data

MCQs on Microcontrollers Part-7

2022-07-01T22:42:00.000-07:00

Microprocessor and Microcontrollers

1. A programme written in machine language is called the______.

a. Object program

b. Source program

c. Hardware program

d. Both (b) and (c)

2. In 8085 microprocessor, the number of interrupts maskable and non-maskable are_____.

a. zero and five respectively

b. five and zero respectively

c. one and four respectively

d. four and one respectively

3. The interrupt pin TRAP of a 8085 microprocessor is______.

a. Level triggered

b. Edge triggered

c. Both edge and level triggered

d. Neither level nor edge triggered

4. A microcontroller differs from a microprocessor in terms of_____.

a. Memory configuration and instruction decoding

b. Memory configuration and I/O interfaces

c. I/O interfaces and instruction decoding

d. data bus width and clock speed

5. A microprocessor program written in assembly language is translated into machine language. The number of instruction in the machine language when compared with the number of instructions in assembly language is______.

a. Less only

b. More only

c. Same

d. Either more or less

6. The number of input pins of 8085 microprocessor are_____.

a. 27

b. 19

c. 21

d. 40

7. Which of the following statements is correct? In 8085 microprocessor, the READY signal is useful when the CPU communicates with_____.

a. A DMA controller chip

b. A PPI chip

c. A slow peripheral device

d. A fast peripheral device

8. The highest integer that can be stored in an 8-bit accumulator is___.

a. 255

b. 144

c. 64

d. 256

9. The number of general 8-bit registers in 8085 microprocessor are_____.

a. 12

b. 6

c. 9

d. 3

10. In 8085 pairing of registers B, C, D, E, H, L is ____.

a. B-C, D-L, H-E

b. B-C, D-E, H-L

c. B-D, C-E, H-L

d. either of these

11. In a microprocessor, the program counter points to the address location from where the______.

a. Next byte is to be fetched

b. Current byte is to be fetched

c. Next byte is to be stored

d. Current byte is to be added

12. Microprocessor based instrument can be used to measure_______.

a. Flow only

b. Temperature only

c. Pressure only

d. All the above quantities

13. Which interrupt has the lowest priority?

a. INTR

b. TRAP

c. RST 4.5

d. RST 7.5

14. What is the vector address of interrupt RST 6?

a. 0030H

b. 0024H

c. 0034H

d. 0038H

15. Which of the following is a software interrupt?

a. RST 4.5

b. RST 0

c. Both of these

d. None of these

MCQs on Control System Part-7

2022-06-24T23:04:00.001-07:00

Control System

1. A first order dynamic linear system with a proportional controller exhibits an offset to a unit step input. The offset can be reduced by _____.

a. Decreasing the proportional gain

b. Adding integral mode

c. Adding derivative mode

d. Increasing the proportional gain

2. Addition of zeros in a transfer function causes______.

a. Lead-lag compensator

b. Lead compensator

c. Lag compensator

d. None of the above

3. A phase lead compensation network_______.

a. Is applied when error constants are specified

b. Reduces the steady state error

c. Decreases the system bandwidth

d. Speeds up the dynamic response

4. The input to a controller is______.

a. Error signal

b. Sensed signal

c. Desired variable signal

d. Servo signal

5. Addition of a pole to the closed-loop transfer function results in_____.

a. Increase in stability of the system

b. Increase in bandwidth

c. Reduction in maximum overshoot

d. Reduction in rise time

6. Which of the following properties is/are not exhibited by a phase lead network?

1. The velocity constant is usually increased

2. The slope of the magnitude curve is reduced at the gain cross over frequency

3. The bandwidth is reduced

4. The response becomes faster

a. 1,2,3 and 4 only

b. 2 and 3 only

c. 3 only

d. 1 only

7. The action of a PD controller is to______.

a. Reduce the rise time and maintain a constant value of steady state error of the system

b. Maintain a constant value of rise time and reduce the steady state error of the system

c. Reduce the rise time and increase the steady error of the system

d. Increase the rise time and steady state error of the system

8. The transfer function of a system is given as:

a. Lag network

b. Lead network

c. Lag-lead network

d. Proportional network

9. Integral feedback control______.

a. Improves steady state response

b. Improves transient response

c. Reduces feedback time

d. None of the above

10. The industrial controller having the best steady state accuracy is______.

a. A proportional controller

b. A rate feedback controller

c. An integral controller

d. A derivative controller

11. With regard to the filtering property, the lead compensator and the lag compensators are respectively______.

a. Both low pass filters

b. Both high pass filters

c. High pass and low pass filters

d. Low pass and high pass filters

12. For arbitrary pole placement, the following combination is necessary______.

a. State feedback and controllability

b. Output feedback and controllability

c. Output feedback and observability

d. State feedback and stability

13. For a linear time invariant system, an optimal controller can be designed if_____.

a. The system is uncontrollable but stable

b. The system is stable and unobservable

c. The system is controllable and observable

d. The system is unstable but observable

14. The eigen values of linear system are the location of_______.

a. Poles of the system

b. Zeros of the system

c. Both (a) and (b)

d. Finite poles and zeros

15. Assertion (A) : Stepping motors are compatible with modern digital systems.

Reason (R) : The nature of command is in the forms of pulses.

a. A is false a but R is true

b. A is true but R is false

c. Both A and R are true and R is a correct explanation of A

d. Both A and R are true but R is not a correct explanation of A

Basic Electrical MCQs Part-9

2022-06-18T05:34:00.000-07:00

Basic Electrical

1. Assertion (A): It is necessary that the tuning coil should be of high resistance and low inductance.

Reason (R): High value of Q-factor means not only higher magnification but also a higher selectivity of the tuning coil.

a. A is true, but R is false

b. A is false, but R is true

c. Both A and R are true, but R is not the correct explanation of A

d. Both A and R are true, and R is the correct explanation of A

2. Voltage transfer function of a simple RC differentiator has______.

a. A zero at infinite and a finite pole

b. A zero at origin and a finite pole

c. A finite zero and a pole at the origin

d. A finite zero and a pole at infinity

3. Assertion (A): Simple resistors, inductors and capacitors are linear elements.

Reason (R): The resistances, inductances and capacitances do not change with a change in applied voltage or the circuit current.

a. A is true, but R is false

b. A is false, but R is true

c. Both A and R are true, but R is not the correct explanation of A

d. Both A and R are true, and R is the correct explanation of A

4. A network function can be completely specified by:_____.

a. Real part of poles

b. Real parts of zeros

c. Poles and zeros

d. Poles, zeros and scalar factor

5. Which of the following property does not relates to LC impedance or admittance functions ?

a. The highest and lowest powers of numerator or denominator polynomials differ by unity

b. Poles and Zeros lie on negative real axis, and they alternate

c. This is the ratio of even to odd or odd to even polynomial

d. There must be either a pole or zero at infinity or origin

6. If the impulse response is realisable by delaying it appropriately and is bounded for bounded excitation, then the system is said to be______.

a. Non-causal and unstable

b. Causal and stable

c. Non-causal but stable

d. Causal but unstable

7. A network-A has zeros only in the left-half of the s-plane while the network-B has zeros only in the right-half of the s-plane. The network-A and Network-B will respectively called______.

a. A minimum phase function and a non-minimum phase function

b. An all pass function ans non-minimum phase function

c. A non-minimum phase function and an unstable function

d. A stable function and an unstable function

8. An LC-admittance or impedance function______.

a. has all zeros on the negative real axis of the s-plane

b. has simple poles and zeros in the left half of the s-plane

c. is an odd rational function

d. has no pole or zero at the origin or infinity

9. A stable system must have______.

a. negative real parts for all zeros and pole

b. positive real part for any pole or zero

c. At least one pole or zero lying in the right-half s-plane

d. zero or negative real part for poles and zeros

10. A Hurwitz polynomial has_____.

a. poles anywhere in s-plane

b. zero anywhere in s-plane

c. only poles in the left half of s-plane

d. only zeros in the left half of s-plane

11. Cauer and Foster forms of realization are used for_____.

a. Transfer impedance functions

b. Driving point impedance functions

c. Transfer reactance functions

d. Driving point reactance functions

12. In the incidence matrix of a graph_____.

a. The determinant value is zero provided the loop is a closed one

b. Algebraic sum of the coulmn entries is zero

c. Both (a) and (b)

c. None of the above

13. Two graphs are said to be isomorphic graph if their incidence matrices_____.

a. Are transpose of each other

b. have a determinant value of unity

c. Are identical

d. have a determinant value of zero

14. The dual of series RL circuit is______.

a. Series RC circuit

b. Parallel RC circuit

c. Series RC circuit

d. Parallel RL circuit

15. Three-phase power can be measured by two-wattmeter method in case of_____.

a. Balanced load only

b. Balanced load and balanced source only

c. Unbalanced load and unbalanced source only

d. Both (b) and (c)

Basic Electrical MCQs Part-8

2022-06-11T23:02:00.006-07:00

Basic Electrical

1. For the parallel RLC circuit to be underdamped_____.

a. `R < 2\sqrt{\frac{L}{C}}`

b. `R>2\sqrt{\frac{L}{C}}`

c. `R>\frac{1}{2}\sqrt{\frac{L}{C}}`

d. `R<\frac{1}{2}\sqrt{\frac{L}{C}}`

2. Pole of a network is frequency at which______.

a. Network frequency becomes unity

b. Network frequency becomes infiniteₐᵥ

c. Network frequency becomes zero

d. None of the above

3. A parallel RLC circuit is said to be underdamped_____.

a. `R < 2\sqrt{\frac{L}{C}}`

b. `R>2\sqrt{\frac{L}{C}}`

c. `R>\frac{1}{2}\sqrt{\frac{L}{C}}`

d. `R<\frac{1}{2}\sqrt{\frac{L}{C}}`

4. In a purely resistive circuit, the average power Pₐᵥ is ______ the peak power Pₘₐₓ.

a. Equal to

b. one-fourth of

c. Non-half of

d. Double

5. For an ideal transformer_______.

a. y-parameters exist, but not the z-parameters

b. z-parameters exist, but not the y-parameters

c. Neither z nor y-parameter exist

d. Both z and y-parameter exist

6. What the greatest mutual inductance that an air-core transformer can have with the self-inductances of 0.3 and 0.7 H respectively.

a. 0.458 H

b. 0.350 H

c. 0.210 H

d. 0.500 H

7. Mutual inductance between two magnetically coupled coils depends on the_____.

a. cross-sectional area of their common core

b. number of turns of the coil

c. permeability of core material

d. All of the above

8. In case all the flux in coil-1 links with coil-2, the coefficient of coupling will be______.

a. zero

b. 0.5

c. 1.0

d. 2.0

9. A 3 H inductor has 1000 turns. What should be the number of turns to increase the inductance to 5 H ?

a. 2560 turns

b. 1290 turns

c. 1625 turns

d. 2000 turns

10. In a double tuned circuit, consisting of two magnetically coupled, identical high Q tuned circuits, at the resonance frequency of either circuit, the amplitude response has_____.

a. Either a peak or dip

b. Neither a peak nor a dip

c. A peak always

d. A dip always

11. A network function contains only poles whose real-parts are zero or negative. The network is_____.

a. Always unstable

b. stable, if jω-axis poles are at most of multiplicity 2

c. stable, if jω-axis poles are simple

d. Always stable

12. The minimum amount of hardware required to make a high pass filter is_____.

a. A resistance, an inductance and an op-amp

b. A resistance and capacitance

c. a. A resistance, a capacitance and an op-amp

d. a. A resistance, an inductance and a capacitance

13. When X_L is equal to X_C, then_____.

a. Z = X_L

b. Z = X_C

c. Z = R

d. None of these

14. If the quality factor of a series resonant circuit is increased then, its selectivity will______.

a. May increase or decrease

b. Remains same

c. Increase

d. Decrease

15. The figure of merit for a capacitor in parallel with a resistance R is given by______.

a. 1/ωRC

b. ωC/R

c. ωRC

d. R/ωC

Basic Electrical MCQs Part-7

2022-06-05T07:37:00.001-07:00

Basic Electrical

Inductance and Capacitors

1. Their inductances, 1 H, 2 H and L H are in parallel. The maximum value of equivalent inductance will be_____.

a. 3 H

b. 0 H

c. 3/2 H

d. None of these

2. Assertion(A) : In steady state condition, the energy consumed is infinite for both inductor and capacitor.

Reason(R) : The current i in the capacitor and voltage v in the inductor are zero in steady state.

a. A is false but R is true

b. A is true but R is false

c. Both A and R true but R is not the correct explanation of A

d. Both A and R true ans R is the correct explanation of A

3. Assertion(A) : If the voltage across the capacitor being constant, current through it is zero.

Reason(R) : On application of dc voltage and with no initial charge, the capacitor first acts as short circuit but as soon as the full charge it retains, the capacitor behaves as open circuit.

a. A is false but R is true

b. A is true but R is false

c. Both A and R true but R is not the correct explanation of A

d. Both A and R true ans R is the correct explanation of A

4. A 100 turn coil has an inductance of 6 mH. If the number of turns is increased by 200%, all other quantities remaining the same, the inductance will be_______.

a. 3 mH

b. 12 mH

c. 24 mH

d. None of these

5. Which of the following statements associated with capacitor is wrong?

a. A finite amount of energy can be stored in a capacitor even if the current through the capacitor is zero, such as when the voltage across it is constant.

b. It is impossible to change the voltage across a capacitor even if the current through the capacitor changes by a finite amount in zero time, for this requires infinite current through the capacitor.

c. A capacitor resists an abrupt change in the current flowing through it.

d. A capacitor resists an abrupt change in the voltage across it in a manner analogus to the way a spring resists abrupt change in its displacement.

6. Assertion(A) : Lower the self inductance of a coil more the delay in establishing steady current through it.

Reason(R): An inductor opposes a sudden change in current

a. A is false but R is true

b. A is true but R is false

c. Both A and R true but R is not the correct explanation of A

d. Both A and R true ans R is the correct explanation of A

7. An open coil has______.

a. Zero resistance and infinite inductance

b. Infinite resistance and zero inductance

c. Infinite resistance and infinite inductance

d. Zero resistance and zero inductance

8. Assertion(A) : A capacitor can store charge.

Reason(R) : The plates of he condenser are conductive.

a. A is false but R is true

b. A is true but R is false

c. Both A and R true but R is not the correct explanation of A

d. Both A and R true and R is the correct explanation of A

9. Assertion(A) : It is possible to change the current through an inductor by finite amount in zero time.

Reason(R): The current through an inductor can be changed by finite amount in zero time only when an infinite voltage is applied across it.

a. A is false but R is true

b. A is true but R is false

c. Both A and R true but R is not the correct explanation of A

d. Both A and R true and R is the correct explanation of A

10. In the complex frequency S= σ + jω , ω has the unit of radian/sec and σ has unit of______.

a. neper

b. radian/sec

c. neper/sec

d. rad

11. At a certain current, the energy stored in iron cored coil is 1000 J and its copper loss is 2000 W. The time constant (in second) of the coil is________.

a. 2.0

b. 1.0

c. 0.5

d. 0.25

12. Laplace transform analysis gives______.

a. Frequency domain response only

b. Time domain response only

c. Both (a) and (b)

d. None of these

13. Assertion(A) : Laplace transform is preferred for solving networks involving higher order differential equations.

Reason(R) : The classical method for solving differential equations of higher order is quite cumbersome.

a. A is false but R is true

b. A is true but R is false

c. Both A and R true but R is not the correct explanation of A

d. Both A and R true and R is the correct explanation of A

14. Assertion(A) : In a purely capacitive circuit, the current wave is more distorted than the voltage wave.

Reason(R) : The harmonics in the current wave are increased in proportion to their frequency numbers.

a. A is false but R is true

b. A is true but R is false

c. Both A and R true but R is not the correct explanation of A

d. Both A and R true and R is the correct explanation of A

15. The initial value theorem does not hold good for which of the following functions?

a. Hyperbolic function

b. Delta function

c. Step function

d. Ramp function