Mentor Graphics PCB Design Tools - PADS

PADS Layering Scheme

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LAYER USAGE

1-18 Trace & Plane Layers (Copper Layers)

19 Targets, Gerber Data Title block, .004” Board Outline

20 Component Placement Courtyards (outline)

21 Solder Mask Top

22 Paste Mask Bottom

23 Paste Mask Top

24 Drill Drawing

25 Plane Layer Clearances, Thermal Relief’s, .100” Board

Outline, Common Split Planes & Common Plane Voids

26 Silkscreen Top

27 Assembly Drawing Top

28 Solder Mask Bottom

29 Silkscreen Bottom

30 Assembly Drawing Bottom

Standard NAMING CONVENTION

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FILENAME Example: XXXXXATS.PHO

Break Down of the above filename: XXXXX= Job Name : 5 Digits

A = Revision : 1 Digit

TS = Top Silk : (See Suffix)

.PHO = Photoplot : (See Gerber Files)

PADS Database Description

_________A.PCB PADS Database (Binary File)

Netcheck Files Description

_________A1.ECO PADS Format Engineering Changes created by NetCheck Tools (ASCII File)

_________A.RPT Detailed Report illustrating the differences between OrCAD & PADS Netlists

Assembly Data Description

_________A.ASC PADS Format ASCII File of full database created by File/Export/ASCII

_________AXYE.ASC PADS Part Placement Coordinate List created by File/Export/ASCII, English

_________AXYM.ASC PADS Part Placement Coordinate List created by File/Export/ASCII, Metric

README_ASSY.TXT Naming Convention Explanation File for Manufacturer

PADS Reports Description

_________ANET.TXT PADS Netlist created by File/Report/PowerPCB Format

Netlist, Includes Part List

_________ANETX.TXT PADS Format Netlist created by File/Report/Netlist w/o pin

info, No Part List

_________ABOM.TXT PADS Format Part List created by File/Report/Part List 2

_________ANON.TXT PADS Format Unconnected Pins Report created by

File/Report/Unconnected Pins

_________ASTA.TXT PADS Format Statistics report created by

File/Report/Statistics

_________A.TST PADS Format Test Point Report created by

File/Report/DFT Test Point Audit

_________ACAM.NET CAM356A Format Netlist

Gerber Files Description

_________A.REP PADS Gerber Aperture Report (ASCII File)

_________AL1.PHO PADS Gerber Data for LAYER 1 (Top Side) (ASCII File)

*Note: There is a .PHO file for every layer of the PCB design. IE: L1, L2, L3, L4 = a four layer board.

_________AST.PHO PADS Gerber Data for SILKSCREEN (Top Side)

(ASCII File)

_________ASB.PHO PADS Gerber Data for SILKSCREEN (Bottom Side)

(ASCII File)

_________AMT.PHO PADS Gerber Data for SOLDER MASK (Top Side)

(ASCII File)

_________AMB.PHO PADS Gerber Data for SOLDER MASK (Bottom Side)

(ASCII File)

_________APT.PHO PADS Gerber Data for PASTE MASK (Top Side)

(ASCII File)

_________APB.PHO PADS Gerber Data for PASTE MASK (Bottom Side)

(ASCII File)

_________ADD.PHO PADS Gerber Data for DRILL DRAWING (ASCII File)

README_FAB.TXT Naming Convention explanation file for manufacturer

Drill Data Description

_________ANC.DRL Numeric Control Drill Report in Exlon Format

_________ANC.LST Numeric Control Drill Report in True-Drill Format

_________ANC.REP Numeric Control Drill Size and Quantity Report

PADS CAM File Description

_________A.CAM PADS Format Post Processing File (ASCII File)

Autoroute Files Description

_________A.DO CCT Autorouter Command File (ASCII File)

_________A.STS CCT Autorouter Statistics Report (ASCII File)

_________A.NON CCT Autorouter Unconnected Pins Report

_________A.WIR CCT Autorouter Wires file with Unmitered Traces

_________A.RTE CCT Autorouter Wires file with Mitered Traces

_________A.ATO CCT Autorouter AutoSave File. Backup file saved after

every route interation

_________A.DSN CCT Autorouter Temp File created during the translation

from PADS to CCT

_________A.DID CCT Autorouter Report on what the router did

_________A.SPI CCT Autorouter temporary translation file

_________A_SP.PCB CCT Autorouter PADS output file name

PADS HPGL File Description

_________ADD.PE1 Pen Plot of Drill Drawing

(HPGL = Hewlett Packard Graphic Language)

_________AAT.PE1 Pen Plot of Top Assembly Drawing (HPGL Data)

_________AAB.PE1 Pen Plot of Bottom Assembly Drawing (HPGL Data)

AutoCAD Files Description

_________ADD.DXF Drill Drawing produced by translating a .PE1 file using

HP2DXF software

_________AAT.DXF Top Assembly Drawing produced by translating a .PE1

file using HP2DXF

_________AAB.DXF Bottom Assembly Drawing produced by translating a .PE1

file using HP2DXF

DD.DWG Temporary Drill Template to be inserted into an

ANSI “B-Size” Format Drawing

AT.DWG Temporary Top Assembly to be inserted into an

ANSI “B-Size” Format Drawing

AB.DWG Temporary Bottom Assembly to be inserted into an

ANSI “B-Size” Format Dwg.

_________AD1.DWG Drill Drawing Page 1 Contains Fabrication Notes,

Lay-up Detail & Drill Chart

_________AD2.DWG Drill Drawing Page 2 Contains the Dimensioned Board

Outline and Drill Symbols

_________AAT.DWG Top Assembly Drawing on ANSI “B-Size” Sheet 1 Format

_________AAB.DWG Bottom Assembly Drawing on ANSI “B-Size”

Sheet 2 Format

_________AD1.PLT Drill Drawing Page 1 HPGL Data

(HPGL = Hewlett Packard Graphic Language)

_________AD2.PLT Drill Drawing Page 2 HPGL Data

(D1 & D2 go with the Fabrication Data)

_________AD1.PDF Drill Drawing Page 1 PDF Data (ADOBE Acrobat File)

_________AD2.PDF Drill Drawing Page 2 PDF Data (ADOBE Acrobat File)

Standard REFERENCE DESIGNATORS

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A Assembly

AR Amplifier

AT Attenuator; Isolator

B Blower

BR Bridge Rectifier

BT Battery

C Capacitor

CB Circuit Breaker

CN Capacitor Network

CP Coupler

CR Diode or Silicon Rectifier

D Diode; Thyristor; Varacter

DC Directional Coupler

DP Duplexer

DL Delay Line

DS Digital Display; LED Lamp

E Miscellaneous Electrical Part

F Fuse

FB Ferrite

FD Fiducial

FL Filter

G Generator

HW Hardware

HY Circulator

I or ICT In Circuit Test Point

J Jack Connector

JP Configuration Jumper

K Relay

L Coil; Inductor

LS Loud Speaker/Buzzer

M Motor

MG Motor-Generator

MH Mounting Hole

MK Microphone

MP Mechanical Part

P Plug Type Connector

PS Power Supply

Q Transistor

R Resistor

RN Resistor Network

RT Thermistor

S Switch

T Transformer

TB Terminal Block

TC Thermocouple

TP Test Point

U Tuner

U Integrated Circuit

V Electron Tube

VR Voltage Regulator

W Cable Transmission

X Sub-circuit

Y Crystal or Oscillator

Z Ref Des Suppressed

PADS Software Reference Designator Rename List

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1. Engineer should specify at the beginning of the design, if the reference designators are to be renamed.

2. Engineer should specify the direction of the rename.

Examples: Top to Bottom, Right to Left

Left to Right, Top to Bottom

3. Engineer should specify any Reference Designators that are not to be renamed.

4. If the engineer is extremely concerned about the flow of the renaming process,

a WAS/IS List should be manually generated by the creation of an ASCII text file.

EXAMPLE:

*PADS-ECO*

*RENPART*

U12 U1

U5 U2

U1 U3

C9 C1

C6 C2

*END*

NOTE:

*PADS-ECO* should be located in the 1^st line of the ASCII text file.

*RENPART* should be located on the 2^nd line.

*END* should be at the end of the file.

PADS Software Netlist Defaults

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NOTE: To prevent a designer from editing engineering netlists, please obey the following rules:

1. Reference Designator Names have a 15 character limit.

2. Pin Names have a 7 character limit.

3. Netnames have a 57 character limit.

4. Illegal characters are * < > ? : . ,

Lower case characters are not allowed.

Avoid \ / because Unix systems do not accept these characters.

5. Please use the abbreviation rather than the full name i.e.: use K, not CATHODE.

Use A, not ANODE.

All new library decals with special alpha pin numbers (IE: NO & NC for switches) must be clearly noted on the data sheet that will be used to create the library decal.

2 & 3 pin devices with alphabetical Pin Names are as follows:

DIODES CATHODE = C

ANODE = A

TRANSISTORS BASE = B

EMITTER = E

COLLECTOR = C

POWER FETS SOURCE = S

GATE = G

DRAIN = D

POTENTIOMETERS CW = 1

WIPER = 2

CCW = 3

CAPACITORS & POSITIVE = 1

BATTERIES NEGATIVE = 2

6. PADS format netlist is preferred.

7. Netlist header should be: !PADS-POWERPCB- V4.0-MILS!

*NET*

8. Netlist footer should be: *END*

9. SAMPLE NETLIST: !PADS-POWERPCB- V4.0-MILS!

*NET*

*SIG N00001

U1.1 C1.1 R1.1

*SIG N00002

U1.2 R1.2

*SIG GND

U1.7 C1.2 U2.7 C2.2

*SIG VCC

U1.14 U2.14 C2.1

*END*

10. File name suffix must be .ASC if you are using PowerPCB.

PADS Software Decal List Defaults

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NOTE: To prevent a designer from editing engineering decal lists, obey the following:

1. Reference Designator Names have a 15 character limit.

2. Decal Names have a 40 character limit.

3. Illegal characters for decal names are * < > ? : . ,

Avoid \ / because Unix systems do not accept these characters.

4. Lower case characters are allowed but pads will convert them to upper case.

5. Decal list must be in PADS format. TANGO format Decal List is not acceptable.

6. Decal list header should be:

!PADS-POWERPCB-V4.0-MILS!

*PART*

7. Netlist footer should be:

*END*

8. SAMPLE DECAL LIST:

!PADS-POWERPCB-V4.0-MILS!

*PART*

U1 SO14

U2 PLCC-52

U4 DIP16

C1 CC1206

Y1 XTAL14

*END*

9. File name suffix default is .ASC in PowerPCB, but .net is acceptable.

10. If a decal is not in the library put “SEE DATA SHEET” in place of the decal name.

Be sure to put the reference designator on the component data sheet, especially if there

is more than one Library part to build.

11. If a new decal has alphabetical pin numbers, be sure that the data sheet clearly

defines the pin numbering assignments.

Example: Transistors with Base, Emitter and Collector.

12. If the Decal List & the Netlist are in the same ASCII file, break them into 2 files.

Always ASCII IN the Decal List first, and trouble shoot and fix the errors.

Then ASCII IN the Netlist.

13. BGA row and column count limit was 45 x 45 pins in Version 3.0.

PCB Design Flow Process (Part 2 of 2)

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The next part of the PCB Design Flow Process starts on the layout until design completion for board fabrication.

15. PREPARE LAYOUT FOR TRACE ROUTING

Compare Schematic CAE net list with the PCB Design net list using Netcheck Tools.

16. SETUP DESIGN RULES

Setup/Design Rules on “Default Clearance” rules and …

Setup/Design Rules on “Net Clearance” rules are to be set up for Voltage, Ground and Critical Nets.

Set class rules for high-speed technology.

17. MANUAL ROUTING

Manually Bus route memory sections using Copy/Paste command.

Manually fan out all Voltages that connect to an inner layer plane using Via Share technique.

Manually fan out all Ground connections so that every Ground Pin gets its own Via.

Manually route all other Voltages that require large trace widths.

Manually route all high-speed matched length traces and critical nets.

Use Tools/Verify Design/Check Planes to insure 100% fan out of all SMT Plane Pins.

Use Tools/Verify Design/Check Clearances to insure no short circuits.

If the design is a 2-Layer board, all voltages should be manually routed per Engineers specification.

18. Second (2nd) SET OF QUALITY PRINTS

PCB Designer will print all layers that were affected by manual routing and give them to the engineer.

If the placement or pad-stacks have changed run check prints of assembly & drill drawing

19. SIGNAL INTEGRITY OUTPUT

Generate a Hyperlynx file for signal analysis.

20. FIX ENGINEERS RED-LINED PRINTS

Incorporate all of the Project Engineers corrections

If there were many corrections, PCB Designer will create a new set of check prints.

21. TESTABILITY

The Project Engineer will be responsible for informing the PCB Designer the Testability Rules, early in the Process.

This includes the following questions:

Does every Net need a test point or just some of the nets?

Do voltage nets require extra test points?

Do non-connected pins need to be testable?

Will the Project Engineer add selective test points to the schematic?

Can vias be used as test points, or do they have to be “Bottom Side” non-drilled Pads?

What size do the test points have to be, what is the point to point spacing requirements & amount of pins per square inch?

Are there vacuum requirements for the test fixture?

If PCB Design requires testability on every net, the PCB Designer will add a test point for every net, using PADS DFT Audit program and place the test points, near one of the pins, of the net it belongs to.

22. ROUTE REMAINDER OF NON-CRITICAL ROUTES

If the PC Board has a large number of production boards made, it should be 100 % manually routed to reduce trace length, reduce via count and reduce layers.

If Project Engineer requested a quick turn proto-type, use an auto router to route remainder of board.

If auto routing is used, clean up the traces on all layers after the auto router has completed 100%

Make and save a pre-auto routed version of the PCB. This will be use for future revisions.

23. FINAL DRC CHECKS

PCB Designer & Project Engineer: Tools/Verify Design – Check Clearances, Continuity and Panes.

24. SILKSCREEN

Create Silkscreen (use 0.05mm snap grid) and bottom side etch text.

All reference designators must be moved outside component, and must not exceed two different rotations. All company identification & REV Blocks must be placed inside the board outline. Default text height/width is .080”/.008” Minimum height/width is .060”/.006”.

All connectors should have text to identify the end-pins. Add connector & jumper text names, if any.

25. Third (3rd) SET OF QUALITY PRINTS

Create check prints of all Routed Layers, Silk-screens, Solder Masks & Paste Masks.

Create check prints of final AutoCAD Drill & Assembly Drawings.

Check final CAE Netlist with final CAD Netlist.

26. FINAL CAM OUTPUT

Make final prints of AutoCAD Assembly & Drill Drawings.

Create Fabrication Data that contains Gerber Data, Drill Data & Fabrication Drawing.

Import the PADS ASCII file into CAM350 to extract an IPC-D-356 Netlist.

Create Assembly X/Y Coordinate Data.

Save all of the final output data to Source Safe.

PCB Design Flow Process (Part 1 of 2)

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Create a set of PCB design flow processes that you can use as a guide to step you through the development of a PCB layout. An efficient design flow helps you avoid duplicating steps. Once you have completed a step, you should never need to repeat it.

1. DESIGN REVIEW

A comprehensive design review should take place between all applicable disciplines: i.e. Hardware Engineer, Project Management, Layout, Mechanical, and Manufacturing.

For the PCB designer the following information needs to be determined: Layer stack-up and plane layers, PCB thickness and board material, default trace width, component complexity and quantity of new components, proto board or production/auto route or manual route, high speed rules, impedance control, testability and Schedule.

2. COMPONENT DATA SHEETS

Engineering Department will submit all component data sheets, (web link), prior to the start date of a PCB layout, of all of the components that cannot be located in your Library Handbook.

3. MECHANICAL DATA SHEET

Engineering Department will also provide a Board Outline constraint drawing if one is available, or as soon as possible. The mechanical constraint drawing should be drawn from the top side, include all mounting holes, fixed connector locations, indicate the Layer Stack-up and board thickness of the PCB. The origin for the constraint drawing should be the lower left mounting or tooling hole.

4. PART NUMBER & BOARD NAME ASSIGNMENT

After the Engineering Department submits the data sheets, a part number and a board name are assigned to the PC Board.

5. LIBRARY MANAGEMENT

As you create your library parts, using the naming convention that you developed, populate the applicable PCB Library with the new decals, representing the pin assignments and all applicable notes and documentation for each part. Keep the PLB file “Up to Date” every time new parts are built.

6. CUSTOM BOARD OUTLINE

Select the correct PADS “Start File” that matches the layering scheme that the Engineer has provided and copy the master “Start File” to a new name.

Fill out the Title Block.

Enter the Board Outline.

Add all Mounting/Tooling Holes and Fiducials that are necessary then glue them down.

Move the Targets to the outer extremities of the board outline.

Fully dimension the board edges and at least one mounting hole.

Create the “Auto router Keep-in/out” inside the Board Outline

7. STANDARD BOARD OUTLINE

If a Standard Board Outline is selected from the Library, the PCB Designer will fill out the Title Block and edit the text on Layer 26 that will eventually go on the Silkscreen.

Setup the correct Layer and Color Scheme.

8. NETLIST

At the start of the PCB design, the Engineering Department will provide a net list, from the schematic capture tool, in PADS format starting with the PADS-PowerPCB header:

! PADS-POWERPCB-V4.0-METRIC!

The net list will contain all of the correct PADS Decal Shape Names.

The net list will not contain Pin Names over four characters long.

The following is a list of acceptable pin names: Collector = C, Emitter = E, Base = B,

Anode = A, Cathode = C, Source = S, Drain = D, Gate = G, Positive = 1, Negative = 2.

Import the netlist into PowerPCB. If errors are found, in the netlist, the Designer will report them to the Project Engineer. The Project Engineer will fix the problems and provide the PCB Designer with an updated netlist.

After the net list is successfully imported into PADS, the PCB Designer will Tools/Disperse the parts.

9. REPORTS

Create and e-mail to Project Engineer Unused Pins, Part List 2 & Statistic Reports.

PCB Designer must review Unused Pins list for 2 pin components.

Project Engineer must review Unused Pins list for possible schematic errors.

10. PART PLACEMENT

The Designer and Engineer will perform the part placement, or Engineers suggested layout.

The placement must meet the Engineers guidelines and design rules. Engineer will provide the design rules.

The placement must meet all manufacturing requirements.

The placement must meet all routability requirements.

Tools/Verify Design - check clearance to ensure no over lapping parts.

11. SPLIT PLANES

Use CAM Plane option and use a 2D-Line to separate the different Plane Nets, or use the Split/Mixed Plane option.

Use the View/Nets feature to discriminate different nets by color.

12. First (1ST) SET OF QUALITY CONTROL PRINTS (PDF Format)

1:1 scale Drill and Assembly drawing laser print or bond paper.

All new Library Decals must be checked for Solder Pattern accuracy.

Print Split Planes if applicable for Project Engineer to check.

13. FINAL PART PLACEMENT

After Split Planes and New library Decals are checked, PCB Designer will make final part placement adjustments.

PCB Designer will make final silkscreen adjustments.

14. GENERATE OUTPUT FOR MECHANICAL PART PLACEMENT 3D MODEL CHECKS USING SolidWorks or PRO‑E TRANSLATORS

Now that you have completed half of the job to complete a project, a more challenging task awaits you on Part 2 of this tutorial...

Have fun!

Data Required for PCB Layout

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Data Required for PCB Layout

DATA SHEETS

Physical description data sheets from the component manufacturer, of all component land patterns that are not in your PCB Design software Libraries. Only mechanical data is required, IE: Pin Spacing in Metric Units, Lead Size or Hole Size in Metric Units, Pin Numbers.

CONNECTOR PIN ASSIGNMENTS

Identify where is pin 1, pin 2, pin 3 and the connector End Pins assignments

Constraint Drawing

Board outline illustrating dimensions in Metric Units and the location of all fixed component coordinates in Metric Units. IE: Mounting Holes, Connectors, Switches, Potentiometers, etc.

This can be obtained from a mechanical drafting tool i.e. AutoCAD or Solidworks in DXF format. Some PCB tools require specific version of the DXF file. It should be noted that the units used in the mechanical draft (DXF) should match the PCB software's design units when importing the DXF file.

Note: The CAD origin, (X=0, Y=0) should be in the lower left Mounting Hole of the board.

Netlist

PowerPCB format netlist including the shape names of the library land patterns is required. The header at the top of the netlist should be: !PADS-POWERPCB-V4.0-METRIC!
(In this example, the software used was PowerPCB which is now Mentor Graphics' PADS)

SCHEMATIC

Need schematic to debug the netlist if “one pin nets” occur or if only one pin of a two pin part is in the netlist. Schematic is also used to place components.

PART PLACEMENT

Pencil sketch of suggested component placement layout map of major components.
It is highly recommended that the engineer participate in the part placement to avoid duplication.

POWER PLANES
Power and Ground Plane instructions including bypass capacitor fanout, BGA & QFP fanout. If there are multiple nets on the same layer, need Split Plane information.

TRACE ROUTING RULES
Clock, or High Speed trace instructions - Matched Length, Differential Pairs and Trace Widths in Metric Units. Special Route Layers, Impedance, etc. and include the net name reference. What needs to be hand routed and what can be auto-routed?

SILKSCREEN LEGEND
Silkscreen text identification requirements including copyright, board name, part number, revision level, connector ID’s, reference designator rotations and polarity markings.

MANUFACTURING INFORMATION
Special fabrication notes, layer construction and panel information.
Provide special assembly notes and drawings that illustrate special assembly information.

PADS PCB Design Solutions: The standard in desktop PCB design (Part 2)

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PCB Layout

As the standard in desktop PCB layout tools, PADS offers unparalleled price-performance for the layout and design of complex circuit boards, including high-speed applications and RF
circuits. PADS offers advanced design rules with real-time design rule checking, bi-directional cross-probing, RF design functionality, split-plane generation, auto-dimensioning, direct DXF import into both the board and part library editors, advanced fabrication verification tools, and 3D viewing. Also available are assembly variantfunctions, test coverage auditing, physical design reuse module, chip-on-board /advanced packaging, and an IDF link to third-party CAD/CAM tools.

Interactive / Autorouting

Many designers of highspeed and/or dense designs require exacting manual control of critical signal traces, but could also use the speed and built-in intelligence of an auto router. The router provides both advanced interactive routing and sophisticated autorouting for highspeed applications.

Whether interactively routing with orthogonal, diagonal, or any-angle styles, or differential pair routing with unique rule assignment or trace length requirements, the router provides exacting control. Intuitive graphical monitoring tools provide real-time feedback for correct-by-construction methodology. Proven routing algorithms enable robust design rules and advanced design constraints to be applied between objects or groups of objects such as components, layers, nets, and vias.

The advanced autorouter simplifies routing operations most suited for an autorouter, including fanout and routing, by individual components or groups of components.

Design for Manufacturing Analysis

DFM Analysis enables PCB design teams to validate that a design is prepared for manufacturing directly within the PADS environment. Regardless of the complexity of their designs, design teams are continuously challenged with getting products into volume production to reach the market quickly.

Manufacturers alone cannot identify all production obstacles; PCB designers must play an earlier role in validating the layout of a design by considering key aspects of fabrication and assembly that directly impact manufacturability.

The DFM Analysis incorporates more than 100 of the most valuable fabrication and assembly related analyses. Examples of issues identified by DFM Analysis include resist slivers, unintended copper exposed by soldermask, and testpoint-to-testpoint spacing, all of which delay production. Identifying and solving these issues early in layout, and long before manufacturing, saves costs and brings the product to market much quicker. Catching DFM issues at the design stage is critical because at each successive step of the production process, the cost of rectifying a problem increases tenfold over the previous step. DFM Analysis identifies these manufacturing issues and works seamlessly to take you directly to the design location within PADS Layout.

PADS PCB Design Solutions: The standard in desktop PCB design (Part 1)

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Overview

PADS, Mentor Graphics’ worldwide leading desktop PCB design solution, enables individuals and small teams to develop PCBs within a highly productive and easy-to-use environment. Integrated and scalable, PADS allows individual engineers and designers to accomplish a wide breadth and depth of core PCB development tasks, including schematic entry, analog design, signal and power integrity, thermal analysis, and PCB layout-to-manufacturing preparation.

PADS offers a low cost of entry, yet delivers high performance that exceeds other desktop PCB design solutions on the market. Long a part of the Mentor Graphics PCB lineup, PADS has benefitted from continuous, solid development and global distribution, making it the most popular desktop PCB software package in the world. And, as a Mentor Graphics PCB solution, PADS provides a clear and connected path to an enterprise flow if your requirements grow.

Are PADS PCB Design Solutions for You?

 Have your current tools “run out of gas,” driving you to explore new options?

 Do demanding design challenges and tight time-to-market demands conflict with strict budget constraints?

 Is cost-of-ownership a primary factor in your buying decision?

 Do you want the shortest learning curve possible and user-experience that doesn’t divert you from focusing on your design?

 Do you do it all – concept, layout, and analysis?

 Are you looking for a plug-and-play solution?

PADS PCB Design Solutions

Mentor Graphics leads the PCB market in providing scalable design solutions that meet or exceed your requirements. Whether you are a single designer, part of a small group, or

an independent group within a larger company, PADS PCB design solutions offer what you need, when you need it, at an affordable cost.

System Design

The PADS flow delivers the most robust system design capture and definition functionality available, including intuitive project and design navigation, unlimited hierarchical support, design reuse, advanced design attribute and rules management, full forward/back annotation including design rules, cross-probing with layout and routing, and a direct schematic-to-signalintegrity analysis link.

Analog Analysis

HyperLynx Analog with EZwave is a board-level simulation analysis and verification environment that is integrated into Mentor Graphics’ DxDesigner board-design environment. Using a single schematic to drive both the simulation and PCB applications

effectively illuminates costly and error-prone schematic re-entry, therefore significantly shortening the overall development cycle.

HyperLynx Analog provides basic simulation capabilities, such as DC, frequency and time-domain analysis, as well as more statistical approaches such as Monte Carlo and multiple sweep analyses. EZwave sets the standard in waveform analysis, with easy-touse drag ‘n’ drop features enabling fast waveform viewing, multiple cursor support to sophisticated operations through the waveform calculator and measurement tools. Waveforms from multiple simulation runs can be overlaid to quickly compare result differences. EZwave also offers a range of plotting formats including time-domain, digital, smiths charts, and bode

plots.

HyperLynx Analog includes thousands of popular proven models, with access to extensive external vendor libraries, the ability to import and convert existing PSpice libraries, and even drag 'n drop symbol generation for automatic symbol creation using commonly found SPICE models.

Signal Integrity Analysis

Signal integrity (SI) analysis is an essential part of modern electronic design. Increasingly-fast edge rates in today’s integrated circuits (ICs) cause detrimental high-speed effects, even in PCB designs running at low operating frequencies. As driver ICs switch faster, a growing number of boards suffer from issues such as crosstalk, over/undershoot, ringing, glitching, and timing problems. PADS design solutions offers powerful and easy-to-use signal integrity capabilities on the engineers desktop. With pre-layout analysis capabilities for defining routing constraints, to verification of the routed board to ensure your design goals are
met, PADS design solutions offer a complete environment for all your signal integrity analysis needs.