Microprocessor Test and Verification Conference

MTV 2011 Announces Dates, Paper Submissions, Scholarship

admin — Mon, 16 May 2011 19:50:08 +0000

We are pleased to announce that the 12th Annual Workshop on Microprocessor Test and Verification will be held from December 5-7th 2011 at the Hyatt Town Lake in Austin, Texas. The purpose of this workshop is to bring researchers and practitioners from the fields of verification and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. For more information on attending, please visit the registration page.

Authors are invited to submit postscript or PDF versions of their papers (maximum 6 pages), with author names, affiliation, addresses, telephone and fax numbers, e-mail address, and the person who will present the work if accepted. Please refer to the paper submissions page for details on presenting at the conference.

Graduate students and recent grads working in the field of processor verification are encouraged to apply to Obsidian Software’s Microprocessor Test and Verification Scholarship in which several students will receive complimentary admission to the workshop, airfare, hotel and a per diem stipend.

2010 Advance Program Announced

admin — Fri, 12 Nov 2010 22:54:43 +0000

December 13-15, 2010
Hyatt Regency Hotel, Austin, Texas, USA

December 12, 2010

6-8pm: MTV Welcome Drink and Early Registration.

Location Hyatt Marker 10 Bar
Meet the MTV organizers to pick-up your registration material early while enjoying a complimentary drink.

Day 1: December 13, 2010

7:30-7:50am: Registration and continental breakfast

7:50-8:00am: Welcome and Opening Remarks by the Workshop General Chair: Magdy Abadir (Freescale, USA)

8:00-9:40am: Debug Session

A.1 On the Resolution of Sequential Debugging

Görschwin Fey, André Sülflow, and Rolf Drechsler (University of Bremen, Germany)

A.2 An Automated Framework for Correction and Debug of PSL Assertions

Brian Keng*, Sean Safarpour (Vennsa Technologies, Canada), Andreas Veneris*, (*University of Toronto, Canada)

A.3 Post-silicon debugging with high level design descriptions and programmable controllers

Masahiro Fujita, Bijan Alizadeh, Hiroaki Yoshida, Takeshi Matsumoto (University of Tokyo, Japan)

A.4 Automation Techniques for Post-Silicon Debug of Timing Errors

Azadeh Davoodi (University of Wisconsin at Madison, USA)

9:40-10:30am: Architecture Validation

B.1 Using Software Architecture Patterns to Validate Performance of a Threaded Processor Architecture

Jim Holt and David Lindberg (Freescale, USA)

B.2 The impact a complete target environment simulation has on architecture validation: Case study of Speculative Execution Proposals

Jack Mason (Nova Southeastern University, USA)

10:30-10:45am Coffee Break

10:45-12:00pm: Validation Test

C.1 Fault Grading of Software-Based Self-Test procedures for Dependable Automotive Applications

Paolo Bernardi, Ernesto Sanchez, Michelangelo Grosso, *Oscar Ballan and *Giovanni Fontana (politecnico di torino, Italy and *STMicroelectronics, Italy)

C.2 Test Generation For Functional Verification of CMP Designs

Padmaraj Singh and *David Landis (Nvidia, *Carnegie Mellon University, USA)

C.3 A kernel based validation framework for functional test selection

Po-Hsien Chang and Li-C Wang (University of California at Santa Barbara, USA)

12:00-1:30pm Lunch break

1:30-3:15pm Panel I: Verification is a problem, but is debug the root cause?

Moderator: Sean Safarpour (Vennsa Technologies)
Participants:
Harry Foster (Mentor Graphics)
Michael Stellfox (Cadence)
Alex Wakefield (Synopsys)
Bindesh Patel (Springsoft)

3:15-3:30pm Coffee Break

3:30-5:10 pm System Level

D.1 FPGA prototyping of the ARM Cortex A8 processor

Steve Ravet (ARM, USA)

D.2 Automatic Fault Localization for SystemC TLM Designs

Hoang M. Le, Daniel Grosse and Rolf Drechsler (University of Bremen, Germany)

D.3 Redesign and Verification of RTL IPs through RTL-to-TLM Abstraction and TLM Synthesis

Nicola Bombieri, Franco Fummi, Valerio Guarnieri, Graziano Pravadelli and Sara Vinco (University of Verona, Italy)

D.4 A Hardware/Software Co-design Framework using Abstract State Machines

Nathan D. P. Buchanan and Hiren D. Patel (University of Waterloo, Canada)

6:30pm MTV Workshop Dinner

Venue: Fogo De Chao, 309 E. 3rd St., Austin, TX 78701, Phone: (512) 472-0220

Description: A short (about 10 minutes) walk from Hyatt Fogo De Chao is located in downtown Austin. It features Brazilian cuisine with over 30 items including fresh cut vegetables, imported cheeses, cured meats and Brazilian side dishes. A wide variety of meat specialties expertly prepared by gaucho chefs and all you can eat gourmet salad and sides bar provides for a great experience amid stimulating discussions.

Transportation: Attendees can stroll to the restaurant or arrange for alternate ground transportation to the restaurant.

Day 2: December 14, 2010

7:30-8:00am Registration and continental breakfast

8:00-9:15am: Formal Verification

E.1 Schedulability Analysis for Multi-Core Global Scheduling under Cache Warm-Up Overheads based on Model Checking

Wei Sheng, Yanyan Gao, Li Xi and Xuehai Zhou (University of Science and Technology, China)

E.2 An Embedded Reachability Analyzer And Invariant Checker (ERAIC)

Ouiza Dahmoune and Robert de B. Johnston (INRS-EMT, Canada)

E.3 Bounded Model Checking of Incomplete Networks of Timed Automata

Christian Miller, Karina Gitina, Christoph Scholl and Bernd Becker (Albert-Ludwigs-Universitaet Freiburg, Germany)

9:15-10:05am: Coverage

F.1 Relational Database Schema for the UltraSparc Functional Coverage Flow

James Roberts, Ray Voith and Michael Burns (Oracle, USA)

F.2 Hi-Fi or One Small Music Library? Exploring the Implementation and Analysis Cost Trade-Offs of Coverage Model Design

Paul Graykowski and Andrew Piziali (Synopsys, USA)

10:05-10:20am Coffee Break

10:20-12:00pm: SoC VerificationG.1 An Efficient Event Generation Method for Testing a SOC with Multiple Processing Elements and Associated Peripherals

Devraj Kallappa Bakchowde and Nanda Kishore A S (Nokia Siemens Networks India Pvt. Ltd, India)

G.2 An enhanced Strategy for Functional Stress Pattern Generation for System-on-Chip Reliability Characterization

Mauricio de carvalho, Paolo Bernardi, Ernesto Sanchez and Matteo Sonza Reorda (Politecnico di Torino, Italy)

G.3 System validation using IP-XACT standards

Rajesh Chirumamilla (ARM, India)

G.4 Using Graphics Processing Units for Logic Simulation of Electronic Desings

Alper Sen, Baris Aksanli, Murat Bozkurt (Bogazici University,Turkey)

12:00-1:30pm Lunch break

1:30-3:15pm Panel II: SystemVerilog Verification Methodology: Challenges and Solutions

Moderator: Bhanu Kapoor (Mimasic)
Participants:
Sharon Rosenberg (Cadence)
Janick Bergeron (Synopsys)
Alan Hunter (ARM)

3:15-3:30pm Coffee Break

3:30-4:45pm Invited Industry Session on Formal Methods for Power & Performance

H.1 Pranav Ashar, CTO, RealIntent

H.2Yuan Lu, CTO, NextOp Software

H.3 Rajeev Ranjan, CTO, Jasper Design Automation

4:45pm Closing Remarks – Magdy Abadir (Freescale)

Day 3: December 15, 2010

Tutorials Day

(Free with MTV registration)

Venue: Freescale Semiconductor Inc

7700 W Parmer Lane, Building A Auditorium, Austin, TX 78729

8:00-11am: Tutorial : Experiences in Validating Power-Managed Processors and Wireless SoCs

Bhanu Kapoor (Mimasic), Alan Hunter (ARM), Amit Kumar (CSR), and Prapanna Tiwari (Synopsys)

In this tutorial, we focus on the power management architecture verification experiences of Wireless SoCs and specifically focus on the tasks for validating a power managed ARM Cortex A-8 core and a power-managed GPS SoC.

The power management verification strategy was put in place with following goals in mind:

Ensuring the intent of power-aware design is implemented per its architecture definition
Correct sequencing of control signals during the switching and scaling of power supplies
Correct input and output functionality of each power domain during the power cycles
- Coverage of all power states and all legal transitions between these power states
- Some of the specific verification issues encountered and to be discussed here include the following:
Ensuring that each of the domains are clamped correctly in all valid power states of the chip
Ensuring level-shifters and level shifting clamps are correctly placed and validated for presence of different voltages and clock frequencies associated with the power domains
Issues with voltages on level-shifters corrupting signals across domains
Delay dependent issue with isolation resulting from voltage ramp times
Un-initialized registers & memory contents on each power cycle corrupting downstream logic

We will review all of the key power management techniques and associated verification issues and then follow it up with the case studies of a processing core and a GPS chip.

2010 Online Registration Now Open

admin — Tue, 12 Oct 2010 18:01:39 +0000

Online registration is now open for the 11th Annual International Workshop on Microprocessor Test and Verification. The workshop will be held from December 13-15, 2010 at the Hyatt Town Lake, in Austin TX. Complete details are available via the registration and hotel page.

MTV Scholarship Deadline Approaching

admin — Tue, 14 Sep 2010 17:04:22 +0000

The application deadline for the MTV Scholarship Program is now less than 30 days away. This scholarship will provide round-trip airfare, conference registration fees, and hotel accommodations for several students across the nation to attend the 11th annual workshop on Microprocessor Test and Verification in Austin, TX.

“It’s always difficult to have to choose applicants”, said Eric Hennenhoefer, President of Obsidian Software. “There are so many talented young engineers out there, and we like to help really determined and motivated individuals whenever we come across them.”

2010 marks the first year of this scholarship, which is open to applicants until October 1st. More information can be found by visiting the scholarship program page:

2010 Microprocessor Test and Verification Scholarship

Call for Papers Deadline Approaching

admin — Thu, 09 Sep 2010 19:21:46 +0000

The September 15th deadline for paper submissions is rapidly approaching. If you would like to request an extension, please contact us.

Authors are invited to submit postscript or PDF versions of their papers (maximum 6 pages), with author names, affiliation, addresses, telephone and fax numbers, e-mail address, and the person who will present the work if accepted. Authors of accepted papers can choose to submit the full paper for inclusion in the formal Workshop proceeding published by IEEE. Special Sessions, Panels and Tutorials: Proposals for special sessions, panels and tutorials are also invited. Please email the abstract of your proposals directly to the program chair as early as possible before paper submission deadline.
Read More >>

Receive Email Notification of MTV Updates

admin — Tue, 03 Aug 2010 16:57:14 +0000

Subscribe here and get the latest info on the upcoming MTV workshop delivered right to your inbox.

MTV 2010 Announces Call for Papers

admin — Tue, 13 Jul 2010 19:16:28 +0000

Authors are invited to submit postscript or PDF versions of their papers (maximum 6 pages), with author names, affiliation, addresses, telephone and fax numbers, e-mail address, and the person who will present the work if accepted. Authors of accepted papers can choose to submit the full paper for inclusion in the formal Workshop proceeding published by IEEE. Special Sessions, Panels and Tutorials: Proposals for special sessions, panels and tutorials are also invited. Please email the abstract of your proposals directly to the program chair as early as possible before paper submission deadline.

AUTHOR’S SCHEDULE: Submission deadline: Sept 15, 2010; Notification: Oct 15; Final version: Nov 10, 2010

11th International Workshop on Microprocessor Test and Verification
Common Challenges and Solutions
December 13-14, 2010, Hyatt Regency On Town Lake,
Austin, Texas, USA.

THE PURPOSE of this workshop is to bring researchers and practitioners from the fields of verification and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges facing us today in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in verification and vice versa. This is the 11th edition of the MTV Workshop, a testament to its success in providing an ideal environment for cross- examination of test and verification experiences and innovative solutions.

http://mtvcon.org

General Chair: Magdy S. Abadir (Freescale, USA) – m.abadir@freescale.com
Program co-Chair: Li-C. Wang (UCSB, USA) – licwang@ece.ucsb.edu
Program co-Chair: Jay Bhadra (Freescale, USA) – jayanta.bhadra@freescale.com