nee-ASIC Design

Standard Cell Rows on Core and RUF

2011-03-31T01:07:00.000-07:00

The area allotted for standard cells on the core is known as standard cell area. This area is divided into the rows known as standard cell rows as shown in the below figure.

The height of this row is equal to the height of the standard cell. In digital designs most of the cases, the height of standard cells are constant and width varies. There may be double height cells , triple height cell, etc. Similarly the rows also have heights accordingly. The standard cells will sit in the row with proper orientation.
The rows may abut or may not. The abutted rows share the power connections ( Will be explained in the Power Planning).

To be continued ....

Aspect Raio of Core/Block/Design

2011-03-28T05:53:00.000-07:00

The Aspect Ratio of Core/Block/Design is given as:

The aspect ratios of different core shapes are given in below :

The Role of Aspect Ratio on the Design:

The aspect ratio effects the routing resources available in the design
The aspect ratio effects the congestion
The floorplanning need to be done depend on the aspect ratio
The placement of the standard cells also effect due to aspect ratio
The timing and there by the frequency of the chip also effects due to aspect ratio
The clock tree build on the chip also effect due to aspect ratio
The placement of the IO pads on the IO area also effects due to aspect ratio
The packaging also effects due to the aspect ratio
The placement of the chip on the board also effects
Ultimately every thing depends on the aspect ration of core/block/design

The all the points are drawn attention in future articles

Physical Design Essentials

Floor Planning in P and R Flow - Part2

2011-03-28T01:59:00.000-07:00

Continued from Part1

The Floorplanning is the first step in the ASIC P and R flow. The following terminologies are required to understand before proceeding further in to the Floorplanning process.

Aspect Ratio of Core or Block or Design
Standard Cell Rows
RUF (Row Utilization Factor)
Congestion
Blockages – Placement and Routing
Guide, Region and Fence

The major part of the Floorplanning is the Deciding the Chip/Block/Design size and placing the macros over the core area. Before proceeding into the Die size calculations understand the Die area and its components.

The die area is divided in to the following areas:

Core area / Core Box
IO area / IO Box
Channel between the Core and IO area

The die consists of the number of IO pads and Corner pads in the IO area, and non or one or more Hard Macros (PLL, RAM, ROM, etc.) and Standard Cells (Flip Flops, NAND, NOR, AOI, etc.) in the core area.

The core logic consist the standard cells and had macros. The IO pads are the interfaces circuits between Core logic and the IO pins present on the IC package. The IC pins are used to connect and mount the IC on a PCB or board.

The core area is allotted for Macros and Standard Cells. The Standard Cell area is divided into the number of standard cell rows.

(Will be Continued in Part3.....Die Size Calculation)

Floor Planning in P and R Flow

2011-03-23T02:38:00.000-07:00

Floorplanning is the art of any physical design. A well thought-out floorplan leads to an ASIC design with optimum area and high performance.

After importing the design into the P&R tools with all libraries and design netlist, floorplan is performed.

Floorplanning is nothing but placing the blocks /macros on the core area or another block after deciding the size of the block or core/die, thereby defining the standard cell areas between the macros/blocks.

We will create and develop a physical model of the design in the form of an initial optimized layout.

The following tasks are done during flooring planning.

1. Deciding the size of the core/die or block

2. Deciding the IO pads locations

3. Placing the Macros at appropriate place on the core

4. Placing any floorplan constrains like placement blockages, routing blockages, macro halos, etc., on the core area

5. Fixing the placement of standard cells of particular module on the core area

6. Deciding the continuous area for standard cell placement

The above tasks are performed based on the connectivity available in the netlist.

Optimization of the layout is in terms of reducing the chip area, reducing the total net length, improving the timing there by increasing the operating frequency, resolving congestion there by maximizing the routability, reducing the crosstalk noise effects, reducing the power consumption, etc.

To be continued in Part2.......

Yield of Integrated Circuits

2011-03-18T05:03:00.000-07:00

The fabrication of ICs is a complex process and involves many chemical, mechanical, electrical, optical variables. Hundreds of ICs are manufactured on a single wafer at a time and the wafers are created in lots.

The integrated circuits are called die (die is singular as well as plural) when they are on a wafer and called chips when they are separated from the wafer.

The die are tested in different methods for its intended functionality, characteristics and parameters like frequency, power consumption, temperature, etc. All die are not up to the mark after manufacturing. Among the reasons to discard a die are wrong resistance, an open circuit, a missing conductor, and being physically too large or too small in some dimension.

Yield is the fraction goods of chip among the total number chips manufactured. The total number may be total chips of a single wafer or total chips of a lot. The yield analytically:

VLSI Design Flow -2

2011-03-18T03:23:00.000-07:00

Start reading from VLSI Design Flow -1

Physical design is performed with respect to design rules that represent the physical limitations of the fabrication medium. For instance, all wires must be a prescribed minimum distance apart and have prescribed minimum width. As such, the design layout must be recreated in (migrated to) each new manufacturing technology.

Physical design directly impacts circuit performance, area, reliability, power, and manufacturing yield. Examples of these impacts are discussed below.

Performance: long routes have significantly longer signal delays.
Area: placing connected modules far apart results in larger and slower chips.
Reliability: large number of vias can significantly reduce the reliability of the circuit.
Power: transistors with smaller gate lengths achieve greater switching speeds at the cost of higher leakage current and manufacturing variability; larger transistors and longer wires result in greater dynamic power dissipation.
Yield: wires routed too close together may decrease yield due to electrical shorts occurring during manufacturing, but spreading gates too far apart may also undermine yield due to longer wires and a higher probability of opens.

Due to its high complexity, physical design is split into several key steps:

Partitioning: Breaks up a circuit into smaller subcircuits or modules which can each be designed or analyzed individually.
Floorplanning: Determines the shapes and arrangement of subcircuit or modules, as well as the locations of external ports and IP or macro blocks.
Power and ground routing: Often intrinsic to floorplanning, distributes power (VDD) and ground (GND) nets throughout the chip.
Placement: Finds the spatial locations of all cells within each block.
Clock network synthesis: Determines the buffering, gating (e.g., for power management) and routing of the clock signal to meet prescribed skew and delay requirements.
Global routing: Allocates routing resources that are used for connections; example resources include routing tracks in channels and in switchboxes.
Detailed routing: Assigns routes to specific metal layers and routing tracks within the global routing resourses
Timing Closure: Optimizes circuit performance by specialized placement and routing techniques.

After detailed routing, electrically-accurate layout optimization is performed at a small scale. Parasitic resistances (R), capacitances (C) and inductances (L) are extracted from the completed layout, and then passed to timing analysis tools to check the functional behavior of the chip. If the analyses reveal erroneous behavior or an insufficient design margin (guard band) against possible manufacturing and environmental variations, then incremental design optimizations are performed.

The physical design of analog circuits deviates from the above methodology, which is geared primarily toward digital circuits. For analog physical design, the geometric representation of a circuit element is created using layout generators or manual drawing. These generators only use circuit elements with known electrical parameters, such as the resistance of a resistor, and accordingly generate the appropriate geometric representation, e.g., a resistor layout with specified length and width.

Physical verification. After physical design is completed, the layout must be fully verified to ensure correct electrical and logical functionality. Some problems found during physical verification can be tolerated if their impact on chip yield is negligible. In other cases, the layout must be changed, but these changes must be minimal and should not introduce new problems. Therefore, at this stage, layout changes are usually performed manually by experienced design engineers.

Design rule checking (DRC) verifies that the layout meets all technology imposed constraints. DRC also verifies layer density for chemical-mechanical polishing (CMP).
Layout vs. schematic (LVS) checking verifies the functionality of the design. From the layout, a netlist is derived and compared with the original netlist produced from logic synthesis or circuit design.
Parasitic extraction derives electrical parameters of the layout elements from their geometric representations; with the netlist, these are used to verify the electrical characteristics of the circuit.
Antenna rule checking seeks to prevent antenna effects, which may damage transistor gates during manufacturing plasma-etch steps through accumulation of excess charge on metal wires that are not connected to PN-junction nodes.
Electrical rule checking (ERC) Verifies the correctness of power and ground connection, and that signal transition times (slew), capacitive loads and fanouts are appropriatelt bounded.

Both analysis and synthesis techniques are integral to the design of VLSI circuits. Analysis typically entails the modeling of circuit parameters and signal transitions, and often involves the solution of various equations using established numerical methods. The choice of algorithms for these tasks is relatively straightforward, compared to the vast possibilities for synthesis and optimization.

Fabrication: The final DRC/LVS/ERC clean layout, usually represented in the GDSII stream format, is sent for manufacturing at a dedicated silicon foundry (fab). The handoff o fthe design to the manufacturing process is called tapeout, even though data transmission from the design team to the silicon fab no longer relies on magnetic tape. Feneration of the data for manufacturing is sometimes referred to as streaming out, reflecting the use of GDSII Stream.

As the fab, the design is patterned onto different layers using photolithographic process. Photomasks are used so that only certain patterns of silicon, specified by the layout, are exposed to a laser light source. Producing an IC requires many masks; modifying the design requires changes to some or all of the masks.

ICs are manufactured on round silicon wafers with diameters ranging from 200mm(8 inches) to 300mm (12 inches). The ICs must then be tested and labeled as either functional and defective, sometimes according to bins depending on the functional or parametric (speed, power) tests that have failed. At the end of the manufacturing process, the ICs are separated, or diced, by sawing the wafer into smaller pieces.

Packaging and Testing: After dicing, fuctional chips are typically packaged. Packaging is configured early in the design process, and reflects the application along with cost and form factor requirements. Package types include DIPs, PGSs, BGAs etc. After a die is positioned in the package cavity, its pins are connected to the package’s pins, eg., with wire bonding or solder bumps (flip-chip). The package is then sealed.

After packaging, the finished product may be tested to ensure that it meets design requirements such as function, timing and power dissipation.

VLSI Design Flow - 1

2011-03-14T01:54:00.000-07:00

VLSI Design Flow:


Fig:1 VLSI Design Flow

The process of designing a very large-scale integrated (VLSI) circuit is highly complex. It can be separated into distinct steps (Fig. 1). Earlier steps are high-level; later design steps are at lower levels of abstraction. At the end of the process, before fabrication, tools and algorithms operate on detailed information about each circuit element’s geometric shape and electrical properties.

System specification. Chip architects, circuit designers, product marketers, operations managers, and layout and library designers collectively define the overall goals and high-level requirements of the system. These goals and requirements span functionality, performance, physical dimensions and production technology. Architectural design. A basic architecture must be determined to meet the system specifications. Example decisions are

Integration of analog and mixed-signal blocks
Memory management – serial or parallel – and the addressing scheme
Number and types of computational cores, such as processors and digital signal processing (DSP) units – and particular DSP algorithms
Internal and external communication, support for standard protocols, etc.
Usage of hard and soft intellectual-property (IP) blocks
Pinout, packaging, and the die-package interface
Power requirements
Choice of process technology and layer stacks

Functional and logic design. Once the architecture is set, the functionality and connectivity of each module (such as a processor core) must be defined. During functional design, only the high-level behavior must be determined. That is, each module has a set of inputs, outputs, and timing behavior.

Logic design is performed at the register-transfer level (RTL) using a hardware description language (HDL) by means of programs that define the functional and timing behavior of a chip. Two common HDLs are Verilog and VHDL. HDL modules must be thoroughly simulated and verified.

Logic synthesis tools automate the process of converting HDL into low-level circuit elements. That is, given a Verilog or VHDL description and a technology library, a logic synthesis tool can map the described functionality to a list of signal nets or netlist, and specific circuit elements such as standard cells and transistors.

Circuit design. For the bulk of digital logic on the chip, the logic synthesis tool automatically converts Boolean expressions into what is referred to as a gate-level netlist, at the granularity of standard cells or higher. However, a number of critical, low-level elements must be designed at the transistor level; this is referred to as circuit design. Example elements that are designed at the circuit level include static
RAM blocks, I/O, analog circuits, high-speed functions (multipliers), and electrostatic discharge (ESD) protection circuits. The correctness of circuit-level design is predominantly verified by circuit simulation tools such as SPICE.

Physical design. During physical design, all design components are instantiated with their geometric representations. In other words, all macros, cells, gates, transistors, etc., with fixed shapes and sizes per fabrication layer are assigned spatial locations (placement) and have appropriate routing connections (routing) completed in metal layers. The result of physical design is a set of manufacturing specifications that must subsequently be verified.

Continue to reading this article here

CTS is Build for 4ns clock period. Is it work for 3ns and 4.5ns period clocks?

2010-06-23T09:33:00.000-07:00

Let us assume the CTS built with 4ns clock period clock have the following characterstics:
Max. insertion delay = 1.2ns
Max. skew = 300ps
Max. transition = 400ps

If above values are ok for the 4.5ns and 3ns clock. Then the same clock three will work for the 4.5ns and 3ns. But it will not work for the 1ns clock as the insertion delay is more than the clock period.

Low Power Design Essentials (Integrated Circuits and Systems)