There has been immense development in physical design aspects of designing with the advent of CAD Tools. It’s not that long ago, that we were hand taping on multiple layers of mylar at 2:1, 4:1 and even 8:1, and then having to shoot the artwork with a camera to reduce the film to 1:1. The power of today’s CAD tools can maximize your time whether it be circuit design, circuit simulation, PCB design, or system-level simulation. In turn, Complex designs can be optimized quicker and more efficiently.

We know that copper traces are used as interconnects or bridges between two unconnected elements of the circuit. The length & shape of these interconnects play an important role in high speed design, since each interconnect is modeled as a combination of resistance, inductance and capacitance, which can in turn change the value of impedance. Taking this into consideration, we try to model PCB Routing Techniques in a more algorithmic and efficient way to improve the speed of the design.

The most challenging task for the designer is the placement of the components in order to minimize the usage of wire and chip area. The design starts with placing the important components of the circuit in terms of design and the entire board to reduce the routing constraints. Finalizing the key elements specific locations (critical components) and routing paths helps in analyzing the critical path and operating frequency of the circuit design. After Placement, particularly for routing a wide variety of analog and digital signals, with varying voltages and currents, ranging from dc to high frequency (GHz), the utmost importance is keeping signals from interfering with one another. The Zero potential planes help in providing a common reference point for devices as well as helping device shielding in order to compensate for any extra amount of current. In the case where signal isolation is required, we need to concentrate on the physical distance between the signal traces.

Major Routing key points

• Distance between two interconnects must be minimized for particular path.
• There should be no sharp bends, (90 Deg.) in the track design.
• Tracks should exit from the center of a connection point, avoiding other interconnects and pads in order to have a high speed and error free design.
• Do not place via under component.

Image: Proper angle routing (left) and bad routing (right)

Reduction in long traces on adjacent layers to prevent capacitive coupling.

• Reduction in long parallel runs and close proximity of signal traces in order to reduce or eliminate inductive coupling (practically impossible) in a design.
• Signal traces requiring high isolation should be routed on separate layers and if not possible, orthogonal routing can be done. Orthogonal routing will help in minimizing the capacitive coupling which will lead to the shielding effect by the ground or zero potential.

Automated Routing Techniques can be used for increasing speed

Auto routing within a Design exhausts all the possible implementations of the given possible design and helps to improve the performance, reliability and cost of the circuit design. This innovation is referred to as Electronic Design Automation. The technology has advanced with usage of Artificial intelligence and neural based technology. Automated routers are mainly used when you have a complex board with little routing space. Advanced automated routers allow you to specify exactly how you electrically want to layout the most important tracks. Below is the list of general purpose routing techniques and algorithms (These are algorithm models related to CAD Routing tools) , apart from this there are special routing techniques for power and clock like H-clock tree synthesis.

The left hand side of the above diagram shows the top view implementation of a PCB design. Due to the simplicity of this design, we can mount all the circuit components on the top layer. The above design will help in eliminating the signal trace which ensures the best possible speed and design of the circuit. The key points in this PCB design is the reduced delay time because the separation of larger bypass caps are placed farther away with ferrite Chips for HF isolation of currents and multiple via which reduces the delay path in the circuit.

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As a printed circuit board manufacturer, PNC Inc., Nutley, NJ, our criteria of acceptability during the inspection process is determined by IPC–A–600. The scope of this document describes the acceptable and non-conforming conditions of a bare boards either externally or internally during the final inspection process. The inspection criteria is then broken down into three classifications of acceptability, Class I, Class II and Class III. Each class’s acceptance criteria is then again broken down into three areas, target condition, acceptable, and nonconforming for the imperfections in question.

At times there can be a disconnect or confusion between the end-user and the manufacturer in terms of acceptability criteria. Why? Is the PC board manufacturer shipping inferior product, or not interpreting the IPC standard incorrectly? Does the end-user use a standard for acceptability during incoming inspection, such as IPC-6012? These are only a couple of questions why there may be a disconnect in determining the acceptance or nonconformance of a bare rigid board.

The intention of this blog is to help inform and decipher the IPC–A–600 acceptance criteria for a bare printed circuit board. Over the next few months, I will break down imperfections with pictorials, and explanations of the acceptance, or nonconformance for a particular imperfection. I will start with the most common defects seen in the manufacturing process of a PC Board.

Today, I’d like to look at one of the most common occurrences, external annular ring of supported holes. The condition in question is where the drill in the plated through hole appears to be off center in the pad, as seen in figure 1 below. This occurrence happens because of manufacturing tole rance build ups through the process. The two main contributors are Drilling and Primary Imaging.

Figure 1

The combined tolerance between the two processes for most PC Board Manufacturers can be +/- .003 for positional accuracy. Typically most Drilling Machines have a positional accuracy of anywhere from .0005” – .001”, whereas primary imaging photo tool registration can be out as much as .003” due to film stretch or shrinkage. In knowing that there are manufacturing tolerances involved, let’s look at the IPC rule for this condition.

According to IPC-A-600, Acceptability of Printed Circuit Boards, we need to determine the minimum annular ring of the supported hole. This can be found in section 2.10.3 External Annular Ring-Supported Holes, as seen in Figure 2103a, since there is no break out. As you can see the target condition is where the hole is centered within the land.

The ruling criteria can also be found in Table 3-5 Minimum Annular Ring from IPC-6012B. For the holes in question from Figure 1, the inspection process used Class II as their criteria.

After viewing the customer’s original Gerber data, we find that the annular ring is specified at .009 “. Our findings at the narrowest point of the annular ring measured was .006” on the board. We know that it does not meet the Target condition for Class II per IPC, so we’ll look at the acceptable condition from Figure 2103b.

In this case, Class III is the only acceptable criteria for this condition which states, “Holes not centered in the lands, but the annular ring measures .050 mm or .002” or more. Also during the observation, there were no defects such as pits, dents, nicks, pinholes or Splay, so we do not use the 20% rule for this condition. Knowing that we have more than .002” of annular ring remaining, this condition passes the inspection process per IPC-A-600 section 2.10.3.

I realize to most of you that this is very elementary, and the rule is straight forward. In saying that, we find ourselves defending the IPC rules with individuals whom are unaware of IPC-A-600 and/or IPC-6012 standards. Over the past 20+ years in this business, I have seen great strides in companies having their employees educated and/or certified to IPC standards. I can only hope the trend continues.

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As we advance into the future, we want everything to be faster, cheaper, compact and durable. Everything around us is electrical. Moore’s law predicted that numbers of transistors per square inch of PCB will double every 2 years and it’s been true too date. Well theoretically it sounds good. But implementing new products with the above requirement comes with a cost. In order to reduce the unit cost of the design, due to noise. Various techniques have been developed in the past few decades to reduce noise in the circuits as the number of components increases and the available size decreases. Design techniques include proper grounding, decoupling, routing and signal multiplexing.

Grounding at PCB level can be in implemented as single point ground. As the name suggests a single point ground is where the complete circuit residing on the PCB has a single ground. This technique is developed by using a ground plane. Ground plane is defined as a highly conductive electrical surface which will be used as a system ground. In printed circuit boards, it is referred to as a large conducting surface of copper foil on either side of the PCB. It is connected to the power supply ground terminal and thus it serves as a return path for current from different components on the board .The fact that a large surface area of highly conductive metal, like copper, has a very low impedance which forms the basis of this method.

Ground plane is laid on the PCB, such that it covers the maximum area which is not occupied by circuitry itself. In multilayer PCB’s, it is often a separate layer covering the entire board. This makes the circuit design easy to implement, thus further allowing the designer to ground any component or subpart of a circuit without adding additional traces. The large area of copper which provides a very low impedance path conducts the large currents originating from other components/subparts without significant voltage drops. This ensures that the ground connection of all the components is at the same reference potential.

Benefits of grounding in PCB are:

• Reducing electrical noise
• Reduce interference being coupled from one part of the circuit to another.
• Reducing crosstalk between adjacent circuit traces.

1) Noise reduction:

When circuits switch states, large current flows from the active devices through the ground. If the power supply and ground traces have noticeable impedance, then the voltage drop across them may create noise voltage that would disturb other parts of the circuit. The large conducting area of the ground plane has much lower impedance than a circuit trace, so the current causes less disturbance.

2) Interference & Crosstalk reduction:

When two traces are placed too close to each other, an electrical signal in one can be coupled into the other. This is due to electromagnetic induction caused by the linking of magnetic field lines from one trace to other. This phenomenon is known as crosstalk. When a ground plane layer is present underneath the circuit in the PCB, it acts as a transmission line for the trace. Thus the direction of current flowing through the ground plane is opposite to the direction of current flowing through the circuit trace. This cancels most of the electromagnetic fields and consequently reduces crosstalk.

Many of the present day circuits consist of both Analog and Digital subparts. To avoid current from one subpart to affect the other subpart, ground planes are split and then connected by a thin trace. The thin trace has low enough impedance to keep the two sides very close to the same potential while keeping the ground currents of one side from coupling into the other side, completing a ground loop.

Thus grounding in PCB can significantly improve the circuit/chip performance. No extra area is added to the chip as leftover areas are used. This method doesn’t add too much of cost to the initial design which makes it readily acceptable at industry level.

Types of single ground connection:

• Series Ground Connection:

• Parallel Ground Connection

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According to the latest surveys/research, currently 40% of the world power/energy are met with the usage of electrical systems, with more advancements in the field of renewable resources, the percentage will be going to shoot up to nearly 70-80% in the coming decade by 2025.The efficiency of power equipment varies from 90% (small design) to 95-98% (big complicated design models). Due to rapid advancements in the field of technology, the cost of the circuit and size is reducing at a faster rate and providing more efficiency as compared to the previous possible designs.

Challenges in Designing Power Electronics

The major challenges in the field of power electronics are cost, reliability, parasitic losses and electromagnetic interference. Areas like aerospace industries, automation and robotics industries has posted the biggest problems in front of power engineers because in order to fulfill the safety requirements. The safety requirement is the most difficult and unsolvable challenge in many fields involving power electronics devices.

The old technology of linear dissipative regulator is reliable as compared to newer regulators since new regulators used the bulky capacitors and lesser amount of shielding in the circuit. If due to some fault, larger supply is fed to the circuit then it will suddenly increase the current in the design which will lead to damaging and even burning of the complete circuit.

Even the latest MOSFETS or transistors, available in the market comes with very low power wattage i.e. 0.5 W or 1W (at max) in order to provide the cost effectiveness but this make the circuit more prone to damage since even small deviation from the expected behavior can lead to damaging the complete circuit. Ex- observed in the latest gadgets like LED TV’s, Mobile phone (since in order to provide cheaper designs, they are using the devices at the bottle neck of their limits).

Electromagnetic Interference in layman terms is defined as the amount of noise/disturbance produced by a power circuit due to change in one of electromagnetic radiation or induction. EMI must be kept in safe level to ensure the reliable operation for the given design.

Issue: Power supplies generate lot of noise in the circuit due to switching current at high operating frequency and most dependent customer being MOSFET for the same. Due to MOSFET, the switching speed is very high varying from 200 KHz to 100 MHz range. The generated EMI due to noise can be characterized as Differential and Common Mode Input

• Differential Mode Input–It basically consists of in and out of flowing current through the power supply by the path going from power lead to the source. It is the dominated in lower frequency range i.e. less than 5 MHz
• Common Mode Input – – It basically consists of in and out of flowing current through the power supply by the path going from power lead to the source through the lowest impedance path i.e. ground. It is the dominated in higher frequency range i.e. greater than 5 MHz

Minimizing EMI

• Bypassing – Bypassing is one of the most effective and cheapest method to tackle this problem. Used for reducing high switching current in the case of MOSFET with the help of large and bulky capacitor.
• Decoupling –Decoupling refers to isolation of two circuits with the help of a common line. It is implemented using low pass filters.
• Layout –Increase the distance between VDD and ground plane at the time of chip layout in order to reduce the EMI, reducing the inductor can also provide minimizing the EMI.
• Shields –Reducing the energy requirement from DC-DC supply by putting a metallic shield outside the power supply.

The single biggest failure for any network/system is power supply which major comprises of the below listed factors

• Internal supply failure- The Internal Supply failure issue arises in the case of ill-handling the devices but mostly to prevent this problem, there is an automatic shut off system inbuilt in our Laptops and other electronic devices.
• Voltage Irregularities- Most commonly consists of high voltage spikes, surges and delay in either input paths which switches the logic value.
• Outraged Power –Mostly external power failures due to change in supply voltage from the plugs can cause outraged power. This will happen for short span of time varying for some seconds to minutes.

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Put surge suppression components on all electrical coils: Resistor/capacitor filters, MOVs, Zener and clamping diodes.
Shield all remote connections, use twisted pairs. Shields should be tied to Earth at one end.
Put all microelectronic components in an enclosure. Keep noisy devices outside. Watch internal temperature.
Ground signal common wiring at one point. Float this ground from Earth if possible.
Tie all mechanical grounds to Earth at one point. Run chassis and motor grounds to the frame, and the frame to Earth.
Isolate remote signals. Solid state relays or opto isolators are recommended.
Filter the power line. Use common RF filters, and use an isolation transformer for worst case.
Filter the lines between the drive output and the motor.

A noise problem must be identified before it can be solved. The obvious way to approach a problem situation is to eliminate potential noise sources until the symptoms disappear, as in the case of ground loops.

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Let me give you few famous examples which have changed our lives:

Fourier series: Fourier observed that any periodic signal is nothing but composition of series of identical signals of different frequencies. It seems very simple, but its applications have made a significant difference in our lives: communication, music, seismic, tidal etc.

Quantum theory: According to Max Plank (Quantum theory), the light is made of trains of elementary particle called photon. What an observation!!! Do you know the applications of quantum physics: Magnetic resonance imaging (MRI), laser, LED.

There are so many other theories based on breaking down an event or object into series of small elements which we have been using knowingly or unknowingly. Few examples of successful applications of this thinking:

Staircase: What is principle behind staircase? Simple!!! It breaks down big chunk of energy required to climb something into steps and that makes life practical. Actually it also gives a time delay at every step. Basically it breaks down time and energy required into pieces.

Switching converters: Unlike linear regulators, in switching regulators energy is pumped from source to load in series small chunks. With switching regulators the efficiency of DC conversion can be achieved up to 97%, same principle of breaking down energy and time into pieces.

LCD Display: Driving LEDs of the screen in series of pulses faster than human being could experience the change, nothing but pulses of energy over time delay.

Computer & Books: Numbers and letters are made of just two bits 0 and 1. Book without letters is impossible.

In general, always think of series of events in minuscule particles, chunks, changes etc. Now where we need to apply this tactic? In last decade energy has turned to be a center focus for everyone as we now rely more and more on machines for daily life. How can we convert any form of energy into electrical energy efficiently and easily? We are very close to it; just need detail micro scoping observation to find out hidden breakdown.

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One of the most common failures is, AC mains conducted emission testing which is listed as IEC 61326-1:2005, Ed. 1 section 7 (CiSPR11:2003). The purpose of the conducted emissions test is to measure noise currents that exit the products ac power cord to be sure the currents are within the regulated limits. The most efficient method for the reduction of conducted emissions is to reduce them at their sources. In this section we will discuss the source of conducted Emission on AC mains and how we can minimize the emissions. In following section we will focus on workarounds for the system has failed pass the AC mains conducted emission test.

Fast recovery diodes snap off sharply and generate high frequency noise compared to slow recovery diodes. In order to reduce this undesirable noise generated in the turnoff of the diode, snubber circuits are generally placed in parallel with the diodes. The snubber circuit consists of a resistor in series with a capacitor that acts as a path to discharge the charge stored at the diode junction when the diode turns off. This tends to smooth the diode current waveform, thereby reducing high frequency spectral content. The high frequency current will circulate through the snubber circuit where the leads need be kept short and the elements placed very close to the diode. In doing this, you will reduce the current loop area and the emissions will be radiated from the loop.

Transformer:

Winding the coils on top of each other introduces a parasitic capacitance between the primary and secondary. This primary-to-secondary capacitance can introduce an undesired coupling that allows noise on the secondary side to be more easily coupled to the primary side. Once the noise is present on primary side, it passes out through the power cord and is measured as a conducted emission by the LISN, unless the power supply is inserted between the power cord and transformer. The efficiency of this coupling, due to the parasitic primary-secondary capacitance increases at higher frequencies. In order to reduce this coupling, there is need for a metallic shield between the primary and secondary coils. This is referred to as a Faraday shield. This shield should be connected to the primary side reference or neutral.

Switching devices:

Primary current begins to flow when a MOSFET(s) is turned on. The transformer primary current ramping to a peak value is determined by input voltage, motor phase inductance, switching frequency and duty cycle. This trapezoidal (or triangular) current waveform is characterized in the frequency domain by a spectrum at the switching frequency. The harmonics are determined by the relative squareness of the waveform and causes the primarily differential mode emission currents to circulate between the AC mains and the power supply input. This current waveform can also create common mode emissions, due to radiated magnetic fields when the current path defined on the PC board layout encircles a large physical area.

The spectral content of the noise that is produced by switching is directly dependent on the rise and fall times of pulses. The slow (high) rise and fall times are desirable from the standpoint of EMC. This causes the MOSFET to spend more time in its active region, which increases its power dissipation, therefore is an undesirable result from the standpoint of thermal consideration. Concurrently, there is an apparent tradeoff between reduction of noise spectral content that will contribute to conducted emissions and the thermal heating of the switching element and related efficiency of the switcher.

Wire Harness and System connections:

Noise current sources appear between live and neutral connections without reference to the earth connection. In circuits with a switching power supply or motor control, the RF emissions are dominated by interference developed across the DC link to the switching devices. Although there will be a bulk capacitor, the high di/dt through this capacitor will generate voltages at the harmonics of the switching frequency across its equivalent series impedance.

The coupling is dominated by the inter-winding capacitance of the isolating transformer, stator-rotor of the motor and system to the chassis. These capacitances are referred to earth, either directly or via the enclosure if this is conductive. A well shielded enclosure will minimize “leakage” of this capacitive coupling and hence reduced conducted emissions. Ideal connections for 2-wire and 3-wire system are shown in figure xx and xx.

This article was written by Sam Sangani Jr., PNC Inc.’s Fellow Design Engineer. For additional information related to this or any other topic, you can reach Sam via e-mail at sam@pnconline.com.

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Unfortunately, I don’t like donuts, but a certain anxiety came over me in wanting to know, what could the topic of discussion be? I could only think of one potential issue we were having. Could it be the unresolved failure of a cooling fan driver board for commercial aircraft? This issue was nearing 6 months, and we couldn’t reproduce a single failure in our lab. At this point, we were getting 8 to 10% failures every month – which is not good. It had become the focal point of entire company. Other Project Team Members were starting to question our abilities and losing confidence in our Team to solve this issue.

The weekend had pasted and the moment of reality was here, Monday morning meeting time. All 8 members of the team were present. As I sat there looking around, there were donuts to be found. The conference room was neat and clean, the white board, projector, and phone were in there usual place. In walks the Project Manager apologizing for not having brought donuts because he had to drop off his daughter at school. He abruptly starts the meeting with, “As no progress has been made in the last 6 months on the cooling fan driver Board, the Director of Engineering wants to reinvent this team and some or all of you may not be working with this team starting next week. “I don’t know whether this means you will be with the company or not, Thanks guys.” Within 5 minutes the meeting was over. He left the conference room leaving the 8 of us to ourselves.

We were all starring at each other without words until one Team member stated – “Hey guys we did all we could do.” Another added – “We did circuit analysis and worst case analysis”. A third member said – “I had performed a series of experiments at 300% stress.” The last comment was – “Several experts and consultants from outside were also involved and they had no clue as well.”

As everyone went back to their desks to start job searching, I sat there struggling to digest the decision the Director of Engineering was taking. I decided to go to the lab where I saw two unknown Engineers standing over our test setup that were not familiar with this project. I introduced myself, and obviously they did as well. In the mean time before I arrived, they had moved the test setup fan, used to simulate air flow on the Board, to avoid the breeze blowing on them. They asked me to give an overview of the test setup and testing procedure, so I explained the setup and procedure step by step. Meanwhile the system was not powered, but I was seeing smoke coming from the Board. At a closer look, the cooling fan on the driver board was spinning, which didn’t make sense. I also noticed that the components on the Board were burned and looked similar to the field failures we were experiencing. I stepped back and asked the two engineers what they had changed. Their reply was, “we didn’t touch anything except for moving the setup test fan. I now understood the reason why the cooling fan was spinning while not powered. Adjacent to our setup fixture was another setup test fan, for another test, that was making our cooling fan on the driver board spin. In fraction of second, a series of thoughts passed thru my mind: back EMF protection in idle state or a requirement escape.

I rushed back to my desk, composed a new email to the Project Manager and all Team members with subject – “Donuts resolved the issue”. The message in the body of the E-mail stated – “If anyone wants to know the root cause, bring the donuts to my desk”. Within 20 minutes our Project Manager and the Director of Engineering walked in with a box a Donuts in hand and their faces expressed a certain calmness.

The Moral of the Story? Be sure the requirements used for measuring reliability are complete.

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Normally bus voltage is in the range of 40VDC of delivery current at 5A to 15A. I have seen this standard implementation in almost 80% of motor drives I’ve come across. There is nothing wrong with this configuration except the linear power supplies’ efficiencies and amount of heat dissipation. Deriving 15V from 40V with a linear regulator at 0.5A load, the system will need a large heat sink and a cooling fan to dissipate 12.5Watt’s of heat. Even worse, if a 5V supply is derived with a linear regulator, due to too much potential difference, the cooling system has to be capable of dissipating an additional 17.5 Watts of heat. On top of these, 3-ϕ bridge inverters and switching loss introduces a sizable amount of heat. Typically, these three sources of heat are tied to a common heat sink to save cost. Each component tied into the common heat-sink runs at a very high temperature from thermal derating, thermal run-away, etc.

Is there a better way to overcome this thermal problem? Yes. One can replace the linear regulators with switching regulators. The problem with switching regulators is the higher peak current requirement which in return creates a higher potential difference, and turns this into another problem by introducing more costly components.

There is an alternate solution by adding (1) wire and (1) diode to overcome this issue. As shown in figure – 2, using the method of center tap secondary, we can generate low voltage DC from half-wave rectifying for the linear regulators

This will reduce the heating by 66%. One note of Importance to keep in mind here is: the center tap is not a ground reference of the system, unlike a full-wave rectifier.

Operation of this half-wave rectifier will be different than an ideal half-wave rectifier. When the center tap is at a higher potential than the lower end of secondary, the diode will conduct and the current will charge the filter capacitor and provide the load current and the return current will flow thru the diode of lower arm of the bridge rectifier.

If load is too small, one can replace the diode with a SCR by setting the appropriate firing angle by means of a resistor, diode and capacitor. This will bring the output of the half-wave rectifier down to an adequate input voltage of the linear regulator.

If we want further optimization, we can replace the 5V linear regulator with a switching regulator to be tied to the half-wave rectifier, as shown in figure -3.

Now we have about 20V from the half-wave rectifier, and an output of 5V. The potential difference went down by 10V which will reduce the peak current requirement for the switch. The efficiency of the switching regulator is normally in the range of 90% to 95%, and will reduce the heating to 10% of the original topology.

With a SCR half wave rectifier and switching regulator, the heat sink is not required; temperature will not rise greater than 20˚C. This eliminates the cost of a heat sink as well as thermal failures.

This article was written by Sam Sangani Jr., PNC Inc.’s Fellow Design Engineer. You can reach Sam via e-mail at sam@pnconline.com

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