Basic 2.5D Structure

These are really exciting times: 3D and 2.5D technology could change the entire landscape and architecture of ASICs. This has already started in FPGAs and ASSPs, but ASICs face a particular challenge. ASICs do not generally have the benefit of high volume required to secure sources, influence foundries, and gain early access to 3D technology — which they need if they want to be in a leadership role in this implementation.

The exponentially rising cost of tapeouts at lower nodes has resulted in fewer tapeouts at these emerging technologies. Therefore, there are fewer experts in this field. Some companies will be able to spend a lot of money developing the technology and hence developing the expertise in the field. The rest of us will need to depend on strategic partnerships to help, to hand-hold, as we cross the threshold into this technology.

Foundries and assembly houses are keeping their 3D-IC cards close to their chest and waiting for industry leadership to come from the users of 2.5D and 3D technology. Obviously, they do not want to spend all that money to determine later they need to change course to follow the prevailing current.

eSilicon has already spent a good amount of time and effort on 3D- and 2.5D-IC technology. We believe that ASICs will need what we are referring to as a menu for “tiles,” such as memories, microprocessor subsystems, integrated passive devices, FPGA die, and other devices. In the eSilicon model, tiles are proven building blocks. A 2.5D or 3D-IC implementation could include tiles in leading-edge technologies like 28nm, with a lower NRE thanks to a 65nm based interposer. The proven tiles mean the design team doesn’t have to re-invent the wheel, saving time and reducing risk.

3D-IC Structure Example

We — along with our partners — are moving forward to provide leadership in the 3D-IC space. At the same time, we look within and beyond our customer base to make sure we know where the prevailing currents are flowing. I do not think any of us will have all the answers, but ongoing conversations with partners and customers are getting us closer to understanding where the need is. Once you know where the need is, the direction will be abundantly clear.

That second sourcing general concept did not mitigate any risk at all when the earthquake, tsunami, nuclear meltdown, loss of life, destruction of infrastructure and power outages hit eastern Japan. We all watched in horror as the people in that region suffered. I was particularly glued to the news channels while one problem after another affected the area near Sendai and Fukushima. While none of my friends and colleagues in Japan nor their families were impacted by anything other than power outages, it was tough not to feel connected with the suffering. 

None of our direct supply partners were affected. In fact, none of their suppliers were significantly affected either. The problem occurred several links down in the supply chain. Unfortunately, even though we were greatly diversified in supply partnerships based throughout the world, once you go a few links deeper in the various supply chains, we realized that many of these companies shared the same links. It was the common links that were directly affected by the disaster. Materials such as the glass fiber used in BGA laminates; the fillers used in soldermask and underfill materials; and the big whammy — the main source in the world for BT (bizmalemide triazine) raw material was shut down. Mitsubishi Gas Chemical (MGC) held about a 70-percent market share and Hitachi held an additional 20 percent. When the crisis occurred both of the plants were closed. Hitachi returned to operation after a couple of weeks but was subject to rolling blackouts like every other company in the area. MGC stayed shutdown a while longer with only a small percentage of production starting a few weeks after the disaster. The industry collectively held its breath and readied itself for a gut-shot. 

It took a few days before we were able to get details on what factories were affected as it is generally difficult to jump more than a few links in the supply chain to get precise information. Luckily our strong strategic partnerships helped with getting the necessary info, and we formed what we called a “tiger team” to understand our exposure and deploy a disaster recovery plan with our supply partners and customers. A dozen members of our eSilicon team had a new half-time job ensuring continuity of supply for our production customers as well as those entering proto-validation phase. This often required the need to change material sets before all of the reliability could be collected. Luckily, there was usually existing data on similar parts that could be leveraged to gain confidence. Those already second-sourced projects were just as affected as the sole-sourced products since the various supply partners shared common supply chain links. So much for good disaster recovery planning prior to the disaster! 

Given that we were not the only ones finding alternate sources, the suppliers of the alternate materials became overloaded with new requests. This was an incredible opportunity for tier-two suppliers to gain market share. In order to ensure the supply, we had to occasionally prepare documentation and tooling for triple sourcing, given the fluidity of the loading at these alternate suppliers. Details changed on a near-daily basis. Luckily, a characteristic of our VCP (value chain producer) model requires relationships with a broad range of suppliers.  This helped us navigate the crisis in a way that other companies, large or small, would have had a much more difficult time with.

 Our customers were kept informed and given recommendations and options. This seemed to keep everyone focused on the end-goal of overcoming the supply problem. So far, we have been able to execute to forecasts with some products requiring material changes. At this point, the worst of the impact will just be an occasional delivery delay of a couple of weeks, which is far better than the customer base expected when the news of the supply problems began to emerge. We are not through the supply crisis, but we appear to be over the hump.

 While we can manage the supply side very well, we have little control over the demand side. In other words, if the world’s supply of mobile phone microphones is wiped out as an example, no one will ship cell phones. This means that even though a company may fully meet their production commitments, they are still potentially victim to the delivery performance of other companies, if they have a common customer. It is clear, we are all in this together.

 Once the dust completely settles, the industry will need to focus on what we learned from this crisis. Our highly globalized industry can easily be impacted yet again if industry clusters like the ones in Taiwan, Korea, Singapore, Japan and the US have a major catastrophe. We, as an industry, need to define second sourcing through many more links in the supply chain than we have in the past.

• Package assembly costs of MCM’s have been dropping in recent years
• MCM package technologies are becoming commonplace instead of being relegated to certain applications such as memory or image sensors.
• Emerging technologies are eliminating performance limits on MCM’s
• Tapeout costs are increasing exponentially as wafer technology nodes shrink

Tapeouts that only cost about $200k a few nodes ago now run in the millions of dollars at 28nm.  This means, companies will need to have fewer tapeouts in order to support their product lines.  The risk with each tapeout is higher and there is not much room for adding different flavors of product unless there is a considerable market for each individual product.  MCM’s may serve as a solution for this issue.  One approach for MCM’s is to create a base chip that can interface with several different devices to make a family of products.  The base chip can remain the same, but be paired with complementary devices and potentially different packages in order to gain the variety of interfaces or functionality needed to serve multiple markets or customer requirements. 

What drives the cost?

The interconnect between these chips is the main cost factor.  Direct die-to-die wirebonding can be the least expensive assuming the die are planned for MCM integration.  This can be seen as the top-most two images on the right.  That means there are no funky wirebond angles or dense traces on a laminate acting as jumpers to move a signal from one side of the die to the other.  Mixing interconnect methodologies such as flipchip and wirebond, can drive up cost, but even this option is becoming main-stream. 

The single most expensive cost-driver is poor planning.  If two die are designed in isolation, integrating them into a low-cost mcm will be more expensive (possibly much more) than if at least one of the die was designed with an awareness of the interconnectivity of the other die in the mcm package.

Area Benefit

Package-on-Package (PoP) technologies have been mainstream for some time.  The last Apple iPhone A4 processor used a flipchip die on the bottom package and two wirebonded stacked memories for the upper package.  The benefit here was driven mainly by board area, but this volume application is also helping to drive down cost for this approach in the industry. 

Applications such as high-end network processors are not as cost sensitive.  For these applications, the adoption of MCM packaging has really been driven by area reduction and external pin count reduction.  By bringing the memory devices into the package, the number of balls needed to connect to the PCB is considerably reduced.  While this does not appear initially to be a cost-incentivized action on the package, it does reduce the overall system cost.  Depending upon how this is executed, bringing external memory (bare die or packaged memory) into the MCM may actually be a much less expensive option under some circumstances.

What will drive MCM adoption?

Cost and area savings are clear and valid reasons for moving towards MCM’s, but a drive towards flexibility may be the next large factor.  The ever-increasing costs of a tapeout means that it may no longer be practical to have a family of parts that serve various segments in a market.  Instead, a single tapeout that integrates other devices to add flexibility may offer the opportunity to have a family of parts with a single tapeout.  This is a new angle on design-and-reuse.  Design-and-reuse which was a cornerstone of SoC IP, but now the reuse may come from die that are shared across multiple packages in order to mix and match interfaces or additional functionality.  We have already seen many of these strategies in the market as well as in our own activity.  This driver, may not tackle the unit-cost challenge, but it certainly addresses the issue of rising NRE costs for the most advanced nodes.  The difficulty here is changing the mindset of ASIC design teams so that they start with this end-game strategy in mind.  This MCM activity requires much more concurrent activity with what was once considered downstream activity such as packaging, thermal management, signal integrity, etc.  Some companies will understand this and take advantage of it sooner.  Once they’ve established a critical mass of complementary die to use in adding flexibility to their ASIC’s they will have an advantage over those who underestimated the extent of  the potenial benefits of MCM adoption.

A low cost package may end up raising your system costs.

So often, I come across questions from customers asking the the lowest cost package technology that will work.  The package by itself should not be the singular focus when considering the lowest-cost solution for a new ASIC.  The best approach is to take a few steps back and consider the system, and what would work best for that given system, from a  variety of standpoints such as routability, thermal, signal integrity, etc. 

Let’s take an example of a basic WiFi enabled ASIC.  What is the lowest cost solution?  Well, it depends upon what it is going into.  If the part is going into a handheld device such as a smartphone, then the lowest cost solution would likely be a WLCSP (wafer-level chip-scale-package) which is much like a bumped die without a package.  Given that the PCBs (printed circuit boards) used by smart phones can handle this smaller bump pitch and trace/space geometry, this makes a lot of sense.  On the other hand, if this was going into a home internet router, a WLCSP would be enormously expensive since it would require utilizing PCB design rules that are uncommon for these larger PCB’s found in typical home routers.  It would end up making the system cost go up as the PCB required to route the WLCSP would be likely cost several dollars more.  Instead going to a larger conventional TFBGA with something like 0.8mm or 1.0mm ball pitch makes sense.  This is a clear example of how a more expensive package is a better cost solution. 

There are many tradeoffs to be made.  The previous example is based on exit routing rules.  Let’s consider an example of thermal and signal integrity considerations on a processor-type device.  When making the tradeoffs between a thermally-enhanced PBGA (HSBGA) or a flipchip BGA (FCBGA), the HSBGA may be less expensive from a packaging cost standpoint.  They may both work thermally and electrically, and the HSBGA may be less expensive, so that may appear as the more logical choice, right?  Maybe not!  With a deeper analysis, you may find that the more expensive FCBGA may be a more prudent solution.  The FCBGA will likely end up consuming less of the signal integrity budget (reflection and loss) and would also be considerably more thermally efficient then a HSBGA.  This may end up requiring a less expensive PCB and a smaller heatsink.  It may also require less airflow or none at all.

Please make sure to consider the cost of the system above all else.  The cost of the individual component may not be nearly as relevant.  Having all of the resources available to make decisions at multiple levels upfront is paramount.  If you do not have these resources easily available, finding a partner than can bring these vantage points to the table will work to your advantage.

RoHS5
Unofficially, the use of a term deemed “RoHS5″ was developed to describe package that had external leadfree interconnects (usually solder balls) but had lead in the first level interconnect.  The original RoHS regulation sought to eliminate six materials from use in products, but given that lead in the die-to-package interconnect was exempted, these parts were referred to as RoHS5.  This RoHS5 term, though widely used, is not documented anywhere in the RoHS regulation.  It appears to have been started by Cisco to describe their devices with leaded bumps, and the term just caught on.

Truly leadfree flipchip devices do exist.  Devices with smaller die, generally less than 16mm on a side can pass reliability testing with completely leadfree bumps.  The assembly plants and third-party bumping facilities were on-board quickly with this capability years ago, but the reliability was always in question given the lack of production experience and long term reliability data.  Wafer fabs were late to the party with most of them lacking their own captive bumping resources.  Many of the major wafer foundries still do not have leadfree bumping capabilities available whereas they were the dominant source for leaded bumping. 

Commercial parts with shorter lifespans were really the first to adopt leadfree bumping processes as longer product lifetimes were not needed.  These commercial flipchip devices generally have smaller die where there is much less stress introduced from thermal expansion mismatches compared to larger die.   The “green” product programs which were most popular in Japan and with Japanese manufacturers also encouraged leadfree assembly but were mostly targeted to commercial products with shorter lifespans as well.  The product types that proved to be the most difficult to migrate to leadfree bumping solutions were larger silicon products that needed longer life spans such as network and storage devices.  These devices generally need to last for 20 years.  This seems to be the last frontier on completely leadfree flipchip devices.  So, if you are in this space, should you take the risk on leadfree bumping?

Big Leadfree Die and the Strategy
Currently, the design rules used for leadfree and conventional leaded bumps are the same.  That means, there is a minimal expense needed to change the alloy from RoHS5 to fully RoHS compliant at a later date.  This expense may include a lower cost bumping mask at the bumping facility, a solder stencil change at the substrate manufacturer and perhaps another stencil at the assembly house for the solder paste used for the passive on the substrate if there are any.  These costs are small compared to the risk taken to use leadfree solder paste on large die in long-life applications.  Why bother when you can just change it later when the EU decides to stop extending the lead exemptions for bumps.  Wait a minute! I obviously neglected the high cost of requalifying the system at a later date when the change is made to leadfree.  While this may be a large expense, I argue that this is a requalification that will happen anyway.  The main difference I see with larger network processors is that they tend to have a lot of familiar company on a PCB.  Chances are, your device would not likely be the only one with lead in the bump alloy on the die.  Therefore, once the EU stops moving the line in the sand, these other component suppliers will update their parts, assuming good leadfree reliability data is available then.  Therefore, the requalification will need to happen at that time anyway, and this is the right time to convert the components to full leadfree configurations, using the latest leadfree bump alloy available and the latest reliability data.

If there is an interest in using an ASIC in an MCM, then designs need to start from the integration of the chip then work backwards to the die floorplan.  This is a reversal of the standard flow and hence may be difficult to drive into the design team mentality.  Many design teams have fallen victim to working on the stand-alone version of a chip without the later MCM integration in mind, which ends up costing much more.  There is a package technology that exists just to fix this oversight seen to the left.  PiP (Package-in-Package) technology integrates an interior package just to reposition the die interfaces to a location what works well with an another die.  Had these ASICs been planned with the MCM in mind, PiP technology would likely not exist.

Tool vendors have proposed integration tools that would help with this system level integration, but tools alone are not the answer.  The ASIC design mindset and culture need to be addressed before any tools are introduced to remedy the issue. 

Another gotcha lurking in the shadows is heat dissipation.  Some of the techniques that allow for better integration lead to thermal barriers.  For example, with stacked die in a package, the maximum specified junction temperature on one die will impose the same restriction on the other die.  Furthermore stacking one wirebond die above a flipchip die eliminates the primary thermal dissipation paths on the package.  In this case, things like thermal vias for the wirebond die or backside expose for the flipchip cannot be used.

A little handholding with an experienced consultant or value chain producer (VCP) with knowledge of MCM and SiP planning may prevent some headaches and schedule slips from occurring.  The design team education and guidance must be introduced early in any MCM program.  Once a design has a solid floorplan, valuable guidance becomes difficult and expensive to implement.