Paolo Mantovani | Publications by date https://www.cs.columbia.edu/~paolo Publications Accelerator Integration for Open-Source SoC Design https://www.cs.columbia.edu/~paolo/pubs/giri_ieeemicro21.pdf Fri, 1 Jan 2021 00:00:00 -0000 Agile SoC Development with Open ESP https://www.cs.columbia.edu/~paolo/pubs/mantovani_iccad20.pdf Thu, 1 Oct 2020 00:00:00 -0000 Ariane + NVDLA: Seamless Third-Party IP Integration with ESP https://www.cs.columbia.edu/~paolo/pubs/giri_carrv20.pdf Fri, 1 May 2020 00:00:00 -0000 ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning https://www.cs.columbia.edu/~paolo/pubs/giri_date20.pdf Sun, 1 Mar 2020 00:00:00 -0000 HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis https://www.cs.columbia.edu/~paolo/pubs/mantovani_cicc20.pdf Sun, 1 Mar 2020 00:00:00 -0000 Runtime Reconfigurable Memory Hierarchy in Embedded Scalable Platforms https://www.cs.columbia.edu/~paolo/pubs/giri_aspdac19.pdf Tue, 1 Jan 2019 00:00:00 -0000 Teaching Heterogeneous Computing with System-Level Design Methods https://www.cs.columbia.edu/~paolo/pubs/carloni_wcae19.pdf Tue, 1 Jan 2019 00:00:00 -0000 Accelerators and Coherence: An SoC Perspective https://www.cs.columbia.edu/~paolo/pubs/giri_ieeemicro18.pdf Thu, 1 Nov 2018 00:00:00 -0000 NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators https://www.cs.columbia.edu/~paolo/pubs/giri_nocs18.pdf Mon, 1 Jan 2018 00:00:00 -0000 COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators https://www.cs.columbia.edu/~paolo/pubs/piccolboni_tecs17.pdf Fri, 1 Sep 2017 00:00:00 -0000 Broadening the Exploration of the Accelerator Design Space in Embedded Scalable Platforms https://www.cs.columbia.edu/~paolo/pubs/piccolboni_hpec17.pdf Sun, 1 Jan 2017 00:00:00 -0000 Scalable System-on-Chip Design https://www.cs.columbia.edu/~paolo/pubs/mantovani_thesis.pdf Sun, 1 Jan 2017 00:00:00 -0000 System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip https://www.cs.columbia.edu/~paolo/pubs/yoon_nocs17.pdf Sun, 1 Jan 2017 00:00:00 -0000 System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip https://www.cs.columbia.edu/~paolo/pubs/pilato_tcad17.pdf Sun, 1 Jan 2017 00:00:00 -0000 Handling Large Data Sets for High-Performance Embedded Applications in Heterogeneous Systems-on-Chip https://www.cs.columbia.edu/~paolo/pubs/mantovani_cases16.pdf Sat, 1 Oct 2016 00:00:00 -0000 An FPGA-based Infrastructure for Fine-grained DVFS Analysis in High-performance Embedded Systems https://www.cs.columbia.edu/~paolo/pubs/mantovani_dac16.pdf Wed, 1 Jun 2016 00:00:00 -0000 Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration https://www.cs.columbia.edu/~paolo/pubs/cota_ics16.pdf Wed, 1 Jun 2016 00:00:00 -0000 High-Level Synthesis of Accelerators in Embedded Scalable Platforms https://www.cs.columbia.edu/~paolo/pubs/mantovani_aspdac16.pdf Fri, 1 Jan 2016 00:00:00 -0000 On the Design of Scalable and Reusable Accelerators for Big Data Applications https://www.cs.columbia.edu/~paolo/pubs/pilato_cf16.pdf Fri, 1 Jan 2016 00:00:00 -0000 An Analysis of Accelerator Coupling in Heterogeneous Architectures https://www.cs.columbia.edu/~paolo/pubs/cota_dac15.pdf Mon, 1 Jun 2015 00:00:00 -0000 A synchronous latency-insensitive \RISC\ for better than worst-case design Thu, 1 Jan 2015 00:00:00 -0000 System-level memory optimization for high-level synthesis of component-based SoCs https://www.cs.columbia.edu/~paolo/pubs/pilato_codesisss2014.pdf Wed, 1 Oct 2014 00:00:00 -0000 Accelerator Memory Reuse in the Dark Silicon Era https://www.cs.columbia.edu/~paolo/pubs/cota_cal14.pdf Wed, 1 Jan 2014 00:00:00 -0000 A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI https://www.cs.columbia.edu/~paolo/pubs/sturcken_jssc12.pdf Wed, 1 Aug 2012 00:00:00 -0000 Coupling Latency-insensitivity with Variable-latency for Better Than Worst Case Design: A RISC Case Study https://www.cs.columbia.edu/~paolo/pubs/casu_glsvlsi11.pdf Sat, 1 Jan 2011 00:00:00 -0000