PCB LAYOUT AUTHORITY

SuperSpeed USB 3 Design Guide

2011-09-16T17:12:00.000-07:00

Introduction

SuperSpeed USB (USB 3.0) delivering data rates up to 5Gbps which is ten times faster than Hi-Speed USB (USB 2.0) with optimized power efficiency. At these high transmission rates, signal integrity issues become increasingly restrictive on PCB trace and cable lengths, and on design implementation and features. Poor signal quality can significantly impact system performance and reliability.

SuperSpeed (USB 3.0) ReDriver in Source Application
Superspeed is a dual channel (TX± and RX±), single lane USB3.0 redriver which use in source application such as Notebooks, Desktops, Docking Station, Backplane and Cabling. Each channel offers selectable equalization setting to compensate the different input trace loss. The block diagram below shows the application on notebook with docking.

SuperSpeed USB Layout Guideline

A. Decoupling capacitor of VDD

It is recommended to put 0.1uF decoupling capacitor at each VDD pin of IC. Below is a layout reference of decoupling capacitor placement on a board. Four decoupling capacitors circled in pink below are located next to the four VDD pins (pins 6, 10, 16 and 20) of the IC.

B. PCB layers

Recommend to use at least four layers PCB for SuperSpeed USB design. Every data signal trace should be routed entirely over the ground plane on an adjacent layer.

C. Routing around the USB connector

On the host design, USB receptacle connector is used on the PCB. For the Vbus trace, it’s suggested to insert a ferrite bead. For the shielding of USB connector (shielding of USB cables), AC isolation to the ground (such as proper value of inductor, instead of connecting the cable shield directly to the PCB ground plane).

For the SuperSpeed signal trace, the impedance should be maintained. Avoiding any stubs and removing any routing that cause signal discontinuity and severe EMC noise issue. Also, do not put any metal between all SuperSpeed signal pair pins on every layer when using receptacles with pins stabbing the PCB.

Crosstalk between the signal trace
There are 3 pairs of signal (SSTX± /SSRX±/ D±) for USB3.0 and these signal pairs will cause three typical type near-end crosstalk:

SSTX± to D± in RX mode
SSTX± to SSRX±
D± to SSRX± in TX mode

In order to minimize the crosstalk issue, the routing of the signal trace between SSTX±/ SSRX± and D± pairs should not be closed to each other.

SuperSpeed signal trace impedance

The layout around USB3.0 receptacle connector was routed as one or more large metal planes in specific layer (such as GND layer). In order to maintain the differential impedance of any SuperSpeed signal trace, make sure there is no metal between pins for any differential pair.

Stub on SuperSpeed trace

The pin on USB3.0 receptacle connector become an open stub if the SS signal trace pair is designed on the top layer which will cause the signal discontinuity issue.
D. Routing around the USB Controller

As high speed signal is sensitive to power signal, therefore the routing on power and ground design of USB controller need to be careful. Same as section (A), the decoupling cap is need for each power pin and it should be place as close as the power pad of USB controller. As USB controller contains both analog and digital section, analog power and digital power is required. In order to avoid the interference from the digital signal cause the malfunction on the analog circuit, the routing between analog power and digital signal trace should be placed as far as possible (including the signal trace). For the same voltage level’s analog power and digital power, a ferrite bead should be added in between for noise filtering.

Capacitive Touch Sensing Layout Guidelines --- > Part 1

2011-08-26T17:11:00.000-07:00

Capacitive Sensing

Capacitive sensing is the art of measuring a relatively very small variation of capacitance in a noisy environment.

To illustrate the principle of capacitive sensing we will use the typical simplest button implementation below but the same basic laws apply to more complex capacitive structures like sliders or wheels.

Figure shows cut view and top view of a typical capacitive button implementation. The sensor connected is a simple round copper area on top layer of the PCB. It is usually surrounded by ground for noise immunity (see § 2.3). For obvious reasons (design, isolation, robustness …) the PCB is stacked behind an overlay which usually consists in the housing of the complete system (notebook, TV, monitor, cell phone, etc) .

When no conductive object, like a finger, is close the sensor only sees an inherent capacity value CEnv created by its electrical field’s interaction with the environment, especially with ground areas. When a conductive object, like a finger, approaches the sensor the electrical field around the sensor will be modified and the total capacitance seen by the sensor increased by the finger capacitance CFinger.

The challenge of capacitive sensing is to detect this relatively small variation of CSensor (CFinger usually contributes for a few percent only) and differentiate it from environmental noise.
For this purpose, Capacitive products integrate an auto offset compensation mechanism which dynamically removes the CEnv component to extract and process CFinger only. CFinger, like any capacitance can be expressed in the formula below :

A is the common area between the two electrodes hence the common area between the finger and the sensor, typically 1cm2 for an adult finger.

d is the distance between the two electrodes hence the overlay thickness, typically 1-3mm. Overlay thickness is a compromise between mechanical/ESD robustness (the thicker the better) and power consumption (if too thick the sensitivity may need to be increased to be able to sense CFinger properly).

εo is the free space permittivity and is equal to 8.85 10e-12 F/m (constant)

εr is the dielectric hence overlay permittivity when finger is touching. Typical permittivity of some common overlay materials is given in table below. Higher εr allows reducing power consumption and/or increasing overlay thickness.

General Guidelines

The Chip

Strong ground connection on bottom exposed pad and ground pin

VANA, VDIG, VDD decoupling capacitors must be placed as close as possible to their associated pin
Integration capacitor Cint (see Figure 1) must be placed as close as possible to the chip and as far as possible from noisy signals

Connections to CAPx Sensors

0.2 mm trace width is recommended
Minimum 0.2mm clearance between CAPx traces, recommended 0.5mm or above. CAPx are sensed serially by the chip, non-sensed CAPx are internally tied to ground hence the clearance requirement.
Connections must be as short and direct as possible.
Preferably not to be routed on top layer to reduce potential finger coupling (must only be maximized on the CAP sensors, not on the traces)
Vias number must be reduced to the minimum.
CAPx signals should be routed as far as possible from noisy signals (LEDs, etc) and ideally on different layer or isolated by ground.
Noisy signals should not be routed below CAP sensors, if needed they must be isolated with ground layer.

Ground Considerations

0.5 to 3mm recommended clearance with CAP sensors. Low values maximize noise immunity while high ones minimize power consumption.
Below 0.5mm clearance is possible but increases significantly ground coupling hence requiring higher sensitivity setting and higher consumption.
Above 3mm clearance is possible but doesn’t reduce significantly ground coupling while reducing noise immunity.
Both top and bottom layers should be filled with hatched ground (typ. 20 %) to improve noise immunity while keeping DC cap low.

Capacitive Touch Sensing Layout Guidelines --- > Part 2

2011-08-26T17:10:00.000-07:00

Buttons

Introduction

Similarly to the mechanical buttons they intend to replace, touch buttons provide ON/OFF information i.e. respectively button touched or not touched by the finger. Each touch button is associated to its dedicated capacitive sensor.

Shape

Round is best while oval or square with round corners are also acceptable
Any other shape with acute angles is not recommended
Possibility to put a hole for reverse mount SMD LED in the middle (will reduce a little bit the sensor surface, can be compensated with higher sensitivity setting or bigger sensor)

Size

1cm diameter is recommended
Above 1.5cm diameter is useless due to finger tip surface
Below 1cm is possible at the expense of higher sensitivity setting hence higher consumption

Pitch

1.5cm is recommended as minimum
Below 1.5cm is possible but reduces user friendliness and improves the risk of side touch effects.

Examples

Slider

Introduction

Similarly to the mechanical sliders they intend to replace, touch sliders monitored by Semtech products provide of course the position information but also an ON/OFF state (i.e. respectively slider touched or not touched by the finger) as well as movement information (move-up or move-down).

Each touch slider is made by several capacitive sensors placed back to back on the PCB.
For good position resolution a slider usually requires interpolation (i.e. number of positions not limited to the number of sensors) which requires a layout ensuring that the finger always touches at least 2 sensors.

Shape

Slider

Straight shape is usually recommended for better user friendliness but other shapes are also possible
Mechanical guide on overlay improves user friendliness and robustness especially for exotic shapes

Sensors

Rectangular shape implies a lot of sensors to ensure interpolation (max half surface of finger per sensor)
Chevron shape is recommended as it provides good interpolation with relatively low number of sensors

Size

Slider

1cm recommended width
Above 1.5cm width is useless due to finger tip surface
Below 1cm width is possible at the expense of higher sensitivity setting hence higher consumption
The number of sensors depends on the length required and resolution targeted

Sensors

The smaller the better, typically below 0.5cm2 recommended (half surface of finger)
Bigger is possible but requires more complex layout (more interpolation required to ensure good resolution)

Pitch

The smaller the better to maximize interpolation
Ground clearance recommendations apply (see §2.3)

Example

Wheel

Introduction

A wheel can be seen as a slider with round shape, as such it has similar layout constraints and also provides position, ON/OFF, and movement information.
Each touch slider is made by several capacitive sensors placed back to back on the PCB.
Similarly to a slider, a wheel usually also requires interpolation but because of its “infinite length” nature, the position precision requirement is usually not as critical as for a slider. (movement detection may be more important)

Shape

Wheel

Round is usually recommended for better user friendliness but other shapes are also possible
Mechanical guide on overlay improves user friendliness and robustness especially for exotic shapes

Sensors

Rectangular shape implies a lot of sensors to ensure interpolation (max half surface of finger per sensor)
Chevron shape is the best but may be complex to design inside a wheel
Whirl shape is recommended as it gives a good compromise between the number of sensors required and layout complexity

Size

Wheel

1cm recommended width
Above 1.5cm width is useless due to finger tip surface
Below 1cm is possible at the expense of higher sensitivity setting hence higher consumption
The number of sensors depends on the wheel diameter required and the resolution targeted

Sensors

The smaller the better, typically 1cm2 recommended for whirl shape (see below)
Bigger is possible but requires more complex layout (more interpolation required)

Pitch

The smaller the better to maximize interpolation
Ground clearance recommendations apply (see §2.3)

Examples

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Touch Sensor PCB and Layout Guidelines Part 1

2011-04-14T16:12:00.000-07:00

Introduction

This note provides guidelines for the construction and the layout of different types of printed circuit boards (PCBs) for the implementation of the Touch Sensor Controller (TSC) capacitive sensors on substrate materials such as FR4, flexible PCBs, or ITO panels. Various substrate materials are available for different PCB design construction. Among the substrate materials currently available on the market, the FR4 is the most common. FR4 is a glass fiber epoxy laminate and PCBs can have one or several layers. Given a limited size of the touch module, the one-layer PCB implementation is not always possible, whereas the fourlayer and the two-layer PCB are more common. For applications requiring a very compact form factor, a flexible PCB can be used. The capacitive touch module on top of the display unit requires a transparent sensor electrode and traces which can be implemented using an Indium Tin Oxide (ITO) layer on a glass/plastic panel.

PCB Design Tips

The Noise Influence by Other Chips

In the touch module, it is recommended that only the Controller be mounted without any other chips because other chips can cause noise signals when controlling components such as LCD or Buzzer, etc.

Cross Coupling Capacitance

Noise signals can be generated between sensor input lines. If sensor lines are both very close to each other and placed in parallel, they can become noise sources to one another. In order to avoid this, it is recommended to design sensor input lines as shown in Figure 2. Enlarge line spacing and make parallel portions as short as possible.

Disposition of Data Lines and Sensor Input Lines

Figure 3 on the following page shows a problem caused by overlapping sensor input lines with data lines. For example, the capacitance generated by power lines with characteristics of consistent voltage output will not deeply affect sensor input lines. However, the capacitance generated by data lines fluctuating high and low voltage output will make sensor input lines unstable. Thus, the data lines in the front panel application should be placed closer to the connector in order to avoid undesirable influence on sensor input lines. Another important aspect in layout design is that sensor input lines should be placed on the opposite side of data output lines. Finally, since overlapping data lines with sensor touch pads will be worse than overlapping data lines with sensor input lines, it is recommended that sensor pads should be apart from data lines.
Several Controller Sensor Line Noise

If two Controller chips are mounted on the same PCB, they can be noise sources to each other. Therefore, in applications that are using two Controller chips, you need to design the touch pad area as shown in Figure 4.

LCD Control Signal Noise Issue

If the PCB, which includes LCD control lines, is located near a touch PCB, it could be a noise source even if it is not on the same PCB. Therefore, you need to design the PCB like Figure 5, which is less affected by LCD control signals. Any kind of pulse-type signals should be as far from the Controller as possible.

Charge Sharing

The sensitivity of the Controller will be decreased if the GND pattern is located close to the sensor input pads and lines because an electrical field generated by GND patterns will attenuate the strength of the capacitance generated by finger touch. This will decrease the sensitivity of the sensor input as shown in (a) of Figure 6 on the next page. Although the GND pattern is used to reduce the interference of the lines, make sure to keep the GND pattern a distance from the sensor input pads.

Mismatch in Each Sensor Input

For a normal AIC function, each sensor input capacitance of the system should be within 6pF.

Large Sensor Input Pad

If a touch pad is larger than 10 x 10mm, it will become very sensitive to external environmental change. As a result, input impedance during no-touch could be unstable. In order to avoid this situation, it is recommended to use a pad layout as shown in example (b) of Figure 7, which is exactly the same pad size as shown in example (a), but it eliminates the problem by reducing real surface area.

Touch Sensor PCB and Layout Guidelines Part 2

Touch Sensor PCB and Layout Guidelines Part 2

2011-04-13T03:38:00.000-07:00

PCB Layout Tips
This section provides guidelines on the design and layout related to several types of PCBs. See Figure 8.
The important task in PCB design is to draw sensor lines to reduce influence from internal and/or external noise sources. The types of noise sources and suggested design guidelines are described next.

Single Layer PCB Construction

A capacitive touch module can be designed in a singlelayer FR4 PCB of standard thickness (1.6mm). See Figure 9. The electrode and all the components are on the same side of the PCB. The other side of the PCB is attached to the overlay panel. The field senses through the PCB, the adhesive layer and the overlay panel to the finger. A one-layer PCB provides a less-costly solution compared to touch modules using more than one layer. However, the touch module using a one-layer PCB can only be implemented if there is enough area on the PCB for the
routing of the signals. Since the sensor electrode is placed at the bottom of the PCB, the sense field passes through the PCB and overlay panel before reaching the finger. In this case, the maximum overlay panel thickness is reduced due to the additional thickness of the PCB. The distance between the sensor electrode and touch sensor controller should be less than 5 inches to avoid excessive parasitic capacitance.
Single Layer PCB Design Rules

Layer 1 – Top layer design Tips

Only the bottom layer is used and the top layer is empty. Non-conductive adhesive is to be applied on the top layer to attach the PCB to the overlay pane

Layer 2 – Bottom Layer design Tips

Maximize the distance between one sensor electrode/ trace to the others in order to minimize crosstalk.
For good sensitivity it is recommended to have a 6 x 6mm sensor area. It is still possible to utilize a sensor area smaller than this, but with reduced sensitivity. However, it is recommended that the sensor size is not larger than 10 x 10mm. If the sensor size is increased beyond this size, sensitivity will not increase as much as expected but the susceptibility to noise will increase substantially.
The sensor signal traces do not need to be the same length. Input tuning capacitors are used to balance input capacitance between channels. However, if there is enough space on the PCB, balancing between the sensor input traces length can be done (sensor electrode size is uniform). In the latter case, only a reference tuning capacitor should be added in order to adjust all of the sensors’ impedance values to be in the center of the dynamic range.
Any clock, data or periodic signal should not be routed side by side with the sensor signal traces. As much as possible these signals should be routed perpendicular with respect to the sensor signals. If they have to run in parallel, route them on a different cross section area of the PCB.

Two Layer PCB construction

In the 2-layer PCB construction, the touch sensor controller and other components are placed at the bottom layer of the PCB. See Figure 10 on the next page. The touch sensor electrodes are placed on the top layer. The distance between sensor electrodes and the controller
should be less than 5 inches to avoid excessive parasitic capacitance.
The tuning capacitor of each sensor channel can be placed directly underneath the sensor electrode itself. However, it is recommended to place the touch sensor controller at the bottom layer area where there is no touch sensor electrode on top.

Two Layer PCB Design Tips Layer 1 – Top Layer

The sensor electrodes are on the top layer of the PCB (top side of the PCB is to be attached to the overlay panel). For good sensitivity it is recommended to have 6 x 6mm sensor area. It is still possible to utilize a sensor area smaller than this, but with reduced sensitivity. However, it is recommended that the sensor size is not larger than 10 x 10mm. If the sensor size is increased beyond this size, sensitivity will not increase as much as expected but susceptibility to noise will increase substantially.

The top layer can be used to route signal traces with the exception of sensor signal traces. As much as possible, sensor signal traces are to be routed at the bottom layer.

Layer 2 – Bottom Layer

The touch sensor controller and passive components are to be placed at the bottom layer.
Controller sensor signal traces are to be routed on the bottom layer. Sensor signal traces of a particular channel should not be routed underneath the sensor electrode of other channels.

Maximize the distance between one sensor electrode/trace to the other in order to minimize crosstalk.
Sensor signal traces do not need to be the same length. Input tuning capacitors are used to balance input capacitance between channels. However if space on the PCB allows, balancing sensor input traces length can be done (sensor electrodes size is uniform). In the latter case, only the reference tuning capacitor should be added in order to adjust all sensor impedance values to be in the center of the dynamic range.
Any clock, data or periodic signal should not be routed side by side with the sensor signal traces. As much as possible these signals should be routed perpendicular with respect to the sensor signals or they should be routed on different area of the PCB.
If clock, data, or any periodic signal traces should run in parallel proximity to sensor signal traces, they should be routed in a different layer and should not overlap. Keep the section where the signals run in parallel as short as possible.

Touch Sensor PCB and Layout Guidelines Part 1

Chip Antenna Mounting and Tuning Techniques

2010-09-17T21:01:00.000-07:00

Chip Antenna Mounting and Tuning Techniques

Motivation

Chip Antenna an efficient means of "connectivity" to modern portable electronic devices.
Miniature portable devices requires small antennas.
Can be internalized – i.e. "Concealed" within adevice.

Pros

Chip antennas are small, cheap and perform well.
Bulky external "whip" type antennas are a thing of the past.

Cons

Must be accounted for during initial circuit design stage
Interference, proximity de-tuning & degradation concerns.

Chip Antenna Characteristics - 1

Features Ag radiating element encapsulated in ceramic.
A quarter-wave ( λ/4 ) monopole system.
Works with GND plane to form dipole system.
Certain "GND clearance" space necessary.
Small form factor, thin profile & light weight

Chip Antenna Characteristics - 2

Omni-directional diversity.
Linear Polarization.
Mounting configuration flexibility.
Frequency range supported: 0.75 GHz thru 10 GHz.
WiFi, BT, WiMAX, UWB, GSM, CDMA, GPS etc.
Suitable for Pick & Place.

Antenna Selection Considerations - 1

Size
Frequency Band
Bandwidth
Polarization
Peak Gain
Ave Gain
Radiation Diversity Pattern

Antenna Selection Considerations - 2

Successful Antenna design means harmonious interaction of the "seven" parameters.
Additional considerations for diversity systems – e.g. MIMO
Overall performance is also system dependent.

Circuit Design Constraints

Size of the Circuit board.
Layout of the other board components.
Complexity of circuit.
Proper GND/No-GND dimensions.
"Tuned" Matching Circuitry
Shielding
Suitable Enclosure (material)

Layout Tips -1

Layout Tips - 2

Don't put any metal plates or batteries above or below the yellow region
Keep away any other metals from the GND clearance area.

Layout Tips - 3

Further examples of good antenna placement schemes
Example of antenna diversity (eliminate low/zero radiation poles)

Layout Tips - 4

Antenna placement schemes for Diversity systems

A. Antenna Matching Setup

B. Measuring Steps

One port calibration for NA Open-Short-Load
Mount probe onto populated PCB and connect to NA
Measure S11 of test board without antenna → S11_open → save trace to memory of NA
Measure S11 of test board with antenna (with enclosure if applicable) and 0 Ω R mounted → S11_antenna
Set NA to data/memory mode (S11_antenna/S11_open) → S11_match
Match the trace of S11_match to 50Ω (center of Smith chart at the desired frequency)

Conclusion – How to design

Determine the antenna location on board
Select the most appropriate antenna model
Implement antenna in conformance with design rules

HDMI Design Guidelines -- > Layer Stack-up, Differential Pair

2010-04-24T00:31:00.000-07:00

Introduction

This article presents design guidelines for helping users of HDMI mux-repeaters to maximise the device’s full performance through careful printed circuit board (PCB) design. We’ll explain important concepts of some main aspects of high-speed PCB design with recommendations.
This discussion will cover layer stack, differential traces, controlled impedance transmission
lines, discontinuities, routing guidelines, reference planes, vias and decoupling capacitors.

Layer stack

The pin-out of a HDMI mux-repeater is tailored for the design in HDTV receiver circuits (see Picture below). Each side of the package provides a HDMI port, featuring four differential TMDS signal pairs, thus resulting in three input and one output port. The remaining signals comprise the supply rails, Vcc and ground, and lower speed signals such as the I2C interface, Hotplug-detect and the mux-selector pins.

FIG 1. The device pin-out is tailored for HDTV receiver applications

A minimum of four layers are required to accomplish a low EMI PCB design (see Figure 2). Layer stacking should be in the following order (top-to-bottom): TMDS signal layer, ground plane, power plane and control signal layer.

FIG 2. Recommended 4- or 6- layer stack for a receiver PCB design

Routing the high-speed TMDS traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects from the HDMI connectors to the repeater inputs, and from the repeater output to the subsequent receiver circuit.
Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance.
Routing the slower speed control signals on the bottom layer allows for greater flexibility as
these signal links usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power / ground
plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

Differential Traces

HDMI uses transition minimised differential signalling (TMDS) for transmitting high-speed serial data. Differential signalling offers significant benefits over single ended signalling.

In single-ended systems, current flows from the source to the load through one conductor and returns via a ground plane or wire. The transversal electromagnetic wave (TEM), created by the current flow, can freely radiate to the outside environment causing severe electromagnetic interference (EMI).

FIG 3. TEM wave radiation from the large fringing fields around a single conductor and the small fringing fields outside the closely coupled conductor loop of a differential signal pair.

Also noise from external sources induced into the conductor is unavoidably amplified by the receiver, thus compromising signal integrity.

Differential signalling instead uses two conductors, one for the forward, the other one for the return current to flow. Thus, when closely coupled, the currents in the two conductors are of equal amplitude but opposite polarity and their magnetic fields cancel.

The TEM waves of the two conductors, now being robbed of their magnetic fields, cannot radiate
into the environment. Only the far smaller fringing fields outside the conductor loop can radiate, thus yielding significantly lower EMI (see Figure 3).

Another benefit of close electric coupling is that external noise induced into both conductors
equally appears as common- mode noise at the receiver input. Receivers with differential inputs are sensitive to signal differences only, but immune to common-mode signals. The receiver, therefore, rejects common- mode noise and signal integrity is maintained.

To make differential signalling work on a PCB, the spacing of the two traces of a differential
signal pair must be kept the same across the entire length of the trace. Otherwise, variations in
the spacing cause imbalances in the field coupling, thus, reducing the cancellation of the magnetic
fields “ leading to increased EMI. In addition to larger EMI, changes in conductor spacing cause the differential impedance of the signal pair to change, thus creating discontinuities in an
impedance-controlled transmission system, which leads to signal reflections compromising
signal integrity.

Besides consistent spacing, both conductors must be of equal electrical length to ensure their signals reach the receiver inputs at the same time. Figure 4 shows the “+” and the “”” signals of a differential pair during logic state changes for traces of equal and different length.

FIG 4. Traces of different electrical length cause phase shifts between signal, generating difference signals that cause serious EMI problems.

For traces of equal length both signals are equal and opposite. Therefore, their sum must add to zero. If the traces differ in electrical length, the signal on the shorter trace changes its state earlier than the one on the longer trace. During that time both traces drive currents into the same direction. Because the longer trace, which is supposed to act as return path, continues to drive current, the current of the “early” driving, shorter trace must find its return path via a reference plane (power or ground).

When adding both signals the sum signal diverts from the zero level during the transition phase. At high frequency these different signals appear as sharp transients of considerable magnitude, showing up on the ground plane, causing serious EMI problems.

Note that the width of the “noise” pulses is equal to the phase shift between the two signals, and can be translated into a time difference for a given frequency. This time difference, also known as intra-pair skew, is specified by HDMI for a receiver with 0.4 TBIT for a TMDS clock rate of 225 MHz, which translates to 178 ps maximum. For an HDMI transmitter the specification calls for 0.15 TBIT for a TMDS clock rate of 225 MHz, which translates to 66 ps maximum.

Because pixel generation requires the synchronous transmission of four differential TMDS signal pairs, (3 data + 1 clock), it must reach the receiver at the same time. Ideally, all four signal pairs should be of equal electrical length to ensure zero time difference. HDMI, however, allows
for a maximum inter-pair skew, the time difference between signal pairs, for a receiver of 0.2 TCHARACTER + 1.78 ns, yielding a total of 2.67 ns for a TMDS clock of 225 MHz. For an HDMI transmitter, the specification calls for 0.2 TCHARACTER resulting in 888ps.

HDMI Design Guidelines -- > Control Impedance, Discontinuities

2010-04-24T00:20:00.000-07:00

Controlled Impedance Transmission Lines

Controlled impedance traces are used to match the differential impedance of the transmission medium, e.g., cables, and the termination resistors. Differential impedance is determined by the physical geometries of the signal pair traces, their relation to the adjacent ground plane and the PCB dielectric. These geometries must be maintained across the entire trace length.

A more accurate, and in the long term cheaper approach, is to use a 2D or better field solver. This is a software tool that solves Maxwell’s Equations and calculates the electric and magnetic fields for an arbitrary cross-section transmission line.

From these, it also calculates the electrical performance terms, such as characteristic impedance, signal speed, crosstalk and differential impedance. Some field solvers can also calculate the current distributions inside conductors. The advantage a 2D field solver wields over an approximation is the flexibility to consider almost any arbitrary cross-section geometry. In addition to the first-order terms such as line width, dielectric thickness and dielectric constant, second- order terms such as trace thickness, solder mask and trace etch back can be considered.

Discontinuities

Discontinuities are locations in the signal path where the differential trace impedance deviates
from its specified value (of 100 15 per cent for HDMI), and assumes either higher or lower impedance values.

Discontinuities cause signal reflections due to impedance mismatch compromising signal integrity. These are primarily the result of changes in the effective trace width or in the line-to-line spacing caused either by unavoidable transitions in the trace geometries along the signal path, or by poor routing of the signal traces.

Potential locations for discontinuities are:

where the solder pads of the HDMI connector meet the signal traces
where signal traces meet vias, component pads of resistors,or IC-pins
90 degrees bends in signal traces
where a signal pair is split to route around an object

Discontinuities are detected during differential impedance, TDR, tests. A TDR, (time-domain reflectometer), is an electronic instrument used to characterise and locate faults in metallic conductors. A TDR transmits a fast rise time pulse along the conductor. If the conductor is of uniform impedance nd properly terminated, the entire transmitted pulse will be absorbed in the far-end termination and no signal will be reflected back to the TDR. But where impedance discontinuities exist, each discontinuity will create an echo that is reflected back to the reflectometer (hence the name). Increases in the impedance create an echo that reinforces the original pulse while decreases in the impedance create an echo that opposes the original pulse.

The resulting reflected pulse that is measured at the output/ input to the TDR is displayed or plotted as a function of time and, because the speed of signal propagation is relatively constant for a given transmission medium, can be read as a function of trace length.

The goal in PCB design must be to minimise discontinuities wherever possible, thus eliminating reflections and maintaining signal integrity. Following a minimum set of routing guidelines helps avoiding unnecessary discontinuities. The remaining, unavoidable discontinuities should be lumped, that is their areas should be kept small and placed together as close as possible.

The idea is to concentrate the points of reflection to a certain area rather than having them distributed across the entire signal path.

FIG 5. TDR display revealing the locations of discontinuities

The magnitude of the discontinuities seen using a TDR are directly effected by the edge rate of the pulse used by the TDR. The faster the TDR edge the more discontinuities will show up, and the larger the impedance spike will appear. With the HDMI specification they have defined the edge rate that is to be used to be 200ps. Figure 5 illustrates this point. The lower line on the graph was taken using a 30ps edge rate and the upper line was taken with a 200pf filter. The discontinuities created by the SMA launch onto the TPA board that show up on the low line are completely invisible when the 200ps edge rate filter is applied.

Chip Antenna Layout Considerations for 802.11 Applications

2010-03-07T15:05:00.000-08:00

Chip Antenna matching and radiation pattern performance can be dramatically affected by the design/layout of a circuit. Antenna mounting, the antenna’s position relative to circuit mismatches, the antenna position relative to adjacent components and ground planes all can affect antenna performance. Thus design engineers must use care when creating a circuit layout which includes an antenna.

Because of the effect of these subtleties, antennas mounted in a specific application are likely to exhibit performance that is different from the published specification. The matching components shown on the test board provide a good starting point for determining the necessary components in a given application. Be sure to keep the antenna free from surrounding ground plane(s), as it is not designed to work against a ground plane or with one in its immediate proximity. Failure to follow this guideline could significantly alter the radiation pattern characteristics.

When determining the matching components needed in an individual application, begin by measuring the return loss (S11) into the matching component(s) feeding the antenna in the same configuration that is planned for the final circuit. Vary the value of the matching components until the return loss dip is centered on the specified operating band.

Some design guidelines are:

The microstripline feeding the antenna is to be considered part of the antenna resonance system.
Connect the edge portion of ground planes (the ground plane surrounding the microstripline feeding the antenna to the bottom ground plane layer) with many through holes (vias). These through holes minimize the electric fields which are generated at the edge, minimizing the effects on the antenna performance.
The length of the microstripline feeding the antenna, and the length and width of the ground plane surrounding that microstripline, together will determine whether the system (antenna, matching and ground plane) acts like a dipole or a monopole. If the ground is about 3-4 cm long and about 1-2 cm wide, then the system will act as a dipole system. If the ground area is large enough, the system will operate like a monopole antenna.
For best results, the chip antenna needs to be removed from surrounding ground planes by at least the amount shown by the following (assuming horizontal mounting as shown below)
a.) More than 2 mm from the shorter edges of the antenna, when mounted as shown on page 3. More than 1 mm from the shorter end of the antenna that is closest to the ground plane, when mounted as shown on page 4.
b.) More than 4 mm from the longer edge of the antenna (the antenna is mounted on the edge of a PCB, so there is no ground plane adjacent to one of the longer sides) The performance greatly deteriorates if the dimensions are less than the minimum dimensions
mentioned above in 4.a and 4.b although the antenna still works.
The feedline that feeds the microstripline (whether coaxial or stripline) should be perpendicular to the microstripline to prevent it from becoming part of the resonance system. (If a feeder becomes an antenna, it leads to deterioration of the desired performance). See the below figure for a figure of this arrangement.

TYPICAL HORIZONTAL ORIENTATION ROUTING

The matching component may be slightly different than that shown depending on distance to ground plane, dielectric constant of PCB, and PCB material thickness.

TYPICAL HORIZONTAL ORIENTATION ROUTING (ALTERNATE)

(Matching circuit and component values will be different, depending on PCB layout) *Line width should be designed to match 50. characteristic impedance, depending on PCB material and thickness.

TYPICAL VERTICAL ORIENTATION ROUTING

(a) Without Matching Circuits (Moderate Bandwidth)

(b) With Matching Circuits (Wide Bandwidth)

*Line width should be designed to match 50. characteristic impedance, depending on PCB material and thickness.

(a) Return Loss Without Matching Circuits

(b) Return Loss With Matching Circuits

Webinar - HyperLynx Analog On-Demand Web Seminar Session 2

2010-01-25T08:47:00.000-08:00

HyperLynx Analog On-Demand Web Seminar Session 2

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