Programmer notes

Auto size page in ExtJS grid.

2017-11-21T22:03:00.004+01:00

Yesterday I was looking for solution to auto size page in grid, but have found not usable solutions and also for old ExtJS version. Then I've tried itself and got this:

You can declare simple two listener in your grid

Ext.define('app.view.main.List', {
    extend: 'Ext.grid.Panel',

    controller: 'list',

...

    listeners: {
     afterrender: 'onAfterRender',
     resize: 'onGridResize'
    }
});

and implement it in controller:

Ext.define('app.view.main.ListController', {
    extend : 'Ext.app.ViewController',
    alias : 'controller.list',

    onAfterRender: function(grid) {
        this.calcPageSize(grid);
    },
 
    onGridResize: function(grid) {
        this.calcPageSize(grid);
    },
 
    calcPageSize(grid) {
        var me = this,
            bodyHeight = grid.body.dom.clientHeight,
            hasLines = grid.rowLines,
            view = grid.getView(),
            row = view.getRow(0),
            // if there is now rows - assume row height 33 pixel
            rowHeight = row ? row.offsetHeight + (hasLines ? 1 : 0) : 33,
            store = grid.getStore(),
            currPageSize = store.getPageSize(),
            newPageSize = Math.floor(bodyHeight/rowHeight);
        if (bodyHeight == 0) {
            Ext.defer(function() {
                me.onGridResize(grid);
            }, 200);
            return;
        }
        if (currPageSize != newPageSize) {
            store.setPageSize(newPageSize);
            // if store loaded - reload them
            if (store.isLoaded()) {
                store.load();
            }
        }
    },
 
...

});

or you can create your own class:

Ext.define('Ext.ux.grid.AutoSizeGrid', {
    extend: 'Ext.grid.Panel',
    xtype: 'autoPageSize',

    initComponent: function() {
        var me = this;
        me.mon(grid, 'resize', me.onGridResize, me);
        me.mon(grid, 'afterrender', me.onAfterRender, me);
        me.callParent(arguments);
    },

    onAfterRender: function(grid) {
        this.calcPageSize(grid);
    },
 
    onGridResize: function(grid) {
        this.calcPageSize(grid);
    },
 
    calcPageSize(grid) {
        var me = this,
            bodyHeight = grid.body.dom.clientHeight,
            hasLines = grid.rowLines,
            view = grid.getView(),
            row = view.getRow(0),
            // if there is now rows - assume row height 33 pixel
            rowHeight = row ? row.offsetHeight + (hasLines ? 1 : 0) : 33,
            store = grid.getStore(),
            currPageSize = store.getPageSize(),
            newPageSize = Math.floor(bodyHeight/rowHeight);
        if (bodyHeight == 0) {
            Ext.defer(function() {
                me.onGridResize(grid);
            }, 200);
            return;
        }
        if (currPageSize != newPageSize) {
            store.setPageSize(newPageSize);
            // if store loaded - reload them
            if (store.isLoaded()) {
                store.load();
            }
        }
    }
});

You can see the example here https://fiddle.sencha.com/#view/editor&fiddle/29vf
Enjoy!

Disable hibernate query cache

2017-11-21T15:56:00.000+01:00

Do you have a problem, that hibernate returns by calling stored procedure with the same parameters the same result also if you put id column is native query?

For example you have stored procedure which delivers last modified date of recent change for some object:

CREATE PROCEDURE GET_LAST_MODIFIED_DATE
(
    @objectId [bigint]
)
AS
BEGIN
    SET NOCOUNT ON

    SELECT
        a.id,
        top(1) a.lastModified
    FROM
        Table a
    WHERE
        a.deleted = 0
        AND a.objectId = @objectId
    ORDER BY
        a.lastModified DESC
END
GO

Solution is simple. You can change cache mode for single query:

    String sql = "exec dbo.GET_LAST_MODIFIED_DATE @objectId=123";
    Query query = entityManager.createNativeQuery(sql);
    query.setHint("javax.persistence.cache.storeMode", "REFRESH");

Connect clock signal to FPGA output pad

2012-01-20T05:56:00.000+01:00

So now i know how to connect some internal clock signal to the output pin. Direct connection is impossible because the only dedicated clock signal buses can be connected only to the clock input pins of the internal flip-flops.
The internal clock signal can be connected to the output pin or to non clock signal with the following construct:

Here is the VHDL sample:

oddr2_0 : ODDR2
    port map(
        Q           => Output_clk_o,
        C0          => Output_clk_i,
        C1          => Output_clk_i,
        D0          => '0',
        D1          => '1'
    );

obuf_0 : OBUF
    generic map (
        CAPACITANCE => "NORMAL",
        IOSTANDARD  => "LVCMOS33",
        SLEW        => "FAST"
    )
    port map (
        O => Output_clk,
        I => Output_clk_o
    );

Where

Output_clk_i is some internal input clock signal
Output_clk_o is intermediate wire between ODDR2 and OBUF
Output_clk is output clock signal, which can be connected to the non clock input or to the output pin.

Same can be made for differential output clock:

Here is the VHDL sample:

oddr2_0 : ODDR2
    port map(
        Q           => Output_clk_o,
        C0          => Output_clk_i,
        C1          => Output_clk_i,
        D0          => '0',
        D1          => '1'
    );

obuf_0 : OBUFDS
    generic map (
        CAPACITANCE => "NORMAL",
        IOSTANDARD  => "LVDS_33",
        SLEW        => "FAST"
    )
    port map (
        O => Output_clk,
        OB => Output_clk_n,
        I => Output_clk_o
    );

Where

Output_clk_i is some internal input clock signal
Output_clk_o is intermediate wire between ODDR2 and OBUF
Output_clk is output clock signal, which can be connected to the non clock input or to the output pin.
Output_clk_n is negative output clock signal, which can be connected to the non clock input or to the output pin.

In the VHDL file in entity block you must define this signals as clock for simulation:

attribute SIGIS : string;
attribute SIGIS of Output_clk         : signal is "CLK";
attribute SIGIS of Output_clk_n       : signal is "CLK";

If you use this code for embedded Xilinx MicroBlaze you must define this signal in MPD file as follow:

PORT Output_clk      = "", DIR = O, SIGIS = CLK
PORT Output_clk_n      = "", DIR = O, SIGIS = CLK

This information is get from Spartan-6 FPGA Clocking Resources on page 112.

Usefull user constraints for axi_ethernet

2012-01-15T17:59:00.000+01:00

If you try to get hardware design using axi_ethernet core you may to need this recommended constraints:
~~AXI_Ethernet v3.00.a - Recommended Constraints for AXI-based Ethernet Systems~~

The above link doesn't exists any more :( Here is carbon copy of them:

This Answer Record provides links to zip files with the recommended constraints for the AXI_Ethernet v3.00.a core logic. The constraints for the Ethernet pins themselves are not included. These constraints have been tested on specific development boards and some attributes such as IDELAY, IDELAYCTRL, and GTP/GTX locations can change in custom implementations.

Designs with AVB Endpoint Enabled (C_AVB = 1)

Virtex-6 Hard TEMAC Implementations

Virtex-6 Hard TEMAC MII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_hard_mii_avb.zip
Virtex-6 Hard TEMAC GMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_hard_gmii_avb.zip
Virtex-6 Hard TEMAC RGMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_hard_rgmii_avb.zip
Virtex-6 Hard TEMAC SGMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_hard_sgmii_avb.zip
Virtex-6 Hard TEMAC 1000 Base-X -http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_hard_basex_avb.zip

Virtex-6 Soft TEMAC Implementations

Virtex-6 Soft TEMAC MII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_soft_mii_avb.zip
Virtex-6 Soft TEMAC GMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_soft_gmii_avb.zip
Virtex-6 Soft TEMAC RGMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_soft_rgmii_avb.zip
Virtex-6 Soft TEMAC SGMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_soft_sgmii_avb.zip
Virtex-6 Soft TEMAC 1000 Base-X - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_soft_base_x_avb.zip

Spartan-6 Soft TEMAC Implementations

Spartan-6 Soft TEMAC MII -http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_s6_soft_mii_avb.zip
Spartan-6 Soft TEMAC GMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_s6_soft_gmii_avb.zip
Spartan-6 Soft TEMAC RGMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_s6_soft_rgmii_avb.zip
Spartan-6 Soft TEMAC SGMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_s6_soft_sgmii_avb.zip
Spartan-6 Soft TEMAC 1000 Base-X - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_s6_soft_base_x_avb.zip

Designs without AVB Endpoint Enabled (C_AVB = 0)

Virtex-6 Hard TEMAC Implementations

Virtex-6 Hard TEMAC MII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_hard_mii.zip
Virtex-6 Hard TEMAC GMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_hard_gmii.zip
Virtex-6 Hard TEMAC RGMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_hard_rgmii.zip
Virtex-6 Hard TEMAC SGMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_hard_sgmii.zip
Virtex-6 Hard TEMAC 1000 Base-X - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_hard_basex.zip

Virtex-6 Soft TEMAC Implementations

Virtex-6 Soft TEMAC MII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_soft_mii.zip
Virtex-6 Soft TEMAC GMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_soft_gmii.zip
Virtex-6 Soft TEMAC RGMII -http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_soft_rgmii.zip
Virtex-6 Soft TEMAC SGMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_soft_sgmii.zip
Virtex-6 Soft TEMAC 1000 Base-X - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_v6_soft_basex.zip

Spartan-6 Soft TEMAC Implementations

Spartan-6 Soft TEMAC MII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_s6_soft_mii.zip
Spartan-6 Soft TEMAC GMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_s6_soft_gmii.zip
Spartan-6 Soft TEMAC RGMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_s6_soft_rgmii.zip
Spartan-6 Soft TEMAC SGMII - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_s6_soft_sgmii.zip
Spartan-6 Soft TEMAC 1000 Base-X - http://www.xilinx.com/txpatches/pub/applications/misc/ar42753_axieth300a_s6_soft_base_x.zip

My first experiments with Xilinx's FPGA

2011-12-28T10:03:00.005+01:00

Ok, I've decided to note my breakthrough with FPGA.
Now I describe short what you need, if EDK say you that it can't find site for some PLL in clock generator you create in design. You must write in the constraint file (usually data\system.ucf) following code:



INST "clock_generator_0/clock_generator_0/PLL0_INST/Using_PLL_ADV.PLL_ADV_inst" LOC = "PLL_ADV_X0Y1";

The appropriate site you can find in the Spartan-6 FPGA Clocking Resources on the page 93 in table 3-1:

Table 3-1: PLLs with Direct Connections to BUFPLL

BUFPLL Location	Bank	Valid PLL Locations by Device Type
BUFPLL Location	Bank	LX4, LX9, LX16, LX25/LX25T	LX45/LX45T	LX75/LX75T LX100/LX100T LX150/LX150T
BUFPLL_X1Y5 BUFPLL_X1Y4 BUFPLL_MCB_X1Y9	0	PLL_ADV_X0Y1 PLL_ADV_X0Y0	PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y1 PLL_ADV_X0Y0	PLL_ADV_X0Y5 PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y0
BUFPLL_X2Y2 BUFPLL_X2Y3 BUFPLL_MCB_X2Y5	1 (5)	PLL_ADV_X0Y1 PLL_ADV_X0Y0	PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y1 PLL_ADV_X0Y0	PLL_ADV_X0Y5 PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y0
BUFPLL_X1Y0 BUFPLL_X1Y1 BUFPLL_MCB_X1Y5	2	PLL_ADV_X0Y1 PLL_ADV_X0Y0	PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y1 PLL_ADV_X0Y0	PLL_ADV_X0Y5 PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y0
BUFPLL_X0Y2 BUFPLL_X0Y3 BUFPLL_MCB_X0Y5	3 (4)	PLL_ADV_X0Y1 PLL_ADV_X0Y0	PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y1 PLL_ADV_X0Y0	PLL_ADV_X0Y5 PLL_ADV_X0Y3 PLL_ADV_X0Y2 PLL_ADV_X0Y0

Eclipse J2EE & IAM - NullPointerException

2010-03-26T10:13:00.006+01:00

An internal error occurred during: "Updating classpath container: ...".

java.lang.NullPointerException
    at org.eclipse.wst.common.componentcore.internal.resources.
        VirtualResource.removeLink(VirtualResource.java:300)
    at org.eclipse.iam.wtp.core.internal.war.MavenWarClasspathListener.
        addOverlayWarFolders(MavenWarClasspathListener.java:89)
    at org.eclipse.iam.wtp.core.internal.war.MavenWarClasspathListener.
        resolved(MavenWarClasspathListener.java:57)

You've seen this error in Eclipse? This error occurs on the Eclipse J2EE in conjunction with Eclipse IAM. If you are writing a web application using maven as the build system - your welcome.
On the Internet I found a temporary solution - every time I load the eclipse and it compiles all projects, I should in web applications delete the folder .settings. However, it is not easy and may not be long-term solution.
After a long search for a solution was found.
In the file .project is necessary to add in a tag natures:

<nature>org.eclipse.wst.common.modulecore.ModuleCoreNature</nature>

Furthermore, in the folder .settings need to create or modify file org.eclipse.wst.common.component. It should contain:

<?xml version="1.0" encoding="UTF-8"?>
<project-modules id="moduleCoreId" project-version="1.5.0">
    <wb-module deploy-name="your-webapp">
         <module-type module-type-id="jst.web">
             <version>2.4</version>
             <property name="context-root" value="your-webapp"/>
             <property name="java-output-path" value="/target/classes/"/>
         </module-type>
         <wb-resource deploy-path="/WEB-INF/classes" source-path="/target/classes"/>
     </wb-module>
</project-modules>

"your-webapp" should be replaced by the name of your project.

I advise you add this file to the version control system.

Oracle WebCenter Interaction 10.3.0 on Mac OS X

2010-03-25T23:04:00.002+01:00

For a week I am a happy owner of MacBook Pro with 8 GB of memory. And since I'm working on a corporate portal for a large company, I needed to install the development environment and the portal directly to Mac OS X. However, the Oracle WebCenter Interaction 10.3.0 distribution does not exist for Mac OS X, I tried to install a version for Linux.
But the distribution of the portal does not install automatically. And I had to unpack it manually.
Since Mac OS X is built on Darwin - clone of FreeBSD, I thought that I could run binary programs for Linux under Mac OS X. But soon it became clear that a Linux program can not run straight under the Mac.
On a Mac there is no Linux emulator or program brandelf, which allows you to run Linux (and Solaris, SCO etc) software on FreeBSD.
Thus, I had the basic portal services installed on Windows 7 x64 in a virtual machine Fusion. In Windows, I installed Api Service, Automation Server, Content Upload, Document Repository, Publisher and Search Server.
Portal itself runs in the Java Virtual Mashine, but to communicate with the portal search server uses a native library. For communication with the search server I had to create RMI bridge between the portal and search server. The portal started running JVM installed on my Mac excelent. Moreover, because now the portal is left native libraries, it runs the same way on 32-bit and 64-bit JVMs.
I must however be noted that an RMI Bridge slowing the search server and can be used only for development. Soon I'll talk about installing programs PTSpy on a Mac.