Beyond Intel Labs’ past breakthrough in intelligent clock gating, ultra low voltage, and low leakage circuits, we have been solving a growing dynamic variation problem. Variations caused by thermal fluctuations, voltage drooping, and transistor aging demand conservative circuit operating guardbands. Processors run slower and consume higher power as a result. Our researchers have invented resilient techniques and deployed novel monitoring and error-correcting circuits that allow the removal of all guardbands. We have implemented a complete processor using these resilient circuits and demonstrated it at 2009 Fall IDF. Our measurements on this functioning processor show a solid 37% power reduction.

Our power architecture research aims at reducing the mismatch between power delivery and power demand of the platform. Peak high power requirement constrains design of battery and power adaptor (BRIC). It forces compromises to ensure they can supply up to certain wattage when needed but still often fall short of true peak demand such as turbo mode. Intel Labs’ researchers came up with a novel super capacitor augmented power architecture to address this problem. Super capacitor is a dense storage capacitor added to power delivery architecture to provide temporary power during short, peak demand cycles. It decouples CPU from battery/BRIC and allows CPU to achieve full turbo mode. It also provides much flexibility in battery design.

While circuit techniques and power architecture provide interesting contributions to energy efficiency, we found compelling opportunities in platform level power optimization. For example, we explore the possibility of having a low-power network agent offload insignificant activities and provide more opportunities to put the main platform to “sleep”. We found that this innovation has the potential to save billions of dollar energy cost yearly.

Our researchers further took a holistic approach in managing power across the platform. First, we focus on aligning and coordinating platform activities to create longer idle periods where we can aggressively reduce power. Second, we explore fine grain control over subsystems across the platform. This enables us to quickly and easily power down elements of the platform not in immediate use and not critical to the compute task at hand. Finally we make sure that software and hardware collaborate seamlessly in realizing fine-grain power saving potential. Our research show that we can get to 50X idle power reduction on Moorestown platform compared with a previous generation platform.

In summary, our research enable running circuits at 37% less active power, reducing platform idle power by 50X, saving billions of dollars in energy cost and providing much more flexibility in future battery design and energy density innovation. It powers the energy efficiency revolution and plants the seeds for many more excitements to come.

Imagine these scenarios: (a) At a coffee shop, you are wanting to share pictures on your home PC with a friend, (b) Online movie distribution service downloads movies, on-demand, to your Home PC, or (c) Enterprise or personal online PC manageability Service Provider updating your PC with latest security patches responding to a PC malware outbreak.

In all these cases, and more, current technology requires the PC to be operating in their “full energy” consumption mode, 24 X 7. A PC, today, continues to consume its maximum power (say, 150W) even when it is doing nothing! That’s just one PC - now, imagine millions of PCs and other Internet connected devices that are consuming close to their maximum energy when doing nothing!!! It quickly assumes a rather serious energy crisis in scale when scaled across a country, or worse, the world. Personally, this feels very wasteful, and on a global scale, this has caught the attention of various regulatory bodies (Climate Savers Computing and Energy Star). Could we get a little smarter in enforcing “workload proportional” PC energy consumption?

Yes, we can. Our Network Proxy technology, now being standardized at Ecma TC32-TG21, allows PCs to maintain Internet connectivity using an ultra low power Proxy (say, 0.5W). The Network Proxy drastically reduces PC energy footprint (say, less than 1/100th of its max energy usage), while making PC “Always Available” to the network and server applications, and waking PC, when more processing is needed. The PC intelligently wakes up, services the request, and goes back to Sleep automatically. And, it does so reliably and predictably, maintaining the same high-quality user experience.

I am delighted to share insights into this technology at the Intel IDF ‘09 Session RESS005 on “Reliable Low-Power Network Proxy for ENERGY STAR*”. We are also excited to share with you our ongoing research proxy prototypes for wireless and remote access at our Demo Booth #484, located at the center of the IDF Technology Showcase, at the Intel Labs pavilion.

Please join us in fueling an energy conscious PC growth - the next Billion Internet devices should not require spending billions firing new power plants.

FRI is interested in virtual worlds because the fashion industry, which creates soft consumer goods, does not typically use the 3D computer aided design (CAD) tools used in the durable goods industry. However, since clothing and accessories are 3D objects with complex shapes, traditional 2D sketches cannot fully convey the exact shapes and sizes that the designer intends for the product. So, when a clothing manufacturer attempts to turn a set of 2D drawings into a 3D object, errors often occur, and it usually takes several attempts before the correct design is produced. Each attempt results in unusable physical samples which cannot be sold (and which are destroyed to prevent poor quality goods from making it into the marketplace).

3D virtual worlds offer a platform for designing apparel with a level of accuracy that is far better than traditional methods, without the cost or complexity of 3D CAD tools. Using VWs for fashion design can significantly reduce waste by eliminating the cost and materials needed to create and re-create prototypes until they are correct. They also allow the designer and manufacturer to review designs together in a virtual space over great distances. Given that many manufacturers are in countries where significant virtual world investment has already occurred (such as China), much of the basic capabilities are already in place.

Through this new collaboration FRI is providing visually compelling, highly detailed content (shown in this video) to aid in Intel’s 3D Internet research. The new 3D content derives from FRI’s “Shengri-La” project and will include highly visual landscapes, structures, and a series of interactive art and fashion exhibits.

To explore these technical challenges, this content is being added to Supercomputing 2009’s ScienceSim, a virtual world created for education and scientific collaboration. Intel is collaborating with SC’09 to develop the hardware and simulation infrastructure behind this world. Based on the OpenSim VW simulator, ScienceSim also seeks to foster open-source innovation as a means to accelerate the proliferation of VW technology. The complex models provided by FRI will allow us to find new ways to push the state of the art for VWs such as ScienceSim in terms of 3D content creation, sharing, and quality.

So what does fashion have to do with science? Well, in addition to researching ways to make the underlying VW simulators capable of rendering more visually appealing content, we also plan to use these experimental regions as a forum to educate people on topics such as the material science behind fashion and the relationship of these complex materials to design and development. How do you make so many kinds of leather with such different properties? How do you develop synthetic fabrics? In fact, there are many aspects to the science of fashion, and virtual design is just one of the latest developments.

To learn a bit more, read this blog by Shenlei Winker, CEO of FRI.

For those of you that remember the late 80’s music scene, you may already know the inspiration for this parody. If not — check it out as well.

VoIP is characterized by small-size, periodic packets and supporting a large number of simultaneous VoIP users in a WiMAX network is a challenge. To understand why, let’s review the IEEE 802.16e WiMAX frame structure, shown in Fig 1.

WiMAX frames comprises of the downlink (DL) and uplink (UL) subframe. The DL subframe contains the MAP region and the DL traffic region. The MAP region describes the data allocations and signals the position, size and modulation and coding scheme (MCS) for each user scheduled in the DL and UL traffic regions. The size of the MAP is proportional to the number of users in the DL and UL region. The small size of VoIP packets allows scheduling a large number of VoIP users in each frame and proportionally the size of the MAP region increases. Analysis shows that for VoIP traffic up to 40 to 45% of the DL subframe is occupied by the MAP. As shown in Fig 2a, the scheduling mechanism in WiMAX requires that MAP overhead for the user is repeated in every frame in which the user is scheduled. Hence, reducing the MAP overhead is necessary to enable scheduling additional VoIP users and to increase the network capacity to handle VoIP traffic.

Persistent scheduling is a mechanism adopted in IEEE 802.16e Rev2, that reduces the MAP signaling overhead for VoIP traffic by allocating resources persistently for VoIP connections, i.e. provide periodic fixed allocation to a connection for multiple frames, eliminating the need to send the signaling information in every frame. Omitting the signaling information over multiple frames saves considerable MAP overhead. Persistent scheduling is shown in Fig 2b where the first frame includes MAP information for the VoIP burst and the information is skipped in subsequent frames. However, persistent scheduling does not allow the position and size of the VoIP allocation to change in subsequent frames, which results in reduced flexibility for the base station for scheduling. The reduced flexibility in resource allocation may cause “resource holes” in the frame when some users are reallocated. Due to this inefficient resource utilization, persistent scheduling may not achieve optimum VoIP capacity. Resource holes can be avoided by repacking users within the frame, however this causes additional overhead. The reduced flexibility with persistent scheduling also makes it harder to achieve statistical multiplexing between users. Group scheduling overcomes the above mentioned limitations of persistent scheduling.

Group scheduling clusters several users into groups based on their channel conditions and the VoIP codec used. The grouping of users makes it redundant to specify common parameters for each user, thereby saving overhead. In addition, the relative positions of users within the group are fixed with respect to each other, eliminating the need to signal the resource location of each user. Further overhead reduction is achieved by using smaller codes to specify the MCS and allocation size. A bitmap is used to specify which users of the group have allocations in a given frame, thereby allowing efficient packing of resources and avoiding resource holes. Group Scheduling thus reduces signaling overhead as well as provides flexibility in resource allocation, thereby providing efficient resource utilization.

To demonstrate the benefits of group scheduling we have built a prototype modifying an IEEE 802.16e BS and MS to support group scheduling. The video below describes the prototype.

Click To Play

This prototype provides an industry-first hardware demonstration of group scheduling an important feature for improving VoIP capacity for next-generation WiMAX systems.

The prototype was developed by Wey-Yi Guy, Minnie Ho, Vijay Kesavan, Kyle McCanta and Somya Rathi. The team acknowledges the contributions from David Bormann, Shweta Shrivastava and Jerry Sydir.

The conference itself is a highly successful, if rather austere affair, where chip designers of all stripes come to strut their stuff. There is none of the usual frippery one associates with professional meetings, no conference banquets, no guided tours or vendor booths (technical books being the only exception). Your steep registration fee gets you a glass of water (no ice) at break times, and the obligatory conference proceedings. That’s it. It is also an exceptionally precise affair with strict rules about font sizes, color schemes on your foils, time limits and general professional bearing. Oh and I almost forgot, attendees are treated to the sight of each session chair silently stalking the aisles, doing head counts during every single paper presentation. They keep statistics of this sort of stuff. About the only real entertainment to be had is to watch the occasional author squirm, under polite, but pointed post paper questioning. Standards are very high, professional reputations are on the line, and you definitely don’t want to show up unprepared.

Nevertheless, the occasion remains a heady mix of imaginative dreamers and precise technicians who keep things interesting and dare I say, fun. Most major advances in our industry have premiered in the conference and acceptance of one’s work at ISSCC has been a hoary rite of passage for generations of chip design professionals. Intel has always had a strong presence and this year was no exception, with 15 presentations. In addition to premiering Nehalem; our presentations spanned a wide range, from memory (SRAM, Flash) and wireless components, to thermal sensors and optical interconnects. The microprocessor session had 4 Intel papers detailing our entire 45nm product line. Much of this has been covered elsewhere and I won’t say more. The session was distinguished by the almost total absence of any one else from the industry (NEC being the exception). Whatever the reasons, one hopes that it is not the beginning of a trend. Competition keeps you sharp, and its absence is missed.

This year also saw Mark Bohr, Intel Senior Fellow, as the second instance (the first was Pat Gelsinger) in the last 10 years, of a plenary speaker from Intel. He gave a quick and lucid review of the golden age of transistor scaling through the 90’s, where area reduced by 50% and voltage scaled by 30% like clockwork. Life was good. Designers rode this wave, surfing and occasionally hiding behind the 50% power reduction that 30% voltage scaling gave us. That era has run its course, to be replaced by a more complex regime where, as Mark says, “Material and structure innovation (like our Hi-K metal gate) is as important as dimension scaling.” Voltage scaling has slowed to a barely perceptible crawl, and low power demands loom large. It is no accident that the end of the voltage scaling era was also the beginning of a new multi core and SOC era. Moore’s law continues, chip sizes decrease and transistor counts increase, but fundamentally different challenges face designers in this new regime. Mark’s plenary talk was a clear description of these challenges and its many real opportunities.

A spirited and occasionally moving plenary talk by John Cohn, an IBM Fellow, followed. Dressed for laughs in full mad scientist regalia (tie dyed lab coat no less), and accompanied by the obligatory Van de Graff generator (remember the frizzy hair folks?), he made three important points: (1) The profession of engineering is viewed very negatively across the board. We trail scientists (our close intellectual cousins), by a whopping 3 to 1 in most measures of positive influence; (2) Young people are increasingly motivated by societal/environmental/energy efficiency concerns. They don’t see anything useful emanating from the engineering field in any of these areas, and; (3) Engineers need to be involved in re-establishing an emotional connection with our customers as well as future entrants into the profession. Perception is often reality and we ignore these trends at our peril. The emotional connection with our customers is especially important. Witness the success of Apple in a difficult macro-economic environment.

The center of gravity of most of the work from industry was clearly 65nm. There were few 45nm designs and fewer still (4 including 2 from Intel) at 32nm. Both of Intel’s 32nm papers (on SRAM’s and thermal sensors) were more mature (with real yield results) than anything else on that node. Our technology lead, relative to the rest of the industry, widens as more and more companies go fabless. The trend towards SOC is relentless but the pace is varied across market segments. In contrast to microprocessors, all of our target growth markets (consumer electronics, embedded and MIDs) were well represented with innovative designs from a slew of competitors. A clear eyed and well executed mixed signal SOC integration story from the cable modem space, was a good example. Everyone is mired in cost/power reduction efforts, where the subtext is the incumbent (non IA) SOC ecosystem, but the optimizations are all around the periphery, i.e. the media processing and mixed signal blocks. This is a clear and compelling opportunity for Intel, given our process advantage and the potential of an IA based SOC.

The semiconductor revolution has reinvented and transformed entire industries, like computing and communications. Doing the same in the energy, automotive, health care and environmental industries will have equally profound and positive consequences. This has clearly not gone unnoticed, with well attended and interesting contributions in energy harvesting, sensor interfaces and silicon based drug delivery systems. Working examples of microwatt mechanical energy harvesters and CMOS micro pipettes for in vitro drug delivery were clear evidence of that heady mix of dreams and precision. Finally, if you are a glutton for punishment, you can attend the late night sessions (they go on until 10PM), where post dinner naps are rudely interrupted by talks on thermal energy harvesters, wireless power delivery and other such cheerful topics. I learned that you can now buy a module that harvests 2mW of electrical energy from about 4W of heat flux. It doesn’t sound like much, but it is not hard to envision completely self powered systems communicating at low duty cycles and low data rates with this sort of source. Our Seattle lab is exploring a similar phenomenon with their WISP and WARP technology. The industry is clearly trying to establish that elusive emotional connection with consumers and is struggling to translate this into an actionable silicon challenge.

So what is the future going to be? I can do no better than to fall back on our old friend the FAP who also famously said: “When you see a fork in the road, take it”

Cheers Soumya

P.S. FAP is of course the inimitable Yogi Berra. If you want to take a look at the ISSCC proceedings your best bet is to go to IEEE explore in a few months when they will be posted online. Some of the papers can be heavy going for the non specialist, but many are surprisingly accessible. They are mercifully short (unlike this blog), and are limited to one page.

Gaming is great, and I certainly have spent my share of hours glued to a computer monitor or console. But, at this stage of my life with everything from work to family getting busier and more complex, I find that I really have to ration my personal time wisely. And that’s fine, but as a result I hadn’t even bothered to login to Second Life, etc. The closest thing to a virtual world I’d experienced is helping my soon-to-be-stepdaughter log into Webkins or Club Penguin.

Yesterday, a group of us at Intel were discussing how to host more virtual meetings or events that would show people the business value of these worlds. Although I’m involved in evangelizing this research area, I have my own skepticisms about the what can be done using present technology. Most of what I hear people doing seems novel, but it seems like these things could still be done better with a combination of a teleconference or video conference plus a chat window. I asked the experts for examples of what unique capabilities virtual worlds would bring to the business world. I was struck by two that finally resonated:

1. The ability to take a large group of people and arbitrarily break them out into smaller sub-teams to discuss some topic (which happens a lot in teambuilding exercises). Trivial for a real life face-to-face meeting. Possible but tough using current conferencing tools. Trivial in a virtual world that has voice enabled.
2. Collaborating on a design for a physical object or event space. For instance, when we showcase demos at our Research@Intel Day event each year, we have a remote team, often working over the phone, trying to divide dozens of demos into a few physical zones and lay them out in a meaningful way. This would be much easier in a virtual environment where we could play around with the design and even simulate crowds or foot traffic patterns.

That meeting finally motivated me to log into a meeting in ScienceSim, a new world we just helped bring online last week for scientific collaboration and education. Experience-wise, it was mostly what I expected from seeing videos of similar worlds today. And I had some problems getting used to the interface (at one point I ended up at the bottom of a lake, and at another my avatar started uncontrollably “moonwalking” backwards). Also, since we are still bringing up voice capability, the dialog in the meeting all occurred in a chat window while the avatars mostly just stood around the common space.

The odd thing I noticed, though, was that even with this fairly low-key virtual interaction (the meat of which occurred in a very 2D chat window), the avatars did make a difference. There were these characters moving around my screen, and I knew that they weren’t just an AI game character — there was a real human somewhere behind it. That fact alone gave them a sense of physical “presence” that a chat window or audio call doesn’t have. Instead of a disembodied “voice,” it was at least partially embodied. And that was something. Enough for me to realize that when you do use voice chat plus things on the horizon like having your webcam track your facial expression and map them onto your avatar, this could actually be quite powerful. Still a long way to go, but that’s exactly why we have researchers looking into the technology underlying these experiences.

I’m sure that those out there who have more direct experience with virtual worlds (or even MMORPGs) have even more examples of how these environments could make professional interactions more productive. If so, I’d be glad to hear your thoughts.

This can be done using a frequency divider, a high frequency block that receive a signal at its input at a specific frequency and produces an output signal at a different frequency, i.e. divided down by 1.25 times. If, for example, we want to transmit at 2.5GHz for a WiFi wireless radio, now the oscillator can operate at 2.5x1.25~3.125GHz. This frequency will be different from the one transmitted by the power amplifier at 2.5GHz, eliminating interference problems (fig. 1).

However, the signal generated by the divider has to be extremely pure, meaning that it should only contain the desired tone at the main frequency (2.5GHz). Any other “spurious” frequency content should be 60dB lower (1’000 times lower amplitude) that the main signal at 2.5GHz. Just to give an idea of how small these spurious tones have to be, imagine that if the main signal amplitude is equivalent to the Empire State Building in New York City, these spurious tones have to be smaller than a fire hydrant (fig. 2)!

The output signal of a typical divider by 1.25 like the one used in this work looks like in Figure 3. Variations and mismatches in the fabrication process result in a small error Δτ appearing in the waveform every 4 cycles of the output (in fact this effect generates a spur at one-fourth the frequency). This error would have to be less than 100fs to achieve the required 60dB signal purity. Achieving such small timing errors is not trivial in today’s scaled CMOS technology. This is where digital-intensive techniques come in to save the day… Thanks to the device miniaturization, digital design can be very small and consume little extra power when compared to the rest of the radio, but still be able to “make-up” for the other component imperfections.

To be able to calibrate the divider and achieve this level of performance, we needed to measure timing errors (fig. 3) as low as the required 100fs. In fact our technique was able to go as low as 20fs. This is an incredibly small quantity…imagine that if we could stretch 20fs to the time needed to snap your fingers, then one second would last more than 1.5 million years, approximately the time from human appearance on earth to today (fig. 4)!

Using this technique, we were able to calibrate one of these dividers to achieve the required signal purity. In Figure 5, the frequency content of the signal generated at 2.5GHz is shown before and after the calibration. You can see how the spurious tones are reduced more than 60dB below the main one (at 2.5GHz).