The latest news and information on semiconductor packaging, including wafer-level packaging, chip-scale packaging, 3-D integration, lead-free solder/RoHS, stacked die/packages, wafer bumping, die bonding, wire bonding, and encapsulation. en-us http://www.semiconductor.net/community/Semiconductor+Packaging/47304.html?nid=3661 2008 Reed Business Information. Subject to its Terms of Use. Mon, 06 Oct 2008 15:09:24 MST http://www.semiconductor.net/article/CA6601680.html?nid=3661 The supervisory board of German equipment vendor SUSS MicroTec removed Stefan Schneidewind as CEO, and immediately placed Christian Schubert on the management board. The board cited “differing views regarding the future strategy of the company.” Fri, 03 Oct 2008 08:38:00 EST http://www.semiconductor.net/article/CA6600823.html?nid=3661 As the 3-D integration infrastructure evolves, it is becoming clear that low-cost, reliable bonding technology is required for 3-D IC integration to become mainstream. Without question, the industry is looking for solutions with lower cost of ownership (CoO). Ziptronix CEO Dan Donabedian thinks his company’s time has come. Wed, 01 Oct 2008 07:12:00 EST http://www.semiconductor.net/article/CA6600495.html?nid=3661 Georgia Tech’s Microsystems Packaging Research Center (PRC) plans to launch the global academia/industry 3-D All Silicon System Module (3DASSM) consortium. Tue, 30 Sep 2008 06:02:00 EST http://www.semiconductor.net/article/CA6600488.html?nid=3661 To meet growing demand for new materials for 3-D packaging and through-silicon vias, DuPont Electronic Technologies is expanding its material offerings. Mon, 29 Sep 2008 19:45:00 EST http://www.semiconductor.net/article/CA6598451.html?nid=3661 A packaging R&D center supported by IBM and New York officials is likely to begin operations soon, even before funding is finalized and construction of the building can begin. Alain Kaloyeros, CEO of the College of Nanoscale Science and Engineering (CNSE) at the University at Albany, said the center will attract a variety of packaging infrastructure companies to the region. Tue, 23 Sep 2008 10:59:00 EST http://www.semiconductor.net/article/CA6595399.html?nid=3661 NEC Electronics has joined the IBM-led Fishkill Alliance, with a goal of implementing NEC’s automotive microcontrollers and other products on the high-k/metal gate process at 32 nm design rules. “Spurred by the success we’ve had in the high-k program, NEC wanted to get involved directly, as well as in the early research work in Albany,” said Gary Patton, vice president of the IBM Semiconductor Research & Development Center. Thu, 11 Sep 2008 10:08:00 EST http://www.semiconductor.net/article/CA6594761.html?nid=3661 Seiko Epson Corp. said its resin-based gold bumping technology has passed reliability tests, leading to its use in applications such as HDTVs. The approach enables display engineers to mount driver chips onto a glass board, using less gold and tighter 20 μm wiring pitches. Wed, 10 Sep 2008 09:46:00 EST http://www.semiconductor.net/article/CA6592502.html?nid=3661 Tegal Corp. said it will acquire product lines from Alcatel Micro Machining Systems, giving it a deep reactive ion etch (DRIE) capability for through silicon vias (TSVs). “This acquisition is really the key piece of our product strategy that has been missing for a couple of years,” said Tegal CEO Thomas Mika. Wed, 03 Sep 2008 10:15:00 EST http://www.semiconductor.net/article/CA6591086.html?nid=3661 STATS ChipPAC has signed on to provide manufacturing services for products using Infineon’s first-generation embedded wafer-level ball grid array (eWLB) technology at its facility in Yishun, Singapore. eWLB is a fan-out wafer-level packaging technology that uses a combination of traditional front-end and back-end manufacturing techniques with parallel processing of all the chips on the wafer to provide a higher integration level. Thu, 28 Aug 2008 08:12:00 EST http://www.semiconductor.net/article/CA6591132.html?nid=3661 The agreement follows on a separate agreement between Infineon, STATS ChipPAC, and STMicroelectronics to jointly develop the next-generation of embedded Wafer-Level Ball Grid Array technology, based on Infineon’s first-generation technology. Thu, 28 Aug 2008 00:00:00 EST http://www.semiconductor.net/article/CA6589117.html?nid=3661 Dow Corning Corp. said a thermally conductive compound, developed for use in Intel's latest mobile processor, is now commercially available. The compound, applied between a chip and its heat sink to carry away heat, can also be used for automotive power devices, LEDs, FPDs and other heat-sensitive systems. Wed, 20 Aug 2008 10:14:00 EST http://www.semiconductor.net/article/CA6585445.html?nid=3661 Targeting the manufacture of future-generation semiconductor packages, STMicroelectronics, STATS ChipPAC, and Infineon Technologies AG said today that they have agreed to jointly develop the next-generation of embedded wafer-level ball grid array technology, based on Infineon’s first-generation technology. Thu, 07 Aug 2008 00:00:00 EST http://www.semiconductor.net/article/CA6584968.html?nid=3661 Shin-Etsu Polymer has developed a lightweight resin frame to handle and transport thinned wafers. The resin frame would replace the conventional stainless steel frames that tend to produce metallic contamination during wafer handling. Thinned wafers are increasingly being used for chips that have 3-D interconnects and ultrathin packages. Wed, 06 Aug 2008 09:49:00 EST http://www.semiconductor.net/article/CA6584971.html?nid=3661 The quarter saw sales growth for 3D packaging, flip chip, and wafer-level packaging and test services, but that growth was more than offset by reduced sales of leadframe packaging and certain of laminate packaging services. Wed, 06 Aug 2008 00:00:00 EST http://www.semiconductor.net/article/CA6584015.html?nid=3661 Shrinking package pitch sizes and higher pin counts are among the many factors forcing the test socket industry to consider new approaches below a 0.4 mm pitch. Mon, 04 Aug 2008 08:05:00 EST http://www.semiconductor.net/article/CA6583487.html?nid=3661 Alchimer SA said experiments have shown that its “electrografting” technology can handle deposition of the insulation, barrier and seed layers in through-silicon vias (TSVs). The privately held company also said its technology is being adopted by the CMOS image sensor vendors. Fri, 01 Aug 2008 07:49:00 EST http://www.semiconductor.net/article/CA6581184.html?nid=3661 MEMS are poised to become the most important technology of the 21st century, but only if packaging issues can be resolved. Substantial progress continues in the key areas of lower-cost ceramics, molded plastic cavities and wafer-level packaging. Fri, 01 Aug 2008 00:00:00 EST http://www.semiconductor.net/article/CA6581030.html?nid=3661 Asahi Glass has developed a release film for molding thin ball grid arrays (BGAs) or chip-scale packages (CSPs). The company said the film reduces resin usage, and nearly eliminates the frequent mold cleanings required with conventional molding technologies. Wed, 23 Jul 2008 07:48:00 EST http://www.semiconductor.net/article/CA6580009.html?nid=3661 Competing Japan-based molding machine manufacturers have developed techniques that support the thinner packages required for cell phones. The new molding methods also ease the mechanical pressure placed on the relatively fragile low-k dielectric materials in leading-edge logic devices. Mon, 21 Jul 2008 08:53:00 EST http://www.semiconductor.net/article/CA6579282.html?nid=3661 In his keynote address, “The Mobile Renaissance: The Era of Smarter SoCs,” Gadi Singer, vice president of the Mobility Group and general manager of the SoC Enabling Group at Intel (Santa Clara, Calif.), shared his compelling vision on the future of the mobile industry. Thu, 17 Jul 2008 10:00:00 EST