Sibridge Technologies

Design Tip - Do's and Don'ts for PCB Layer Stack-up

2012-10-17T23:27:00.000-07:00

Introduction

Each day the electronic gadgets complexity increases with the miniaturization requirements, boards are becoming much denser. Multilayer PCB technology can satisfy today’s miniaturization board requirement. Multilayer PCBs has more than two layers of PCBs, arrangement of layer should be done with great care because inefficient layer arrangement will lead to the noisy board with unexpected performances. This article addresses the layer stack-up basics and the general layer stack-up considerations.

Layer stack-up basics

Layer stack-up specifies the proper arrangement of circuit board layers for multilayer boards before starting board layout design. Stack-up mainly defines which layers should be solid power and ground planes, the substrate (dielectric constant), and the spacing between layers. While planning a layer stack-up, also compute the desired trace dimension and minimum trace spacing.

Multilayer boards are made up of one or more cores and prepreg as shown in figure 1(c). Cores are made up of a copper-plated glass-reinforced epoxy laminate sheets. Figure 1(a) shows a core can have copper on one or both sides. Cores are glued together with sheets of a partially cured epoxy. This sheets are referred to as prepreg as shown in figure 1(b).

Figure 1: (a) Core (b) Prepreg (c) 8 Layer stack-up (Side view)

Planning the good multilayer stack-up is the most important factor in determining the EMC performance of a product. A well designed layer stack-up not only minimizes the energy it radiates, but can also make circuit relatively immune from external noise sources. A well stacked PCB substrates can also reduce signal crosstalk and impedance mismatch issues. On the other hand an inferior stack-up can increase the EMI radiation, cause reflections and ringing in the system due to impedance mismatch which can dramatically reduce the product performance and reliability.

Types of Layers

One of the keys in determining well layer stack-up for high-speed circuit boards is to understand how and where the signal and return currents actually flow. Accordingly the layers should be defined and arranged. Figure 2 shows one of possible eight layer stack-up. The “H” in the figures implies horizontal routing and the “V” implies vertical routing. General layers are ground layer (return plane), power plane, signal layer, high speed signal layer, solder mask, and silk screen.

Figure 2: Examples of 8 layer stack-up (Side view)

Below points set out some basic do’s and don’ts points for planning layer stack-up.

Things to Do

· To reduce the layer stack-up planning complexity and time, first plan the power and ground layers. To plan a power and ground layers, first establish the signal rise times, the number of signals, and the physical dimensions of circuit board. As the trace width assumption is not particularly critical at this stage, make a guess for the trace width. Determining the best trace width for board is matter of experience and guesswork.

· Rent’s equation can also be used to figure out the number of routing layers.

Where, N = Number of netlists

Pavg = Average trace pitch, in

a = Board length, in

l = Board height, in

M = Number of routing layers

· As ground planes diminish the electromagnetic interference and electromagnetic radiation by absorbing high frequency noises, plan ground plane on the outer sides of the board. It is good practice to have ground plane on either one-side or both-side of board.

· Noise and crosstalk generation due to inductance and capacitance may generate crisis, so next estimate the mutual-inductance, mutual-capacitance by building desired models of solid power, split power, hatched, and solid ground plane. This model will give the complete idea of actual current directions, which help to provide stable voltage references, too. Generally split power planes should use to provide proper isolated areas on a power plane layer while providing an electrically different reference point (analog and digital sources).

· In high speed circuit board use solid ground and solid power plane in pair that gives best capacitive coupling to reduce power supply noises.

· Sometimes to reduce the return current path, power planes can be used as low-inductance signal return-current paths just as ground plane.

· For external interfaces (Ethernet, PCIe, USB, etc.), high speed signals need to drag outside boards. If the ground for that high speed interface is connected to ordinary digital ground, the effective interface output may be affected by a noise voltage presented on the digital logic ground.

· As the digital logic grounds are notorious for high speed noise voltages which can exceed FCC limits, one effective solution to this problem is to add an extra chassis ground plane to the same layer as shown in figure 3. Some below mentioned rules of thumb should be followed for planning chassis ground plane.

Figure 3: Chassis ground plane (Top view)

· Chassis ground plane should stack directly next to a ground plane, giving a very tight capacitive coupling between the two planes. Then chassis ground plane should screw, solder, or weld to external chassis to the earth.

· For only high frequency noises, chassis ground plane is effectively shorted to the digital ground via high voltage capacitor with low ESR. This bypass capacitor also provides best ESD protection.

· With the chassis ground plane approach, the digital and external chassis remain electrically isolated at low frequencies for desirable for safety proposes.

· In case of isolation is not mandatory, simply short digital logic ground directly the the chassis without using a separate chassis ground layer.

· With more layers, board size can spread out farther. That makes routing easier and reduces the risk of crosstalk problems. Unfortunately, PCB cost is proportional to the number of layers and the board surface area. So design should have fewest number of layers.

· Forcing traces tightly together increases the circuit board density. Vary dense designs required fewer circuit board layers.

· Smaller, more closely spaced traces also can produce more crosstalk and less power handling capacity. So plan traces width and pitch according to amount of current flowing through it and type of signal. This tradeoff among crosstalk, routing density, and power capacity is critical to low-cost production device.

· Use 0.5 oz copper thickness for outer side layers, and use 1 oz thickness for inner side layers to provide better current handling capacity with drastic temperature rise.

· High speed plane, used to design striplines or microstrips can buried between power or ground plane layers for extra shielding as show in figure 2.

· The purpose of solder mask layer is to physically and electrically insulate those circuits to which no soldering is required. Solder mask can reduce a little impedance on thin traces. But as the trace thickness increases solder mask has less affect. So the effect of the solder mask should be considered during impedance calculation.

· Much of the board manufacturer is following commercial standards that are published by the IPC organization for board manufacturing, assembly, and quality control. So IPC standard adoption for board dimensions, board thickness, core thickness, copper cladding thickness, Prepreg thickness, solder mask tolerance can reduce the production time and cost, increases the product reliability.

Things not to Do

· Do not design odd number of layers in stack-up. Odd layers boards can be manufactured, but it is usually simpler and less expensive to manufacture boards with an even number of layers. It is recommended to add an extra ground layer rather than designing odd layer boards.

· Do not split the ground plane into separate planes for analog, digital, power pins. A single and contiguous ground plane is recommended.

· Do not overlap two different high speed signals on two different layers, the capacitive coupling should be minimum to reduce the crosstalk across them. It is recommended to reduce overlap area by planning adjacent horizontal and vertical planes as show in figure 2.

· Do not overlap power supply layer and digital high speed signal layer. It is recommended to prepare layer partition map after components placement.

· Do not leave void spaces in layer, It is recommended to pour void spaces by copper. And short pour copper to ground plane by printed through hole which reduces the electromagnetic interference and the crosstalk.

· Do not use ordinary capacitors as a bypass capacitor between chassis ground and digital ground, because they might have too much lead inductance and also high ESR. Use only the high voltage capacitors with low ESR and low temperature coefficient as a bypass capacitor.

Summary

This document outlines numerous points that must be carefully reviewed and while determining the stack-up, try to achieve below points.

1. Manufacturing limitation needs to be check with respect to maximum number of layer, minimum trace width, and minimum drill size, aspect ratio of the board, PCB material thickness and type.

2. Signal layer should have at least one adjacent plane without any split.

3. Power and ground layer should be adjacent to each other.

4. High speed signal layer should be sandwich between two ground layer which provides shielding effect.

5. Power plane can also work as return plane for the high speed signal routing.

Acronyms

PCB Printed Circuit Board

EMC Electromagnetic Compatibility

EMI Electromagnetic Interference

PCIe Peripheral Component Interconnect Express

USB Universal Serial Bus

FCC Federal Communications Commission

ESR Equivalent Series Resistance

ESD Electrostatic Discharge

IPC Institute for Printed Circuits

Reference

High-Speed Digital Design - A Hand Book of Black Magic

-By Howard Johnson and Martin Graham

Design Tip - SDIO Support in Linux kernel

2012-10-11T23:32:00.000-07:00

Earlier there was no support of SDIO in Linux mainline kernel. Developers had to rely on proprietary stacks. Starting from 2.6.24 version SDIO support is part of mainline kernel. The mainline kernel SDIO stack is very different from other proprietary stacks. It hides all the details of SDIO protocol in well-designed API. In other implementations SDIO function drivers need to handle details of SDIO protocol. Mainline kernel implementation provides simple readX /writeX kind of routines as available for PCI. In fact its model is largely based on PCI.

SDIO device IRQ handler is called in process-context hence all SDIO I/O API can sleep. Support for asynchronous transfers doesn’t exist.

API for SDIO function drivers

sdio_register_driver

Registers SDIO function driver to the SDIO sub-system. Driver specifies probe, remove routines and deiceID table.

sdio_unregister_driver

Un-Registers SDIO function driver from the SDIO sub-system.

sdio_claim_irq

Claims and activates the IRQ for the given SDIO function. The provided handler will be called when interrupt is asserted.

sdio_release_irq

Releases and de-activates the IRQ for the given SDIO function.

sdio_claim_host

Exclusively claims a bus for a certain SDIO function. It provides locking mechanism. This lock must be held before doing any I/O operation for the function.

sdio_release_host

Release a bus for a certain SDIO function.

sdio_enable_func

Enables a SDIO function for usage. SDIO function driver’s first need to call this function after the SDIO device is successfully probed.

sdio_disable_func

Disables a SDIO function. Drivers call it when SDIO device is removed.

sdio_set_block_size

Sets the block size of an SDIO function. Though SDIO stack automatically sets block size, drivers can alter it.

sdio_max_byte_size

Returns the maximum byte mode transfer size.

sdio_align_size

Pads a transfer size to a more optimal value. Sometimes due to limitations of DMA controller transfers need padding. This function facilitates that.

sdio_readb

Reads a single byte from a SDIO function. This uses direct transfer mode of SDIO protocol.

sdio_writeb

Write a single byte to a SDIO function. This uses direct transfer mode(CMD52) of SDIO protocol.

sdio_memcpy_fromio

Reads a chunk of memory from a SDIO function. This uses extended transfer mode(CMD53) of SDIO protocol. If count is multiple of block size, it uses block transfer. If count is not multiple of block size, it uses byte transfer for the last transfer.

sdio_memcpy_toio

Writes a chunk of memory to a SDIO function. This uses extended transfer mode of SDIO protocol. If count is multiple of block size, it uses block transfer. If count is not multiple of block size, it uses byte transfer for the last transfer.

sdio_readsb

Reads from a FIFO on a SDIO function. This uses extended transfer mode of SDIO protocol. If count is multiple of block size, it uses block transfer. If count is not multiple of block size, it uses byte transfer for the last transfer.

sdio_writesb

Writes to a FIFO of a SDIO function. This uses extended transfer mode of SDIO protocol. If count is multiple of block size, it uses block transfer. If count is not multiple of block size, it uses byte transfer for the last transfer.

sdio_readw

Reads 16 bit integer from a SDIO function. This uses extended byte transfer mode of SDIO protocol.

sdio_writew

Writes 16 bit integer to a SDIO function. This uses extended byte transfer mode of SDIO protocol.

sdio_readl

Reads 32 bit integer from a SDIO function. This uses extended byte transfer mode of SDIO protocol.

sdio_writel

Writes 32 bit integer to a SDIO function. This uses extended byte transfer mode of SDIO protocol.

Writing SDIO function driver

In module_init of our driver, register probe and remove routines for SDIO function device using sdio_register_driver. Device ID table is also specified in this step.
Whenever the device is inserted in SDIO socket, based on vendorIDdeviceID pair, SDIO sub-system calls our probe routine.

In probe routine, allocate the private data for our function driver.
Enable the SDIO function using sdio_enable_func
Register IRQ handler using sdio_claim_irq
If required set the block size using sdio_set_block_size
SDIO IRQ handler is called from dedicated kernel thread for all the SDIO function drivers. So it is advisable not to do very large I/O operations from SDIO IRQ handler. Large I/O operation can be differed to work-queue. Create work-queue as our bottom half handler mechanism.

Based on device architecture, device can signal data read FIFO full or write FIFO empty through interrupt. SDIO sub-system calls our IRQ handler.

Find cause of interrupt and submit SDIO I/O operation work to the workqueue. Inside work-queue function any of the following API can be used to perform read/write.
<![if !supportLineBreakNewLine]>
<![endif]>

sdio_readb/sdio_writeb
sdio_readw/sdio_writew
sdio_readl/sdio_writel
sdio_readsb/sdio_writesb
sdio_memcpy_fromio/sdio_memcpy_toio

In module_exit of our driver unregister our probe and remove methods using sdio_unregister_driver. This calls our remove routine.

In remove routine, wait for pending transfers and then release IRQ handler using sdio_release_irq
Disable SDIO function using sdio_disable_func
Free private data for our driver.

Remove routine is also called when device is hot-unplugged from SDIO bus. In this case cleanup is tricky and 100% cleanup may not be possible.

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Design Tip - Automated Validation for SoC using Oscilloscope

2012-10-10T05:04:00.001-07:00

Automated Testing is the use of software to control the execution of tests, the comparison of actual outcomes to predicted outcomes, the setting up of test preconditions, and other test control and test reporting functions. Commonly, automated testing involves automating a manual process already in place that uses a formalized testing process.

Description:

FPGA/SoC Board: This is the DUT (Device under Test). Actual test cases are running on this Board. The board can be connected with peripheral board to provide support for external connectivity and reference devices. Through the peripheral board DUT needs to be connected to PC.

Mux/Demux: This module is important if multiple modules are required to be verified and numbers of test points are more. This module helps to avoid making different connections to measure various signals with limited channels on Oscilloscope or Analyzer. User can make the connections initially and need not worry about each and every test case. This Mux/Demux can be controlled via PC using Parallel port (or USB depending upon Mux/Demux support). When the test case execution is controlled by PC, it is easier to configure the Mux/Demux module just before the test case execution.

Oscilloscope/Analyzer: This device is used to measure various signals. Nowadays these devices have inbuilt PC connectivity. They can be controlled via PC through Network or USB and several other connectivity methods. Manufacturers provide libraries to communicate with these devices through PC application. We just need to integrate that !P I’s to our test utility. Several !P I’s are very useful such as snapshot of signals. Snapshot can be saved for each test-case and can be used for reports and future exploration. If the user needs to save the snapshots manually it will be difficult to be consistent in naming convention of the images and will be time consuming.

PC: Main test application will run on PC and controls all devices depending upon the tests running. This application will be responsible for controlling the execution of tests on DUT, controlling Mux/Demux and Oscilloscope/Analyzer. This application can be GUI based and user friendly thus tester does not need to go through complexity of the entire test setup. Tester can just follow the simple steps and will be ready with test results after detailed testing done without understanding of complex protocols. Also when t est s are st art ed they don’t require manual operations, thus testers can run multiple tests on different test setups simultaneously.

Benefits:

Reduced Time: If the testing is done manually, then the average time taken for one test is about 5 to 6 minutes. Therefore, [10 test cases]/hr and [80 test cases]/day (8 working hrs). But with the help of the automated testing using oscilloscope the same test-case can be tested in just few seconds. Considering [15 sec]/test the output will be 24 times faster, resulting in [1920 test cases]/day (8 working hrs). This automation doesn’t require manual operation, thus can be operated 24hrs a day, giving throughput of 5760 tests vs. 80 tests if done manually.

Minimal Complexity While Testing: Once the code is written for automation the user performing the testing need not require have the knowledge of various protocols. Therefore the testing can be performed by anyone with minimum operating skills.

More detailed error free results: Snapshots can be captured for all tests those are useful for further observations by different departments. Also result can be exported in csv, charts or other required formats. As this process is automated there are no human errors (more observed when numbers of tests are high).