SOC Design

This blog has moved

2008-06-12T20:58:00.000-07:00

A year ago, I moved this blog to http://www.edn.com/blog/980000298.html to get a wider audience and to sidestep blogspam. See you there!

Quantum Conundrum

2007-02-20T21:57:00.000-08:00

Last week, I attended the debut of what may become the first commercial quantum computer. Or not. The EDN article I wrote about this demonstration is here: http://www.edn.com/article/CA6416905.html?ref=nbsa&text=quantum

D-Wave, the company that has been developing this quantum hardware for eight years, used the Computer History Museum for it's introduction venue. However, the computer itself was located in Burnaby, British Columbia and was operated via the Internet. So we have to take D-Wave's word that we were watching an actual quantum computer solve problems. That's not to say I disbelieve D-Wave, only that I cannot say with 100% confidence that I indeed saw a quantum computer in action.

Other press outlets have published quotes that scientists are "dubious" about D-Wave's claims. I think that's the wrong word. D-Wave hasn't been forthcoming about key technical details (but says they will be in the future) so I'd say that the community is presently "unconvinced." We'd like more information before passing judgement. In the meanwhile, I consider quantum computing to be "spooky information processing at a distance," to paraphrase Einstein.

D-Wave's Orion, the name of their proof-of-concept machine, solve's NP-complete problems. These are the sort of problems that require a full solution search in conventional computers, which is a very slow process for problems with large solution sets. As it is today, Orion is about 100x slower than today's computers because it's only a 16-qubit (quantum bit) machine. By the end of 2008, D-Wave believes it can have a 1024-qubit machine running that would be 10x faster than conventional binary computers at solving NP-complete problems.

CES Update: The Revolution Will be Televised

2006-01-07T11:35:00.000-08:00

The revolution will not be televised, will not be televised,
will not be televised, will not be televised.
The revolution will be no re-run brothers;
The revolution will be live. - Gil Scott-Heron

I have just returned from the 2006 CES in Las Vegas. It was packed with people. As the volume driver in the electronics industry has switched from personal computers to consumer electronics, CES has taken the mantle as the industry's leading light into the murky future from Comdex. The mantle had previously passed from the National Computer Conference (NCC) to Comdex around 1981 when PCs started to dwarf mainframes in market dominance and NCC refused to heed the change.

The big news at Comdex, er CES, this year was a 100-year-old idea called television. New-millennium television is becoming a when-you-want-it, where-you-want-it, how-you-want-it affair. Dick Tracy had this capability in his wristwatch exactly 60 years ago. Now it seems that it's time for everyone else to have it too.

The "when you want it" phase started with VCRs in the 1970s and it has evolved into today's DVD recorders and PVRs (personal video recorders). However, all of these devices are tethered to coaxial cables tied to stuck-in-the-wall cable sockets and immobile satellite dish antennas. Also, these consumer products are only time-shifting devices; they don't jimmy with the image format and resolution. How-you-want-it and where-you-want-it boxes such as Apple's video iPod and other personal media players are just starting to appear.

As CES 2006 demonstrated, the industry is full of companies working on place-shifting and format-shifting video products. Two new classes of video place shifters I saw at CES are mobile phone handsets capable of receiving video broadcasts and boxes that cram video into IP packets and unleash them onto the Internet. LG seems to be way ahead on phone handsets that receive terrestrial and satellite video. The company was showing several video-capable handsets at CES. They just wouldn't let me shoot photos of them. So only the 140,000 other people at CES got to see them.

The other place-shifting product is epitomized by the Sling box from Sling Media. This oddly shaped box (looks like a large silver-colored bar of candy or a silver-colored gold bar to me), takes in video and spits packets out of an an Ethernet port. What you do with those packets is your business. Receive them on your computer at work, your laptop at Starbucks, or your Treo wherever you happen to be.

Both the mobile handsets and the Sling box need to reformat video to fit a target playback device that clearly isn't a conventional television receiver. Their ability to reformat images must satisfy three conflicting goals.

The video should look good.
The compression format used to send the video should consume very little bandwidth.
The amount of power required to encode and decode the compressed video should be small.

Companies that master video-compression algorithms supporting these goals will be in high demand.

Gil Scott-Heron clearly got it right in the 1970s. But in the 21st century, the revolution will be televised.

ST backs NOC for SOC design productivity

2005-12-15T09:52:00.000-08:00

From EE Times:

"ST says an effective NoC architecture will be a crucial precondition for cost-effective SoCs targeted at convergence devices and, in particular, NoC technology will play a major role in improving design productivity."

Networks on Chip

2005-12-15T09:41:00.000-08:00

Earlier this week, EDN.com published an article I wrote about networks on chip (NOCs) called "NOC, NOC, NOCing on Heaven's Door" (another song reference, this time to Bob Dylan). The article's based on some really great presentations I saw last month at the SOC conference held in Tampere, Finland. Cool place. Literally.

Pun of the day

2005-12-15T09:36:00.000-08:00

The irresistable "fish with chips" from a Reuters story as published online by MSNBC. The chips are tracking devices, of course, and are made of silicon not Idaho potatoes.

Dare to be stupid, Dare to be stupid

2005-12-15T06:14:00.000-08:00

Want to get confused? Really confused? Then take a look at this blog entry on Geek.com discussing multiple processor cores in PC-processor land. Be sure to read the comments made by the informed, the uninformed, the partially informed, and the intentionally lame.

Hopefully, SOC designers aren't nearly this confused. I also hope the advice delivered in the SOC design community isn't this, er, diffuse.

Thanks to Tensilica's Lee Vick for the pointer to the blog.

(BTW: The title of this blog entry is a reference to a Wierd Al song that apes the music of Devo.)

SOC Design: Just what do you optimize?

2005-12-14T14:51:00.000-08:00

A recent article and an unrelated analyst presentation give excellent advice to SOC designers and managers comtemplating the plunge below 100nm. The rules of system design below this lithography threshold change and the article and the presentation provide some partial roadmaps to success.

EE Time's EDA editor Richard Goering wrote a recent column on Design for Inefficiency that questions how SOC design teams trade off transistor budgets for time to market. Sound like heresy? I remind you, oh gentle reader, that precisely the same discussions about using C for embedded systems software were occurring 20 years ago. If you haven't heard, the relatively inefficient C language won over efficient assembly code precisely because of time-to-market issues. Most of today's systems would never get to market if they were solely or even largely based on software written in assembly language.

Last week at Gartner's Semiconductor Industry Briefing held at the Doubletree in San Jose, Research VP and Chief Analyst Bryan Lewis discussed "second-generation SOCs" in his presentation titled Charting the Course for Second-Generation SOC Desvices, in which he described second-generation SOCs as high-gate-count devices using mixed process technologies, multiple processors, and multiple software layers. In Lewis' vision of a second-generation SOC, the multifunctional chip is built with multiple processor cores, each driving its own subsystem with its own operating system and application firmware. This design approach is unlike today's most common design approach of loading up one main processor with as many tasks as possible, and then some.

Lewis' second-generation vision encompasses a divide-and-conquer approach to complex system design and it closely relates to Goering's theme of asking, "Just what do you optimize?" The more you burden one processor with an increasing number of tasks, the more complex the software gets and the faster the processor must run. The result: exponentially increasing software complexity (think lost time to market and bug-riddled code) and exponentially incresing power dissipation and energy consumption (think less battery life or more expensive power supplies; noisy, expensive, and relatively unreliable cooling fans; and larger, more costly product enclosures).

Once again, the question of the decade is: "What do you optimize?" Do you optimize transistor count to absolutely minimize chip cost while greatly increasing design time and cost and possibly missing market windows, or do you waste truly cheap transistors to buy back some of that time?

I think the answer's pretty clear: 90nm and 65nm transistors are cheap and engineering time is expensive. Lost time to market is virtually priceless. What do you think?

More wisdom from Jack

2005-12-14T14:46:00.000-08:00

Jack Ganssle, who writes for Embedded Systems Design and Embedded.com almost always has interesting things to say. His latest column on NRE versus cost of goods sold is no exception. See it here. Although Jack is writing about purchased software in his column, his arguments are equally applicable to IP blocks for SOC designs.

The Lessons of History

2005-12-01T09:01:00.000-08:00

Lessons of history from Leslie Berlin’s “The Man Behind the Microchip: Robert Noyce and the Invention of Silicon Valley”

Everyone knows, and no one remembers, that history repeats itself. This maxim is true even in the short history of the electronics industry. Here are a few excerpts from Dr. Leslie Berlin’s Bob Noyce biography, “The Man Behind the Microchip,” that serve as gentle reminders:

1. The time is late in 1949, two years after Bell Labs announces the creation of the transistor. Bob Noyce has just started his first year of graduate studies at MIT:

“… [Wayne Nottingham’s] Physical Electronics seminar might well have been Noyce’s only direct instruction on the topic [transistors] that year, for MIT had yet to incorporate the transistor into its formal curriculum. Nottingham’s Electronics class, for example, did not mention the device at all in 1949. The transistor was a new technology, and it had very real problems. It was hard to build a functional point-contact transistor; indeed, simply replicating the Bell team’s results was difficult. Vacuum tubes, by contrast, were entering their heyday: they were far cheaper and more stable than ever before. No one—certainly not Nottingham—saw any evidence to indicate that the point-contact transistor would be in a position to replace tubes for a long, long time.”

Within the next 10 years, Bob Noyce would join the transistor research group at Philco; in 1956 he would then leave Philco and join Shockley Transistor Labs in Palo Alto; and then less than two years later he would found Fairchild Semiconductor with seven other Shockley refugees/traitors. In 1959, only 10 years after Noyce started his MIT graduate work, Fairchild’s Jean Hoerni would develop the planar process with its protective coating of silicon dioxide, which tremendously boosted transistor ruggedness and reliability and gave Noyce the missing piece of the IC puzzle. Hoerni’s development of the planar process enabled the invention of the integrated circuit and is the bedrock foundation of all semiconductor manufacturing more than 40 years later. Today, we take transistors for granted, but in 1949 they were weak, unreliable laboratory curiosities with no hope of competing against five decades of vacuum tube R&D.

2. The year is 1961. In March of this year, Fairchild Semiconductor introduced the first integrated circuits, dubbed Micrologic:

“The reaction was gratifying but did not translate into widespread adoption. By the end of 1961, Fairchild had sold fewer than $500,000 of its Micrologic devices, which were priced at about $100 apiece. Texas Instruments, the only other major supplier, was having such problems selling integrated circuits that it cut prices from $435 to $76 in 90 days. The move had little effect.

Customers’ objections to integrated circuit technology abounded. The devices were extremely expensive relative to discrete components—up to 50 times the cost for comparable performance, albeit in a smaller package. Many engineers, designers, and purchasing agents working for Fairchild’s customers feared that integrated circuits would put them out of work. For decades, these customers had designed the circuits they needed from off-the-shelf transistors [and vacuum tubes before transistors], resistors, and capacitors that they bought from manufacturers like Fairchild. Now Noyce wanted to move the Fairchild integrated circuit team into designing and building standard circuits that would be sold to customers as a fait accompli. If the integrated circuit manufacturers designed and built the circuits themselves, what would the engineers at the customer companies do? Moreover, why would a design engineer with a quarter century’s experience want to buy a circuits designed by [a] 30-year-old employee of a semiconductor manufacturing firm? And furthermore, while silicon was ideal for transistors, there were better materials for making the resistors and capacitors that would be built into the integrated circuit. Making these other components out of silicon might degrade the overall performance of the circuits.

As late as the spring of 1963, most manufacturers believed that integrated circuits would not be commercially viable for some time, telling visitors to their booths at an industry trade show that ‘these items would remain on the R&D level until a breakthrough occurs in technology and until designs are vastly perfected.’”

In the spring of 1964, Bob Noyce started selling Micrologic flip-flops for less than the cost of the discrete components needed to build an equivalent flip-flop, and for less than the manufacturing cost of the IC:

“Less than a year after the dramatic price cuts, the market [for ICs] had so expanded that Fairchild received a single order (for half-a-million circuits) that was the equivalent of 20 percent of the entire industry’s output of circuits for the previous year. One year later, in 1966, computer manufacturer Burroughs placed an order with Fairchild for 20 million integrated circuits.”

“By the middle of the 1960s, Fairchild was one of the fastest-growing companies in the United States.”

Today, we take the integrated circuit and Moore’s Law for granted, but in the early 1960s, their future was anything but sure.

3. By 1968, Bob Noyce was fed up with the management at Fairchild Camera and Instrument, the parent company of Fairchild Semiconductor. He and Gordon Moore incorporated a company called NM Electronics in July, 1968. NM Electronics would become Intel by the end of the year.

“Just as the industry’s high hopes for integrated circuits had launched the earlier gaggle of startup companies, the 1968-1969 generation was inspired by a belief that semiconductors were on the cusp of another dramatic technological breakthrough… Already, Moore’s own R&D group at Fairchild had fit a once-unthinkable 1,024 transistors onto a single circuit. In 1968, this circuit was little more than a lab curiosity, but the general consensus held that circuits with more than 1,000 components integrated together—so-called Large Scale Integrated circuits—should be physically possible to mass produce by 1970.”

However, large-scale integration (LSI) was certainly not considered a slam-dunk technological leap in 1968:

“… Noyce and Moore, in fact, had settled on computer memories as a first product not primarily because the computer market was growing—although that was a welcome reality—but because memories would be the easiest types of LSI circuits to build. … In Moore’s words, LSI was a “technology looking for applications” in 1968. Which is to say: if LSI technology was going to work anywhere, it would work first in memories. If it worked in memories, Noyce and Moore could anticipate an ever-growing market of computer makers ready to buy.”

The plan therefore, was to replace core memories with semiconductor memory. Core memory, developed in the early 1950s, pervaded computer design in the late 1960s. Mainframes and minicomputers used core memories because there simply was no alternative memory technology that could compete with core memory on the basis of cost/bit, energy consumption, or size. Even so, core memory was vulnerable to attack if a superior, more cost-effective technology could be developed:

“Magnetic cores had their shortcomings, however, and in these Noyce and Moore had seen a potential foothold for Intel. Cores were not a particularly fast means of storing data. … Moreover, the core memories were built by hand. Every one of those iron donuts was individually strung on a wire by a woman in a factory, most likely in Asia. Noyce and Moore knew that this labor-intensive means of production was not sustainable for a computer market growing exponentially, just as they had known a decade earlier that hand-wired discrete components could not serve the exploding market for space-age electronics.”

Even with these shortcomings, Noyce and Moore knew by now that not all technological improvements are immediately hailed by design engineers:

“Moore and Noyce knew that the problems with cores were irrelevant to most computer engineers, who did not spend their time thinking about how they would build their machines ten years in the future. These engineers cared about how their computers work now, and so the cost advantages of semiconductor memory would have to be overwhelming before engineers would consider abandoning the clunky, but reliable, magnetic cores. A sense of déjà vu may again have struck Noyce and Moore, who faced a similar obstacle when they initially brought the integrated circuit to market. Noyce, the architect of Fairchild’s decision to sell integrated circuits below cost to get a foothold in the discrete components market, was betting a similar strategy would work for semiconductor memories.”

These first memories weren’t easy to manufacture, and the low yields didn’t allow them to be sold cheaply. Intel’s first MOS memory, the 256-bit 1101 static RAM (SRAM), was too slow and expensive when it was introduced in September, 1969. At 20-60 cents/bit, it was 5x to 12x more expensive than core memory per bit. Even reducing the price of the 1101 by 75% didn’t help sales.

However, Intel pressed on and introduced the 1-Kbit 1103 dynamic RAM (DRAM) in October, 1970:

“To be sure, the device was far from perfect. Among the 1103’s many failings known to Intel was the fact that, in Andy Grove’s words, ‘under certain adverse conditions, the thing just couldn’t remember’—a problem for a memory. Some 1103s failed when they were shaken. A few developed moisture under the glass used to seal them. Often no one knew why the devices would stop working. The problems inspired Ted Hoff to write a 28-page memo explaining the 1103’s operation and quirks.

Andy Grove had nightmares that boxes and boxes of 1103s would be returned to the company for defects—and would run Intel entirely. Gordon Moore, on the other hand, wondered if, in some perverse way, the 1103’s problems made it easier to convince customers to use the device. Engineers who specialized in core memories recognized analogs in the 1103. Both suffered from voltage and pattern sensitivity. … ‘All these things made the 1103 more challenging and less threatening to engineers [at customer companies],’ Moore explains. ‘We did not plan it to happen this way, but I think that if [the 1103] had been perfect out of the box, we would have had a lot more resistance [to it] from our customers.’”

By 1972, Intel was building 100,000 1103 DRAMs per year and was still unable to meet demand for the device, even with a Canadian second source that had paid Intel millions of dollars for the second-source rights to the device. Essentially, all of Intel’s 1972 revenue, $23.4 million, came from sales of the 1103.

4. Today, Intel’s no longer in the memory business—microprocessors are now the company’s bread and butter. Intel entered the microprocessor business completely by accident. It then took a lot of missionary work before the microprocessor became a successful product category:

“Intel’s microprocessor story opens in the spring of 1969, around the time that [Gordon] Moore called [Bob] Noyce in Aspen to tell him that the MOS team had a working silicon-gate memory. A manager from a Japanese calculator company called Busicom, which was planning to build a family of high-performance calculators, contacted either [marketing manager] Bob Graham or Noyce to ask if Intel, which had a small business building custom chips designed by customers, would like to manufacture a chip set that would run the calculator. Calculator companies around the world were seeking out semiconductor companies to build chips for their machines, and Noyce said that Intel was nearly the only manufacturer left who had not already agreed to work with a calculator company. … Busicom, which was designing a particularly complex calculator, wanted a set of a dozen specialized chips with 3,000 to 5,000 transistors each. Busicom planned to send a team of engineers to Intel to design the chips on-site and would pay Intel $100,000 to manufacture its calculator chip sets. Busicom expected to pay Intel about $50 for each set manufactured and promised to buy at least 60,000 of them. Intel agreed to this arrangement.”

Noyce made Ted Hoff, Intel’s resident computer expert, the company liaison to the Busicom design team. Hoff did more than he was assigned. He took a technical interest in the Busicom design and soon concluded that disaster was on the horizon. The projected transistor count for each chip was beyond the state of the art and the large number of chips in the set was going to drive the component cost well above the $50 target.

Hoff developed an alternative scheme based on a general-purpose programmable chip that would act like a small computer processor. This device could then be programmed using memory devices (Intel’s primary intended product line at the time) and the whole Busicom system could then be built using far fewer device types. The programmable device, of course, was a microprocessor. Hoff tried to convince the Busicom engineers to shift their direction, but he failed to convince them.

Consequently, Hoff went to Noyce and convinced him. Noyce told Hoff to go off and develop his idea, just in case the predicted disaster materialized. By August, 1969, Noyce wrote to the president of Busicom and took Hoff’s position. There was no way that Intel would be able to manufacture the chip set currently under development and sell it to Busicom for $50/set. Noyce estimated that the price would be more like $300/set. He asked if Busicom still wanted to continue the project.

In September, Bob Graham sent a similar letter but also suggested that Intel had developed an in-house alternative that might better meet Busicom’s cost target. Busicom sent two executives to Intel in October. They considered the alternatives and chose Intel’s approach, with a projected cost of $155/chip set. Then, Hoff and Intel did nothing. The agreement wasn’t signed until February, 1970. In March, 1970, Busicom sent a “How’s it going?” letter to Intel. Only then did Intel hire Federico Faggin to work on the microprocessor’s design. In nine short months, he designed and then produced working samples of the four chips in the Intel calculator chip set.

However, the calculator market had gotten competitive and Busicom indicated that it wanted to negotiate a price reduction, even before volume production started. Noyce asked Hoff for advice on the contract renegotiation. Hoff said to place highest priority on the right to sell the chips to other customers. The renegotiation was stalled until August, 1971 and finalized in September. Intel had gotten the right to sell the microprocessor, which it introduced as the 4004 in November, 1971, a month after Intel’s IPO.

However, the microprocessor was not an overnight sensation. For example, Noyce foresaw the microprocessor’s use in automobiles and went to General Motors in 1971 to talk about adopting microprocessors for automotive applications. GM already had an automotive electronics program underway but the GM execs were skeptical that someting as advanced as Intel's computer-on-a-chip would be controlling vehicle brakes or anything else inside of a car soon.

“… Noyce almost certainly told them, their skepticism was well grounded. No one would want the 4004 controlling brakes in production cars; the device was too slow and too rudimentary for general use. And its successor, the 8008 (introduced in April 1972) was not much better.

But Noyce was not trying to sell 4004s or 8008s to General Motors. He was starting conversations that he expected would only bear fruit years later. He knew he was contending with entrenched ways of thinking and years-long design cycles. He felt confident that by the time these customers were prepared to experiment with microprocessors, the technology would have caught up with his visions for it. And indeed it did.”

The Silicon Steamroller

2005-10-06T07:35:00.000-07:00

In an October 5 article, EE Times' editor Dylan McGrath writes: "There is a widespread misconception about the current size and strength of the Chinese fabless semiconductor industry, according to Lung Chu, president of the Asia Pacific region for Cadence Design Systems Inc...

Chu said total revenue for Chinese fabless companies in 2004 was less than $1 billion and that most of the companies' designs are 0.18 micron or 0.25 micron."

So, things look pretty good still for the rest of the world, which seems to hold the high ground of advanced semiconductor design. That is, until you couple this October 4 story about IC mask making written by Richard Goering, also for EE Times. Goering writes about this year's version of an annual mask-usage study sponsored by Sematech and conducted by Shelton Consulting:

"Only 5 percent of IC photomasks are below 100 nm...according to a 'mask industry assessment' study presented at the BACUS Photomask Technology symposium... According to the study results, just under 50 percent of masks use 350 nm or greater ground rules, 12 percent are below 130 nm, 5 percent are below 100 nm and just 0.8 percent are below 70 nm. The study looked at volumes, not revenues or IC transistor counts."

Using these numbers, by my count Chinese fabless design companies can already handle well over 50%, and perhaps as much as 80%, of the designs being created today. That fraction will increase rapidly over the next few years as the design houses in China climb the design learning curve.

As a country, China has proven many times over that it can steamroller any learning curve it wishes. The only way to avoid being crushed by a steamroller is to find a way to run faster than the steamroller or find a faster vehicle to escape. It's foolish and dangerous to think that the steamroller will run out of fuel before it can reach you.

Moore's Law Moves Along

2005-10-03T23:35:00.000-07:00

EE Times reports the first public announcement of a 65nm tapeout by Silicon and Software Systems (S3). It's a 500-MHz chip intended for consumer devices and is expected to ship in very high volumes, hence the desire to use 65nm design rules to minimize the silicon real estate. The chip was designed with Cadence tools.

Is the end near?

2005-09-01T13:44:00.000-07:00

Today's Electronic News carries an interview with Rick Hill, chairman and CEO of IC-manufacturing equipment supplier Novellus. Hill says that 65nm manufacturing technology looks like the economic end of the road for lithography shrinks because we're getting perilously close to tolerances measured in single atomic layers and we're using charge packets composed of very few electrons to represent ones and zeroes. Thoughtful reading.

More on Multicore Design

2005-08-30T13:10:00.000-07:00

Market research firm IDC in Framingham, Massachusetts has declared that IC design using multiple processor cores may be one of the most significant industry developments of the past 40 years.

The IDC study is called "Multicore Processing Scenarios, 2005-2009: Disrupting the IT Market in Three Generations?" (IDC #33789).

Two cores, four cores, eight cores, and so on

2005-08-29T14:29:00.000-07:00

Last week at the Intel Developer Forum in San Francisco, Intel’s President and CEO Paul Otellini estimated that his company would ship over 60 million dual-core Pentium processors over the next 18 months. He also said that the company has ten quad-core projects in the works. Intel has gotten that good ole’ multi-core religion big time, following AMD’s lead with its dual-core Opteron. Although big doings in the PC space often lead to similar developments in the embedded-systems arena, this time the PC processor giants are playing catch-up with the embedded league.

There are many technical reasons for going to multiple processor cores. First, this approach allows the system design to cut clock rate and thus operating power. Cut clock rate by 50% and a variety of factors will result in a power reduction of more than 50%, which more than makes up for the extra power needed to run the added processor.

Cutting the clock rate eases memory-access timing, which is another big plus for system designers. Cutting clock rate also allows the chip designers to back away from the bleeding edge of IC-fabrication technology. These factors cut manufacturing costs.

Finally, adding more processor cores to a chip allows IC designers to do something really useful with all of those extra transistors Moore’s Law keeps dumping on our doorsteps. Instead of spending these transistors on increasingly complex processor architectures that get only a few percent faster for the effort, adding another processor core can substantially boost system performance, if the system software is written correctly.

Intel’s and AMD’s move towards multiple-core processors is potentially good news for embedded system designers because PC programmers, a group larger by far than embedded-system programmers, will start to think in terms of getting tasks done with multiple processors. We will start to leave the “one-big-processor” paradigm behind. Because many embedded-systems programmers first learn their craft on PCs, this trend bodes well for all system design.

Al's Story

2005-07-15T14:50:00.000-07:00

My friend and neighbor Al has been in the electronics business a bit longer than I have. I spent a week traveling all over Western Nevada with Al two weeks ago, so we spent a lot of time in the car together. Al told me that one of his first jobs was to develop a transistor tester to characterize the hand-made junction transistors his company was getting from RCA, Philco, and other vendors. Transistor-to-transistor device characteristics varied wildly back then because transistor manufacture was pure alchemy in the 1950s.

Another job Al had in that era was to linearize some signals. Al told me it was pretty tough to do this back then. All he had to work with was resistors, capacitors, diodes, and discrete transistors.

Last week, I read about a new microcontroller from Zilog called the Z8 Encore XP, which would have made this job much easier. The Z8 Enxore XP is based on the 8-bit Z8 processor core, which I recall using to design the electronics for a total-organic-content water analyzer back in the early 1980s.

Today's Z8 processor comes packaged in an 8-lead SOIC and costs around a dollar. In addition to the processor core, the Z8 Encore XP includes four 10-bit A/D converters and 4K bytes of flash memory on chip. You program it in C. If I could go back 50 years to tell my friend Al that I could do a piecewise linearization of four of his signals to about 0.1% for a buck (that would be linearization for 25 cents per signal), and that I could get a prototype running in a day, I wonder what he'd say.

The point in telling you Al's story is to remind you that no technology stands still. Consequently, your approach to system design can't stand still either. We all chuckle a bit about Al's predicaments 50 years ago because we have far more advanced ways of dealing with the problems he had to solve using much cruder tools.

However, is Al's situation still funny when you're using the same SOC design techniques that you used 10 years ago?

To infinity and beyond!

2005-07-15T13:38:00.000-07:00

The title quote is from Buzz Lightyear but the topic of this post is David Lammer's cover article on 65nm process technology in the July 11 EE Times. The article is about the 2005 Symposium on VLSI Technology held in Kyoto, Japan last month. A few points in this excellent article caught my eye with respect to system design.

Point one: 65 nm technology buys you a cool 10 million transistors per square millimeter! An economical chip is around 100mm squared, which works out to one billion transistors on the chip. Even a cheap 5x5mm chip made with 65nm technology carries 250 million transistors. Hand-coding enough RTL to fill these chips will take, like, "To infinity and beyond!" You'd better get ready to find a more efficient way to design chips.

Point two: If you sniff at point one and say that leading-edge 65nm process technology is only for high-priced, cutting-edge products, read the statement from Mark Pinto, Chief Technology Officer at Applied Materials: "Demand from China is only going to grow—and 65nm is absolutely ideal for consumer chips aimed at growing markets."

Point three: Srini Raghvendra, Senior Director of Design For Manufacturing at Synopsys said: "Design productivity, measured in terms of gates per engineering workday, must improve fourfold at 65nm over the 130nm node." Do you have a plan to achieve that?

Point four: Process technology, especially at the 65nm node and future nodes, will no longer provide the automatic power reductions that "classical" Moore's-Law scaling has delivered for the past 40 years. "Addressing the problem requires architectural, system-level decisions." said Eric Filseth, a Cadence marketing manager.

Point five: Hardware/software codesign becomes more crucial at 65nm. "Teams must start on software creation at the same time that RTL design commences." according to Tohru Furuyama, general manager of R&D at Toshiba's SOC engineering center in Kawasaki, Japan.

Point 6: Mask costs for 65nm chips are estimated at $3 million. That's still small compared to the cost of designing a chip with as many as a billion transistors, but it's not an insignificant sum. You'd better have some good simulation models that will run your application code before you tape out a mask set.

Point 7: Process variations can occur across a single die at the 65nm node, which means that more functional chips can be out of spec. To weed these out, you will need more at-speed testing, which means more built-in self testing (BIST) because otherwise, you can count on leaving these chips on testers for an hour apiece. Do you have a plan to add BIST to your designs? You'd better.

All of these issues are addressed by processor-centric SOC design. If you haven't yet read Engineering the Complex SOC by Chris Rowen and Steve Leibson, this would be a good time to do so. We keep a nice writeup on the book on the Tensilica Web site if you need more information.

Rumors of RISC's demise somewhat premature

2005-07-11T15:28:00.000-07:00

This week in EE Times, Ron Wilson writes about a keynote given by MIPS CEO John Bourgoin lamenting the demise of RISC processors (MIPS' main product). When the idea of RISC's clock-per-instruction concept started in the 1980s at IBM, processor clock cycles and memory access times were near parity so the RISC concept made sense for minicomputer and mainframe processor design. RISC processor design eschews complex, multiclock processor instructions and essentially replaces microcode ROM with single-cycle instruction RAM caches and optimizing compilers.

Even the most successful CISC instruction set ever invented, that of the 8086 microprocessor and its descendants, became "RISC-ified" in the 1990s. Inside modern x86 processors, an instruction chopper/shredder (see the end of the movie "Galaxy Quest" for a vivid visualization of this device) finely slices the CISC x86 instructions into simpler operations that are then distributed to one or more RISC engines hidden deep inside the machine.

Today's problem with the RISC concept, which Wilson addresses, is that memory access time is now much slower than today's processor clock cycle times, at least for DRAMs. The result is a heavy reliance on increasingly large SRAM caches that continue to keep up with processor clock rates, barely.

However, this situation is not strictly the fault of RISC's pipelined one-instruction/clock approach. The problem is caused by another RISC fault, the reduction in the number and complexity of instructions to a basic set of less than 100 instructions. Compilers can indeed create instruction streams that perform complex tasks from these simple instructions, but it takes a lot of instructions to do so. If complex programs require many instructions to function, then they need larger caches and higher clock rates to meet performance goals. Larger caches and higher clock rates ultimately increase product cost.

Enter post-RISC configurable processors. With such processors, design teams can add specialized, task-specific instructions to the processor that function like CISC instructions (by doing complex things) but adhere to RISC's pipelined, one-instruction/clock approach. These processors work well as deeply embedded task engines inside of SOCs where task specificity is easy to define and appropriate to use. In such applications, programs are typically small and do not require large caches. In addition, specialized instructions reduce the number of instructions needed to perform the target tasks, which relieves the pressure to constantly boost clock rate.

In short, RISC (like the dinosaurs) isn't dead, it has evolved.

Go to the Processor Forum, now!

2005-05-06T16:57:00.000-07:00

Anyone working on SOC development needs to know about the latest advances in processor technology and design. The place to get a concentrated dose of processor education is the upcoming Spring Processor Forum, held in San Jose at the Doubletree Hotel this year on May 16-19. Go sign up. Tell 'em Steve sent you.

Wim Roelandts: ASICs will never die

2005-05-06T13:38:00.000-07:00

For a good interview with Wim Roelandts, CEO of Xilinx, check out this article written by Ed Sperling at Electronic News. Instead of the usual FPGA bravado about taking over the world, Roelandts gives a very realistic picture of the FPGA versus ASIC design decision process as well as a good summary of Moore's Law and its immediate future.

The humbling elegance of butterfly navigation

2005-05-06T09:08:00.000-07:00

Two scientists at the University of Massachusetts Medical School have discovered how Monarch butterflies navigate over thousands of miles between the US and Mexico during their annual migrations. The butterfly's eyes contain photoreceptors that are tuned to receive polarized UV light from the sun. These receptors are directly linked via neural fibers to a region of the butterfly's brain called the dorsolateral protocerebrum, which contains a circadian clock that controls the butterfly's metabolic cycles. By neurally combining the time of day and the incident angle of UV light from the sun, the Monarch's brain computes a compass heading in real time.

The next time you think you've designed a really "hot," complex embedded system, consider how difficult it still is for human designers to develop something as elegant and complex as the Monarch's migratory navigation system. Also, consider how you'd power such a system on fruit nectar and water.

More advice on designing multiprocessor SOCs

2005-05-06T07:48:00.000-07:00

Earlier today, I wrote up Jack Ganssle's article on the software aspects and advantages of multiprocessor SOC design. TI Principal Fellow Gene Frantz has written up some good guidelines on how to develop multiprocessor SOCs in EE Times. Worth a look.

Build complex SOCs faster and cheaper

2005-05-06T07:35:00.000-07:00

I've written before about the great articles authored by my good friend Jack Ganssle. He's a very popular engineer/writer with a better handle on embedded software issues than anyone else in the business. His latest article in Embedded Software Programmaing magazine, Subtract Software Costs by Adding CPUs, provides real meat in the form of quantitative substantiation to a gut feel that I've had for a while. Specifically, Ganssle's numbers show that you can get a system-level project out the door a lot faster by chopping the software into manageable pieces and assigning the pieces to a number of independent, intercommunicating processors.

There are many advantages to this approach. First, each piece of software can be written by a much smaller design team with much less communications overhead between team members. Second, you don't need one monster processor running at multiple gigahertz to execute all the code. Several smaller, slower processors can do the job in a less costly IC fab process and at much lower power. And third, this approach seems to cut the bug rate on embedded code.

RAW deal—duel of the digicam file formats

2005-04-27T09:07:00.000-07:00

As the “digitization of everything” continues at breakneck speed, one of the real success stories is the rapid replacement of film cameras with digital versions. At the top of the digicam pyramid reside the digital SLRs (“dSLRs”) made by Canon, Nikon, Olympus, Pentax, etc. Although almost all digicam’s produce images in standard file formats (JPEG and/or TIFF), the dSLRs can also record images in an uncompressed format known as “RAW.” Photo professionals and top-end photo enthusiasts prefer the RAW format because it can produce pictures with the greatest resolution and color depth and it avoids all compression artifacts. However, every digicam vendors’ RAW format is proprietary and different.

Consequently, every digicam vendor that makes cameras with RAW file capability must offer a proprietary RAW converter program so that their RAW images can be converted to the standard file formats at some point. In addition, vendors of image-editing and image-manipulation programs such as Adobe, Bibble Labs, and DxO offer their own homegrown RAW converters, but not for every camera.

As dSLRs evolve, the problem of proprietary RAW formats grows and the professionals and enthusiasts in the dSLR market are increasingly up in arms about proprietary formats. Most recently, Nikon has marketed itself straight into the crosshairs of what may well turn out to be a shooting war. Nikon has drawn fire because it is encrypting the white-balance data in its RAW files (called Nikon Electronic Format or NEF files) from the Nikon D2X and D2Hs dSLRs (as reported in dpreview.com, the Engadget blog, ). This encryption effectively cripples third-party image-processing programs and forces users of those two cameras to employ Nikon’s own Nikon Capture program (sold separately). Nikon has an SDK that converts NEF files into standard image files that can be processed by third party programs. Nikon says it will license the SDK to what the company calls “bona fide” software developers, but the encryption has been cracked by at least two developers, although such actions may open the third-party developers to prosecution under the Digital Millennium Copyright Act (DMCA).

There are some signs of sanity on the horizon. One of the first is the openRAW project, an attempt to get digicam manufacturers to openly document their RAW formats for the benefit of the entire photographic industry. Adobe is taking a different tack, trying to drum up support for a universal RAW format that it introduced last year called the Digital Negative (DNG) format, which is based on the TIFF 6.0 standard. Here’s hoping the imaging mavens wake up sooner rather than later.

Shoe Biz Redux

2005-04-26T16:51:00.000-07:00

Last month, I wrote about German shoe maker Adidas' new, $250, computerized Adidas 1 running shoes that automatically and continuously adjust the shoes' cushioning based on the runner's gait. Each shoe has a 5-MIPS processor in it (presumably there's a left processor and a right processor). Each processor accepts feedback data from a magnetic impact sensor, computes the "optimal" amount of cushioning using a "proprietary" algorithm, and drives a small electric motor that adjusts the shoe accordingly. It turns out that a real runner can feel the difference. For a positive, hands-on (feet-on?) review of the Adidas 1 shoes, see Frank Bajak's MSNBC article online.

For a nice exploded diagram and technical explanation of the shoe, click here.