Researchers Demonstrate a Practical Path Toward Stacked Silicon Logic Chips

The semiconductor industry has spent years discussing the promise of monolithic 3D integrated circuitsA semiconductor technology that stacks multiple layers of silicon transistors vertically within a single chip to increase density and performance.. The concept is straightforward: instead of arranging transistors side-by-side across a flat silicon surface, stack multiple layers of transistors vertically. The result could be dramatically higher transistor density, shorter signal paths, reduced power consumption, and significantly more computing capability within the same chip footprint.

The challenge has never been the idea itself. The challenge has been manufacturing.

Researchers at the University of Illinois Urbana-Champaign recently reported a breakthrough that may help overcome one of the biggest barriers to practical 3D silicon chips. Their work, published in Nature, demonstrates a method for stacking multiple layers of silicon transistors while avoiding the high-temperature processing that traditionally damages circuitry already fabricated on lower layers.

Why Technology is Chasing 3D Chips

For decades, the semiconductor industry has relied on shrinking transistor dimensions to improve performance and efficiency. However, as process technologies approach physical limits, continued scaling becomes increasingly expensive and difficult.

Three-dimensional integration offers an alternative path forward.

Instead of making transistors smaller, engineers can build upward. Similar to constructing a skyscraper rather than expanding horizontally, multiple layers of circuitry can occupy the same footprint while providing substantially more computing resources.

The approach has attracted interest for applications ranging from AI accelerators and advanced processors to next-generation memory technologies. Readers familiar with 3D NAND flash memory will recognize a similar concept of building upward rather than outward, although the new research focuses on stacking logic transistors rather than memory cells.

The Problem They Are Trying To Solve

Traditional silicon transistor fabrication requires process steps that involve temperatures exceeding several hundred degrees Celsius.

When building a second or third transistor layer above an existing circuit, these temperatures can damage the completed structures underneath.

Previous research attempted to address this issue by replacing silicon with alternative semiconductor materials that can be processed at lower temperatures. While these approaches reduced thermal stress, they often sacrificed performance, limiting their commercial appeal.

The Illinois team chose a different strategy.

Instead of abandoning silicon, they found a way to continue using it.

Thin-Silicon Might Become The Solution

The researchers developed ultra-thin silicon sheets approximately 10 nanometers thick.

To appreciate how thin this is, a human hair is typically around 80,000 to 100,000 nanometers wide.

These silicon filmsUltra-thin layers of silicon used in advanced semiconductor manufacturing for stacking transistors vertically. are peeled from a specially prepared substrate and transferred onto an existing chip structure using a rolling transfer process. The entire operation occurs at temperatures below 200°C, well within the safe thermal limits of previously fabricated circuitry.

Once transferred, the team creates transistor structures using a design that avoids the high-temperature processing normally associated with conventional silicon devices.

The result is a multi-layer silicon architecture that preserves the performance advantages of traditional silicon technology while meeting the temperature requirements of monolithic 3D integration.

Is the Tape the Breakthrough?

One aspect of the research that attracted attention was the mention of adhesive tape being used to separate the ultra-thin silicon sheets from their source substrate.

At first glance, this may sound like the central innovation. It is not.

The tape functions primarily as a transfer mechanism. Similar transfer techniques have been used in various advanced materials applications for years.

The true breakthrough lies elsewhere:

• Producing silicon layers thin enough to be transferred without damage
• Maintaining high-performance silicon characteristics
• Performing the transfer at temperatures compatible with existing circuitry
• Achieving the precision required for multi-layer chip fabrication

The adhesive simply helps move the silicon from one location to another.

In commercial production, the transfer mechanism could eventually evolve into a different process entirely while preserving the core technology.

Alignment Is Everything For 3D Chips

Perhaps even more impressive than the transfer process is the reported alignment accuracy.

According to the researchers, successive silicon layers can be aligned within less than 10 nanometers.

This detail may prove more significant than the transfer method itself.

Modern integrated circuits rely on billions of precisely positioned features. When multiple transistor layers are stacked, electrical connections must line up with extraordinary accuracy. Even slight misalignment can prevent circuits from functioning correctly.

Achieving sub-10-nanometer alignment suggests the process may be capable of supporting the dense vertical interconnections required by future commercial devices.

While the research paper does not fully detail every alignment technique used, semiconductor manufacturing typically employs alignment marks, high-resolution optical systems, nanometer-scaleRefers to dimensions or structures measured in nanometers, typically on the order of billionths of a meter. positioning stages, and advanced lithography methods to achieve this level of precision.

The flexibility of the ultra-thin silicon sheets may also contribute by allowing them to conform closely to the underlying surface, reducing mechanical imperfections during placement.

Prelim Results

To validate the concept, the team fabricated working three-layer memory structures.

According to the researchers, the stacked design reduced circuit area by as much as three times compared with an equivalent planar implementation.

The fabricated devices also demonstrated electrical characteristics comparable to conventional silicon transistors, suggesting that performance need not be sacrificed to achieve three-dimensional integration.

So What Is Next?

Although the results are promising, significant challenges remain before the technology reaches commercial production.

Laboratory demonstrations are typically performed on relatively small samples under carefully controlled conditions. Semiconductor manufacturers must eventually scale the process to large production wafers while maintaining yield, reliability, throughput, and cost targets.

Nevertheless, the research represents an important milestone.

The semiconductor industry already possesses decades of expertise, manufacturing infrastructure, and supply chains built around silicon.

The industry’s experience scaling vertically stacked memory devices provides some confidence that complex three-dimensional manufacturing can eventually reach production. Recent examples include Micron’s 232-layer 3D NAND technology, which demonstrated how aggressively modern semiconductor manufacturers can scale vertical structures.

A successful path toward monolithic 3D circuits that preserves silicon compatibility could be considerably more attractive than transitioning to entirely new materials.

For now, the work serves as an encouraging indication that the future of chip scaling may not depend solely on making transistors smaller. Instead, the next major leap in computing performance could come from stacking silicon circuits vertically and transforming today’s flat chips into true three-dimensional systems.

As AI workloads, high-performance computing, and data center demand continue to grow, advances such as these may ultimately determine how much additional performance the semiconductor industry can deliver in the decade ahead.

3D Chip Overview – Image

Monolithic 3D Silicon Chip Fabrication Process

Micron Briefly Crosses the $1 Trillion Valuation Mark

Today was a major moment for the memory industry as Micron Technology (NASDAQ: MU) briefly traded above a $1 trillion market capitalization during intraday trading.

The move reflects how dramatically the perception of memory companies has changed over the last couple years. Historically, NAND and DRAM manufacturers were viewed as cyclical commodity suppliers. Today, investors are increasingly treating memory as critical AI infrastructure.

Much of the momentum behind Micron comes from explosive demand for HBM (High Bandwidth Memory), which has become one of the key bottlenecks in AI server design. Reports indicate Micron’s HBM production for 2026 is already sold out as hyperscale AI deployments continue ramping worldwide.

The shift is important because memory bandwidth is now nearly as strategic as the GPU itself. AI workloads are no longer limited only by compute power. Moving data quickly between processors and memory has become equally important.

Analysts also pushed Micron higher after increased price targets and stronger outlooks tied to AI infrastructure spending. While the company did not officially close above the trillion-dollar threshold, simply reaching that level during trading represents a symbolic shift for the broader memory industry.

For anyone who has followed NAND, DRAM, SSDs, and flash memory over the past two decades, today’s trading activity feels like another sign the market no longer views memory as a background component. Memory has become part of the AI story itself.

Related Reading

• Micron On A Stock Price Run – AI To Thank?
• Memory Stocks Are Rallying, But The Market Is Pricing A Longer Shift

Samsung Strike Threat Explained: Why the World’s Largest Memory Chip Maker May Walk Off the Job

Samsung is facing one of the biggest labor disputes in its modern history, and even people outside the tech industry are starting to notice. The reason is simple: Samsung is not just a phone company. It is one of the largest producers of memory chips in the world, and those chips now sit at the center of the artificial intelligence boom.

The company is currently dealing with a possible 18-day strike in South Korea involving tens of thousands of workers. While negotiations are still ongoing, the situation has become serious enough that investors, governments, and the technology industry are all watching closely.

For someone outside the semiconductor industry, the headlines can feel confusing. Is this about factory workers? Engineers? Phones? AI? Politics? The answer is a little bit of everything.

What Is Actually Happening?

The strike threat is centered around Samsung Electronics employees in South Korea, particularly workers connected to the semiconductor division. That includes chip fabrication employees, technical staff, engineers, support teams, and some office workers tied to semiconductor operations.

The key issue is compensation.

Samsung workers believe the company benefited enormously from the recent AI surge and growing demand for memory chips, especially products used in AI servers and data centers. Employees argue those profits are not being fairly shared through bonuses and incentive programs.

A major source of frustration comes from comparisons to SK Hynix, Samsung’s largest Korean memory rival. SK Hynix has become one of the biggest suppliers of High Bandwidth Memory, better known as HBM, which is the ultra-fast memory technology used alongside AI processors.

From the workers’ perspective, Samsung is participating in the AI boom while employees feel left behind financially.

Why This Matters More Than a Typical Labor Strike

Most people hear the word “strike” and think about automotive factories, shipping docks, or airlines. Semiconductor manufacturing is different.

Modern chip fabrication facilities operate almost like giant automated laboratories. The buildings are filled with robotic handling systems, wafer processing tools, clean rooms, and highly specialized production equipment that runs around the clock.

Even though much of the process is automated, semiconductor fabs still rely heavily on skilled engineers and trained technical staff to monitor, calibrate, troubleshoot, and maintain operations.

That is especially true for advanced memory production.

• DRAM memory
• NAND flash memory
• Enterprise SSD components
• High Bandwidth Memory used in AI servers

Those products feed directly into AI servers, cloud computing, smartphones, laptops, gaming hardware, and enterprise storage systems.

In other words, this is not a strike at a local appliance factory. These are workers tied to one of the most important supply chains in the global technology economy.

Is Samsung Shutting Down?

Not at the moment.

As of now, the strike has not officially started. Negotiations are still taking place between Samsung management and union leaders. Current reports say Samsung and the union are expected to resume pay talks with a government mediator, while the union has continued to warn that a strike may proceed if meaningful progress is not made.

However, Samsung is reportedly preparing contingency plans inside some manufacturing facilities in case operations are disrupted. That alone tells you Samsung believes the threat is credible.

At the same time, semiconductor manufacturing is highly automated, so even a large labor action may not completely stop production. Some operations may continue, but output, efficiency, maintenance response, and production scheduling could still be affected.

The larger concern is not necessarily a total shutdown. The concern is reduced output, slower production ramps, delayed shipments, and uncertainty during a period when AI-related memory demand is already extremely high.

Samsung Has Not Historically Been a Union Company

One reason this story is getting attention in South Korea is because Samsung spent decades with a reputation for being strongly anti-union.

For years, large-scale labor actions at Samsung Electronics were extremely rare. That changed in 2024 when Samsung workers staged the company’s first meaningful strikes in modern history.

• A one-day walkout in June 2024
• A three-day strike in July 2024
• Later threats of indefinite labor action

While those earlier strikes caused headlines, the impact was relatively limited compared to what could happen now.

The difference today is timing.

The AI industry has exploded. Demand for advanced memory is surging. Samsung is trying to compete aggressively in HBM and advanced semiconductor packaging, and the global market is watching every move the company makes.

That gives workers far more leverage than they had only a few years ago.

Market Impact: Why an 18-Day Strike Could Last Longer Than 18 Days

The most important market point is this: an 18-day semiconductor strike does not always equal only 18 days of lost production.

Memory production is not like stopping and restarting a packaging line. NAND flash, DRAM, and HBM production involve long manufacturing cycles, clean-room controls, tool scheduling, wafer movement, testing, binning, and quality validation. If a fab slows down or reduces output, the lost time can ripple forward.

That means the market impact could come from two directions at once.

• First, fewer wafers and finished memory products may be produced during the strike window.
• Second, even after a settlement, Samsung may need additional time to normalize tool flow, staffing, inspection, testing, and shipment schedules.

So while the strike threat is being discussed as an 18-day event, the real supply impact could extend beyond those 18 days. If production tools are slowed, schedules are rearranged, or wafer starts are reduced, the market may feel the delay later in the form of tighter NAND availability, slower SSD shipments, or firmer memory pricing.

This does not automatically mean a memory shortage will happen. Samsung has inventory, customers have supply agreements, and semiconductor companies plan for disruption. But NAND is a high-volume, timing-sensitive market. When one of the world’s largest memory suppliers faces labor uncertainty, buyers pay attention.

The NAND market could be hit especially hard if the strike overlaps with strong demand from AI storage infrastructure, enterprise SSD orders, mobile device production, or data center purchasing cycles. Even a temporary disruption can become meaningful when the entire supply chain is already running tight.

Readers interested in broader NAND pricing trends can also review our article about memory chip prices spike and how supply discipline has already been tightening the market before this labor situation developed.

For readers newer to flash storage technology, our overview explaining 3D NAND flash memory provides additional background on how modern memory is manufactured and why advanced fabrication facilities are so difficult to pause and restart.

Bottom line: the strike itself may be scheduled for 18 days, but the production effect could last longer. In the memory business, lost fab time does not always come back cleanly the next morning.

The Bigger Picture

This labor dispute is also a reminder of how central semiconductors have become to the modern economy.

A decade ago, a memory chip strike in South Korea might have been viewed as a niche manufacturing story. Today, it affects discussions around AI infrastructure, GPU supply chains, cloud computing growth, enterprise server deployment, memory pricing, and global technology competition.

Put simply, AI systems cannot scale without memory.

Companies like NVIDIA may receive most of the public attention, but advanced memory suppliers like Samsung and SK Hynix have become equally important behind the scenes.

That is why this labor dispute matters well beyond South Korea.

The final outcome is still uncertain. The strike may be avoided through negotiations, reduced to a partial walkout, or delayed by government intervention. But regardless of what happens next, one thing is already clear: Samsung’s labor environment has fundamentally changed, and the semiconductor industry is entering a period where workforce pressure now carries real global economic weight.

Why legacy USB boot support is more about BOT than cylinder and head count

Every so often, a customer will ask about cylinder countA legacy hard drive parameter representing the number of cylindrical tracks on a disk platter., head count, or sector configuration for a USB flash drive. The question usually comes from someone working with older hardware, embedded systems, industrial equipment, BIOS-level booting, or legacy imaging software.

The question makes sense. For decades, hard drives were described using cylinder, head, and sector values. That was how older systems understood where data lived on a spinning disk.

But USB flash memory is not a hard drive.

A hard disk has platters, tracks, and read/write heads. NAND flash does not. Flash memory is organized around pages, blocks, controllers, firmware, error correction, bad block handling, and wear leveling. The USB device may appear to the computer as a “disk,” but inside the device, the storage method is completely different.

This is why most USB flash mass production tools do not provide a setting for cylinder count or head count. Those settings come from the hard disk world. They do not describe the physical structure of NAND flash memory.

In modern flash media, the controller presents storage to the host using logical block addressing. In plain English, the host computer asks for logical storage locations, and the controller decides where that data actually lives inside the NAND. The controller may report compatibility values when needed, but those values are usually translated or simulated. They are not physical geometry.

So if the real goal is boot compatibility on older systems, cylinder and head count are usually not the right place to focus.

The better question is whether the USB device is using BOTBOT (Bulk-Only Transport) and UASP (USB Attached SCSI Protocol) are two USB data transfer methods, with UASP providing faster speeds and more efficient communication than the older BOT standard. or UASPBOT (Bulk-Only Transport) and UASP (USB Attached SCSI Protocol) are two USB data transfer methods, with UASP providing faster speeds and more efficient communication than the older BOT standard..

BOT stands for Bulk-Only Transport. It is the older and more widely compatible USB mass storage method. It has been around for many years and is what most legacy BIOS environments, older boot systems, industrial equipment, and simple embedded platforms expect when they try to boot from USB.

UASP, or USB Attached SCSI Protocol, is the newer method. It is generally faster and more efficient, especially for SSD-style storage and modern operating systems. But faster does not always mean more compatible. UASP was built for newer storage behavior, not for the broadest possible legacy boot support.

That is the key point.

When someone asks about cylinder and head count, the underlying concern is usually not really geometry. The real concern is, “Will this USB drive boot in my older system?”

For that question, BOT is usually the more important factor.

Trying to manipulate cylinder and head count on NAND flash media is often chasing the wrong setting. In many cases, the controller tool does not expose those values because they are not meant to be manually configured. The flash controller handles the logical translation internally.

By contrast, the USB transport behavior can have a real impact. A legacy BIOS or embedded device may understand BOT and fail to recognize or boot properly from a UASP-based device. That does not mean UASP is bad. It simply means UASP is not always the best match for older boot environments.

A good way to think about it is this:

Cylinder and head count describe an old physical disk layout. BOT describes how the USB storage device communicates with the host.

For NAND flash, the communication method is usually more important than old disk geometry.

This is especially true when dealing with industrial equipment, medical devices, kiosks, test systems, bootable utilities, or older PCs. These systems often care less about maximum transfer speed and more about predictable, simple USB mass storage behavior. BOT gives them the familiar path they were designed to understand.

There can always be exceptions. Some systems are picky about partition style, boot sector layout, file system format, removable versus fixed disk reporting, or how the image was written to the device. However, in most cases, if the conversation starts with cylinder and head count, the practical answer is to step back and check the USB mass storage transport first.

We covered the technical differences between BOT and UASP in a separate article on GetUSB.info called Why Some USB Devices Use BOT While Others Use UASP.

Another related topic is how some flash devices can emulate or report themselves differently to the operating system. Our article about using microSD cards as a hard drive also touches on how flash storage can behave differently depending on the controller and configuration.

For USB flash memory, cylinder and head count are mostly legacy terms. They belong to the hard drive era. NAND flash does not have cylinders or heads, and most modern controller tools are not going to expose those settings because there is nothing physical to configure.

For legacy boot support, focus on BOT over UASP. That is usually the setting that matters more.

Pro Tip:

If your legacy BIOS or industrial hardware won’t boot, don’t hunt for cylinder settings. The issue is likely the transport protocol. Focus on using a drive configured for BOT (Bulk-Only Transport), as most older systems cannot communicate with the newer UASP protocol.

When Micron Technology and SanDisk post gains of this magnitude — 500%+ and 3,000%+ respectively — the first instinct is to call it a cycle.

That’s been the right instinct for years.

Memory has always moved in waves. Supply comes online, pricing collapses, demand absorbs it, then the process resets.

But what’s happening now doesn’t fit that pattern as cleanly as before.

The market isn’t just reacting to strong demand. It’s starting to price in durability.

Analysts Are Stretching the Timeline

The most important signal isn’t the price targets being raised. It’s how far out the conversation is moving.

When analysts begin talking about demand staying strong “through the end of the decade,” that’s not a short-term call. That’s a structural one.

You typically only see that kind of language when three things line up at the same time:

• Demand is visible and sustained
• Supply can’t respond quickly
• Buyer behavior starts to change

All three are in play right now.

Buyer Behavior Is Quietly Shifting

The clearest signal isn’t coming from stock charts. It’s coming from contracts.

Large buyers — especially hyperscalers — are locking in memory supply years in advance. In some cases, three to five years out.

That’s a different mindset.

Historically, memory buyers stayed flexible. They played pricing cycles. They avoided long-term commitments whenever possible.

That strategy works when supply is predictable.

It doesn’t work when supply becomes the risk.

Companies like Broadcom securing memory through 2028 isn’t about cost optimization. It’s about access.

And once access becomes the priority, the market starts to behave differently.

Supply Still Moves on a Multi-Year Clock

On the supply side, nothing has sped up.

Building new memory capacity still takes years. Not quarters.

Micron Technology is investing tens of billions across multiple regions. SK Hynix and Samsung Electronics are expanding as well.

But those fabs don’t come online immediately. They arrive years after the decision is made.

That delay matters.

Because demand — largely driven by AI infrastructure — is accelerating now, not later.

Pricing Power Is Starting to Look Different

One of the more interesting shifts is how analysts are talking about margins.

“Durability” isn’t a word typically associated with memory pricing.

But if demand holds, supply stays tight, and buyers commit long-term, pricing stops behaving like a short spike.

It starts to look more stable.

That’s what the market is trying to reconcile.

The Effects Are Already Showing Up Downstream

You don’t need to follow equity research to see the impact. It’s showing up in everyday pricing.

• PC prices are expected to rise meaningfully
• Solid-state drives now cost two to three times what they did just months ago
• Electronics pricing is adjusting across the board

Those changes don’t happen in isolation. They reflect upstream constraints working their way through the system, something we’ve already seen building in this earlier analysis on AI-driven memory pricing pressure.

There Are Still Risks — And the Market Knows It

This doesn’t mean memory has suddenly become stable or predictable.

There are still real risks in the system:

• AI spending could slow
• New capacity could arrive faster than expected
• Long-term contracts could overshoot actual demand

Memory doesn’t stop being cyclical overnight.

But the shape of those cycles may be changing.

From the Market Desk

The tone shift is the part worth paying attention to.

Analysts aren’t just reacting to quarterly results. They’re starting to frame memory as a strategic layer tied directly to AI infrastructure.

That moves the sector into a different category.

And markets tend to reprice categories when that shift becomes clear.

Final Take

The takeaway isn’t that memory is “hot.”

It’s that the market is beginning to treat memory less like a commodity and more like a constrained resource with long-term importance.

That doesn’t remove cycles. But it does change how those cycles behave — and how investors respond to them.

If the current trajectory holds, the next few years won’t look like the last two decades of memory markets.

And that’s what this rally is really trying to price in.

CAMM2 is what happens when laptop memory stops swiping and starts tapping

CAMM2 stands for Compression Attached Memory Module 2, and even the name tells you what makes it different. This is not the usual stick of laptop RAM sliding into a socket at an angle. CAMM2 is a flatter memory module that sits against the motherboard and is pressed into place through a compression-style connection. It sounds like a small mechanical change, but it has bigger technical consequences than most people realize.

The fun way to think about CAMM2 is through the old credit card payment process. Traditional laptop memory, especially SO-DIMM, is like swiping a card. You make contact, it works, and for years that was good enough. But a swipe depends on a longer interaction path, older physical assumptions, and a design that starts to feel clumsy as speeds go up and form factors get thinner.

CAMM2 is more like tap-to-pay. The connection is flatter, cleaner, and more direct. You are not dragging the module through a longer slot path and hoping everything behaves nicely at higher frequencies. Instead, the memory makes broad, even contact with the board through compression. In engineering terms, that means shorter trace paths, cleaner signaling, better integrity at high speed, and a layout that works much better inside thin laptops.

That is the key point – CAMM2 is not exciting because it invents a new type of memory all by itself. It is exciting because it gives modern memory a better way to connect. When the electrical path is cleaner, the system can run faster, use less power, and avoid some of the routing penalties that older SO-DIMM designs bring along. The memory chips still matter, of course, but the interface suddenly stops being such a stubborn bottleneck.

This is also where the low-power version enters the conversation. LPCAMM2 is built around LPDDR memory, the same family known for efficiency and strong bandwidth in portable devices. Historically, if a laptop maker wanted those low-power benefits, the common tradeoff was soldered memory. That gave you efficiency, but no upgrade path. With LPCAMM2, the industry gets much closer to having both – low-power memory behavior with a modular design that can actually be serviced or upgraded.

Put simply, old laptop memory said: pick two – speed, thinness, or upgradeability. CAMM2 changes that conversation. It is still technical, still very much an interface story, but it fixes one of the most frustrating compromises in modern laptops. Nobody likes opening a machine and realizing the memory was permanently decided on the day it left the factory.

That is why CAMM2 matters. Not because it is flashy, but because it is practical. It takes the swipe-era thinking of laptop memory and replaces it with something closer to a tap – faster, neater, and built for where portable computing is already heading. If you want a broader look at how memory architecture is being pushed in modern systems, see our post on why the memory hierarchy is being stretched.

USB hardware dongles didn’t disappear – they moved into the environments where cloud licensing stops being dependable

That USB software donglesUSB-based devices used to enforce software licensing and control access. are obsolete is one of those ideas that sounds true if your whole frame of reference is SaaS, browser-based licensing, and systems that assume a permanent connection to something upstream. But once you step into controlled environments, secure networks, isolated labs, or industrial systems where a failed license check can shut down a perfectly functional workflow, that assumption falls apart in a hurry.

This perspective builds on an earlier editorial from GetUSB, which called the shift correctly. The cloud did not eliminate hardware dongles. It simply forced them into the places where physical control, predictable behavior, and independence from outside services still matter.

Cloud licensing solved convenience, but introduced fragility

Cloud licensing works very well when every layer underneath it is stable. That is the part people like. It is easy to provision, easy to update, and easy to manage from a distance. But what gets glossed over is that the license check is no longer a simple local event. It becomes a chain of dependencies tied to connectivity, authentication endpoints, certificates, policies, account state, and time synchronization. The software may be fine, the workstation may be fine, and the operator may be ready to work, yet access still fails because something external decided not to cooperate.

That is exactly why hardware-based licensing remains common in environments where uptime matters more than convenience. Air-gapped defense systems, laboratory instruments, secure engineering networks, and industrial control deployments do not care how elegant the cloud looks on a product page. They care whether the system starts when it is supposed to start. In those settings, removing outside dependency is not old-fashioned thinking. It is risk control.

The cloud did not replace dongles. It exposed where the cloud itself becomes the weak point.

The traditional dongle model never changed very much

What is interesting is not that dongles survived. It is that most traditional dongles stayed architecturally the same while deployment models around them evolved. Companies such as Thales with Sentinel and Wibu-Systems with CodeMeter built serious ecosystems around hardware authentication, and those ecosystems remain proven for good reason. They are mature, deeply integrated, and trusted in places where software protection has to be enforceable.

But the underlying pattern is familiar. A dedicated chip answers an authentication request, the application validates the response, and the software decides whether to proceed. That model works, but it comes with baggage. It typically means SDK integration, runtime support, and a tighter dependency on the vendor’s development path. The dongle becomes a single-purpose object whose job is to answer one question – is this license valid?

That made sense when software delivery and software enforcement were treated as separate problems. It makes less sense when the USB device itself is often part of the deployment method.

The shift is subtle, but it changes what the device actually does

What is changing now is not the need for hardware enforcement. What is changing is the role of the device inside that enforcement model. Nexcopy’s approach is different because it does not treat the USB device as a passive token alone. It treats the device as a controlled storage environment, which is a much more interesting idea once you understand the implications.

Instead of simply validating access at the application layer, the device participates in what happens to the data from the moment it is connected. It can be configured around controller-level behavior, read-only states, partition rules, and usage control in a way that moves enforcement closer to the hardware itself. That is a different posture than the old challenge-response model because the device is no longer just proving identity. It is helping define behavior.

That is a better fit for real-world USB workflows, where the same physical device often carries software, content, updates, or controlled material that must be distributed while also being protected.

Storage and enforcement are starting to converge

Traditional dongles separate delivery from validation. One piece of hardware says the user is allowed in. Something else handles the actual content or software package. But when the USB device itself becomes the delivery medium, that separation starts to look inefficient.

What makes the device-level model worth paying attention to is that storage and enforcement begin to converge. The same medium can carry the application or data set while also defining what the host system is allowed to do with it. That reduces some integration burden in certain deployment cases, simplifies how controlled media is distributed, and shifts security policy closer to the controller layer rather than leaving everything to software hooks and external checks.

That does not mean encryption goes away, and it does not mean traditional licensing stacks become irrelevant. It means there is now a more practical middle ground for deployments that need control without dragging in an entire cloud or entitlement framework.

Different models solve different problems

There is no reason to pretend one approach replaces the other. Traditional dongle ecosystems are still the right answer where centralized entitlement management, floating licenses, and deep application integration are required. Those platforms were built for that job and they continue to do it well.

But device-level USB enforcement fits a different category of need. Controlled media distribution, offline validation, simplified deployment, and environments where the physical device is part of the workflow all benefit from this model. These are not fringe use cases. They are simply less visible to people who think software distribution begins and ends with a login screen.

The real change is moving from license validation to hardware control

For years, the dongle category was defined by one narrow question – can this key prove the software is authorized? That is still important, but it is no longer the whole conversation.

The more relevant question now is what the device allows once it is attached. What can be read, what can be copied, what can be modified, and what is locked down before the operating systemSoftware that manages hardware resources and provides services for computer programs. or application layer ever gets involved. That is a broader and more useful model of enforcement because it reflects how USB hardware is actually used in the field.

That is why hardware dongles did not die. They matured into a narrower, more serious role. And in that role, they may be more relevant now than they were when everyone assumed the cloud was going to replace them entirely.

Yes, Researchers Are Trying It, but No, It’s Nowhere Near Ready for Real-World AI

Every so often a technology story comes along that sounds like science fiction got tired of waiting and decided to show up early.

That is pretty much what happened with the recent headlines about a company growing human neurons on computer chips and talking about “biological computers” and even “biological data centers.” On paper, it sounds wild. In practice, it is still wild, but in a much more grounded, early-stage, scientific-lab kind of way.

The company behind the attention is Cortical Labs, an Australian biotech startup working on what it calls a biological computer. Their system uses living human neuronsHuman nerve cells grown in a lab that can be connected to electronic chips to study and utilize their electrical activity. grown on a chip, then connected to electronics that can both stimulate the cells and measure how they respond. The dramatic version of the story is that this could someday change computing. The realistic version is that this is a fascinating research platform that may eventually find a place in specialized computing, but it is nowhere near replacing conventional AI hardware.

That difference matters, because this is one of those stories where the headlines can sprint a lot faster than the actual science.

First, what is this thing supposed to be?

The basic setup is simpler than it sounds. Researchers take living neurons, place them on a chip, and then use electronics to send signals into those cells and record the electrical responses coming back out. So it is not a human brain in a box. It is not consciousness in a server rack. It is a lab-grown network of neurons interacting with a piece of hardware.

If that still sounds like a movie prop, that is fair. But the underlying concept is real. Neurons communicate through electrical activity. Chips can measure electrical activity. So the idea is to build a bridge between biology and electronics, then see whether a living neural network can be guided into doing something useful.

That is the scientific question. The marketing question is whether this can become a new kind of computing platform.

Those are not the same question.

So are they literally gluing brain cells onto chips?

Not with a glue stick, no.

This was one of the funniest and most natural questions to ask, because when people hear “neurons on a chip,” they imagine someone in a lab with tweezers and adhesive doing arts and crafts with brain cells. The reality is more elegant than that.

Researchers usually prepare the chip surface with a biological coating that cells like to attach to. Think of it less like glue and more like making the surface hospitable. Once the surface is treated, neurons can settle onto it, stick, survive, and grow. Over time, they extend connections and form networks across the chip.

So the cells are not being glued down like hardware components. They are being cultured onto a surface designed to support them.

That small detail is actually important, because it tells you what kind of system this really is. It is not manufactured the way a traditional processor is manufactured. It is grown, maintained, and managed more like a biological experiment merged with an electronics platform.

That alone should tell you this is not your next graphics card.

How does a chip actually “read” a brain cell?

This is where the story gets much less mystical and much more understandable.

A chip is not reading thoughts. It is not reading a soul. It is not pulling ideas out of a neuron like a USB file transfer. What it is usually measuring is the electrical activity of the neuron itself.

Neurons work by moving ions across their membranes. When they fire, tiny electrical changes happen around them. If you place very small electrodes near those cells, the electrodes can detect those changes. That is the core idea behind a microelectrode array, which is one of the most common ways to build these systems.

So the process looks something like this: the neuron fires, the electrical environment around it changes, the nearby electrode senses that change, and the electronics amplify and record the signal.

That is a much more useful way to think about it. The chip is not reading one magic molecule inside a brain cell. It is listening for electrical activity from living cells sitting on or near the sensing surface.

In plain English, the chip is acting like a microphone for tiny biological electrical events.

Fine. But how would anyone control this enough to do useful work?

That is the big question, and it is also where a lot of the hype starts to thin out.

The chip does not control the cells the way a transistor controls current in a standard processor. It cannot simply command a neuron to calculate something. What it can do is control the environment around the neurons and influence how the network behaves over time.

That means sending electrical inputs into the network, measuring how the neurons respond, and then adjusting the next round of inputs based on those responses. In other words, it is a feedback loop.

This is why the better way to describe the system is not “programming cells” but “training a biological network.” The setup creates an artificial world for the neurons. The chip provides input. The cells react. The chip records that reaction. Then software changes the input again. After enough rounds, the network may begin to respond in a more useful or consistent way.

That is not the same as programming a GPU. It is closer to conditioning a living system.

This is also why these demos often involve games. A game creates a closed loop. The neurons receive signals representing a changing environment, and researchers can study how the network adapts. That is interesting science. It does not automatically mean the same system is ready to handle enterprise AI workloads.

Could this replace AI computing?

Honestly, no. Not anytime soon.

That does not mean the work is fake. It means the gap between “this is scientifically interesting” and “this can replace Nvidia hardware” is enormous.

Modern AI systems depend on precise, scalable, repeatable math. GPUs are great at that. They do massive amounts of matrix calculations quickly and consistently. A living neuron culture is almost the opposite. It is adaptive, messy, variable, delicate, and influenced by biological conditions that are much harder to standardize than silicon.

That can be a feature in a research lab. It is a problem in a production data center.

So when you hear that biological computing could someday reduce power consumption or handle certain tasks differently, that is worth watching. But when you hear it framed as if racks of wetware are about to shove conventional AI chips out the door, that is where the brakes need to come on.

This is not going to replace Nvidia anytime soon.

That line is not meant as a cheap joke. It is the most grounded takeaway from the whole story. The current public evidence suggests this field is in the very early stage of development. Interesting demos, interesting possibilities, real science, yes. Practical replacement for large-scale AI infrastructure, no.

Then what might it actually be good for?

This is where the conversation gets more interesting, because “not a replacement” does not mean “useless.”

A system like this may eventually prove useful in narrow areas where adaptation, low-power response, or biological realism matters more than raw computational horsepower. It could become valuable as a research platform, a neuroscience tool, a testing environment, or a specialized kind of hybrid processor for certain closed-loop tasks.

That is a very different role than replacing mainstream AI compute.

And that is okay. New technologies do not have to overthrow everything to matter. Plenty of important technologies started out looking impractical because people kept judging them against the most mature tools in the room.

At the same time, that does not mean every strange new platform deserves automatic faith. A healthy reaction here is curiosity mixed with skepticism. That is probably the right balance.

A simple example helps

Imagine you want a system to sort something into two buckets, like A or B.

A conventional AI system would convert the input into numbers, run it through a trained model, and produce an answer. Clean, fast, and repeatable.

A biological chip setup would be far less direct. The input would be turned into a pattern of electrical stimulation across the chip. The neurons would respond. The system would record the response pattern. Then software would interpret whether that response looks more like A or B. Over many rounds, the feedback loop would try to nudge the network toward more consistent behavior.

So even in that simple example, the living cells are not replacing the whole computing stack. The digital system is still doing a lot of the heavy lifting. The neurons are more like an adaptive layer inside the loop.

That is why the phrase “biological computer” sounds more complete than the reality probably is right now.

Why people are paying attention anyway

Part of the excitement comes from power consumption. If a biological system could perform certain adaptive tasks while using very little energy, that would be a big deal. Conventional AI infrastructure uses huge amounts of power, cooling, and physical resources. Any serious alternative, even a narrow one, would get attention.

The other reason is simpler: it captures the imagination.

Human neurons on chips. Wetware. Biological data centers. This is headline fuel. It sounds futuristic because it is futuristic. It also sounds a little creepy because it is, at minimum, a little creepy. That combination tends to travel fast.

But after the dramatic phrasing wears off, the practical question remains the same: can it do useful work, reliably, at scale, and better than existing hardware in any meaningful category?

That question is still very much unanswered.

Our takeaway from all this:

The story here is not that human brain cells are about to take over AI computing. The story is that researchers are exploring whether living neural networks can be coupled to electronics in ways that create useful new forms of computation.

That is a real scientific effort. It is worth watching. It is also still early enough that people should resist the urge to turn every lab milestone into a Silicon Valley overthrow narrative.

The most honest summary is probably this: neurons on chips are fascinating, the underlying science is real, the demos are intriguing, the long-term possibilities are uncertain, and this is not replacing mainstream AI hardware anytime soon.

In other words, yes, it is a serious area of research.

No, you are not about to cancel your GPU order because somebody cultured neurons onto a chip with what definitely is not glue.

If you want a related read from our archive, this article on SLC flash memory is a good example of how emerging hardware topics often sound simpler than they really are.

A customer places an order for USB flash drives. The samples were approved. The controller was chosen. Capacity, performance, and cost all look fine. Then somewhere between quoting and production, the factory comes back with a revision:

“We want to switch the NAND.”

Maybe the original plan was Micron and now they want to use Intel-origin NAND. Maybe it is Kioxia to SK hynix. Maybe the explanation sounds simple: same capacity, same function, no issue.

That kind of change is not automatically a problem. In manufacturing, memory substitutions happen for real reasons. Supply gets tight. Lead times move. Pricing shifts. A preferred lot dries up. Sometimes the replacement is perfectly acceptable and the finished product performs exactly as expected.

Here’s the point: a NAND brand swap should never be treated like a casual purchasing note. It is a specification change.

That does not mean the customer should panic. It means the customer should ask better questions.

The first thing to understand is this: the brand name on the NAND is only one layer of the story. Two USB drives can both be sold as 64GB products, both work on day one, and still behave very differently in the field depending on the NAND generation, controller pairing, firmware tuning, lot consistency, and sourcing path behind the build.

So if a factory wants to move from Micron to Intel, or from one memory supplier to another, the smart response is not yes or no. The smart response is: tell me exactly what is changing.

Why Factories Request NAND Substitutions

This is normal manufacturing behavior. Flash memory is a commodity component, and the market moves around more than many buyers realize. A factory may be trying to hold your price, protect delivery, or work around a shortage. In some cases, the substitute memory may be every bit as good for the application. In other cases, the substitute may be older stock, a different NAND typeClassification of NAND flash memory based on cell architecture affecting performance, endurance, and cost., or a part that requires new qualification work.

That is why the request itself is not the red flag. The lack of detail is the red flag.

A careful factory should be able to explain the change clearly. A sloppy factory usually hides behind broad language like “equivalent memory” or “same spec.” Chances are, if that is all they can offer, they have not given the change the engineering review it deserves.

Brand Names Alone Do Not Tell You Enough

Micron and Intel are useful examples because most buyers recognize the names. Both have strong reputations in memory history, and both names can sound reassuring in a sourcing conversation. But the customer still needs more than a recognizable brand.

For example, “Intel memory” might mean older Intel-era inventory still moving through the market. It might mean Intel-origin technology that later moved under different corporate ownership. It might also just be factory shorthand that is too loose to evaluate properly. None of those possibilities are automatically bad. They are just different, and “different” needs to be documented.

The same goes for Micron. Seeing Micron on a parts list does not magically answer questions about endurance, lot date, controller compatibility, or long-term supply.

Bottom line: the label is not the qualification plan.

What the Customer Should Actually Ask

Here is the checklist a buyer, engineer, or product manager should walk through before approving a NAND substitution.

The Best Factories Do Not Resist These Questions

A good factory should not get defensive when a customer asks for this level of detail. In fact, a capable manufacturing partner should welcome it. These are not hostile questions. They are professional questions.

If a supplier can tell you the exact NAND part, explain why it was selected, show qualification results, and provide samples, that is a healthy sign. It suggests the change was reviewed properly and not just pulled from whatever happened to be available in the channel that week.

On the other hand, if the answers stay fuzzy, that tells you something too.

“We have used it before” is not documentation.
“It is the same quality” is not a test report.
“Do not worry” is not an engineering conclusion.

When a Substitution Is Probably Low Risk

A NAND substitution can be low risk when the factory is transparent, the part is traceable, the controller pairing is understood, and the revised build has been tested against the original requirements.

In that case, the change may be nothing more than good supply-chain management. The customer still reviews it, signs off on it, and moves on.

That is how this should work.

When the Customer Should Slow Things Down

The situation deserves a harder look when the factory cannot provide the exact part number, cannot explain the sourcing path, cannot show test data, or pushes for approval without sample validation.

That does not prove the substitute is bad. It does suggest the change is not being managed with enough discipline.

And when you are building a USB product that carries your name, that distinction matters.

The Takeaway

When a factory wants to change the NAND brand in your USB drive, the right response is not fear and it is not blind trust. It is review.

Micron to Intel may be perfectly fine. Intel to Micron may be perfectly fine. One reputable brand swapped for another is not the issue by itself. The issue is whether the factory can show that the replacement memory will meet the same expectations for performance, reliability, and continuity.

Put simply, a NAND substitution is not just a sourcing note. It is a product change.

Treat it that way.

If you strip away the marketing language, the AI hardware race right now is about one thing: moving data is expensive.

Not financially. Electrically.

Every time information leaves memory, crosses a bus, hits a processor, and comes back, energy gets burned. At scale, that energy becomes heat. Heat becomes infrastructure. Infrastructure becomes cost.

That’s why HBM exists.

High Bandwidth MemoryA type of stacked DRAM designed for extremely fast data transfer rates by minimizing distance between memory and GPU. is stacked DRAM sitting inches — sometimes millimeters — from the GPU die. Wide buses. Short traces. Massive parallel lanes. The whole design is built around minimizing travel distance.

It’s brutally fast. Terabytes per second fast. And correspondingly expensive.

HBM is where AI training lives. When you’re updating billions of weights repeatedly, latency and bandwidth aren’t optional.

If you want a deeper historical backdrop on how flash evolved into today’s density race, see our piece on flash memory — where did it start?

But training isn’t the only workload anymore.

Inference — actually running the model — behaves differently. It streams, references, and reads far more than it rewrites. Still heavy. Just not the same access pattern.

That shift is what opened the door for HBF.

High Bandwidth Flash isn’t a retail product yet. It’s a structural idea: take NAND flash, move it closer to compute, widen the interface, expose more parallelism, and create something that sits between DRAMRandom Access Memory, a type of computer memory used for temporary data storage and fast access. and SSD.

On paper, it looks elegant.

Flash is cheaper per gigabyte than DRAM. If you can give it more bandwidth and reduce the distance to the processor, you’ve potentially unlocked larger working sets without HBM pricing.

Here’s the landscape as it stands:

That middle row is where the argument lives.

Flash memory does not behave like DRAM. It never has. NAND stores charge in floating gates or charge traps. Writing requires erase cycles. Erase cycles happen in blocks. You don’t overwrite a byte — you reset a region.

That’s why latency jumps from nanoseconds to microseconds. Packaging doesn’t change electron tunneling time.

If you want a refresher on how erase behavior impacts performance, read why NAND flash erase speed still matters.

So if HBF is going to work, it works because inference is read-dominant. Streaming patterns are friendlier to flash. Predictability helps. Random writes hurt.

Now zoom out further.

CXL memory expansion doesn’t change memory type at all. It extends DRAM outward. Compute Express Link allows large external pools of DRAM to behave coherently with the CPU. Latency rises compared to local DIMMs, but capacity scales without adding sockets.

Near-memory compute moves in the opposite direction. Instead of dragging data to a processor, it embeds logic closer to memory. Logic layers inside HBM stacks. Small compute engines inside arrays. The goal is fewer round trips.

Computational storage pushes filtering into the SSD itself. If only a fraction of stored data is useful, process it inside the drive before sending it across PCIe. Less movement. Less power.

All of these ideas orbit the same constraint: bandwidth costs energy.

HBM attacks latency directly. CXL stretches DRAM capacity. Near-memory compute reduces movement. Computational storage trims waste. HBF tries to bend economics in the middle.

None of them break physics. They rearrange trade-offs.

At hyperscale, trade-offs decide architecture. Speed is impressive. Efficiency keeps the lights on.