http://synopsys.com/Company/Pages/Webinars.aspxSynopsys Webniars RSSCopyright 2016. All rights reserved.In this webinar, discover how native integrations of Verdi design debug technologies with Synopsys’ power analysis and verification solutions help catch power-related bugs earlier and faster. The industry-leading Verdi platform couples powerful tracing techniques with unique source code and schematic browsers, enabling teams to quickly debug low power issues in RTL or netlist designs, as well as in the UPF power intent specification. These specialized power-aware debug capabilities accelerate low power verification and ensure successful delivery of intended low power features.http://event.on24.com/r.htm?e=1234976&s=1&k=3764E150C7359DE9B2133A4027CAB814Tue, 08 Nov 2016 08:00:00 GMTWith TetraMAX II, Synopsys’ next-generation ATPG and diagnostics solution, pattern generation has been re-engineered to deliver unprecedented speed and efficiency. Following a brief introduction of the product, our guest speaker describes STMicroelectronics’ motivation to achieve faster ATPG turnaround time for high defect-coverage manufacturing tests, and shares his evaluation results. Synopsys then shows how breakthrough “iCube” technology in TetraMAX II generates fewer patterns and enables order-of-magnitude faster runtime than existing solutions.http://event.on24.com/r.htm?e=1282145&s=1&k=3EC37B159AA2C61898E8AABAD010FF84Thu, 27 Oct 2016 07:00:00 GMTLearn how new PrimeTime ECO technology has allowed users to reduce the memory required to complete ECO closure by 5X while retaining QoR. Includes case studies from AMD, Broadcom, and Renesas.http://event.on24.com/r.htm?e=1284014&s=1&k=3B84866426EE2E5C7FDB09B42ECAE20AWed, 26 Oct 2016 07:00:00 GMTLearn about countermeasures for side-channel analysis attacks, cryptography implementation options to defend against logical and physical attacks and how to develop a TEE on an ultra-low power core.https://webinar.techonline.com/2527?keycode=CAA1CCTue, 25 Oct 2016 07:00:00 GMTFunctional ECOs bring uncertainty to the design schedule. This webinar highlights four different customer case studies on how to quickly and predictably implement functional ECOs using Formality Ultra. http://event.on24.com/r.htm?e=1278095&s=1&k=9EBBBED54F275F5C80EA738103305ECDThu, 13 Oct 2016 07:00:00 GMTElectrical and electronic architecture evolution is having a direct impact on automotive networks. When it comes to in-vehicle networks, Ethernet is the fastest growing network.https://event.webcasts.com/starthere.jsp?ei=1117334Wed, 12 Oct 2016 07:00:00 GMTIn this webinar, you will learn how to automatically “build-in” high reliability with Synopsys Synplify Premier FPGA design tools.http://event.on24.com/r.htm?e=1251208&s=1&k=73BA4192F11A0F7ECBA429E2AF5E1390&partnerref=syn_webTue, 27 Sep 2016 07:00:00 GMTIn this webinar, you will learn about the ISO 26262 functional safety standard and how it is driving DFT requirements today.http://event.on24.com/r.htm?e=1253805&s=1&k=1A5B234B57D588C30CA69E4A81AAF8B7Thu, 22 Sep 2016 07:00:00 GMTIn this webinar, we will discuss how SpyGlass Power delivers an integrated early power analysis and exploration solution that includes: estimation, profiling, reduction and exploration.http://event.on24.com/r.htm?e=1234948&s=1&k=DB74D064A37BCBFEBD872CF4629A4C1BWed, 21 Sep 2016 07:00:00 GMTBased on years of hands-on experience and the latest debug features of VC Formal with Verdi, this webinar will give a practical guide to various debug techniques for analyzing formal verification results that will enable verification teams to get the most out of integrating formal verification into their flow. Using debug challenges such as assertion failures and sequential equivalence mismatches this webinar will guide users on the fastest way to a resolution. It will also show Navigator - a powerful new debug solution in Verdi – that allows quick waveform based what-if analysis on design functionality without any need for a testbench environment or assertion expertise. http://event.on24.com/r.htm?e=1251765&s=1&k=7B08D966F77B16896BE29B54326209AFWed, 14 Sep 2016 07:00:00 GMTIn this Synopsys webinar, we will show how you can cut your debug time in half with innovative Verdi design debug techniques. Specifically, you will learn how Verdi enables you to quickly explore, visualize and debug complex, and even unfamiliar designs; how you can quickly root-cause and debug simulation failures with Verdi debug techniques such as temporal flow view, automated X-tracing, assertion analyzer etc; and how Verdi’s unified debug platform extends the intuitive and familiar Verdi debug use-model to natively integrated Synopsys static and formal verification solutions.http://event.on24.com/r.htm?e=1251130&s=1&k=C123FA1E47D8A44B102914ECCD3D247ATue, 13 Sep 2016 07:00:00 GMTLearn about the key advantages of MIPI CSI-2 and DSI through application uses cases, as well as MIPI's new I3C specification and its advantages for multiple sensor connectivity.https://webinar.techonline.com/2181?keycode=CAA1CCWed, 07 Sep 2016 07:00:00 GMTIn this webinar, we will demonstrate how Verdi Power-Aware Debug greatly simplifies low-power debug and identifies potential design-killing bugs earlier and faster, with a unified and comprehensive view of the design and its power intent. Specifically, you will learn how visualization of the power architecture can help identify power strategy and connectivity issues upfront; how to use annotated power intent on source code, schematics and waveforms to rapidly root-cause power-related errors back to UPF/RTL; how to debug unexpected design behavior such as Xs caused by incorrect power-up/down sequences etc.http://event.on24.com/r.htm?e=1234795&s=1&k=6CD3EA9EB0158B7F2F886E8F3307557EWed, 31 Aug 2016 07:00:00 GMTLearn about the latest new features for SpyGlass CDC/RDC including "Smart Netlist Verification" and "RDC (Reset Domain Crossing)".http://event.on24.com/r.htm?e=1227443&s=1&k=4588E3C99C2C39C557407F8DFF586932&partnerref=CoWebTue, 30 Aug 2016 07:00:00 GMTIn this session, we will discuss UPF based static and dynamic verification techniques to address these challenges. We will also discuss the problems addressed by Synopsys’ VC LP and VCS NLP tools, to streamline the entire verification process.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1228225&sessionid=1&key=C6FA6D3C0D97BA659F772A6753888783Wed, 10 Aug 2016 07:00:00 GMTThis webinar introduces the new HAPS adaptor to connect a Juno ARM® Development Platform (ADP) to a Synopsys HAPS® Prototyping System or DesignWare® IP Prototyping Kit .https://webinar.techonline.com/2115?keycode=CAA1BCThu, 21 Jul 2016 07:00:00 GMTIn this Synopsys webinar, we will show how interactive debug is ushering in a new era in testbench debug. Specifically, you will learn: how interactive and reverse interactive debug capabilities allow you to quickly root-cause and debug simulation failures; how what-if analysis improves TB debug efficiency by combining diagnosis and cure into a single step; how to navigate and effectively debug a UVM-based testbench https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1216171&sessionid=1&key=427A3F6DD4AD0618FDF063F246CC7338Wed, 20 Jul 2016 07:00:00 GMTThis webinar discusses how to integrate USB Type-C and DisplayPort functionality, including solving critical hardware and software partitioning challenges.http://www.eet-cn.com/webinar/Synopsys_20160719Tue, 19 Jul 2016 07:00:00 GMTLearn what to look for when selecting Foundation IP for your automotive IC. Your PPA requirements are a given — learn about specific automotive requirements such as ISO 26262, TS 16949, zero DPPM & morehttps://webinar.techonline.com/2174?keycode=CAA1CCTue, 19 Jul 2016 07:00:00 GMTLearn about mathematical requirements for your targeted applications as well as new formats for use in hardware mathematics that can help you make clear design trade-offs and achieve design precision.https://webinar.techonline.com/2039?keycode=CAA1CCThu, 14 Jul 2016 07:00:00 GMTLearn about the power of Application-Specific Instruction-Set Processors (ASIPs) and the growing need for more flexible, programmable accelerators for SoC designs.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1212975&sessionid=1&key=48EE604A71C3EA25EB9980ACC870015CWed, 13 Jul 2016 07:00:00 GMTLearn about diagnosis, debug and self-test and repair solutions for memories, logic, AMS and interface IP blocks for automotive requirements to satisfy key criteria like low DPPM.http://www.eet-cn.com/webinar/Synopsys_20160712Tue, 12 Jul 2016 07:00:00 GMTSecurity is critical to the success of IoT SoCs and must be an early design consideration. This webinar discusses IoT security threats and use cases requiring a secure root of trust.http://www.eet-cn.com/webinar/Synopsys_20160705Tue, 05 Jul 2016 07:00:00 GMTLearn how Synopsys’ new embedded vision processor family with advanced vision capabilities can enable powerful and flexible vision solutions for your next-generations SoCs.https://webinar.techonline.com/2106?keycode=CAA1CCWed, 29 Jun 2016 07:00:00 GMTSamsung and Synopsys together present a webinar on the manufacturing and physical verification challenges and solutions at 14nm.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1204664&sessionid=1&key=61FF92A473F96D2E96CE99F30F1D1775&partnerref=cowebTue, 28 Jun 2016 07:00:00 GMTSTMicroelectronics will share their experiences with performance and efficiency advantages seen with the latest releases of StarRC and how they are helping ST to roll out their own products.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1201810&sessionid=1&key=ABDA213993EFE0BFEAF47D5C3F764FC4&partnerref=cowebThu, 23 Jun 2016 07:00:00 GMTThis 60-minute Webinar will provide an overview of virtual hardware ECUs and how to integrate them into the automotive system development process to manage these challenges.https://event.webcasts.com/starthere.jsp?ei=1102792Tue, 21 Jun 2016 07:00:00 GMTThis webinar will provide an overview of the concepts, requirements, and approaches for automotive IC designers and verification teams to understand what’s needed for ISO 26262 compliance for safety-critical SoCs and IP blocks. Capsule Module: Enabling ISO 26262 Compliance with Synopsys’ Automotive Safety Verification Solutionhttps://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1195835&sessionid=1&key=31E9FBC93341DDC769D681CA1A193C3CThu, 16 Jun 2016 07:00:00 GMTIn this webinar, we will show how simultaneous, synchronized views of design behavior at the software and hardware levels helps engineers at both levels debug efficiently and effectively. We’ll demonstrate how the Synopsys Verdi HW SW Debug solution seamlessly combines the industry-leading Verdi hardware debug with Eclipse-based software debug to provide a simple, yet powerful unified debug environment. Further, we will show how the solution is adapted easily to different processor core families including custom cores, as well as how it scales to debug multiple cores on a single SoC. Overall, these techniques will enable better SoC verification, accelerate software bring up and help achieve faster time-to-market.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1201490&sessionid=1&key=E1A1BE4E1EF1BA0A1F2B9306D029640BWed, 15 Jun 2016 07:00:00 GMTLearn best practices that designers should follow for systems-on-chips (SoCs) connecting to DDR4 in their enterprise applications.https://webinar.techonline.com/1878?keycode=CAA1CCThu, 02 Jun 2016 07:00:00 GMTLearn about the latest key feature updates for the SpyGlass version 5.5.0 and 5.6.0 family of products including SpyGlass Lint, SpyGlass CDC, SpyGlass Constraints, SpyGlass Power, and SpyGlass DFT.http://event.on24.com/r.htm?e=1180915&s=1&k=818F2B77CA172783E31D2F6C6DE625A9&partnerref=CoWebWed, 01 Jun 2016 07:00:00 GMTJoin Synopsys and ARM to learn more about accelerating timing closure by implementing timing constraint best practices.http://event.on24.com/r.htm?e=1187572&s=1&k=131AB9898A232AF91B871546F4EDAA48&partnerref=cowebThu, 26 May 2016 07:00:00 GMTJoin Synopsys and ARM to learn more about accelerating timing closure by implementing timing constraint best practices.http://event.on24.com/r.htm?e=1186559&s=1&k=25381C386B9AB52DF26707CBD29F51FB&partnerref=cowebThu, 26 May 2016 07:00:00 GMTJoin Synopsys and ARM to learn more about accelerating timing closure by implementing timing constraint best practices.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1181017&sessionid=1&key=1BC621D9471260C6A3BCDD0743A49BBCWed, 25 May 2016 07:00:00 GMTIn this webinar, we will discuss how SpyGlass RDC delivers a unique solution to address RDC issues early at RTL, saving valuable time and costly design re-spins. SpyGlass RDC leverages the industry leading SpyGlass Platform and GuideWare methodology for an easy to use and comprehensive flow for RTL signoff.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1186297&sessionid=1&key=6C558F7577B97547CCA8D05E925296B9Tue, 24 May 2016 07:00:00 GMTIn Part I of a multi-part webinar series on Verification Planning and Coverage, we will focus on how verification planning using Verdi Coverage can help make your coverage closure goals SMART. We’ll start with a demonstration of how to create an executable verification plan from design specifications and how to structure it based on specific features, functions and design modes that need to be verified. We will then discuss the formulation of a meaningful coverage model that takes into account structural and functional coverage, as well as the different sources of coverage information. Finally, we’ll show how the verification plan acts as a centerpiece and ties together the verification data with the spec, helping provide actionable metrics to drive verification closure.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1186116&sessionid=1&key=100E5261F590BCB190AD506CFE7965DCWed, 18 May 2016 07:00:00 GMTIn this webinar, we will discuss USB verification challenges and how the Synopsys USB Type-C verification subsystem is addressing these challenges.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1183605&sessionid=1&key=999F0F33D9FD1232F2E7788036B65C05Thu, 12 May 2016 07:00:00 GMTEarly detection of testability issues can prevent major bottlenecks downstream and avoid time-consuming design iterations. In this webinar, Synopsys presents new techniques and capabilities available in SpyGlass DFT ADV such as high-impact test points to boost coverage, reduce the number of patterns, and minimize test costs. Our guest speaker from Xilinx discusses test challenges associated with large SoC designs such as the Xilinx Zynq® UltraScale™ chip family, and illustrates how SpyGlass DFT ADV addresses testability issues early in the design flow, saving weeks of complex DFT-related ECOs.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1173551&sessionid=1&key=B121388DB0CEAC49A02F88B3A72D4E05Thu, 28 Apr 2016 07:00:00 GMTLearn about Synopsys' new full-custom solution that features a visually-assisted automation flow tuned for FinFET-based designs to speed up common design tasks, reduce iterations and enable reuse.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1164103&sessionid=1&key=A22830ADCEAF97FC2377CA08BC24B737&partnerref=HLThu, 21 Apr 2016 07:00:00 GMTLearn about Synopsys VC Formal advanced techniques and formal coverage metrics that provide better convergence and simulation-like visibility, to achieve formal verification signoff.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1160521&sessionid=1&key=2C9C08C6CD93DE9D04E1775697108A38&partnerref=CoWebWed, 20 Apr 2016 07:00:00 GMTThis webinar discusses how to integrate USB Type-C and DisplayPort functionality, including solving critical hardware and software partitioning challenges.https://webinar.techonline.com/1846?keycode=CAA1CCTue, 19 Apr 2016 07:00:00 GMTSecurity is critical to the success of IoT SoCs and must be an early design consideration. This webinar discusses IoT security threats and use cases requiring a secure root of trust.https://webinar.techonline.com/1754?keycode=CAA1CCThu, 14 Apr 2016 07:00:00 GMTThis webinar introduces how simulation-based Virtualizer Development Kits are the perfect technology to enable the integration and testing of hardware dependent software in a continuous manner.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1159204&sessionid=1&key=72377B54FF07454E5B4427385D9CF7E4&partnerref=syn_webWed, 13 Apr 2016 07:00:00 GMTLearn about diagnosis, debug and self-test and repair solutions for memories, logic, AMS and interface IP blocks for automotive requirements to satisfy key criteria like low DPPM.https://webinar.techonline.com/1849?keycode=CAA1CCTue, 12 Apr 2016 07:00:00 GMTLearn about Socionext’s ever-evolving UPF design flow and their experience with successfully deploying a Golden UPF-based methodology using Synopsys tools.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1156552&sessionid=1&key=F2B0E7E59E3A7BD6F9873690B8A83C2F&partnerref=CoWebThu, 07 Apr 2016 07:00:00 GMTLearn about Socionext’s ever-evolving UPF design flow and their experience with successfully deploying a Golden UPF-based methodology using Synopsys tools.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1157184&sessionid=1&key=D8F200E17E91C695C670C03E9F7B0D56&partnerref=CoWebThu, 07 Apr 2016 07:00:00 GMTThis webinar will detail how Synplify Premier supports each design phase through improvements in automation, constraint setup, technologies for the best timing QoR and debugger information.https://webinar.techonline.com/1812?keycode=CAA1BCWed, 23 Mar 2016 07:00:00 GMTIn this webinar, we will demonstrate how Synopsys' new Verdi Advanced AMS debug solution, based on the market-leading Verdi SoC debug platform, delivers groundbreaking co-simulation debug for both analog and digital engineers, as well as system integrators.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1142860&sessionid=1&key=FC8042E6AB4C54DBFEFC959E0BDFE872Tue, 15 Mar 2016 07:00:00 GMTLearn about TSMC’s 10nm design enablement readiness & the tooling supported in their physical design flow; Synopsys will cover new technologies addressing the challenges of 10nm design verification.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1109442&sessionid=1&key=664DA028AF92D88AB0ED6D79C66735E0Thu, 03 Mar 2016 08:00:00 GMTUnderstand the challenges associated with testing FinFET-based memories and new methods to address FinFET-specific defects.https://webinar.techonline.com/19654?keycode=CAA1CCThu, 03 Mar 2016 08:00:00 GMTThis webinar will provide an overview of the wide spectrum of critical debug techniques for efficient FPGA-based prototype bring-up, embedded software development and hardware/software integration.https://webinar.techonline.com/1674?keycode=CAA1BCWed, 02 Mar 2016 08:00:00 GMTIn this webinar, Martin Liu, CAD engineer for Sunplus, discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how Sunplus deployed a PrimeRail vector-free analysis methodology using RTL VCD to achieve fast performance and superior accuracy of voltage drop results.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1122553&sessionid=1&key=A9C437CAF1094C44F25F21D6280C07F2Wed, 24 Feb 2016 08:00:00 GMTIn this webinar, Martin Liu, CAD engineer for Sunplus, discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how Sunplus deployed a PrimeRail vector-free analysis methodology using RTL VCD to achieve fast performance and superior accuracy of voltage drop results. http://event.on24.com/r.htm?e=1122500&s=1&k=86C109915A173C4C5E3D6AF2979CD645Wed, 24 Feb 2016 08:00:00 GMTIn this webinar, Martin Liu, CAD engineer for Sunplus, discusses the challenges of a traditional vector-free dynamic analysis flow for early stage designs that produces less than accurate voltage drop results and shows how Sunplus deployed a PrimeRail vector-free analysis methodology using RTL VCD to achieve fast performance and superior accuracy of voltage drop results.http://event.on24.com/r.htm?e=1124088&s=1&k=89FBC2102D42A855290033454E4E1A2EWed, 24 Feb 2016 08:00:00 GMTIn this webinar, we will discuss the latest technology in storage protocols, NVMe, a rapidly evolving high performance storage standard developed to reduce latency and support parallelism. https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1131497&sessionid=1&key=251C1243368D133CC008B6ADF8E6F88ETue, 23 Feb 2016 08:00:00 GMTLearn about the comprehensive GUI-based transistor-level simulation and analysis environment that is deeply integrated with CustomSim, FineSim, and HSPICE circuit simulators.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1124711&sessionid=1&key=032614775DD266384B97EE7EA99C869DWed, 17 Feb 2016 08:00:00 GMTThis webinar uses case studies to address the challenges of integrating IP into an SoC, optimizing IP subsystem architecture, and simplifying IP subsystem verification.https://webinar.techonline.com/1436?keycode=CAA1CCWed, 10 Feb 2016 08:00:00 GMTLearn about the growing IoT market trends, the required wireless connectivity and new process technologies to achieve low-power consumption and enable efficient connectivity between devices.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1109482&sessionid=1&key=4F621EBFB6995B2E7AE8118F72932B65&CAA1CCWed, 03 Feb 2016 08:00:00 GMTMaximizing IC performance and reducing area are key for Sunplus to deliver competitive and cost-effective multimedia products to market while meeting aggressive schedules. In this webinar, John Yeh CAD engineer will discuss how Sunplus uses the latest Design Compiler technologies to improve predictability, reduce schedules and achieve superior results. He will show how DC Explorer helps speed up the development of high quality RTL and constraints and allows early physical exploration. He will also discuss how Design Compiler Graphical enables Sunplus to achieve higher performance and tighter correlation to IC Compiler for faster design convergence.http://event.on24.com/r.htm?e=1120808&s=1&k=80C5C6C124A040C8949D55640505B0E8Thu, 28 Jan 2016 08:00:00 GMTMaximizing IC performance and reducing area are key for Sunplus to deliver competitive and cost-effective multimedia products to market while meeting aggressive schedules. In this webinar, John Yeh CAD engineer will discuss how Sunplus uses the latest Design Compiler technologies to improve predictability, reduce schedules and achieve superior results. He will show how DC Explorer helps speed up the development of high quality RTL and constraints and allows early physical exploration. He will also discuss how Design Compiler Graphical enables Sunplus to achieve higher performance and tighter correlation to IC Compiler for faster design convergence.http://event.on24.com/r.htm?e=1120685&s=1&k=AD2DCA6738D785CF99EDC0C29BC2A3CCThu, 28 Jan 2016 08:00:00 GMTLearn about StarRC's recent enhancements in RC netlist reduction & how these improvements are helping Synopsys IP developers verify the performance & integrity of their industry-leading IP portfolio.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1116723&sessionid=1&key=A1F0229DE4A0B02989EE811D884474CFWed, 27 Jan 2016 08:00:00 GMTIn this webinar, we will discuss how the SpyGlass CDC solution enables comprehensive clock and reset domain crossing (CDC/RDC) verification for more than a billion gates, helping designers to avoid costly chip killer bugs, re-spins and achieve signoff quality verification. https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1114936&sessionid=1&key=EE0C2743EDA9FED54FA86F03AE5A54B0Tue, 26 Jan 2016 08:00:00 GMTThis webinar will cover the new, innovative SiliconSmart capabilities that will enable you to work smarter in solving your toughest FinFET library characterization challenges.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1110885&sessionid=1&key=3B639DC354288CA8D9EFEAD2D08C795FWed, 13 Jan 2016 08:00:00 GMTIn this webinar, we will discuss how the newly introduced SpyGlass Lint Advanced solution identifies RTL issues at their source, pinpoints structural, coding and consistency problems in the RTL descriptions, and helps designers resolve issues quickly before design implementation.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1098112&sessionid=1&key=90B10DB978DC8834E20BEE785CCF79E9Tue, 08 Dec 2015 08:00:00 GMTThis webinar will provide insight into IoT edge device security requirements and how they can be met with an ultra-low power processor.https://webinar.techonline.com/1094?keycode=CAA1CCThu, 03 Dec 2015 08:00:00 GMTLearn about ISO 26262 and AEC Q100 standards; latency, power, reliability and process-related design challenges; and how certified IP helps ensure functional safety, reliability and quality management.https://webinar.techonline.com/1145?keycode=CAA1CCWed, 02 Dec 2015 08:00:00 GMTIP blocks alone can't address designers' growing SoC design & integration challenges. Learn how DesignWare IP Prototyping Kits ease IP configuration & integration and accelerate software development.http://www.eet-cn.com/webinar/Synopsys_20151201Tue, 01 Dec 2015 08:00:00 GMTSponsored by Synopsys and Arteris, this webinar illustrates how virtual prototyping tools and high-level architecture models provide SoC architects with deep, system-level analysis.https://webinar.techonline.com/1084?keycode=CAA1BCThu, 19 Nov 2015 08:00:00 GMTIn this webinar, we will discuss how to take advantage of the system-level capabilities of Synopsys Verification IP for ARM® AMBA® protocols to verify cache-coherent interconnects. Synopsys VIP includes system-level interconnect test suites and system-level coverage to accelerate verification closure.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1083119&sessionid=1&key=9A8DA0C37237D76E16D501D2385CD0ACWed, 18 Nov 2015 08:00:00 GMTSynopsys will review the PrimeTime POCV technology that helps designers reduce design margins in FinFET designs, and you will learn about NVIDIA’s latest FinFET tapeout experience with PrimeTime POCV.http://event.on24.com/r.htm?e=1082444&s=1&k=1B137C277BC7A39BF2D511AB1CAF9694&partnerref=CoWebTue, 17 Nov 2015 08:00:00 GMTSynopsys will review the PrimeTime POCV technology that helps designers reduce design margins in FinFET designs, and you will learn about NVIDIA’s latest FinFET tapeout experience with PrimeTime POCV.http://event.on24.com/r.htm?e=1082358&s=1&k=92EA8B1BF95F581F937B3867D79AC73B&partnerref=CoWebTue, 17 Nov 2015 08:00:00 GMTIn this webinar, we introduce the challenges facing of designers of high-reliability ICs for the automotive market, and discuss some of the proven Galaxy Design Platform IC implementation and sign-off solutions being deployed by automotive design teams worldwide. https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1082911&sessionid=1&key=A6CD72CB4FA30CB243B79B97FDFD0B27Thu, 12 Nov 2015 08:00:00 GMTCo-hosted by Chris Rommel of VDC, this webinar will explore the value between prototyping methods and their benefits for enabling early architecture exploration, software development, hardware-software integration and system validation.https://webinar.techonline.com/1069?keycode=CAA1GCWed, 04 Nov 2015 08:00:00 GMTIn this Webinar, we will review the evolution of memory technology leading to the latest development in DDR, LPDDR, eMMC, High Bandwidth Memory (HBM) and Hybrid Memory Cube (HMC). We will highlight key concerns in the verification of these protocols, and their contributing concerns to overall System Validation. Finally, we will review successful methodologies and techniques that assure project success.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1063417&sessionid=1&key=EE8E225166981397923C3B260A500003Thu, 29 Oct 2015 07:00:00 GMTLearn about the IBIS-AMI model & how PHY features and performance are implemented into the model. See a comparison between IBIS-AMI simulation results & silicon measurements for a 16Gbps PCIe 4.0 link.http://event.on24.com/r.htm?e=1047145&s=1&k=E6FFD15892EE7B0773D03C6D0E583327&partnerref=SynopsysWed, 28 Oct 2015 07:00:00 GMTLearn how a tool-based approach using Synopsys' ASIP Designer can shrink the time and effort required to create a fully-featured SDK and can minimize the maintenance and support effort required. https://webinar.techonline.com/1095?keycode=CAA1CCTue, 27 Oct 2015 07:00:00 GMTLearn how inductance impacts high-frequency design performance, and how StarRC’s new clock net inductance extraction feature has been specifically designed to model this new parasitic effect.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1052526&sessionid=1&key=D792BEBF52AD9AA0E7AEF8B10663DC4E&partnerref=CoWebThu, 15 Oct 2015 07:00:00 GMTControl your design's floating point logic using the DesignWare Foundation Cores flexible floating point format.https://webinar.techonline.com/1029?keycode=CAA1CCTue, 13 Oct 2015 07:00:00 GMTAchieving higher performance, lower power and smaller die size in an efficient timeframe is key for GUC’s ASIC design services. In this webinar, Kazuyuki Irie, Department manager for GUC Japan discusses the challenges of a traditional ASIC design flow that required timing margin in synthesis for faster design closure; leading to less than optimal area and power results. He will discuss how GUC Japan recognized a Design Compiler Graphical based methodology that improves predictability, reduces schedule and achieves superior results for GUC Japan. https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1044725&sessionid=1&key=0BBE610C8DDB0B9896180133979A09BEThu, 08 Oct 2015 07:00:00 GMTThis webinar will introduce Synopsys' HAPS®-80 Series of FPGA-based prototyping systems, which have been designed to deliver maximum system performance and support for up to 1.6 billion ASIC gates.https://webinar.techonline.com/204?keycode=CAA1CCWed, 30 Sep 2015 07:00:00 GMTThis webinar highlights how to find low power issues during verification using Formality.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1038237&sessionid=1&key=F1A5162D30EFBDE61B622471956178B9&partnerref=CoWebTue, 29 Sep 2015 07:00:00 GMTThis webinar highlights how to find low power issues during verification using Formality. - Traditional Chinesehttp://event.on24.com/r.htm?e=1038258&s=1&k=D58FC88B13F8F1D4F97D2DA5BAC91EC4&partnerref=CoWebTue, 29 Sep 2015 07:00:00 GMTThis presentation will take you through implementation of a 16 processor ARM Cortex-A53 based network computing reference design targeting Samsung’s 14LPP FinFET technology using Lynx Design System.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1034665&sessionid=1&key=45F16BE6E44EC3CA16B9557092DA499D&partnerref=CoWebWed, 09 Sep 2015 07:00:00 GMTThis webinar shows how to leverage protocol, methodology, verification and productivity features of Synopsys VC VIP and UVM source code test suites for accelerated verification closure of PCIe Gen4 based designs. https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1031542&sessionid=1&key=B4C1D6AFC69450857F293ABE19607497Wed, 19 Aug 2015 07:00:00 GMTJoin TSMC and Synopsys as we discuss N16FF+/early N10 certification collaboration activities and how CustomSim 2015.06 addresses the design needs of FinFET technology nodes.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1030154&sessionid=1&key=448CCB043CDDEA8B88A2A6C7D84C8EE3Wed, 12 Aug 2015 07:00:00 GMTICs targeted for safety-critical applications must be able to perform in-system self-test in compliance with functional safety standards such as ISO 26262. In this webinar, Synopsys highlights synthesis-based logic BIST that addresses the self-test requirements for safety-critical designs. Our guest speaker from STMicroelectronics presents results and details of Synopsys’ test solution successfully deployed on production designs.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1019626&sessionid=1&key=D66205B3A3303A5032DA747701F6F2FEThu, 30 Jul 2015 07:00:00 GMTSTMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1022309&sessionid=1&key=370534733B58B355B537EF50B64DEE70&partnerref=CoWebWed, 29 Jul 2015 07:00:00 GMTSTMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.http://event.on24.com/r.htm?e=1022647&s=1&k=92601032956EB57A13EC1B1B03E168EB&partnerref=CoWebWed, 29 Jul 2015 07:00:00 GMTSTMicroelectronics will outline how PrimeTime ECO noise fixing fits with their PrimeTime and IC Compiler signoff flow, and share some results from real designs showing 95%+ noise fixing rates.http://event.on24.com/r.htm?e=1022323&s=1&k=EC1DFDC8CB47AA0A230A7D3BCBE712C7&partnerref=CoWebWed, 29 Jul 2015 07:00:00 GMTLearn from Synopsys Professional Services experts how to accelerate hardening of DDR interface IP in context of SoC design and performance requirements.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=1019124&sessionid=1&key=0120035FF15D4167DEDAEF5DE1805E1A&partnerref=CoWebTue, 28 Jul 2015 07:00:00 GMTThis webinar will provide details on how foundation IP - logic libraries and embedded memories - can help designers of IoT applications take advantage of the power benefits available in 40nm processes.https://webinar.techonline.com/20022?keycode=CAA1CCTue, 21 Jul 2015 07:00:00 GMTLearn about the required network connectivity for automotive applications like ADAS and the importance of integrating Ethernet IP that is certified to be ASIL B Ready for ISO 26262 functional safety.https://webinar.techonline.com/19930?keycode=CAA1CCTue, 14 Jul 2015 07:00:00 GMTIP blocks alone can't address designers' growing SoC design & integration challenges. Learn how DesignWare IP Prototyping Kits ease IP configuration & integration and accelerate software development. http://webinar.techonline.com/19810?keycode=CAA1CCWed, 03 Jun 2015 07:00:00 GMTWe will outline in detail the verification challenges of current and future Ethernet speeds and explain how Accellera UVM Methodology, IEEE 1800-2012 System Verilog Functional Coverage, and SystemVerilog Ethernet Verification IP empowers design and verification teams with methodology, techniques and tools they need to achieve success.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=988079&sessionid=1&key=2A0CABBBC95A9843AD9B7F7CD2F38324Wed, 20 May 2015 07:00:00 GMTLearn how integrating an ARMv8-based virtual prototype, an FPGA-based prototype, pre-verified IP, and PHY daughter boards, can accelerate time-to-market.http://webinar.techonline.com/19894?keycode=CAA1CCTue, 19 May 2015 07:00:00 GMTIn this webinar, we highlight two methodologies, multisite test and concurrent test, that minimize test application time and maximize throughput.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=972455&sessionid=1&key=3F9CF2B5BD465CAD93B3366F7EF5DD05Thu, 30 Apr 2015 07:00:00 GMTIn this joint webinar, ARM describes methodologies, design choices and results achieved by an area-centric reference implementation of the ARM Mali GPU using Design Compiler Graphical and IC Compiler.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=976889&sessionid=1&key=4B282BF2180BA595BF361358A7BFB593Thu, 23 Apr 2015 07:00:00 GMTLearn about the architecture of the new DesignWare Embedded Vision (EV) Processors and the open source vision tools used to program the processors to ensure efficient resource utilization.http://webinar.techonline.com/19737?keycode=CAA1CCTue, 21 Apr 2015 07:00:00 GMTUnderstand how Virtualizer™ Development Kits (VDKs) can be used to accelerate DesignWare® Interface IP driver development and integration into a 64-bit ARMv8 Linux software stack.http://webinar.techonline.com/19733?keycode=CAA1CCThu, 16 Apr 2015 07:00:00 GMTLearn about the architectural differences between enterprise and consumer multiprotocol PHY and the optimal PHY solution for your SoC that meets your specific design requirements. http://webinar.techonline.com/19668?keycode=CAA1CCThu, 02 Apr 2015 07:00:00 GMTUnderstand the 90-nm to 10-nm technology process and IP requirements for wearable/IoT devices and mobile application processors.http://webinar.techonline.com/19732?keycode=CAA1CCTue, 31 Mar 2015 07:00:00 GMTUnderstand the challenges associated with testing FinFET-based memories and new methods to address FinFET-specific defects. http://webinar.techonline.com/19654?keycode=CAA1CCTue, 03 Mar 2015 08:00:00 GMTThis webinar will help you understand a Liberty-based approach for effective IP reuse in implementation of a multi-voltage hierarchical design using the IEEE 1801 (UPF) standard.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=935473&sessionid=1&key=E2CD1FFB34067DB81621B9E6986EF6FEThu, 26 Feb 2015 08:00:00 GMTUnderstand the USB Type-C specification from an SoC designer’s perspective, how to add USB Type-C to existing designs and recommendations for new SoC architectures.http://webinar.techonline.com/19414?keycode=CAA1CCWed, 18 Feb 2015 08:00:00 GMTSTMicroelectronics describes how they used Formality® Ultra to meet their tight release schedule for their ARM® core based designs despite having to implement multiple functional ECOs late.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=924046&sessionid=1&key=402359D9B924F915F4E0F272F13A576B&partnerref=CoWebThu, 05 Feb 2015 08:00:00 GMTLearn how new investments in IP help improve system power usage and energy efficiency and enable added functionality for IoT applications including wearable and machine-to-machine devices.http://webinar.techonline.com/19365?keycode=CAA1CCTue, 27 Jan 2015 08:00:00 GMTAttend this webinar to gain a demonstration of the architectural exploration flow based on IP Designer, Synopsys' ASIP design tool.http://webinar.techonline.com/19364?keycode=CAA1CCWed, 21 Jan 2015 08:00:00 GMTGet an in-depth look at the changes in the USB 3.1 specification’s physical layer, link layer, protocol layer, and hub.http://webinar.techonline.com/19413?keycode=CAA1CCTue, 13 Jan 2015 08:00:00 GMTLearn about connecting multiple channels of DRAM, tradeoffs in SoC floorplans, logical to physical addressing, connecting to on-chip buses, and low-power design methods for LPDDR4.http://seminar2.techonline.com/registration/distrib.cgi?s=2192&d=4111Tue, 02 Dec 2014 08:00:00 GMTLearn from Synopsys applications engineers how to get the most out of HSPICE analysis. Topics will include how to most effectively use S-element, eye diagrams, IBIS-AMI, RUNLVL, and more. New mini webinars will premiere monthly.http://us02vwwww1/Tools/Verification/AMSVerification/CircuitSimulation/HSPICE/Pages/hspice-webisode-series.aspxMon, 03 Nov 2014 08:00:00 GMTLearn about the benefits and challenges of moving from a planar CMOS process to FinFET and how DesignWare® embedded memory and logic library IP can enable this move. https://webinar.techonline.com/18538?keycode=CAA1CCTue, 22 Jul 2014 07:00:00 GMTAs silicon capacity continues to grow following Moore's law, so has the growth in computational power. This, along with the complexities of today's designs, has led to the need for multi-processor core SoC's to achieve design goals. Managing the complexity of designs that include CPUs, GPUs, and DSPs in a single chip can be quite challenging. Based upon years of Synopsys' consulting experience implementing hundreds of these SoC's, this webinar will outline design best practices and pitfalls to avoid, to enable you to achieve the right balance of high performance, low power and smaller area.https://event.on24.com/eventRegistration/prereg/register.jsp?eventid=789098&sessionid=1&key=80475A015AAE67B06A87EE20F23C1E24&partnerref=CoWebTue, 13 May 2014 07:00:00 GMTHow Synopsys designs and executes on a silicon testing methodology for embedded MTP NVM IP technology, enabling SoC designers with reliable and qualified solutions for their end applications.http://us02vwwww1/IP/Pages/multiple-time-programmable-nvm-ip-webinar.aspxWed, 05 Oct 2011 07:00:00 GMTLearn about the building blocks and integration challenges faced by SoC designers integrating MIPI protocols to interface to camera, display, RFIC, storage and chip to chip connectivity.http://us02vwwww1/IP/Pages/complete-mipi-solutions-webinar.aspxTue, 26 Jul 2011 07:00:00 GMTThe IEEE IP-XACT specification is a valuable format that can help solve IP integration challenges when combined with quality tools designed for an IP-based design and verification flow.http://us02vwwww1/IP/Pages/designware-ip-xact.aspxThu, 17 Mar 2011 07:00:00 GMTLearn how ESP-CV performs functional equivalence checks between a Verilog design and its transistor level implementation.http://us02vwwww1/cgi-bin/protected/espcv/reg.cgi?file=esp-cv-faster-redundancy-verification.htmlWed, 19 Jan 2011 08:00:00 GMTIn-Design reliability analysis and physical verification save time by avoiding useless translations of data back and forth and also allow users to catch and fix problems on-the-go, preventing costly iterations between implementation and signoff. http://solvnet.synopsys.com/onlinetraining/SNUG_BestOfEurope_S08_ICC-ICValidatorandICC-PrimeRailNewIn-DesignFeatures/index.htmlThu, 10 Jun 2010 07:00:00 GMTIn today’s designs, it is not unusual to have hundreds of clocks, power management, multiple modes, in-house or third-party IP with their own set of timing constraints that need to be integrated at the top level. This increased complexity together with tighter schedules makes finalizing the design timing constraints extremely challenging. Thu, 10 Jun 2010 07:00:00 GMTThis paper demonstrates two techniques of clock tree implementation with comparative analysis data. The first is a traditional cluster-based clock tree common in ASIC flows (CTS), the other is a unique technique used in various high-frequency designs based on non-uniform fishbone mesh. http://solvnet.synopsys.com/onlinetraining/SNUG_BestOfEurope_S14_ClockTreeImplementationTechniques/index.htmlThu, 06 May 2010 07:00:00 GMTIn this paper we show how to take advantage of multicore systems to accelerate simulation performance. First, we introduce an algorithm for automatically partitioning the design for multicore simulation. Second, we present an approach to use the GPU to further increase simulation acceleration (around 100X faster). http://solvnet.synopsys.com/onlinetraining/SNUG_BestOfEurope_S15_SimAccelerationUsingMulticore/index.htmlThu, 06 May 2010 07:00:00 GMTThis presentation covers how the latest pin-limited testing enhancements have been deployed successfully on Wolfson’s latest devices. http://solvnet.synopsys.com/onlinetraining/SNUG_BestOfEurope_S11_ScanCompressionWLimitedPinAccess/index.htmlThu, 06 May 2010 07:00:00 GMTDFTMAX compression can achieve over 100X compression. However, small compression factors can be achieved using ”multi-mode” scan architectures. For small- and medium-size mixed-signal designs these provide a low-cost alternative to full compression. http://solvnet.synopsys.com/onlinetraining/SNUG_BestOfEurope_S05_ScanCompression/index.htmlThu, 06 May 2010 07:00:00 GMTDesigners are increasingly adopting DFT methodologies that limit the number of pins allocated for manufacturing test. In this tutorial, we examine what is driving this trend and how you can use new capabilities in DFTMAX to reduce the cost of pin-limited test for your designs. http://solvnet.synopsys.com/onlinetraining/SNUG_BestOfEurope_S03_ReducingtheCostofPin-LimitedTest/index.htmlThu, 06 May 2010 07:00:00 GMTStrategies and methods for correct Extracted View Sets generated with StarRC and results from a real design implemented at 28nm show how post-layout verification can be sped up, substantially improving the turnaround time of the AMS design flow. http://solvnet.synopsys.com/onlinetraining/SNUG_BestOfEurope_S04_EffectivePostLayoutVerification/index.htmlWed, 28 Apr 2010 07:00:00 GMTThis tutorial addresses feasibility during the pre-route stages of the design flow and introduces an automated way to identify and analyze problems that impact timing, routability and congestion. http://solvnet.synopsys.com/onlinetraining/SNUG_BestOfEurope_S06_ICCompilerFeasibility/index.htmlWed, 28 Apr 2010 07:00:00 GMTThis paper describes using the black-box flow in IC Compiler for early floorplanning analysis and timing checks in a 65nm ASIC with large busses. This approach saves development time and, for the first time, supports a real RTL-backend co-design. http://solvnet.synopsys.com/onlinetraining/SNUG_BestOfEurope_S10_ExperiencesWICCBlackBoxFlow/index.htmlWed, 28 Apr 2010 07:00:00 GMTJoin this webinar to hear directly from senior product team members on how you can achieve superior results faster utilizing sophisticated optimizations of DC Ultra. http://us02vwwww1/cgi-bin/protected/dcultra/webinar/reg1.cgiTue, 21 Apr 2009 07:00:00 GMT