Synopsys Webinars

Advanced-node Custom Layout Using the Laker Custom IC Solution

Thu, 30 May 2013 07:00:00 GMT

Learn about Laker’s rule-based layout, schematic-driven layout, and pattern-based multi-device layout features--ideal solutions for those seeking to improve custom layout productivity at 20-nm and below.

Verilog-to-Verilog Equivalence Checking Using ESP

Wed, 29 May 2013 07:00:00 GMT

This Webinar gives a quick introduction to ESP-CV and how recent features are used to verify various Verilog-to-Verilog scenarios. Coverage analysis of the results is also discussed.

Samsung Foundry and Synopsys Discuss Enabling 14-nm FinFET Design

Tue, 28 May 2013 07:00:00 GMT

Samsung Foundry and Synopsys present the challenges and opportunities of manufacturing with Samsung's 14-nm FinFET process and how these changes impact design enablement.

TSMC and Synopsys Present: DFTMAX Compression, Hierarchical Test and iJTAG

Thu, 23 May 2013 07:00:00 GMT

As the complexity of systems-on-chip increases, so does the need to leverage standards-based methodologies to implement test in a hierarchical manner, across multiple cores.

Transaction Debug with Verdi3

Wed, 22 May 2013 07:00:00 GMT

In this webinar, you'll learn how to maximize your productivity by using Verdi's Transaction Debugging technology to dump, visualize and trace transactions. You'll learn how the tool's vertical correlation allows you to take the debug to the signal level waveform while retaining all of the necessary debugging details.

Discovery-AMS for Mixed-Signal Verification - An ST-Ericsson Case Study

Tue, 21 May 2013 07:00:00 GMT

ST-Ericsson shares details on how they leveraged new Discovery-AMS multi-core technology to improve their overall verification flow.

Conquering HSPA+ Modem Design

Wed, 15 May 2013 07:00:00 GMT

To understand the design flow and provide an introduction to InterDigital’s HSPA+ modem IP.

3 Easy Ways to Accelerate Development of your Embedded SoC

Tue, 14 May 2013 07:00:00 GMT

In this webinar we will show you 3 easy ways to accelerate development time for your embedded SoC software with the DesignWare ARC EM Starter Kit.

Achieving Predictable and Highly Reliable 10G Backplane Designs

Thu, 09 May 2013 07:00:00 GMT

This webinar explores the challenges of implementing 10G backplane systems. The webinar walks through a case study and explores techniques that help designers meet stringent backplane requirements.

Late-Stage Leakage Recovery using the Lynx Design System

Wed, 08 May 2013 07:00:00 GMT

The rate of increase in SoC design complexity continues to challenge even the most experienced design teams. Synopsys’ Lynx Design System can help manage many of these complexities. This webinar will discuss strategies that leverage Final Stage Leakage-Power Recovery (FSLR) in IC Compiler, the new PrimeTime ECO Leakage flow and multi-channel libraries to recover leakage power late in the design cycle. These methodologies, as a part of a complete RTL-to-GDSII design solution available in Lynx, can help you achieve your power targets while maintaining design performance. These capabilities will be shown live in a short demo.

Case Study: Design and FPGA-Prototyping of an Application Specific Processor for Embedded Vision

Tue, 07 May 2013 07:00:00 GMT

This webinar introduces Synopsys’ Vision Processor Design and Prototyping solution, featuring Processor Designer and HAPS FPGA-prototyping.

Ease Debug and Control of Network Software Using Virtual Prototypes to Do Full System Simulation

Thu, 02 May 2013 07:00:00 GMT

Learn how you can use a virtual prototype with a DesignWare Gigabit Ethernet model and ARM Cortex-A processor models to simulate a network application like e.g. a server farm.

Implementing Ethernet QoS for use in Automotive Networking Designs

Wed, 01 May 2013 07:00:00 GMT

Learn about Ethernet in automotive designs, Audio Video Bridging (AVB), the driving forces and predictions for Ethernet in the automotive market, and Synopsys’ DesignWare Ethernet QoS IP solution.

New Features and Updates: Sentaurus TCAD (H-2013.03)

Tue, 30 Apr 2013 07:00:00 GMT

Learn about the new features and enhancements in our H-2013.03 release of Sentaurus TCAD products . Continuing with our effort to enable modeling of technologies at the cutting edge of both, More-Moore and More-than-Moore technologies, we have recently introduced new features and model enhancements for FinFETs and alternative channel transistors, high power wide-band-gap devices and opto-electronics.

Optimizing and Validating the Performance of Your AMBA®4 Interconnect

Thu, 25 Apr 2013 07:00:00 GMT

Learn how to use Synopsys Platform Architect to drive performance criteria that can now be verified in the functional verification process through tight integration with Synopsys Verification IP.

A Hierarchical, Low Power Design Approach for Gigascale Designs

Wed, 24 Apr 2013 07:00:00 GMT

This webinar will help you understand the best practices for implementation of a Multi-Voltage hierarchical design using the IEEE 1801 (UPF) standard.

What, Where, Who? Integrating Audio Analog Functionality into SoCs (Mandarin)

Wed, 10 Apr 2013 07:00:00 GMT

Learn what performance trends to consider, where in the system to integrate audio, what challenges are associated with integrating audio in advanced nodes and who to consider in a make vs buy decision.

Verifying Advanced Low Power Designs: Find Design-Killing LP Bugs Early and Easily

Thu, 04 Apr 2013 07:00:00 GMT

Learn how VCS with MVSIM Native Low Power provide the accuracy and comprehensive LP support needed at RTL, and enable LP bugs to be found and fixed early and easily in the design cycle.

Logic Libraries for High-Performance, Processor-Based, Energy-Efficient SoCs

Tue, 02 Apr 2013 07:00:00 GMT

Learn about ways to maximize system performance while managing power budgets of CPU, GPU, and other SoC blocks, each with different performance/power/area targets.

Reducing Multi-mode STA Turnaround Time with PrimeTime Mode Merging - LSI Case Study

Wed, 27 Mar 2013 07:00:00 GMT

This webinar will introduce new PrimeTime technology to help design teams manage scenario increases by merging modes. LSI will discuss how PrimeTime mode merging allows them to reduce timing analysis.

Accelerate PCIe Integration Testing with Next-Generation Discovery VIP

Wed, 20 Mar 2013 07:00:00 GMT

Learn an optimal strategy for integration testing using UVM in conjunction with next-generation features of PCIe VIP for more efficient test development, error injection and debug.

Designing with FinFETs

Thu, 14 Mar 2013 07:00:00 GMT

Learn about the benefits and challenges of transitioning from planar to FinFET technologies and their implications for IP design.

Recover Leakage and Maintain Signoff Timing Using PrimeTime ECO - Simplified Mandarin

Tue, 12 Mar 2013 07:00:00 GMT

This webinar will introduce new PrimeTime ECO technology designed to reduce leakage power while maintaining signoff QoR. We’ll share customer data from Samsung and STMicroelectronics.

Recover Leakage and Maintain Signoff Timing Using PrimeTime ECO - Traditional Mandarin

Tue, 12 Mar 2013 07:00:00 GMT

This webinar will introduce new PrimeTime ECO technology designed to reduce leakage power while maintaining signoff QoR. We’ll share customer data from Samsung and STMicroelectronics.

10 ways to Debug your FPGA Design

Tue, 12 Feb 2013 08:00:00 GMT

Learn how to cut FPGA debug time with more effective diagnosis of FPGA design setup and design specifications, and by identifying design errors en-masse in a single iteration. If you are an ASIC designer, learn techniques to more quickly make your design "FPGA friendly" to get working FPGA implementation on the board.

New FPGA-based Prototyping Solution: HAPS-70 Series - Best Practices

Wed, 06 Feb 2013 08:00:00 GMT

This webinar is intended for designers who are already prototyping their ASIC design or considering prototyping their next ASIC design. Learn about best practices and new HAPS-70 system technology.

Accelerating Embedded Software Development for Renesas RH850 Microcontroller

Thu, 31 Jan 2013 08:00:00 GMT

Learn about the concepts of virtual prototyping and their application to the Renesas RH850 MCU family through the Renesas Velocity Lab and the Synopsys VDK for Renesas RH850 MCU.

Recover Leakage and Maintain Signoff Timing – with Customer Case Studies

Tue, 29 Jan 2013 08:00:00 GMT

This webinar will introduce PrimeTime ECO technology designed to recover leakage power, without introducing timing violations. We’ll share customer data that shows leakage power recovery up to 40%.

Designing to the New PCI Express 3.0 Equalization Requirements

Thu, 24 Jan 2013 08:00:00 GMT

Designers using PCI Express 3.0 should attend this technical webinar to understand the new Tx and Rx equalization enhancements such as CTLE and DFE, necessary for optimal interconnect performance.

Accelerate Design Closure with PrimeRail In-Design Rail Analysis

Wed, 23 Jan 2013 08:00:00 GMT

Hear how to use PrimeRail’s In-Design Rail Analysis within IC Compiler to help you identify problems early in the design cycle and achieve faster design closure.

Proven Techniques for Hierarchical Design Complexity using Lynx (Simplified Chinese)

Mon, 21 Jan 2013 08:00:00 GMT

You will learn about advanced f techniques within Synopsys' IC Compiler and Lynx Design System to manage hierarchical design complexity.

Synopsys Vision Processor Starter Kit: Implementing Embedded Vision Applications Optimized for Power

Wed, 16 Jan 2013 08:00:00 GMT

This webinar introduces the new Vision Processor Starter Kit from Synopsys, featuring Processor Designer, the industry’s leading ASIP design tool.

ARC Processors for Linux: Embedded Linux has a New Kid in Town

Tue, 15 Jan 2013 08:00:00 GMT

Learn how Synopsys optimized its DesignWare® ARC™ processor to run Linux and what open source tools and software are available to support the processor.

Functional Signoff: Measuring and Improving Verification Quality to Ensure Bug-Free Designs

Thu, 10 Jan 2013 08:00:00 GMT

In this webinar you will learn how Certitude Functional Qualification can be added to traditional coverage techniques, to provide unique insight into the quality of RTL simulation and formal verification environments. Certitude uses a proprietary mutation-based process to insert “artificial bugs” or faults into the design and measure the ability of your existing verification environment to detect these faults. The results of this process provide an objective measure of overall verification quality – the ability of the environment to activate, propagate and detect potential bugs – and identify specific holes and weaknesses like incomplete test scenarios, missing checkers and assertions, or infrastructure problems that can allow RTL bugs to slip through the process undetected. Fixing these weaknesses makes your verification environment stronger and reduces the risk of signing off or taping out with functional bugs.

Reducing Design Margins Using PrimeTime Advanced OCV - Simplified Mandarin

Wed, 12 Dec 2012 08:00:00 GMT

Learn how designers are using Advanced OCV to speed design closure by eliminating overly pessimistic violations, and hear about customer and foundries’ deployment and support model for this technology.

Reducing Design Margins Using PrimeTime Advanced OCV - Traditional Mandarin

Wed, 12 Dec 2012 08:00:00 GMT

Using Advanced Verification IP Capabilities to Accelerate Ethernet Verification

Tue, 11 Dec 2012 08:00:00 GMT

This webinar will be based around a typical Ethernet switch design including a processor, switch fabric and Ethernet MACs. Learn how SystemVerilog, UVM and VIP are utilized to verify the Ethernet digital core and then integration of the core into the system. We also cover advanced VIP features, including test suite and debug, to accelerate productivity.

Fujitsu’s Experience: Addressing Large Design Challenges with the latest Design Compiler Technologies

Thu, 06 Dec 2012 08:00:00 GMT

Increased design size and complexity can lead to exponential growth in turn-around-time (TAT). This webinar describes the methodology Fujitsu developed using DC Explorer and Design Compiler Graphical to achieve faster design convergence and reduced TAT on large, 40 million+ instance designs. You will hear how DC Explorer speeds up the development of high-quality RTL and constraints and generates an early netlist for guiding and optimizing floorplanning. This early floorplan exploration helps identify layout issues and provides more accurate area estimation up-front in the design flow to help create optimal design partitions, with a better starting point for implementation. Learn how Fujitsu then uses Design Compiler Graphical to achieve higher performance and tighter correlation with place and route for faster design convergence.

Double Patterning Ready Extraction and Signoff: TSMC and Synopsys Update

Wed, 05 Dec 2012 08:00:00 GMT

Learn how double patterning technology (DPT) has emerged as a critical technique to ensure printability of device and interconnects layers in IC manufacturing.

Double Patterning Ready Extraction and Signoff: TSMC - Simplified Mandarin

Wed, 05 Dec 2012 08:00:00 GMT

Learn how double patterning technology (DPT) has emerged as a critical technique to ensure printability of device and interconnects layers in IC manufacturing.

Double Patterning Ready Extraction and Signoff: TSMC and Synopsys Update - Traditional Mandarin

Wed, 05 Dec 2012 08:00:00 GMT

Learn how double patterning technology (DPT) has emerged as a critical technique to ensure printability of device and interconnects layers in IC manufacturing.

Synopsys Automotive Solutions

Wed, 14 Nov 2012 08:00:00 GMT

The electrical and electronic content of modern vehicles continues to grow creating many significant design and verification challenges for automotive OEMs and Tier 1 companies. This webinar provides an overview of these challenges and how Synopsys’ automotive solutions for under-the-hood and driver assistance applications are helping automotive companies worldwide manage the increasing software content and system complexity due to the proliferation of electronic hardware and power systems in modern automobiles.

Demystifying DDR4 SDRAM for Embedded Applications

Tue, 13 Nov 2012 08:00:00 GMT

Learn about the major features of DDR4 SDRAM as they apply to embedded applications, including key areas for SoC designers to note to take advantage of DDR4’s enhancements over previous generations.

LTE-Advanced Modems Coming to Life

Thu, 08 Nov 2012 08:00:00 GMT

This webinar will explain the steps that need to be taken at the different stages of the design process, and how these steps can be integrated into a complete design and verification flow.

Samsung and Synopsys Share Multicorner-Multimode Perspectives

Wed, 31 Oct 2012 07:00:00 GMT

This webinar highlights strategies for dealing with the large number of scenarios in the physical implementation flow. Samsung Semiconductor Inc. shares their experience using the IC Compiler- based MCMM solution to successfully meet their aggressive design objectives and Synopsys shares its multicorner-multimode (MCMM) design solution for addressing variability and design complexity at advanced technology nodes.

Static Verification of Advanced Low Power Designs

Tue, 30 Oct 2012 07:00:00 GMT

Learn about advanced low power techniques and the static checking capabilities designers need to verify the consistency and correctness of low power intent and implementation through the flow.

A Large Capacity SRAM Alternative to Embedded DRAM (Mandarin)

Thu, 25 Oct 2012 07:00:00 GMT

Learn how combining innovative power management schemes with TSMC certified bitcells delivers a compelling alternative to embedded DRAM.

Accelerate Time-to-Tapeout with IC Compiler Custom Co-Design

Wed, 24 Oct 2012 07:00:00 GMT

Learn how using IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits to IC Compiler designs at any stage of development.

Low Power Video Processing for the Mobile SoC

Thu, 18 Oct 2012 07:00:00 GMT

Learn how Synopsys Platform Architect is used to efficiently explore and optimize the HW-SW partitioning and mapping to get the most from Embedded GPUs.

Open Your Eye with HSPICE Fast and Accurate Eye Diagram Analysis

Wed, 17 Oct 2012 07:00:00 GMT

Learn how HSPICE can help you quickly model high-frequency channel components, run fast transient with long cable S-parameter models, and accurately analyze eye measurement.

Eliminate the Digital Implementation Bottleneck with Fast and Accurate Library Characterization

Tue, 16 Oct 2012 07:00:00 GMT

Learn how SiliconSmart can help you produce accurate model libraries that are tightly correlated with Synopsys' digital implementation tools and PrimeTime

Debugging with Virtual Prototypes

Thu, 11 Oct 2012 07:00:00 GMT

Learn about the Lauterbach TRACE32 development tool and its seamless integration with Virtualizer, supporting a broad set of debugging capabilities for virtual prototypes.

New Features and Methodologies for Simplifying Hierarchical Low Power Verification with Formality

Wed, 10 Oct 2012 07:00:00 GMT

This webinar will discuss new features in Formality to help make low power hierarchical verification easer. We will also cover how to write your power intent (UPF) to help you implement a robust, simplified, hierarchical verification flow.

Memory Timing Analysis and Characterization using NanoTime

Tue, 09 Oct 2012 07:00:00 GMT

This webinar will outline the advanced features in NanoTime that enable designers to accurately and quickly identify timing issues associated with the embedded SRAM. Complex clocking analysis and mode.

Accurate Early Stage Power Estimation with PrimeTime PX: The NVIDIA Experience

Thu, 04 Oct 2012 07:00:00 GMT

In this webinar we will review the need for early power analysis, and show how useful power estimates can be achieved even with early and/or incomplete data. NVIDIA will outline their strategies.

Deploying UVM Effectively: How to Simplify Testbench Debug and Improve Turn-around-time with VCS

Tue, 02 Oct 2012 07:00:00 GMT

Learn how to utilize VCS and DVE to most effectively deploy, debug and optimize UVM testbenches.

FinFET Process Modeling and Extraction at 16-nm and Below

Thu, 27 Sep 2012 07:00:00 GMT

Synopsys' R&D will discuss the motivation behind FinFETs and describe how Synopsys is driving the collaboration with major foundries to develop a next-generation extraction solution.

Proven Techniques for Hierarchical Design Complexity using Lynx

Wed, 26 Sep 2012 07:00:00 GMT

In this webinar, you will learn about advanced flows and techniques available with Synopsys' IC Compiler and Lynx Design System to manage hierarchical design complexity.

Save Weeks Fixing ECOs with PrimeTime (Simplified Mandarin)

Wed, 26 Sep 2012 07:00:00 GMT

Learn how PrimeTime Next-Generation ECO guidance automatically fix DRC, setup and hold violations to reduce iterations and shorten ECO fixing turn-around time.

Save Weeks Fixing ECOs with PrimeTime (Traditional Mandarin)

Wed, 26 Sep 2012 07:00:00 GMT

Learn how PrimeTime Next-Generation ECO guidance automatically fix DRC, setup and hold violations to reduce iterations and shorten ECO fixing turn-around time

What, Where, Who? Integrating Audio Analog Functionality into SoCs

Tue, 25 Sep 2012 07:00:00 GMT

Sentaurus TCAD G-2012.06 New Features and Updates

Thu, 20 Sep 2012 07:00:00 GMT

This webinar presents the new features and enhancements in the G-2012.06 release of Sentaurus TCAD.

Achieve Lower Silicon Cost Using Embedded Memory Test and Repair

Wed, 19 Sep 2012 07:00:00 GMT

Learn about the technical trends and challenges associated with embedded test, repair and diagnostics in today’s designs and how Synopsys’ STAR Memory System® addresses these challenges.

Debugging Methods for FPGA-Based Prototypes - Best Practices for System Troubleshooting and RTL Debug

Tue, 18 Sep 2012 07:00:00 GMT

Learn about new methods and technology to increase the ROI of an FPGA-based prototype and expand its role for hardware/software validation.

Verification of MIPI Protocols on a Mobile Platform SoC

Tue, 07 Aug 2012 07:00:00 GMT

This webinar is based around a MIPI-based mobile platform that consists of an application processor, baseband IC and RF IC with interfaces to the peripheral devices like camera, and display. The Webinar shows how SystemVerilog, UVM and verification IP (VIP) are utilized to verify the SoC that implements that platform. It will specifically focus on how to validate the data flow for typical scenarios involving the camera (CSI) and display (DSI) interfaces.

Optimizing Power in High-Performance SoCs using Multiple Voltage/VT/Channel Length Libraries

Thu, 02 Aug 2012 07:00:00 GMT

Learn ways to maximize system performance and minimize cost while slashing power budgets of SoC blocks operating at different clock speeds.

5X Faster PrimeTime Multivoltage Timing Signoff: A Renesas Case Study

Tue, 31 Jul 2012 07:00:00 GMT

Learn how PrimeTime’s new multivoltage aware analysis technology reduces risk and speeds signoff for designs with multiple voltage domains, and how Renesas has successfully deployed it to reduce signoff turnaround time by 5X.

A Large Capacity SRAM Alternative to Embedded DRAM

Thu, 19 Jul 2012 07:00:00 GMT

Learn how combining innovative power management schemes with TSMC certified bitcells delivers a compelling alternative to embedded DRAM.

Enabling 3D-IC Integration

Wed, 18 Jul 2012 07:00:00 GMT

Hear how Xilinx is using SSI technology to deliver higher levels of integration and flexibility in FPGA products, and learn how Synopsys' silicon-proven tools are enabling 3D-IC integration.

High-Productivity Analog Verification and Debug with CustomSim and CustomExplorer Ultra

Wed, 11 Jul 2012 07:00:00 GMT

See how Synopsys' advanced analog verification solution can dramatically increase your verification productivity with CustomExplorer Ultra, along with CustomSim and CustomSim-VCS.

Chinese Version: Audio IP Subsystems Made Easy with a Complete, SoC-Ready Solution

Thu, 28 Jun 2012 07:00:00 GMT

Learn how dedicated audio subsystems can offload the audio processing from the host processor, thus reducing design complexity and improving performance and efficiency of SoCs.

Reduce Mobile Device Costs and Board Area with MIPI Low Latency Interface (LLI) and M-PHY

Wed, 27 Jun 2012 07:00:00 GMT

Learn how the MIPI Alliance Low Latency Interface (LLI) and M-PHY can help future-proof a mobile device design while giving it an advantage in cost, board space, performance, and time-to-market.

AMD Perspective: Achieving Superior QoR Faster with the Latest Design Compiler Technologies

Tue, 19 Jun 2012 07:00:00 GMT

Jack Randall, principal member of the technical staff at AMD, describes his design methodology for implementing a low power, multi-million instance processor core with the latest Design Compiler technologies.

Improved Test for Pin-Limited and Multi-Voltage Designs Using DFTMAX™ Compression and TetraMAX® ATPG

Wed, 23 May 2012 07:00:00 GMT

Learn how to use Synopsys' synthesis-based test solution to reduce test cost and improve test quality for designs with few available test pins, and for designs with multiple power domains.

Foundry-Fabless Collaboration for Higher Starting Yields and Faster Yield Ramp

Thu, 17 May 2012 07:00:00 GMT

Learn about GLOBALFOUNDRIES??? foundry-fabless collaboration model for volume diagnostics that resolves the issue of gaining access to closely guarded design data by eliminating the need for design IP to leave foundry customers.

Early Optimization of Multicore SoC Architectures Using Synopsys' Platform Architect and Arteris FlexNoC

Tue, 15 May 2012 07:00:00 GMT

Learn how to efficiently explore and optimize the dynamic system performance of an Arteris FlexNoC based SoC design in SystemC using a mobile device case study example in Synopsys' Platform Architect.

Faster Timing Closure with the Lynx Design System

Wed, 09 May 2012 07:00:00 GMT

Using the Lynx Design System, you will learn how to leverage the advanced timing closure features available with Synopsys’ IC Compiler and PrimeTime.

Chinese Version: ARC Android - Making Android Affordable Anywhere

Wed, 09 May 2012 07:00:00 GMT

Learn about the ARC processor architecture in the DesignWare ARC Android solution which enables performance optimizations for the most power and cost sensitive market segments.

Achieving Rapid Verification Convergence of ARM® AMBA® 4 ACE™ Designs using Discovery™ VIP

Tue, 08 May 2012 07:00:00 GMT

Overview of challenges of verifying a coherent design. Shows how the features and architecture of Synopsys’ new Discovery VIP helps overcome these challenges to simplify verification of ACE design.

Achieving Verification Success with Formality while Enabling the Best QoR with Design Compiler

Thu, 03 May 2012 07:00:00 GMT

Learn how Formality utilizes powerful links with Design Compiler that enable you to achieve maximum Quality of Results (QoR) while maintaining verifiability.

Enabling 20nm Design: A Foundry and EDA Perspective

Tue, 01 May 2012 07:00:00 GMT

TSMC and Synopsys will jointly present some of the key design and manufacturing challenges at 20nm process technology. They will highlight the need for early collaboration between EDA, customers and the foundry to ensure a smooth path to tape-out and first-time silicon success.

Audio IP Subsystems Made Easy with a Complete, SoC-Ready Solution

Thu, 26 Apr 2012 07:00:00 GMT

Learn how dedicated audio subsystems can offload the audio processing from the host processor, thus reducing design complexity and improving performance and efficiency of SoCs.

Faster PrimeTime Signoff - Tips, Tricks and New Technology

Wed, 25 Apr 2012 07:00:00 GMT

Learn how to achieve a 2X reduction in signoff TAT, and build the expertise to create high-performance signoff scripts.

Effect of Jitter on Data Converters

Tue, 24 Apr 2012 07:00:00 GMT

Learn about the frequency domain mechanisms that relate jitter to sampling errors which enables designers to handle the design trade-offs and to achieve optimal system and data converter performance.

SoC FPGA Virtual Target: A Virtual Prototyping Application

Thu, 19 Apr 2012 07:00:00 GMT

In this webinar, you will be introduced to the Altera SoC FPGA for the Altera Cyclone V and Arria V SoC FPGA devices and its associated Virtual Target.

Bringing Embedded MTP NVM IP to Advanced Process Nodes

Thu, 12 Apr 2012 07:00:00 GMT

Learn how Synopsys aligns application/market needs to provide embedded multiple time programmable (MTP) non-volatile memory (NVM) IP at advanced nodes with optimized, targeted technology capabilities

Design and Analysis of ESD Protection Structures with Sentaurus TCAD

Wed, 11 Apr 2012 07:00:00 GMT

Hear Synopsys discuss the physical modeling of ESD structures, with a focus on the underlying physical mechanisms that limit protection, and illustrate the TCAD ESD design methodology in a 32nm bulk C

Efficient Clock Distribution: A Critical Factor in Design Performance

Wed, 04 Apr 2012 07:00:00 GMT

Synopsys and LSI jointly present on designing today’s high frequency, low power clocks. LSI will present their perspective on the challenges of clock distribution and Synopsys will focus on the solutions that enable designers to achieve the best QoR and lowest power at today’s advanced technology nodes.

Streamlining Your ECO Flow For Fastest Setup, Hold and Timing DRC Closure

Wed, 14 Mar 2012 07:00:00 GMT

Learn what’s new with timing-aware DRC guidance for ECOs and which design flow and tool settings provide the fastest timing closure at 28 nm and below.

LTE-A Physical Layer Design & Simulation

Thu, 08 Mar 2012 08:00:00 GMT

Learn about the LTE-Advanced standard (3GPP Rel.10), its main enhancements over LTE Rel.8 and their impact on the overall system performance.

Low Power Designs Made Easy: Create, Visualize and Debug Your Power Intent

Wed, 07 Mar 2012 08:00:00 GMT

This webinar will show you the various steps to easily generate, view, refine and debug the power intent of your design, as specified with the IEEE 1801 (UPF) format. You will learn effective techniques to speed up the implementation of your advanced low power designs. This webinar will be valuable for both new and experienced users of power intent. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.

Programmable Hardware Accelerators Made Easy: Implementing Custom Processors without Compromising Performance, Power or Area

Tue, 28 Feb 2012 08:00:00 GMT

Learn how custom processors or ASIP can provide the right trade-off between flexibility and power, performance and area requirements.

ARC Android - Making Android Affordable Anywhere

Wed, 18 Jan 2012 08:00:00 GMT

Learn about the ARC processor architecture in the DesignWare ARC Android solution which enables performance optimizations for the most power and cost sensitive market segments.

Managing Hierarchical, Low Power Design Challenges with the Lynx Design System

Tue, 17 Jan 2012 08:00:00 GMT

In this seminar, we will demonstrate silicon-proven methodologies to describe power intent with IEEE 1801 (UPF) using a hierarchical design flow to address power consumption and design size concurrently. We will walk you through some of the key steps in implementing and analyzing a hierarchical design using UPF for both bottom-up and top-down Synopsys Galaxy-based flows.

Lowering Validation Costs for Multi-Channel, Wideband Digital Systems Using FPGA-Based Prototyping

Wed, 11 Jan 2012 08:00:00 GMT

See examples of how FPGA-based prototyping can be used to deal with the high data rates of multi-channel, wideband digital systems while reducing systems validation and hw/sw integration costs.

Reliability and Qualification of MTP NVM IP from Commercial to Automotive Applications

Tue, 10 Jan 2012 08:00:00 GMT

How Synopsys designs and executes on a silicon testing methodology for embedded MTP NVM IP technology, enabling SoC designers with reliable and qualified solutions for their end applications

Get the Most from Your HSPICE Simulation

Wed, 30 Nov 2011 08:00:00 GMT

Unleash the power of HSPICE simulations with useful tips and tricks to reduce simulation time without compromising HSPICE’s gold-standard accuracy.

LTE-A Physical Layer Design: Downlink

Tue, 15 Nov 2011 08:00:00 GMT

Learn about the LTE-A standard (Rel.10) with a focus on the downlink configuration, and understand the main enhancements over LTE Rel.8 and their implication on the overall system complexity.

Expediting Design Schedules with DC Explorer - Qualcomm’s Experience

Tue, 01 Nov 2011 07:00:00 GMT

Learn how DC Explorer enables early RTL exploration leading to a better starting point for RTL synthesis and accelerates design implementation.

Meet Your Schedule with New ECO Verification and Other Enhancements in Formality

Thu, 27 Oct 2011 07:00:00 GMT

Hear about the new ECO Verification capabilities in Formality and other key new features, including its low power library checker, ease of use improvements and runtime enhancements.

Understand and Avoid Electromigration (EM) & IR-drop Effects in Custom IP Blocks

Wed, 26 Oct 2011 07:00:00 GMT

Learn how process technology & changing design styles increase the impact of EM & IR-drop effects on the performance/reliability of AMS, memory & custom digital IP blocks at 28nm and below.

Faster Clock Analysis and Debug

Tue, 25 Oct 2011 07:00:00 GMT

Learn how to save time using Galaxy Constraint Analyzer and PrimeTime to ensure clean clock constraints and keep clocks free of timing violations during signoff.

Introducing the DesignWare ARC EM 32-bit Processor Family for Embedded Applications

Tue, 25 Oct 2011 07:00:00 GMT

Learn how the new ARC EM processor family enables development of advanced processors with optimum balance of performance, power and area; performance exceeding 1.5 DMPS/MHz; and power-efficiency of less than 2uW/DMIPS at 28-nm.

Chinese Version: Introducing the DesignWare ARC EM 32-bit Processor Family for Embedded Applications

Tue, 25 Oct 2011 07:00:00 GMT

Learn how the new ARC EM processor family enables development of advanced processors with optimum balance of performance, power and area.

Addressing Challenges at 20nm: A Foundry and EDA perspective

Mon, 24 Oct 2011 07:00:00 GMT

Synopsys and Samsung jointly present some of the key challenges of designing and manufacturing at 20nm. Learn about solutions that address these challenges.

Addressing the Challenges of Designing an AMBA(R)-based SoC with a PCI Express(R) Interface

Thu, 20 Oct 2011 07:00:00 GMT

The Webinar will explore trade-offs and implementation issues through lessons learned from the development of Synopsys DesignWare IP for PCI Express solutions and the customers that have used them.

Use IC Compiler and Custom Designer to Shave Weeks Off Your SoC Development Cycle

Wed, 19 Oct 2011 07:00:00 GMT

Learn how the seamless integration between IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits at any stage of development.

Chinese Version: Build Low-power, high-performance mobile SoCs with complete MIPI solutions

Mon, 17 Oct 2011 07:00:00 GMT

Learn about the building blocks and integration challenges faced by SoC designers integrating MIPI protocols to interface to camera, display, RFIC, storage and chip to chip connectivity.

Lighter, Easier and More Flexible Approaches for Multi-Voltage Low Power Design Specification

Wed, 12 Oct 2011 07:00:00 GMT

In this webinar you will learn how various ways of describing power intent with IEEE 1801 (UPF) can help you achieve more efficient low power designs. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.

New Features in TCAD Sentaurus: September 2011 Release

Thu, 06 Oct 2011 07:00:00 GMT

The latest release delivers new capabilities in advanced structure generation, new models in process and device simulation and new methods for modeling semiconductor device variability.

Reliability and Qualification of MTP NVM IP from Commercial to Automotive Applications

Wed, 05 Oct 2011 07:00:00 GMT

How Synopsys designs and executes on a silicon testing methodology for embedded MTP NVM IP technology, enabling SoC designers with reliable and qualified solutions for their end applications.

Advanced Fault-Injection Methods for Automotive Safety Critical Systems

Thu, 29 Sep 2011 07:00:00 GMT

Learn about fault-tolerance mechanism and fault-injection techniques and HW fault-tolerance mechanisms available in "state-of-the-art" Micro-Controller Units.

Embedded Memory Test and Repair Solution: Keeping Up with Changing Design Applications and Shrinking Process Technologies

Tue, 13 Sep 2011 07:00:00 GMT

This webinar discusses key points of interest for implementing embedded memory test, repair and diagnostics solution in today's designs.

Build low–power, high-performance mobile SoCs with complete MIPI solutions

Tue, 26 Jul 2011 07:00:00 GMT

Learn about the building blocks and integration challenges faced by SoC designers integrating MIPI protocols to interface to camera, display, RFIC, storage and chip to chip connectivity.

How to Enable Prototyping of Multi-Million ASIC Gate Designs

Thu, 21 Jul 2011 07:00:00 GMT

Learn how the new HAPS-600 series of FPGA-based prototyping systems enables early hardware & software validation, debug and development for much larger SoC projects than ever before. The webinar introduces this addition to the HAPS family and provides an overview of the complete solution. Designers can reduce initial turnaround times and subsequent iterations with the HAPS-600 series' highly automated software flow from RTL code to the FPGA-based prototype utilizing Synopsys' patented programmable switch routing technology.

Save Weeks Fixing ECOs with PrimeTime and IC Compiler

Wed, 20 Jul 2011 07:00:00 GMT

See how design teams are saving weeks during implementation and signoff. Learn how PrimeTime Next-Generation ECO guidance and IC Compiler automatically fix DRC, setup and hold violations to reduce it.

Optimize in Less Time: Rapid Design Exploration with Lynx Design System

Tue, 19 Jul 2011 07:00:00 GMT

Every SoC design requires a unique implementation strategy to navigate the tradeoffs between power, performance and area to achieve the best results for the specific use.

Faster, Safer Implementation of High-Reliability, High Availability Designs using FPGAs

Thu, 14 Jul 2011 07:00:00 GMT

Learn techniques on how to build high operation reliability into your FPGA designs in the face of radiation-induced errors in the field, and how to validate and trace the result of your design implementation before you deploy your FPGA-based system.

Using TetraMAX Diagnostics and Yield Explorer for Rapid Failure Analysis

Tue, 28 Jun 2011 07:00:00 GMT

Learn how TetraMAX ATPG and Yield Explorer provide a fully automated diagnostics solution for isolation of silicon defects and analysis of systematic yield issues.

Lithography Verification on Advanced Nodes with Proteus LRC

Fri, 03 Jun 2011 07:00:00 GMT

Learn about Proteus LRC, Synopsys' next-generation lithography rule check tool, and how it can be used to accelerate your technology ramp.

Modeling Semiconductor Device Variability with TCAD Sentaurus

Wed, 01 Jun 2011 07:00:00 GMT

Learn a methodology for variability analysis at the technology level combining 3D process simulation with a device simulation technique known as Impedance Field Method.

Fast Timing Constraint Cleanup with Galaxy Constraint Analyzer

Wed, 18 May 2011 07:00:00 GMT

Learn how Galaxy Constraint Analyzer helps to produce signoff-quality timing constraints quickly, for even the most complex designs. Hear how AMD uses Galaxy Constraint Analyzer for quality assurance.

Volume Diagnostics for Rapid Yield Ramp at Nanometer Nodes

Tue, 03 May 2011 07:00:00 GMT

Learn how Yield Explorer, Synopsys' unique design-centric yield analysis solution, can help you accelerate yield ramp for your next device.

Harness the Power of SystemVerilog with Design Compiler to Increase Productivity

Wed, 27 Apr 2011 07:00:00 GMT

Learn how the use of SystemVerilog constructs can result in concise, portable RTL that is easier to maintain and consistent with verification requirements.

Debug Timing Faster with PrimeTime Visualization Tools

Wed, 20 Apr 2011 07:00:00 GMT

Save time debugging complex timing paths during implementation and signoff using new visualization techniques in PrimeTime. See new clock and data analysis capabilities in action.

Reduce Power Consumption 30% with Advanced Synthesis Techniques

Thu, 14 Apr 2011 07:00:00 GMT

In this webinar you will learn how new advances in clock gating and voltage threshold (Vt) optimization available in Design Compiler can reduce your dynamic and leakage power by 10-30%. An interactive Q&A session follows the technical presentation.

Building High-Performance SoCs with Configurable and Extensible Processors

Thu, 07 Apr 2011 07:00:00 GMT

Learn how the configurable, extensible DesignWare® ARC™ 32-bit processors offers a broad range of features that enable you to tailor the core for your specific embedded or host application.

HDMI: Enabling the 3D Revolution

Thu, 31 Mar 2011 07:00:00 GMT

This webinar discusses the latest trends in HDMI and how advanced features address the challenges of implementing 3D capabilities in SoC design.

Modeling Semiconductor Reliability with TCAD Sentaurus

Wed, 30 Mar 2011 07:00:00 GMT

Learn how TCAD simulation can provide insight into underlying degradation mechanisms and can guide process changes to improve semiconductor reliability.

Implementing an Embedded Memory Subsystem in Mobile Applications

Tue, 29 Mar 2011 07:00:00 GMT

Learn how to minimize low-power design complexity for your mobile SoC applications with embedded memory IP that is optimized for power, performance and density.

Using IP-XACT to Streamline SoC Design and Verification

Thu, 17 Mar 2011 07:00:00 GMT

The IEEE IP-XACT specification is a valuable format that can help solve IP integration challenges when combined with quality tools designed for an IP-based design and verification flow.

Advanced Capabilities and Design Interaction with FPGA-Based Prototyping

Thu, 24 Feb 2011 08:00:00 GMT

In order to boost the utility of an FPGA-based prototyping platform, certain critical components are required, including a high-performance, low latency communication channel and direct access to all pins, signals, nodes and registers within the FPGA. Discover how the advanced capabilities of Synopsys HAPS(R) High-performance ASIC Prototyping System(TM) and the new Universal Multi-Resource Bus interface (UMRBus) improves the overall design, verification and software development of an ASIC or SoC.

Reducing Design Margins Using PrimeTime Advanced OCV – TSMC and User Views

Wed, 23 Feb 2011 08:00:00 GMT

Learn how designers are using PrimeTime Advanced OCV to speed design closure by eliminating overly pessimistic violations, and hear about TSMC’s views and support model for these new technologies.

Using ESP-CV for Faster Redundancy Verification in Memory Designs

Wed, 19 Jan 2011 08:00:00 GMT

Learn how ESP-CV performs functional equivalence checks between a Verilog design and its transistor level implementation.

New Features in TCAD Sentaurus: December 2010 Release

Tue, 18 Jan 2011 08:00:00 GMT

Introduction to new features in the December 2010 release of TCAD Sentaurus. Learn about Sentaurus' new capabilities in 3D structure generation, process modeling, quantization in device physics, variability modeling and optoelectronics.

LTE Physical Layer Design: Basics

Wed, 15 Sep 2010 07:00:00 GMT

Overview of the LTE standard, LTE simulation library and Synopsys SPW algorithm design tool.

LTE Physical Layer Design: Optimization

Wed, 18 Aug 2010 07:00:00 GMT

Learn more about LTE physical layer design and how design choices can impact implementation and performance.

Simulation of Power Devices with TCAD Sentaurus

Fri, 30 Jul 2010 07:00:00 GMT

A complete review of TCAD simulation of power devices from the latest trends to future outlook, including silicon-based, SiC & GaN power devices. (Japanese/English)

Utilizing Design Compiler to Double Synthesis and P&R Productivity

Thu, 22 Jul 2010 07:00:00 GMT

See how new Design Compiler 2010 technologies double the productivity of synthesis and P&R by enabling RTL designers to perform floorplan exploration while still in synthesis.

LTE Physical Layer Design: Synchronization

Wed, 21 Jul 2010 07:00:00 GMT

Learn more about some of the features of the LTE User Equipment (UE) acquisition and synchronization process.

Faster ECO Fixing Flows with PrimeTime and IC Compiler

Tue, 20 Jul 2010 07:00:00 GMT

This technical webinar will explain how IC Compiler and PrimeTime can be used to close timing during signoff. It will focus on the use of Distributed Multi-Scenario Analysis for automatic set-up and hold fixing, and will explain new PrimeTime 2010.06 DRC fixing capabilities. Attendees will learn how to minimize fixing run times, which approaches are best for closing setup and hold violations, and how to deploy SI fixing most effectively.

New Enhancements for Debugging Inconclusive and Non-Equivalent Verifications in Formality

Thu, 24 Jun 2010 07:00:00 GMT

This webinar will address what to do when faced with an inconclusive for non-equivalent design in Formality. Common types of failures will be discussed as well as suggestions for resolving them. New features in Formality 2010.03 will be presented which help the designer quickly identify the sources of the issue and makes recommendations on how to resolve them. Recent Formality low power enhancements will also be discussed.

Best of SNUG: New In-Design Features (IC Compiler, IC Validator, PrimeRail)

Thu, 10 Jun 2010 07:00:00 GMT

In-Design reliability analysis and physical verification save time by avoiding useless translations of data back and forth and also allow users to catch and fix problems on-the-go, preventing costly iterations between implementation and signoff.

Best of SNUG: Galaxy Constraint Analyzer: Constraint Debugging Made Easy

Thu, 10 Jun 2010 07:00:00 GMT

In today’s designs, it is not unusual to have hundreds of clocks, power management, multiple modes, in-house or third-party IP with their own set of timing constraints that need to be integrated at the top level. This increased complexity together with tighter schedules makes finalizing the design timing constraints extremely challenging.

Best of SNUG: Clock Tree Implementation Techniques—A Comparative Analysis

Thu, 06 May 2010 07:00:00 GMT

This paper demonstrates two techniques of clock tree implementation with comparative analysis data. The first is a traditional cluster-based clock tree common in ASIC flows (CTS), the other is a unique technique used in various high-frequency designs based on non-uniform fishbone mesh.

Best of SNUG: Simulation Acceleration using Multicore Systems

Thu, 06 May 2010 07:00:00 GMT

In this paper we show how to take advantage of multicore systems to accelerate simulation performance. First, we introduce an algorithm for automatically partitioning the design for multicore simulation. Second, we present an approach to use the GPU to further increase simulation acceleration (around 100X faster).

Best of SNUG: Scan Compression with Limited Pin Access

Thu, 06 May 2010 07:00:00 GMT

This presentation covers how the latest pin-limited testing enhancements have been deployed successfully on Wolfson’s latest devices.

Best of SNUG: Scan Compression without 'Scan Compression'

Thu, 06 May 2010 07:00:00 GMT

DFTMAX compression can achieve over 100X compression. However, small compression factors can be achieved using ”multi-mode” scan architectures. For small- and medium-size mixed-signal designs these provide a low-cost alternative to full compression.

Best of SNUG: Reducing the Cost of Pin-Limited Test using DFTMAX Compression

Thu, 06 May 2010 07:00:00 GMT

Designers are increasingly adopting DFT methodologies that limit the number of pins allocated for manufacturing test. In this tutorial, we examine what is driving this trend and how you can use new capabilities in DFTMAX to reduce the cost of pin-limited test for your designs.

Eliminating Late-Stage DRC Surprises with In-Design Physical Verification

Wed, 05 May 2010 07:00:00 GMT

Third in the In-Design technology series featuring several high productivity in-design physical verification flows with IC Validator, including Automatic DRC Repair and Pre-Routing Verification – all from within IC Compiler.

Best of SNUG: Effective Post-Layout Verification of AMS Designs at 28nm

Wed, 28 Apr 2010 07:00:00 GMT

Strategies and methods for correct Extracted View Sets generated with StarRC and results from a real design implemented at 28nm show how post-layout verification can be sped up, substantially improving the turnaround time of the AMS design flow.

Best of SNUG: IC Compiler Feasiblity, Planning and Implementation

Wed, 28 Apr 2010 07:00:00 GMT

This tutorial addresses feasibility during the pre-route stages of the design flow and introduces an automated way to identify and analyze problems that impact timing, routability and congestion.

Best of SNUG: Experiences with IC Compiler Black Box flow

Wed, 28 Apr 2010 07:00:00 GMT

This paper describes using the black-box flow in IC Compiler for early floorplanning analysis and timing checks in a 65nm ASIC with large busses. This approach saves development time and, for the first time, supports a real RTL-backend co-design.

Introduction to TCAD Sentaurus: March 2010 Release

Tue, 27 Apr 2010 07:00:00 GMT

Introduction to the latest release of TCAD Sentaurus including new features and capabilities for addressing technologies such as CMOS, memory, power, analog/RF and optoelectronics.

Design Compiler 2010: Double the Productivity of Synthesis and Place & Route

Tue, 20 Apr 2010 07:00:00 GMT

Learn about a new capability in Design Compiler that allows RTL designers to perform floorplan exploration from within the synthesis environment to efficiently achieve an optimal floorplan. Hear about Design Compiler’s new scalable infrastructure tuned for multicore processors yielding 2X faster synthesis runtimes on quad-core compute servers.

Custom Designer: Advances in Custom Layout Automation with SmartDRD

Tue, 23 Mar 2010 07:00:00 GMT

SmartDRD technology visualizes, prevents and automatically fixes DRC violations to help designers quickly achieve DRC clean designs with significantly reduced effort.

In-Design for Faster Design Closure

Tue, 02 Mar 2010 08:00:00 GMT

First in a series addressing 32/28nm sign-off bottleneck challenges and the solutions best suited to mitigate these challenges. Learn how Synopsys’ In-Design solutions make it possible for place-and-route engineers to accelerate design closure by enabling signoff analysis from within the implementation flow.

3-D TCAD Simulation with Sentaurus

Wed, 24 Feb 2010 08:00:00 GMT

The latest algorithms and best practices for 3-D TCAD simulation to derive maximum benefit from the comprehensive 3-D capabilities in Sentaurus TCAD.

Reducing Design Margins Using PrimeTime Advanced OCV

Wed, 17 Feb 2010 08:00:00 GMT

How Advanced On-Chip-Variation works in comparison to flat-derate OCV and SSTA-based signoff technologies. Techniques for deploying PrimeTime to reduce pessimistic endpoints and slack pessimism.

DesignWare IP for AMBA 3 AXI On-Chip Bus

Wed, 10 Feb 2010 08:00:00 GMT

This webinar details the flexible on-chip bus architecture of the DesignWare interconnect fabric that enables dedicated high-performance and shared low-performance links to be combined within a single AMBA 3 AXI on-chip interconnect, eliminating unnecessary logic within the design to deliver maximum bandwidth while reducing area, routing congestion and power.

Addressing Signal Integrity Noise in Low Power Design

Wed, 20 Jan 2010 08:00:00 GMT

A discussion on the impact of low power design and the resulting requirements that drive the technologies in today’s static timing analysis tools. Learn about PrimeTime SI techniques that will enable you to deploy the SI noise-aware flow that best fits your needs for fast, accurate signoff.

Simulation of Advanced Semiconductor Devices Including High-k/Metal-gate Transistors and FinFETs

Tue, 01 Dec 2009 08:00:00 GMT

This webinar discusses the application of TCAD to high-k/metal-gate transistors and 3-D modeling FinFET devices, focusing on the physical models and 3-D modeling techniques required to achieve successful simulations.

HSPICE/Custom Designer for Analog & RF Circuit Design

Thu, 05 Nov 2009 08:00:00 GMT

Analog/RF design solution helps meet design challenges

Front-to-Back AMS Flow using Custom Designer

Tue, 03 Nov 2009 08:00:00 GMT

Follow the front-to-back development of an AMS block using Synopsys' Galaxy Custom Designer implementation solution.

Stratix-based Algorithm Acceleration Prototyping

Thu, 29 Oct 2009 07:00:00 GMT

This webinar discusses how the unique features of Altera's high-end Stratix-FPGAs combined with Synopsys high-performance rapid protoyping solutions enable new use modes and capabilities for algorithmic acceleration, as well as for highest performance rapid prototyping.

Successful Equivalence Checking of Highly Optimized DC Ultra Designs

Tue, 21 Apr 2009 07:00:00 GMT

Join us for an in-depth technical webinar focused on how to achieve successful verification on high-performance designs compiled with DC Ultra.

Accelerate your design closure with DC Ultra

Tue, 21 Apr 2009 07:00:00 GMT

Join this webinar to hear directly from senior product team members on how you can achieve superior results faster utilizing sophisticated optimizations of DC Ultra.

Simulation of Multi-Junction Solar Cells Using TCAD Sentaurus

Wed, 15 Apr 2009 07:00:00 GMT

This webinar addresses the design and optimization of multi-junction solar cells using Synopsys' TCAD Sentaurus tools.

Achieving predictable success in FPGA Projects

Mon, 09 Mar 2009 07:00:00 GMT

This 3-part series introduces Synopsys tools for FPGA users, including model-based algorithmic design, IP integration tools, tightly coupled constraint and analysis environments, integrated synthesis and placement, and on-board assertion-based verification linked to RTL simulation.

Thin Film Solar Cell Simulation

Wed, 20 Aug 2008 07:00:00 GMT

Thin film solar cells are currently the focus of worldwide research and development efforts aimed at bringing to market more efficient and cost effective processes and designs.

Modeling Non-volatile Memory Technologies with Sentaurus TCAD

Thu, 29 May 2008 07:00:00 GMT

A new generation of non-volatile memory devices have kept scientists and designers busy researching and optimizing designs like SONOS memory, new materials like chalcogenide (GST) for Phase Change Memory, or means to pump charge into Nano Crystals to store information.

Gallium Nitride HFETs: Physical Models and Simulations for RF and Power Applications

Thu, 21 Feb 2008 08:00:00 GMT

This webinar concentrates on simulation of GaN HFET devices using TCAD Sentaurus Device including treatment of spontaneous and piezoelectric polarization effects, numerical accuracy settings, assignment of bulk and interface traps, and selection of mobility and transport models.