Synopsys Webinars

LTE-A Physical Layer Design & Simulation

Thu, 08 Mar 2012 08:00:00 GMT

Learn about the LTE-Advanced standard (3GPP Rel.10), its main enhancements over LTE Rel.8 and their impact on the overall system performance.

Programmable Hardware Accelerators Made Easy: Implementing Custom Processors without Compromising Performance, Power or Area

Tue, 28 Feb 2012 08:00:00 GMT

Learn how custom processors or ASIP can provide the right trade-off between flexibility and power, performance and area requirements.

Managing Hierarchical, Low Power Design Challenges with the Lynx Design System

Tue, 17 Jan 2012 08:00:00 GMT

In this seminar, we will demonstrate silicon-proven methodologies to describe power intent with IEEE 1801 (UPF) using a hierarchical design flow to address power consumption and design size concurrently. We will walk you through some of the key steps in implementing and analyzing a hierarchical design using UPF for both bottom-up and top-down Synopsys Galaxy-based flows.

Lowering Validation Costs for Multi-Channel, Wideband Digital Systems Using FPGA-Based Prototyping

Wed, 11 Jan 2012 08:00:00 GMT

See examples of how FPGA-based prototyping can be used to deal with the high data rates of multi-channel, wideband digital systems while reducing systems validation and hw/sw integration costs.

Reliability and Qualification of MTP NVM IP from Commercial to Automotive Applications

Tue, 10 Jan 2012 08:00:00 GMT

How Synopsys designs and executes on a silicon testing methodology for embedded MTP NVM IP technology, enabling SoC designers with reliable and qualified solutions for their end applications

Get the Most from Your HSPICE Simulation

Wed, 30 Nov 2011 08:00:00 GMT

Unleash the power of HSPICE simulations with useful tips and tricks to reduce simulation time without compromising HSPICE’s gold-standard accuracy.

LTE-A Physical Layer Design: Downlink

Tue, 15 Nov 2011 08:00:00 GMT

Learn about the LTE-A standard (Rel.10) with a focus on the downlink configuration, and understand the main enhancements over LTE Rel.8 and their implication on the overall system complexity.

Using High-Level Synthesis to Streamline ASIC Multi-Rate Communications Design

Thu, 03 Nov 2011 07:00:00 GMT

Learn how high-level synthesis can be used to efficiently create multi-rate hardware for ASIC and FPGA while keeping algorithm development simple.

Expediting Design Schedules with DC Explorer - Qualcomm’s Experience

Tue, 01 Nov 2011 07:00:00 GMT

Learn how DC Explorer enables early RTL exploration leading to a better starting point for RTL synthesis and accelerates design implementation.

Meet Your Schedule with New ECO Verification and Other Enhancements in Formality

Thu, 27 Oct 2011 07:00:00 GMT

Hear about the new ECO Verification capabilities in Formality and other key new features, including its low power library checker, ease of use improvements and runtime enhancements.

Understand and Avoid Electromigration (EM) & IR-drop Effects in Custom IP Blocks

Wed, 26 Oct 2011 07:00:00 GMT

Learn how process technology & changing design styles increase the impact of EM & IR-drop effects on the performance/reliability of AMS, memory & custom digital IP blocks at 28nm and below.

Faster Clock Analysis and Debug

Tue, 25 Oct 2011 07:00:00 GMT

Learn how to save time using Galaxy Constraint Analyzer and PrimeTime to ensure clean clock constraints and keep clocks free of timing violations during signoff.

Introducing the DesignWare ARC 32-bit Processor Family for Embedded Applications

Tue, 25 Oct 2011 07:00:00 GMT

Learn how the new ARC EM processor family enables development of advanced processors with optimum balance of performance, power and area; performance exceeding 1.5 DMPS/MHz; and power-efficiency of less than 2uW/DMIPS at 28-nm.

Addressing Challenges at 20nm: A Foundry and EDA perspective

Mon, 24 Oct 2011 07:00:00 GMT

Synopsys and Samsung jointly present some of the key challenges of designing and manufacturing at 20nm. Learn about solutions that address these challenges.

Extraction Features & PDKs for Accurate Analog Design

Thu, 20 Oct 2011 07:00:00 GMT

Learn how StarRC new custom design features including 3D symmetric net extraction, optimized PCELL solution, and qualified PDK support, enable accurate and productive analog/mixed-signal design.

Addressing the Challenges of Designing an AMBA(R)-based SoC with a PCI Express(R) Interface

Thu, 20 Oct 2011 07:00:00 GMT

The Webinar will explore trade-offs and implementation issues through lessons learned from the development of Synopsys DesignWare IP for PCI Express solutions and the customers that have used them.

Use IC Compiler and Custom Designer to Shave Weeks Off Your SoC Development Cycle

Wed, 19 Oct 2011 07:00:00 GMT

Learn how the seamless integration between IC Compiler and Galaxy Custom Designer accelerates the SoC design cycle by enabling quick and reliable custom edits at any stage of development.

Chinese Version: Build Low-power, high-performance mobile SoCs with complete MIPI solutions

Mon, 17 Oct 2011 07:00:00 GMT

Learn about the building blocks and integration challenges faced by SoC designers integrating MIPI protocols to interface to camera, display, RFIC, storage and chip to chip connectivity.

Using High-Level Synthesis and Open Source Imaging Libraries to Streamline ASIC/FPGA IP Development

Thu, 13 Oct 2011 07:00:00 GMT

Introduces a HLS flow from OpenCV (Open Computer Vision) environment using Synphony C Compiler. It will cover techniques in using C++ classes and templates to make re-usable imaging libraries.

Lighter, Easier and More Flexible Approaches for Multi-Voltage Low Power Design Specification

Wed, 12 Oct 2011 07:00:00 GMT

In this webinar you will learn how various ways of describing power intent with IEEE 1801 (UPF) can help you achieve more efficient low power designs. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.

New Features in TCAD Sentaurus: September 2011 Release

Thu, 06 Oct 2011 07:00:00 GMT

The latest release delivers new capabilities in advanced structure generation, new models in process and device simulation and new methods for modeling semiconductor device variability.

Reliability and Qualification of MTP NVM IP from Commercial to Automotive Applications

Wed, 05 Oct 2011 07:00:00 GMT

How Synopsys designs and executes on a silicon testing methodology for embedded MTP NVM IP technology, enabling SoC designers with reliable and qualified solutions for their end applications.

Advanced Fault-Injection Methods for Automotive Safety Critical Systems

Thu, 29 Sep 2011 07:00:00 GMT

Learn about fault-tolerance mechanism and fault-injection techniques and HW fault-tolerance mechanisms available in "state-of-the-art" Micro-Controller Units.

VCS Productivity Technologies - Reducing the Growing Verification Cycle

Wed, 21 Sep 2011 07:00:00 GMT

Learn about VCS’ most recent technology advancements and new features enabling productivity in the following key areas: performance and capacity, verification planning, coverage and debug.

Divide and Conquer: Faster FPGA Delivery using Hierarchical, Parallel Design Development

Tue, 20 Sep 2011 07:00:00 GMT

Lean how to use "divide and conquer" hierarchical approaches for parallel machine execution or team-based design, and how to develop, tweak and debug your FPGA design efficiently.

Embedded Memory Test and Repair Solution: Keeping Up with Changing Design Applications and Shrinking Process Technologies

Tue, 13 Sep 2011 07:00:00 GMT

This webinar discusses key points of interest for implementing embedded memory test, repair and diagnostics solution in today's designs.

New Advancements in Verification Methodology (VMM and UVM)

Thu, 28 Jul 2011 07:00:00 GMT

Learn about the latest improvements in verification performance and productivity including the new Synopsys features offered in support of standards-based SystemVerilog verification methodologies.

Build low–power, high-performance mobile SoCs with complete MIPI solutions

Tue, 26 Jul 2011 07:00:00 GMT

Learn about the building blocks and integration challenges faced by SoC designers integrating MIPI protocols to interface to camera, display, RFIC, storage and chip to chip connectivity.

How to Enable Prototyping of Multi-Million ASIC Gate Designs

Thu, 21 Jul 2011 07:00:00 GMT

Learn how the new HAPS-600 series of FPGA-based prototyping systems enables early hardware & software validation, debug and development for much larger SoC projects than ever before. The webinar introduces this addition to the HAPS family and provides an overview of the complete solution. Designers can reduce initial turnaround times and subsequent iterations with the HAPS-600 series' highly automated software flow from RTL code to the FPGA-based prototype utilizing Synopsys' patented programmable switch routing technology.

Save Weeks Fixing ECOs with PrimeTime and IC Compiler

Wed, 20 Jul 2011 07:00:00 GMT

See how design teams are saving weeks during implementation and signoff. Learn how PrimeTime Next-Generation ECO guidance and IC Compiler automatically fix DRC, setup and hold violations to reduce it.

Optimize in Less Time: Rapid Design Exploration with Lynx Design System

Tue, 19 Jul 2011 07:00:00 GMT

Every SoC design requires a unique implementation strategy to navigate the tradeoffs between power, performance and area to achieve the best results for the specific use.

Faster, Safer Implementation of High-Reliability, High Availability Designs using FPGAs

Thu, 14 Jul 2011 07:00:00 GMT

Learn techniques on how to build high operation reliability into your FPGA designs in the face of radiation-induced errors in the field, and how to validate and trace the result of your design implementation before you deploy your FPGA-based system.

Bringing Up and Optimizing Software Power Management Using Virtual Prototyping

Thu, 30 Jun 2011 07:00:00 GMT

This webinar introduces a solution to the challenges that software developers face when bringing up or optimizing system power management.

Using TetraMAX Diagnostics and Yield Explorer for Rapid Failure Analysis

Tue, 28 Jun 2011 07:00:00 GMT

Learn how TetraMAX ATPG and Yield Explorer provide a fully automated diagnostics solution for isolation of silicon defects and analysis of systematic yield issues.

FPGAs in the Signal Path: Comm and Video Apps

Thu, 23 Jun 2011 07:00:00 GMT

Whether it's communications or video, FPGAs are showing up more and more in the signal path because they offer performance to handle the load and flexibility to address a wide variety of signal processing tasks. IP and libraries, development kits, and board/system level solutions available today for innovative communications and video applications based on FPGAs let designers focus on getting the job done fast.

Lithography Verification on Advanced Nodes with Proteus LRC

Fri, 03 Jun 2011 07:00:00 GMT

Learn about Proteus LRC, Synopsys' next-generation lithography rule check tool, and how it can be used to accelerate your technology ramp.

Modeling Semiconductor Device Variability with TCAD Sentaurus

Wed, 01 Jun 2011 07:00:00 GMT

Learn a methodology for variability analysis at the technology level combining 3D process simulation with a device simulation technique known as Impedance Field Method.

Using High-Level Synthesis for the Design and Optimization of Multi-Rate Communications Hardware

Wed, 25 May 2011 07:00:00 GMT

In this webinar see concrete examples of how high-level synthesis can be used to efficiently create multi-rate hardware for ASIC and FPGA while keeping algorithm development simple.

Fast Timing Constraint Cleanup with Galaxy Constraint Analyzer

Wed, 18 May 2011 07:00:00 GMT

Learn how Galaxy Constraint Analyzer helps to produce signoff-quality timing constraints quickly, for even the most complex designs. Hear how AMD uses Galaxy Constraint Analyzer for quality assurance.

Advanced Regression and Analysis for Mixed-Signal Verification Using CustomExplorer Ultra

Wed, 11 May 2011 07:00:00 GMT

Learn how CustomExplorer Ultra enables high verification productivity for complex SoCs using advanced strategies that surpass traditional verification approaches.

Closing the Verification Gap: Integrating Algorithm and RTL Verification for Signal-Processing Apps

Thu, 05 May 2011 07:00:00 GMT

Learn how to take advantage of behavioral models for RTL verification to create an integrated signal-processing verification flow from algorithm concept to RTL.

Accurate Jitter and Noise Analysis Using HSPICE Transient Noise Techniques

Wed, 04 May 2011 07:00:00 GMT

Learn about new time-domain noise analysis approaches available in HSPICE, and how transient noise analysis can verify critical timing and noise performance characteristics.

Volume Diagnostics for Rapid Yield Ramp at Nanometer Nodes

Tue, 03 May 2011 07:00:00 GMT

Learn how Yield Explorer, Synopsys' unique design-centric yield analysis solution, can help you accelerate yield ramp for your next device.

Harness the Power of SystemVerilog with Design Compiler to Increase Productivity

Wed, 27 Apr 2011 07:00:00 GMT

Learn how the use of SystemVerilog constructs can result in concise, portable RTL that is easier to maintain and consistent with verification requirements.

StarRC High Performance Multicore and Hierarchical Extraction

Tue, 26 Apr 2011 07:00:00 GMT

Learn the details of the faster multicore architecture, and the techniques to achieve best correlation between hierarchical and full-chip flat extraction.

New Levels of Productivity for USB 3.0 Verification

Thu, 21 Apr 2011 07:00:00 GMT

This Webinar will highlight recent advances in Synopsys verification IP technology that build on a pure SystemVerilog implementation.

Debug Timing Faster with PrimeTime Visualization Tools

Wed, 20 Apr 2011 07:00:00 GMT

Save time debugging complex timing paths during implementation and signoff using new visualization techniques in PrimeTime. See new clock and data analysis capabilities in action.

Reduce Power Consumption 30% with Advanced Synthesis Techniques

Thu, 14 Apr 2011 07:00:00 GMT

In this webinar you will learn how new advances in clock gating and voltage threshold (Vt) optimization available in Design Compiler can reduce your dynamic and leakage power by 10-30%. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.

Noise Analysis and CCS Noise Model Generation for Custom Digital Designs

Wed, 13 Apr 2011 07:00:00 GMT

Learn how the advanced features in NanoTime enable designers to accurately and quickly identify timing issues early in the design cycle to avoid expensive silicon re-spins.

From Advanced OCV to UPF: Superior Results with the Lynx Design System

Tue, 12 Apr 2011 07:00:00 GMT

In this webinar you will learn how the built-in features of the Lynx Design System can help you achieve predictable design closure with superior results for low power chips.

Building High-Performance SoCs with Configurable and Extensible Processors

Thu, 07 Apr 2011 07:00:00 GMT

Learn how the configurable, extensible DesignWare® ARC™ 32-bit processors offers a broad range of features that enable you to tailor the core for your specific embedded or host application.

Performance Analysis of ARM CoreLink NIC-301 based Systems Using Synopsys Platform Architect

Tue, 05 Apr 2011 07:00:00 GMT

Hosted by ARM and Synopsys, this webinar highlights system-level methods for performance analysis and optimization featuring Platform Architect, the SBL-301 SystemC Bus Library, and ARM AMBA Designer.

HDMI: Enabling the 3D Revolution

Thu, 31 Mar 2011 07:00:00 GMT

This webinar discusses the latest trends in HDMI and how advanced features address the challenges of implementing 3D capabilities in SoC design.

Modeling Semiconductor Reliability with TCAD Sentaurus

Wed, 30 Mar 2011 07:00:00 GMT

Learn how TCAD simulation can provide insight into underlying degradation mechanisms and can guide process changes to improve semiconductor reliability.

Implementing an Embedded Memory Subsystem in Mobile Applications

Tue, 29 Mar 2011 07:00:00 GMT

Learn how to minimize low-power design complexity for your mobile SoC applications with embedded memory IP that is optimized for power, performance and density.

Custom Processors: The Optimal Tradeoff Between Flexibility, Power and Performance

Tue, 22 Mar 2011 07:00:00 GMT

Learn how to easily create efficient custom processors or programmable accelerators using Processor Designer as an alternative to complex, inflexible and difficult to verify fixed hardware blocks.

Using IP-XACT to Streamline SoC Design and Verification

Thu, 17 Mar 2011 07:00:00 GMT

The IEEE IP-XACT specification is a valuable format that can help solve IP integration challenges when combined with quality tools designed for an IP-based design and verification flow.

Successful Formality Equivalency Checking for Low-power Designs – Tips from the Experts

Tue, 15 Mar 2011 07:00:00 GMT

Learn from the expert how to successfully complete low power EC faster, and quickly address verification issues, with UPF in Formality.

Advanced Capabilities and Design Interaction with FPGA-Based Prototyping

Thu, 24 Feb 2011 08:00:00 GMT

In order to boost the utility of an FPGA-based prototyping platform, certain critical components are required, including a high-performance, low latency communication channel and direct access to all pins, signals, nodes and registers within the FPGA. Discover how the advanced capabilities of Synopsys HAPS(R) High-performance ASIC Prototyping System(TM) and the new Universal Multi-Resource Bus interface (UMRBus) improves the overall design, verification and software development of an ASIC or SoC.

Reducing Design Margins Using PrimeTime Advanced OCV – TSMC and User Views

Wed, 23 Feb 2011 08:00:00 GMT

Learn how designers are using PrimeTime Advanced OCV to speed design closure by eliminating overly pessimistic violations, and hear about TSMC’s views and support model for these new technologies.

Considerations for Implementing an Embedded Memory Subsystem in Graphic Applications

Wed, 23 Feb 2011 08:00:00 GMT

Learn about considerations for implementing an embedded memory subsystem in graphic applications

Scaling High-Level Synthesis for Complex Image and Video Processing Designs

Wed, 02 Feb 2011 08:00:00 GMT

In this one-hour webinar, you will learn about Synphony's basic, high-level synthesis flow for hardware design and verification, how to efficiently synthesize more complex loops and functions in hierarchical C/C++ code, and how to use high-level synthesis for more productive video and image processing in FPGAs and ASICs.

Selecting the Best Non-Volatile Memory IP for RFID Applications

Thu, 27 Jan 2011 08:00:00 GMT

Get a brief overview of DesignWare NVM IP specifically multiple time programmable, one time programmable & embedded Flash/EEPROM as well as NVM specifications such as endurance and retention.

CustomSim and VCS Extend Digital Verification Techniques to Mixed-Signal Designs

Wed, 26 Jan 2011 08:00:00 GMT

Use CustomSim and VCS to create reusable mixed-signal verification environments that enable analog assertions, analog verification planning, analog stimulus and analog self-checkers to find bugs related to analog and digital interfaces sooner.

DDR3 PHY IP Shootout - 1600 Mbps in Wire Bond vs. Flip Chip Packaging

Thu, 20 Jan 2011 08:00:00 GMT

This webinar will compare and contrast two identical test chips using Synopsys DesignWare DDR3/2 PHY and controller IP, the first using a flip chip package and the second using a wire bond package.

Team Design for Large FPGA Projects

Thu, 20 Jan 2011 08:00:00 GMT

Team design for FPGAs can be a confusing process if you don't have the right tools and infrastructure in place. Join Amelia Dalton from TechFocus Media as she chats with Jeff Garrison, Director FPGA Implementation Marketing about the unique challenges facing design teams as they take advantage of the incredible power of today's huge FPGAs.

Using ESP-CV for Faster Redundancy Verification in Memory Designs

Wed, 19 Jan 2011 08:00:00 GMT

ESP-CV performs functional equivalence checks between a Verilog design and its transistor level implementation. The designs may be described as Verilog behavioral models, RTL, or gates, and a SPICE netlist. The new redundancy verification features in ESP-CV provide the ability to quickly and efficiently verify memory designs implemented with row and column redundancy.

New Features in TCAD Sentaurus: December 2010 Release

Tue, 18 Jan 2011 08:00:00 GMT

Introduction to new features in the December 2010 release of TCAD Sentaurus. Learn about Sentaurus' new capabilities in 3D structure generation, process modeling, quantization in device physics, variability modeling and optoelectronics.

Performance Validation of Advanced LTE MIMO Receivers Implemented with Xilinx LogiCORE IP

Wed, 12 Jan 2011 08:00:00 GMT

Learn how Xilinx MIMO IP can help you implement advanced MIMO receivers for LTE base stations (eNodeB) with up to 4 Multi-User MIMO codewords and validate its performance in the Synopsys LTE library.

Advances in Circuit Analysis with the Custom Designer Simulation and Analysis Environment

Wed, 27 Oct 2010 07:00:00 GMT

Learn how to efficiently use Custom Designer's SAE in conjunction with HSPICE and Custom WaveView to analyze a design across process and parameter variations.

Accelerate Analog Simulation with HSPICE Precision Parallel Technology

Wed, 20 Oct 2010 07:00:00 GMT

Learn how HSPICE Precision Parallel technology accelerates verification of analog/mixed-signal circuits up to 7X on 8 cores while maintaining gold-standard accuracy.

28nm Silicon and Design Enablement – A Foundry and EDA Vendor Perspective

Wed, 13 Oct 2010 07:00:00 GMT

In this final webinar of the 32/28nm design series, Synopsys and GLOBALFOUNDRIES share their perspectives on 28nm process technology and design enablement and 32/28nm design solutions respectively.

Power Intent Verification For Low Power Designs Using ESP-CV

Wed, 15 Sep 2010 07:00:00 GMT

ESP-CV is a tool designed to perform functional equivalence checks between two different design representations. The new power intent verification features in ESP-CV provide the ability to verify various types of power management circuitry used in low power designs. These designs may be described as Verilog behavioral models, RTL, gates, transistors, or a SPICE netlist.

LTE Physical Layer Design: Basics

Wed, 15 Sep 2010 07:00:00 GMT

Overview of the LTE standard, LTE simulation library and Synopsys SPW algorithm design tool.

Gold-Standard Extraction at 28nm with StarRC

Tue, 14 Sep 2010 07:00:00 GMT

Increasing design complexity and the impact of new parasitic effects make accuracy and productivity for IC design and signoff analysis even more challenging beyond the 28nm process node. In this webinar, Synopsys experts will discuss how StarRC addresses these advanced challenges at 28nm through silicon-accurate modeling and high-performance extraction, enabling SoC designers to achieve signoff with increased confidence.

Tips for Embedding Flexible Analog Interface IP into Digital SoCs for Broadband Communications

Thu, 09 Sep 2010 07:00:00 GMT

Learn how DesignWare® Data Converter IP blocks can be integrated to create a flexible interface that seamlessly communicates with any RF transceiver block without penalty in the total system power dissipation

VCS Coverage Driven Verification

Wed, 08 Sep 2010 07:00:00 GMT

As the challenge of verification continues to grow, engineers are increasingly turning to verification planning, advanced coverage techniques and unique coverage technologies to optimize the tracking of verification progress and significantly improve the quality of their designs. In this webinar, you will learn about the latest advances in verification planning, coverage and coverage methodology. In addition, you will also discover some of the unique advantages of using VCS, including VCS’ Echo testbench coverage convergence technology.

Take Control of Your Design With the Lynx Design System

Wed, 25 Aug 2010 07:00:00 GMT

Learn how the Lynx Design System, including a production flow, the ability to pre-validate libraries and technology data, and project tracking and reporting features, helps control your design schedule!

Multi-Gigabit Signal Integrity Analysis with HSPICE

Wed, 18 Aug 2010 07:00:00 GMT

Learn about HSPICE capabilities for modeling high-frequency channel components, and high-performance simulation and analysis features for characterizing multi-gigabit links.

LTE Physical Layer Design: Optimization

Wed, 18 Aug 2010 07:00:00 GMT

Learn more about LTE physical layer design and how design choices can impact implementation and performance.

Manufacturing-Aware Routing at 32/28nm

Wed, 11 Aug 2010 07:00:00 GMT

Considering yield as one of the objectives during design has become a necessity at the 32/28nm node. In this webinar, you will learn techniques for addressing manufacturing during routing with IC Compiler’s Zroute technology which considers manufacturability as a routing objective.

Accurate Power Analysis of Low Power Techniques Using PrimeTime PX

Tue, 03 Aug 2010 07:00:00 GMT

This technical webinar will explain how PrimeTime PX can be used to analyze the effectiveness of low power design techniques such as clock gating, use of multi-voltage rails and power gating. Attendees will learn how to further optimize their designs for power by analyzing which low-power techniques work best under differing conditions. You will also learn how to use PrimeTime PX to understand which modes of operation consume the most power.

Simulation of Power Devices with TCAD Sentaurus

Fri, 30 Jul 2010 07:00:00 GMT

A complete review of TCAD simulation of power devices from the latest trends to future outlook, including silicon-based, SiC & GaN power devices. (Japanese/English)

The Next Generation of Ethernet: How New IEEE Standards Enable Energy Efficiency & Quality-of-Service

Thu, 29 Jul 2010 07:00:00 GMT

In this webinar, come hear about the new IEEE specifications enabling Quality-of-Service and Energy Efficient Ethernet. You will also get an introduction to the DesignWare® Ethernet QoS and GMAC Universal MAC IP cores and how they can help you launch a new generation of networking products.

Realizing Today’s 32nm and Beyond Large Capacity Designs

Wed, 28 Jul 2010 07:00:00 GMT

Synopsys Design Planning R&D will highlight the latest hierarchical design exploration and planning technology available in IC Compiler for handling today’s large 32/28nm designs.

Utilizing Design Compiler to Double Synthesis and P&R Productivity

Thu, 22 Jul 2010 07:00:00 GMT

See how new Design Compiler 2010 technologies double the productivity of synthesis and P&R by enabling RTL designers to perform floorplan exploration while still in synthesis.

Simulation in Photovoltaics with TCAD Sentaurus and Saber

Thu, 22 Jul 2010 07:00:00 GMT

This webinar focuses on optimization of rear point contact solar cells using 3-D TCAD simulation and addresses system-level simulation of PV arrays

Find Electrical Violations Before Tapeout with CustomSim Circuit Check

Wed, 21 Jul 2010 07:00:00 GMT

Learn how customers are using CustomSim Circuit Check to analyze designs with hundreds of millions of transistors to catch electrical violations before tapeout.

LTE Physical Layer Design: Synchronization

Wed, 21 Jul 2010 07:00:00 GMT

Learn more about some of the features of the LTE User Equipment (UE) acquisition and synchronization process.

Faster ECO Fixing Flows with PrimeTime and IC Compiler

Tue, 20 Jul 2010 07:00:00 GMT

This technical webinar will explain how IC Compiler and PrimeTime can be used to close timing during signoff. It will focus on the use of Distributed Multi-Scenario Analysis for automatic set-up and hold fixing, and will explain new PrimeTime 2010.06 DRC fixing capabilities. Attendees will learn how to minimize fixing run times, which approaches are best for closing setup and hold violations, and how to deploy SI fixing most effectively.

New Enhancements for Debugging Inconclusive and Non-Equivalent Verifications in Formality

Thu, 24 Jun 2010 07:00:00 GMT

This webinar will address what to do when faced with an inconclusive for non-equivalent design in Formality. Common types of failures will be discussed as well as suggestions for resolving them. New features in Formality 2010.03 will be presented which help the designer quickly identify the sources of the issue and makes recommendations on how to resolve them. Recent Formality low power enhancements will also be discussed.

Best of SNUG: New In-Design Features (IC Compiler, IC Validator, PrimeRail)

Thu, 10 Jun 2010 07:00:00 GMT

In-Design reliability analysis and physical verification save time by avoiding useless translations of data back and forth and also allow users to catch and fix problems on-the-go, preventing costly iterations between implementation and signoff.

Best of SNUG: Generating Low-Power ATPG Patterns using a Shift Power Effort

Thu, 10 Jun 2010 07:00:00 GMT

This technical paper presents experimental work and associated conclusions based on the simulation and silicon results on two different designs using Synopsys‘ new ATPG low-power algorithm.

Best of SNUG: Galaxy Constraint Analyzer: Constraint Debugging Made Easy

Thu, 10 Jun 2010 07:00:00 GMT

In today’s designs, it is not unusual to have hundreds of clocks, power management, multiple modes, in-house or third-party IP with their own set of timing constraints that need to be integrated at the top level. This increased complexity together with tighter schedules makes finalizing the design timing constraints extremely challenging.

Understanding PCI Express 3.0 and How to Implement the New Features

Tue, 25 May 2010 07:00:00 GMT

The next generation of the PCI Express® protocol, PCI Express 3.0, incorporates significant changes that go beyond the increase in link speed from 5 GT/s to 8 GT/s. In this webinar hear about the key specification changes for the PCI Express 3.0 protocol, equalization procedure, PIPE interface and electrical interface. In addition, learn about the trade-offs and practical implementation issues through examples and lessons learned from the development of Synopsys DesignWare IP for PCI Express 3.0. Finally, get a brief overview of the DesignWare® IP for PCI Express 3.0 solution.

Best of SNUG: Clock Tree Implementation Techniques—A Comparative Analysis

Thu, 06 May 2010 07:00:00 GMT

This paper demonstrates two techniques of clock tree implementation with comparative analysis data. The first is a traditional cluster-based clock tree common in ASIC flows (CTS), the other is a unique technique used in various high-frequency designs based on non-uniform fishbone mesh.

Best of SNUG: Simulation Acceleration using Multicore Systems

Thu, 06 May 2010 07:00:00 GMT

In this paper we show how to take advantage of multicore systems to accelerate simulation performance. First, we introduce an algorithm for automatically partitioning the design for multicore simulation. Second, we present an approach to use the GPU to further increase simulation acceleration (around 100X faster).

Best of SNUG: Energy-Efficient Processor Implementation with Eclypse Low Power Solution

Thu, 06 May 2010 07:00:00 GMT

This tutorial provides a technical case study of a 32nm Eclypse-based implementation of an ARM Cortex-A5 multi-processor with IEEE-1801 UPF-based power intent.

Best of SNUG: Scan Compression with Limited Pin Access

Thu, 06 May 2010 07:00:00 GMT

This presentation covers how the latest pin-limited testing enhancements have been deployed successfully on Wolfson’s latest devices.

Best of SNUG: Scan Compression without 'Scan Compression'

Thu, 06 May 2010 07:00:00 GMT

DFTMAX compression can achieve over 100X compression. However, small compression factors can be achieved using ”multi-mode” scan architectures. For small- and medium-size mixed-signal designs these provide a low-cost alternative to full compression.

Best of SNUG: Reducing the Cost of Pin-Limited Test using DFTMAX Compression

Thu, 06 May 2010 07:00:00 GMT

Designers are increasingly adopting DFT methodologies that limit the number of pins allocated for manufacturing test. In this tutorial, we examine what is driving this trend and how you can use new capabilities in DFTMAX to reduce the cost of pin-limited test for your designs.

Eliminating Late-Stage DRC Surprises with In-Design Physical Verification

Wed, 05 May 2010 07:00:00 GMT

Third in the In-Design technology series featuring several high productivity in-design physical verification flows with IC Validator, including Automatic DRC Repair and Pre-Routing Verification – all from within IC Compiler.

Unleash the Power of Hybrid Formal Verification for Advanced Bug Hunting

Tue, 04 May 2010 07:00:00 GMT

Successful, cost-effective verificaiton of a design requires quick and early bug detection. In this webinar, you will learn how Synopsys' Magellan hybrid technology speeds up bug hunting and provides unique value to design and verification teams.

Static Verification Throughout the Low Power Design Flow

Wed, 28 Apr 2010 07:00:00 GMT

Learn how MVRC and Formality tools complement each other to statically verify your design from RTL to transistors.

Best of SNUG: Power-Aware Test Solution

Wed, 28 Apr 2010 07:00:00 GMT

This tutorial provides an overview of Synopsys’ power-aware and pin-limited testing features. It outlines how designers can generate patterns that are aligned with the functional power budget and reduce both dynamic and leakage power during scan testing.

Best of SNUG: Effective Post-Layout Verification of AMS Designs at 28nm

Wed, 28 Apr 2010 07:00:00 GMT

Strategies and methods for correct Extracted View Sets generated with StarRC and results from a real design implemented at 28nm show how post-layout verification can be sped up, substantially improving the turnaround time of the AMS design flow.

Best of SNUG: IC Compiler Feasiblity, Planning and Implementation

Wed, 28 Apr 2010 07:00:00 GMT

This tutorial addresses feasibility during the pre-route stages of the design flow and introduces an automated way to identify and analyze problems that impact timing, routability and congestion.

Best of SNUG: Experiences with IC Compiler Black Box flow

Wed, 28 Apr 2010 07:00:00 GMT

This paper describes using the black-box flow in IC Compiler for early floorplanning analysis and timing checks in a 65nm ASIC with large busses. This approach saves development time and, for the first time, supports a real RTL-backend co-design.

Introduction to TCAD Sentaurus: March 2010 Release

Tue, 27 Apr 2010 07:00:00 GMT

Introduction to the latest release of TCAD Sentaurus including new features and capabilities for addressing technologies such as CMOS, memory, power, analog/RF and optoelectronics.

Reducing the Cost of Pin-Limited Test Using DFTMAX Compression

Wed, 21 Apr 2010 07:00:00 GMT

Designers are increasingly adopting design-for-test methodologies that limit the number of pins allocated for manufacturing test. During this technical webinar, we will examine what is driving this trend and how you can use new capability in DFTMAX compression to reduce the cost of pin-limited test for your designs.

Design Compiler 2010: Double the Productivity of Synthesis and Place & Route

Tue, 20 Apr 2010 07:00:00 GMT

Learn about a new capability in Design Compiler that allows RTL designers to perform floorplan exploration from within the synthesis environment to efficiently achieve an optimal floorplan. Hear about Design Compiler’s new scalable infrastructure tuned for multicore processors yielding 2X faster synthesis runtimes on quad-core compute servers.

Shaping the Perfect Audio Codec: How Your SoC Can Benefit from the Right Audio Functions’ Line-Ups

Tue, 13 Apr 2010 07:00:00 GMT

In this webinar, you will get an overview of a wide range of audio functions that can be optimized for low power consumption and small silicon area such as volume control, high isolation inputs, crosstalk, headset drivers, Class-G, pop-noise suppression and clock management. You will also learn how to select the right analog audio block lineups for different types of applications, and you will understand how Synopsys’ high-quality DesignWare Audio IP solutions can deliver performance levels at par with those from discrete components

Complementing Emulation with FPGA-Based Prototyping

Wed, 31 Mar 2010 07:00:00 GMT

Discover how FPGA-based prototyping is used as a natural progression to complement emulation when the shortening of development time is critical to the overall success of ASIC and SoC projects.

Verify Digitally-Assisted Analog Circuits with CustomSim Fast Transient Analysis

Thu, 25 Mar 2010 07:00:00 GMT

Learn how the CustomSim high-capacity, fast transient analysis solution can help you increase design confidence and reduce project development time.

Custom Designer: Advances in Custom Layout Automation with SmartDRD

Tue, 23 Mar 2010 07:00:00 GMT

SmartDRD technology visualizes, prevents and automatically fixes DRC violations to help designers quickly achieve DRC clean designs with significantly reduced effort.

The Big Design Squeeze: How to get faster design turns in FPGA-based designs

Wed, 03 Mar 2010 08:00:00 GMT

Whether you are using FPGAs to verify your ASIC or as a final implementation platform, this webinar will illustrate techniques to help you speed up your synthesis iterations by a factor of 2 vs. traditional approaches, and achieve up to 2 times the turnaround time from RTL to board with better results stability from one run to the next. Techniques for more efficient debug and optional team design techniques are also covered.

In-Design for Faster Design Closure

Tue, 02 Mar 2010 08:00:00 GMT

First in a series addressing 32/28nm sign-off bottleneck challenges and the solutions best suited to mitigate these challenges. Learn how Synopsys’ In-Design solutions make it possible for place-and-route engineers to accelerate design closure by enabling signoff analysis from within the implementation flow.

3-D TCAD Simulation with Sentaurus

Wed, 24 Feb 2010 08:00:00 GMT

The latest algorithms and best practices for 3-D TCAD simulation to derive maximum benefit from the comprehensive 3-D capabilities in Sentaurus TCAD.

Reducing Design Margins Using PrimeTime Advanced OCV

Wed, 17 Feb 2010 08:00:00 GMT

How Advanced On-Chip-Variation works in comparison to flat-derate OCV and SSTA-based signoff technologies. Techniques for deploying PrimeTime to reduce pessimistic endpoints and slack pessimism.

DesignWare IP for AMBA 3 AXI On-Chip Bus

Wed, 10 Feb 2010 08:00:00 GMT

This webinar details the flexible on-chip bus architecture of the DesignWare interconnect fabric that enables dedicated high-performance and shared low-performance links to be combined within a single AMBA 3 AXI on-chip interconnect, eliminating unnecessary logic within the design to deliver maximum bandwidth while reducing area, routing congestion and power.

Transaction-level Debug Using VCS

Wed, 27 Jan 2010 08:00:00 GMT

In this webinar, you will learn about the basics of transaction-level modeling, why it is needed, how it integrates with an RTL design and how the Synopsys VCS functional verification solution supports both transaction-level and pin-level debug in its Discovery Visualization Environment (DVE).

Addressing Signal Integrity Noise in Low Power Design

Wed, 20 Jan 2010 08:00:00 GMT

A discussion on the impact of low power design and the resulting requirements that drive the technologies in today’s static timing analysis tools. Learn about PrimeTime SI techniques that will enable you to deploy the SI noise-aware flow that best fits your needs for fast, accurate signoff.

Low Power Algorithm Exploration

Tue, 19 Jan 2010 08:00:00 GMT

Learn how to use the Synphony high-level synthesis tool to do architectural power exploration within days of a having a high level algorithm model in MATLAB or Simulink.

Efficient & Accurate Memory Timing & Power Analysis using CustomSim

Wed, 16 Dec 2009 08:00:00 GMT

With the growing complexity of device models and the increasing impact on timing and power measurements from physical layout effects, accurate memory verification within a reasonable timeframe is a necessity. This webinar highlihgts memory verification methodologies and how choosing the right methodology enables memory designers to produce the highest-accuracy timing and power measurements in the shortest turnaround time. Learn how Synopsys’ CustomSim™ solution is being used today for accurate and efficient memory timing and power analysis.

CustomSim for Memory Timing & Power Analysis

Tue, 15 Dec 2009 08:00:00 GMT

This webinar highlights memory verification methodologies and how choosing the right methodology enables memory designers to produce the highest-accuracy timing and power measurements in the shortest turnaround time.

Simulation of Advanced Semiconductor Devices Including High-k/Metal-gate Transistors and FinFETs

Tue, 01 Dec 2009 08:00:00 GMT

This webinar discusses the application of TCAD to high-k/metal-gate transistors and 3-D modeling FinFET devices, focusing on the physical models and 3-D modeling techniques required to achieve successful simulations.

The Recipe for Successful Formal Verification: Proper Constraining of Your Design

Wed, 11 Nov 2009 08:00:00 GMT

Learn all about constraints and how their proper specification and use will help you quickly achieve your verification goals. Synopsys’ Magellan hybrid formal tool helps detect and debug over-constraining of your formal setup, thereby increasing your confidence in your formal verification results.

HSPICE/Custom Designer for Analog & RF Circuit Design

Thu, 05 Nov 2009 08:00:00 GMT

Analog/RF design solution helps meet design challenges

Front-to-Back AMS Flow using Custom Designer

Tue, 03 Nov 2009 08:00:00 GMT

Follow the front-to-back development of an AMS block using Synopsys' Galaxy Custom Designer implementation solution.

IC Compiler Ecosystem

Sat, 31 Oct 2009 07:00:00 GMT

There is a thriving ecosystem around IC Compiler and the Galaxy Implementation Platform products engineered to work together to speed design closure. Hear from designers who share how they have relied on the IC Compiler ecosystem to achieve faster time to results and improved productivity.

Stratix-based Algorithm Acceleration Prototyping

Thu, 29 Oct 2009 07:00:00 GMT

This webinar discusses how the unique features of Altera's high-end Stratix-FPGAs combined with Synopsys high-performance rapid protoyping solutions enable new use modes and capabilities for algorithmic acceleration, as well as for highest performance rapid prototyping.

Achieving 2x Verification Speedup with VCS Multicore

Tue, 27 Oct 2009 07:00:00 GMT

Learn how VCS multicore technology allows users to reduce verification time for long-running tests by leveraging their multicore computing infrastructure. We cover VCS multicore technology’s two flexible use models: application-level parallelism (ALP) and design-level parallelism (DLP).

Guidelines for Mixed-Signal PHY IP Integration, Debug and Test

Tue, 13 Oct 2009 07:00:00 GMT

This webinar explains how high-performance DesignWare Mixed-Signal PHY IP addresses issues such as jitter, robustness, power, testability and PVT invariance and provides insights on how to ensure high yield across process corners and manufacturing variations.

VMM: The Next Generation - Delivering Enhanced Ease-of-use, TLM 2.0 Support and Robust Block-to-top Reuse

Tue, 13 Oct 2009 07:00:00 GMT

VMM base classes, VMM Applications and VMM-LP are deployed worldwide to address the toughest verification challenges. In this webinar, our experts cover new enhancements like TLM 2.0 support, improved block-to-top reuse heirarchical phasing and additional ease-of-use deployment features.

Fundamentals of Low Power IC Design

Thu, 01 Oct 2009 07:00:00 GMT

The power consumed by electronic devices has been on a downward path for many years as a result of the hard work and creativity of talented engineers. This course looks at the fundamentals of achieving the low power operation needed with nearly all of today's leading-edge chip designs.

Extraction Techniques to Accelerate High-Capacity Simulation

Tue, 22 Sep 2009 07:00:00 GMT

StarRC can enable up to 10x speed-up in simulation runtime while preserving golden accuracy. In this webinar our experts explain innovative techniques to boost simulation performance and capacity for your custom digital, memory or AMS designs.

Combining Formal Verification with Simulation: The Best of Both Worlds

Tue, 25 Aug 2009 07:00:00 GMT

Learn how Synopsys' Magellan seamlessly integrates formal verification with simulation to achieve complete verification of today's complex designs.

Everything You Always Wanted to Know About Low Power Verification

Tue, 11 Aug 2009 07:00:00 GMT

An understanding of the impact on verification from the deployment of low power design techniques is key to successful verification. Learn why verification has changed for low power designs and how Synopsys' VCS with MVSIM and MVRC comprehensively and accurately meet these challenges.

A Structured Methodology for Verifying Low Power Designs

Tue, 11 Aug 2009 07:00:00 GMT

In this webinar, we focus on the bug types that are new to low power design and introduce a structured and reusable methodology highlighting VMM extensions to base classes for low power that can be quickly used to replicate an efficient verification environment for low power designs.

Faster Power/Ground Grid Closure with In-Design Rail Analysis

Thu, 25 Jun 2009 07:00:00 GMT

Join our experts to learn how you can use In-Design Rail Analysis to analyze and debug voltage drop, power up and electromigration (EM) effects as early as placement, helping you accelerate the path to final design closure.

Faster Design Closure with Congestion Minimization

Tue, 09 Jun 2009 07:00:00 GMT

This webinar will show you how predictable routing congestion from synthesis to tapeout eliminates unnecessary iterations, speeding up your overall turnaround time.

Lynx Product Overview & Demo

Wed, 03 Jun 2009 07:00:00 GMT

This one-hour webinar includes a brief overview presentation on Lynx followed by a detailed product demonstration. For more information on the Lynx Design System, visit: www.synopsys.com/Lynx.

In-Design PV for Faster Time-to-Tapeout

Wed, 20 May 2009 07:00:00 GMT

Synopsys’ physical design and verification technologists will show you how in-design physical verification combines timing awareness and signoff accuracy to speed up your tapeout schedule.

The VCS Discovery Visualization Environment (DVE)

Thu, 30 Apr 2009 07:00:00 GMT

The Discovery Visualization Environment (DVE) offers unified debug and analysis of Verilog, VHDL, C/C++/SystemC, SystemVerilog Assertion/Design/Testbench and analog waveforms. Learn about DVE features such as coverage, planning, and interactive debug of a VMM environment with SystemC.

HSPICE StatEye – ISI Predictions Made Easy

Wed, 29 Apr 2009 07:00:00 GMT

Are your high-speed serial link simulations taking too long? Want to speed up your eye diagram generation and ISI predictions by 100X? If so, learn how to speed up high-speed serial link analyses and get the most out of the statistical eye diagram capability in HSPICE.

Increase Design Confidence with CustomSim

Tue, 28 Apr 2009 07:00:00 GMT

Learn how CustomSim addresses verification challenges for a diverse array of functional blocks, including custom digital, analog and memory designs. Learn how to take advantage of multi-threading capabilities to achieve an additional 4x performance improvement.

Successful Equivalence Checking of Highly Optimized DC Ultra Designs

Tue, 21 Apr 2009 07:00:00 GMT

Join us for an in-depth technical webinar focused on how to achieve successful verification on high-performance designs compiled with DC Ultra.

Accelerate your design closure with DC Ultra

Tue, 21 Apr 2009 07:00:00 GMT

Join this webinar to hear directly from senior product team members on how you can achieve superior results faster utilizing sophisticated optimizations of DC Ultra.

Simulation of Multi-Junction Solar Cells Using TCAD Sentaurus

Wed, 15 Apr 2009 07:00:00 GMT

This webinar addresses the design and optimization of multi-junction solar cells using Synopsys' TCAD Sentaurus tools.

Accelerating Time-to-SI Closure

Tue, 31 Mar 2009 07:00:00 GMT

View this webinar to learn how to use signoff-driven SI-closure to keep your schedule on track and your performance on target.

Achieving predictable success in FPGA Projects

Mon, 09 Mar 2009 07:00:00 GMT

This 3-part series introduces Synopsys tools for FPGA users, including model-based algorithmic design, IP integration tools, tightly coupled constraint and analysis environments, integrated synthesis and placement, and on-board assertion-based verification linked to RTL simulation.

Leveraging Constraint Solver Technology in VCS

Thu, 29 Jan 2009 08:00:00 GMT

Learn how VCS constraint solver technology can increase design quality while accelerating verification and minimizing cost. In addition, the speakers address debugging and profiling of constraints and discuss a few "tips and tricks" that help simplify constraint writing.

Verifying Complex Power-managed Designs

Thu, 18 Dec 2008 08:00:00 GMT

An overview of approaches that address the difficult task of verifying low power designs.

Thin Film Solar Cell Simulation

Wed, 20 Aug 2008 07:00:00 GMT

Thin film solar cells are currently the focus of worldwide research and development efforts aimed at bringing to market more efficient and cost effective processes and designs.

Modeling Non-volatile Memory Technologies with Sentaurus TCAD

Thu, 29 May 2008 07:00:00 GMT

A new generation of non-volatile memory devices have kept scientists and designers busy researching and optimizing designs like SONOS memory, new materials like chalcogenide (GST) for Phase Change Memory, or means to pump charge into Nano Crystals to store information.

Electromagnetic Simulation of Image Sensors: From Design to Manufacturability

Thu, 20 Mar 2008 07:00:00 GMT

This webinar discusses the application of TCAD Sentaurus Device EMW to the electromagnetic simulation of CMOS image sensors (CIS) and charge-coupling devices (CCD).

Gallium Nitride HFETs: Physical Models and Simulations for RF and Power Applications

Thu, 21 Feb 2008 08:00:00 GMT

This webinar concentrates on simulation of GaN HFET devices using TCAD Sentaurus Device including treatment of spontaneous and piezoelectric polarization effects, numerical accuracy settings, assignment of bulk and interface traps, and selection of mobility and transport models.