Tensilica News

New IEEE Computer Article features Work at Lawrence Berkely Labs

2009-11-13T11:11:00.000-08:00

See the article in the Nov. issue of Computer titled "Energy-Efficient Computing for Extreme-Scale Science" by CTO Chris Rowen and others about the work on low-power design at Lawrence Berkeley Labs. http://www.tensilica.com/uploads/pdf/ieee_computer_nov09.pdf

Everything You Know about Microprocessors is Wrong

2009-11-12T09:54:00.001-08:00

Here's a great web seminar that's archived, so you can view it any time. Many system-engineering concepts and "best practices" with respect to system design are no longer valid at the chip level. For example, bus-centric design--made popular by the introduction of the first commercial microprocessor in 1971--continues to dominate on-chip design 36 years later even though nanometer silicon has completely changed the rules of system interconnect.

Xtensa 8 and LX3 are out - it's time to party

2009-11-11T14:53:00.000-08:00

Today we have a company-wide bowling tournament offsite to celebrate the release of our eight generation processors - Xtensa 8 and Xtensa LX3. Fun for all!

What's the fastest route from C algorithm to gates?

2009-11-09T09:42:00.000-08:00

You've got an algorithm written in C. You can quickly see how that will run on a standard processor core, but you'd be amazed how much faster that algorithm can run on a specially tailored processor. A simple example is an audio stream. If the datapath of a processor is specially tailored just for audio data, that's going to go through the processor much faster, and therefore better quality sound. The same holds true for other data-intensive applications, especially when the datapath doesn't exactly fit into 32 bit words. Find out more from this white paper: http://www.tensilica.com/products/literature-docs/white-papers/fast-path-from-c-to-gates/

Xtensa 8 or Xtensa LX3?

2009-11-05T13:32:00.000-08:00

Xtensa LX3 is a superset of Xtensa 8 and adds some very powerful features. Find out more at http://www.tensilica.com/products/xtensa-customizable/xtensa_choice.htm

Grant Martin at Synopsys Interoperabity Forum Tomorrow 1:15 in Santa Clara

2009-11-04T11:50:00.000-08:00

See our Chief Scientist talk in the System-level design section - topic: Getting high with a little help from my friends: Configurable processor interoperability with ESL tools.

Xtensa LX3 - 10 GigaMAC/Sec DSP Performance, tops 1 GHz

2009-11-02T10:06:00.000-08:00

The base Xtensa LX3 DPU configuration can reach speeds of over 1 GHz in 45nm process technology (45GS) with an area of just 0.037 mm² and power of 0.015 mW/MHz. When built with the new ConnX Baseband Engine DSP (ConnX BBE), the Xtensa LX3 processor delivers over 10 Giga-MACs-per-second performance, running at 625 MHz with a footprint of 0.93mm² (post place-and-route 45GS) and consuming just 170 mW (including leakage).

Grant Martin in Tutorial at ICCAD 4:30 today

2009-11-02T10:00:00.000-08:00

Embedded Processors, Methods and Applications: Computer Architects Perspective

As feature sizes diminish and transistors multiply, designers are compelled to move to higher levels of abstraction to overcome the productivity gap. Increasingly designers use processors as the main module in embedded system design. The available choices to the modern designer include processor (which are both non-configurable and configurable), DSP and GPU cores. This tutorial explores the available processors, details methodologies and explains applications.

The tutorial is divided into three parts: the first will explore the field of embedded processors; the second will look design methodologies based on embedded processors; the third, will describe an application in detail. This tutorial will be presented by three experienced researchers with industrial and academic experience, and will benefit students, researchers, and design engineers.

Speakers:

Grant Martin - Tensilica, Inc.
Sri Parameswaran - Univ. of New South Wales
Anand Raghunathan - Purdue Univ.
http://www.iccad.com/events/eventdetails.aspx?id=106-3-E

Sign up for our Web Seminar: The 5 Pitfalls of 4G Baseband Design

2009-10-21T13:51:00.000-07:00

Sign up now for our web seminar next Tuesday, October 27, at 11 am pacific daily time. It will be recorded, so you can watch it later, too. Chris Rowen, our CTO, will talk about the emerging LTE standard, which is complex, requires extraordinary computation throughput and much better power efficiency than previous wireless baseband PHY subsystems. Because of the complexity, designers are taking many different approaches to chip design for LTE.

This webinar explores five significant challenges faced by designers of efficient digital basebands, including pitfalls in LTE's many modes, excessive cost and power, the "million MIPS" hurdle of Turbo decoding, and the dilemma of choosing the right communications among the LTE building blocks. This webinar uses detailed examples from an end-to-end LTE PHY baseband architecture to highlight the key dos and don'ts. http://seminar2.techonline.com/registration/wcIndex.cgi?sessionID=tensilica_oct2709

More Configuration Optons Than Ever in Xtensa 8

2009-10-20T12:53:00.000-07:00

Want your processor core your way but don't want to work hard at it? Just look at all of the configuration options you get with Xtensa 8. Just click on a button or use a pull-down menu to make your selections - then you can get your processor you way. See http://www.tensilica.com/products/xtensa-customizable/xtensa/configurability.htm

Xtensa 8 - Our 8th Generation Processor with Novel I/O

2009-10-19T09:49:00.000-07:00

By embedding functionality right into the processor datapath itself, designers can use the Xtensa 8 DPU to not only perform control functions, but also some of the finite state machine tasks that manage RTL blocks and some of the RTL functionality as well. This makes for a smaller, more efficient chip design, and it significantly reduces the verification challenges associated with new RTL designs. See http://www.tensilica.com/products/xtensa-customizable/xtensa.htm

Monday's Big News - Stay Tuned!

2009-10-16T10:13:00.000-07:00

Busy today putting the finishing touches on the website update for a new processor announcement on Monday. Very cool stuff.

Why use Tata's Ro-SES OS?

2009-10-15T10:02:00.000-07:00

Today we announced that Tata Elxsi's RoS-ES (Real Time Operating System for Embedded Systems) OS is now available for Xtensa and Diamond Standard processors. So why use a small OS like this rather than Linux? When you're using deeply embedded controllers in the dataplane, you don't need all the overhead of most OSes. Tata Elxsi's RoS-ES is a compact real-time operating system (RTOS) that provides an impressive array of capabilities making it well suited to networking and consumer electronics applications. More information on the RoS-ES RTOS is available at www.tataelxsi.com/roses.

Multiple Codec Operation Apnote

2009-10-14T11:05:00.000-07:00

This application note describes a multi-stream audio decoder test bench that works without needing a threading operating system. A software test bench is provided for the Diamond 330HiFi processor that supports decoding and audio mixing of an arbitrary number of homogenous or heterogeneous audio streams. This application note describes the test bench, and discusses the coding techniques used to reduce memory requirements and to synchronize/mix audio decoded from multiple streams.
http://www.tensilica.com/products/literature-docs/application-notes/audio-application-notes/multiple-audio-codec.htm

Hi Fi Audio DSP Gets DTS-HD Master Audio Certification

2009-10-13T11:16:00.000-07:00

Tensilica's HiFi Audio DSP is the first IP core to achieve certification. Having the HiFi DSP IP core certified independent of the choice of silicon implementation will significantly ease Tensilica's customers' efforts to design Blu-ray Disc and Audio Video Receiver SOCs and complete chip and system level certification with DTS.

White Paper: Get Your ASICs Off the Bus

2009-10-12T09:44:00.000-07:00

This paper describes the most common hardware mechanisms - buses, direct connections, and data queues - used to interconnect processor cores on ASICs. It explains how direct processor-to-processor connections reduce the cost and latency of inter-processor communications.
http://www.tensilica.com/products/literature-docs/white-papers/get-off-the-bus/

Interesting apnote on Optimizing for Low Power

2009-10-08T14:04:00.000-07:00

It's amazing how little decisions can make a big difference in energy consumption. Read our apnote: Optimizing for Energy using the Xenergy Energy Optimizator Tool.
http://www.tensilica.com/products/literature-docs/application-notes/xtensa-tools/xenergy-energy-optimizator.htm

Whitepaper: How to Manage Video Frame-Processing Time Deviations

2009-10-07T10:00:00.000-07:00

Whitepaper: How to Manage Video Frame-Processing Time Deviations in ASIC and SOC Video Processors - you can substantially differentiate an HD product’s design by improving the video image stream—both before video compression and after. http://www.tensilica.com/products/literature-docs/white-papers/video-frame-processing/

CTO Chris Rowen Giving Baseband Talk Tomorrow at SOC Conf in Tampere

2009-10-06T13:48:00.000-07:00

From 13.20-14.40 Rowen will discuss A DSP architecture optimized for wireless baseband. The high computation demands of next generation cellular and broadcast wireless require both higher efficiency and greater flexibility in baseband processing. This paper introduces a new DSP architecture optimized for baseband applications, especially applications with heavy workload of complex filtering, FFT and MIMO matrix operations. http://soc.cs.tut.fi/2009/Technical_program.php

White Paper: TIE - The Fast Path to High Performance Embedded SOC Processing

2009-10-06T09:49:00.000-07:00

TIE, Tensilica’s Instruction Extension language, is a simple way to make Xtensa processor cores faster and more efficient by adding new task-optimized instructions and I/O interfaces.TIE looks a lot like Verilog, but anyone can learn the basics of TIE in a few minutes whether they already know how to write Verilog descriptions or not. Just a few lines of TIE can make a dramatic difference in an Xtensa processor’s performance and flexibility for targeted tasks. Xtensa processors with TIE customizations can compute and move data tens or hundreds of times faster than conventional processor cores. As a result, your SOC gets smaller, cheaper, and faster and it will consume less power. http://www.tensilica.com/products/literature-docs/white-papers/tie---the-fast-path.htm

Excellent AMD ATI Video with Xtensa

2009-10-05T10:35:00.000-07:00

Tensilica's processors configured to accelerate video stream decoding are an ingredient in every UVD-powered AMD ATI graphics chip, including those iwth ATI Avivo HD video and dipslay techology, which provdes PC users with crisp images, smooth videos and true-to-life colors. UVD is a dedicated video decode processing unit introduced with the ATI Radeon HD 2000 series graphics processors that offloads the CPU from the decoding process. UVD technology reduces power use, helps decrease system noise and helps to increase notebook battery life during HD video playback. AMD's graphics products provide for DirectX10 gaming and allow PCs to be hooked up to big-screen TVs with HDMI and built-in 5.1 surround sound audio to enjoy Blu-ray and HD DVD movies. http://www.tensilica.com/markets/customer-gallery/graphics.htm

Everything You Wanted to Know About Blu-ray Audio

2009-09-29T10:26:00.000-07:00

Although Blu-ray discs look physically like DVDs, there are many differences including many differences in the audio. This white paper discusses those differences and the design issues surrounding the development of audio subsystems for Blu-ray disc players and related equipment.
http://tinyurl.com/yc9ekeq

The Fastest DSP Core Tested by BDTI

2009-09-28T10:13:00.000-07:00

See BDTI's report on Xtensa LX - the fastest DSP core BDTI has ever tested. http://www.tensilica.com/uploads/pdf/BDTI-tensilica_wp-1.pdf

Apnote: Fast Interrupt Handling

2009-09-25T09:42:00.000-07:00

Fast interrupt handling is important to system throughput and responsiveness. This application note describes a method to use existing Xtensa features and configuration options to support very fast interrupt handling. This note focuses on the interrupt handling case, i.e, that case where one task is running, but is preempted at some random point by an external or timer interrupt, which then performs an independent task. See http://www.tensilica.com/products/literature-docs/application-notes/system-software/interrupt-handling.htm

White Paper: Get Your ASICs and SOCs Off the Bus!

2009-09-24T10:06:00.000-07:00

This paper describes the most common hardware mechanisms - buses, direct connections, and data queues - used to interconnect processor cores on ASICs. It explains how direct processor-to-processor connections reduce the cost and latency of inter-processor communications.

http://www.tensilica.com/products/literature-docs/white-papers/get-off-the-bus/