Theremin World Recent Forum Posts

Let's Design and Build a (mostly) Digital Theremin! (by dewster)

Hard Core Logo *

I'm hoping the whole "use PCB material as panels" works out. Here is the D-Lev logo plate rendered in KiCAD:

I removed the outer ring that is normally there when the logo plate is 3D printed. The ring helps to keep everything level when sanding off the matte black spray paint, but I think it looks a bit cheesy. Here the background is matte black solder mask and the white lettering is silkscreen. The base is 1.6mm FR4 with HASL over the copper. The same logo is on the back, so hopefully at least one side will be cosmetically useful. I ordered quantity 10 from JLCPCB for $13.58 including shipping, and this will be a test for how the larger PCB panels might turn out.

* https://en.wikipedia.org/wiki/Hard_Core_Logo

Let's Design and Build a (mostly) Digital Theremin! (by dewster)

DIY DSE

Whenever I change anything in the D-Lev FPGA logic, I usually have to compile it many times in Quartus before hitting on a build that meets timing (or is close enough). The builds are tedious because I have to manually change the place & route seed between each build, and the build takes around 5 minutes on my aging PC, so there's a lot of sitting around and babysitting. This activity is known as "seed sweeping". The 180MHz processor clock domain is the hardest to reach timing closure, usually giving me results in the high 160s to mid 170s, and rarely a bit higher than 180.

Quartus has a built-in tool to automate this process called "Design Space Explorer". IMO DSE tries to do too much though, as it juggles various synthesis and place & route build parameters, when all you generally want is a seed sweep of a single initial synthesis result. I never felt all that secure about committing to the best timing result as there just were too many parameters in play. In their infinite wisdom, Intel / Altera decided to remove DSE from the free version of Quartus, which strikes me as kinda nuts as a business strategy, but who am I. They also removed the LogicLock feature, which might have helped me speed up the average build. And they 86ed the simulator a long time ago. By all means, let's hobble the hardware we're trying to sell by crippling critical software support of it, that's the ticket.

Anyway, I'm in the process of redesigning the D-Lev kit, and a new FPGA pinout seemed called for in order to help clean up the routing on the main printed circuit board. One of the really great features of FPGAs is the ability to move the pin assignments all over the place. I'm sure this has saved many a prototype from the trash.

Back to the build, I consulted with Chat GPT and it suggested a BASH script. The script opens the config text file that contains the seed number, deletes that line, and adds a new line with the new seed. It then performs a place & route followed by timing analysis by calling the Quartus command line executable versions of these Quartus modules. Finally, it greps the timing results file and reports the top speed of both clock domains to the screen and also by appending the results to a text file. It does all this in a loop, incrementing the seed until it reaches the maximum value specified in the script, and then stops.

Where has this script been all my life? I've spent many days just doing builds, particularly when designing and implementing the processor. What a relief!

Here's a the results of sweeping seeds 5 through 10:

Code:

Seed 5:
; 166.09 MHz ; 166.09 MHz      ; pll_core|altpll_component|auto_generated|pll1|clk[0]  ;      ;
; 211.19 MHz ; 211.19 MHz      ; pll_spdif|altpll_component|auto_generated|pll1|clk[0] ;      ;
Seed 6:
; 166.92 MHz ; 166.92 MHz      ; pll_core|altpll_component|auto_generated|pll1|clk[0]  ;      ;
; 212.49 MHz ; 212.49 MHz      ; pll_spdif|altpll_component|auto_generated|pll1|clk[0] ;      ;
Seed 7:
; 181.52 MHz ; 181.52 MHz      ; pll_core|altpll_component|auto_generated|pll1|clk[0]  ;      ;
; 219.2 MHz  ; 219.2 MHz       ; pll_spdif|altpll_component|auto_generated|pll1|clk[0] ;      ;
Seed 8:
; 172.8 MHz  ; 172.8 MHz       ; pll_core|altpll_component|auto_generated|pll1|clk[0]  ;      ;
; 212.09 MHz ; 212.09 MHz      ; pll_spdif|altpll_component|auto_generated|pll1|clk[0] ;      ;
Seed 9:
; 165.7 MHz  ; 165.7 MHz       ; pll_core|altpll_component|auto_generated|pll1|clk[0]  ;      ;
; 213.54 MHz ; 213.54 MHz      ; pll_spdif|altpll_component|auto_generated|pll1|clk[0] ;      ;
Seed 10:
; 175.38 MHz ; 175.38 MHz      ; pll_core|altpll_component|auto_generated|pll1|clk[0]  ;      ;
; 209.16 MHz ; 209.16 MHz      ; pll_spdif|altpll_component|auto_generated|pll1|clk[0] ;      ;

Seed 7 meets 180MHz timing, so I picked that. The other clock has to hit 196.666666MHz, and it's rare that it doesn't.

Let's Design and Build a (mostly) Digital Theremin! (by dewster)

"What a nice photo!" - JPascal

It was a very nice visit! Carolina took us to nature areas where we hiked the trails, and we got to sit in on a rehearsal of the concert she performed in last weekend, which was thrilling!

Theremin Model AR-1264 & RCA Speaker At Auction (by sebastiancharles)

Manufactured in 1929. A packet of information will be provided with the theremin, including the electrical tests, coil data measurements, a reproduction of the original RCA Theremin Instruction Manual, and more. The Theremin was fully serviced and tuned. See the listing for more details.

Auction is online, with pre-bidding open now. It's a live auction that starts October 1st, 1pm CDT. Starting bid is $500.

https://bid.sebastiancharles.com/online-auctions/sebastiancharles-auctions/theremin-model-ar-1264-rca-speaker-9605533

Let's Design and Build a (mostly) Digital Theremin! (by JPascal)

What a nice photo!

ETHERWAVE PRO CASE (by ILYA)

test

ETHERWAVE PRO CASE (by dewster)

Wow, you can upload photos again!

Let's Design and Build a (mostly) Digital Theremin! (by dewster)

Carolina!

Above: Tammie, Carolina Eyck, and me at Ontario Beach Park, Rochester, NY.

Tammie and I traveled up to Rochester to deliver an Etherwave Pro to Carolina, which she then used in concert this last weekend. We got to hang out with her for a couple of days, hiked some nature trails, ate at some good restaurants, and sat in on her rehearsal with the orchestra. Good times!

ETHERWAVE PRO CASE (by ILYA)

"I wish I could post some pictures here but I can't figure out how."

You can first 'create a new album' (http://www.thereminworld.com/photoalbums/New) then add photos to it, and then paste the photo links into your post, mate.

Rams Almost Landed A.J. Brown And June 1 Could possibly Distinction Every thing (by dewster)

And it's no use marking it as spam.

Rams Almost Landed A.J. Brown And June 1 Could possibly Distinction Every thing (by pegamin)

And thus, robots took over Theremin World.

ETHERWAVE PRO CASE (by pegamin)

Alright, so after three years I have finally purchased a case for my beautiful EPro, and I thought I would share it here since perhaps other happy owners of this theremin might be in need of one.
It seems that a Pelican 1600 case would fit it fine, but they cost nearly $400 so that was a no-no. I went instead for a knockoff of the Pelican. It fits really well and I'm a happy camper.
Details:
VEVOR 2.4 cubic feet. $80, free delivery. Worth every penny.
It comes with pre-cut foam, you simply will have to pull little squares of foam to fit the instrument. Fits like a glove, I made holes for the body, salami rod, and two antennas. Just perfect.
They sell it in Amazon but I recommend not to buy anything from that rotten site, whose owner earned 84 million dollars today, as he did yesterday and will do again tomorrow. I bought it directly from the VEVOR site. Yes, it will take longer for delivery, but probably you'll sleep better.
I would like to stress that I'm in not affiliated with this brand or product.

https://www.vevor.com/gun-cases-c_13335/vevor-2-4-cu-ft-weatherproof-hard-case-with-handle-clips-padlock-holes-foam-p_010438335551

I wish I could post some pictures here but I can't figure out how.
Best,
Pegamín

Has Anyone Tried Skillzifi for Learning New Skills? (by skillzifi)

I recently came across Skillzifi while searching online for resources to learn and improve different skills. I was browsing through the website to see what kind of learning content and opportunities are available. It looks like it focuses on helping people develop useful skills that can be helpful for personal learning or career growth.

I’m still exploring the site, so I’d like to hear from people who have already used it. How was your experience with the available courses or learning resources? Did you find the content easy to follow and useful for beginners? I’m also interested in knowing whether the platform is better suited for someone starting from scratch or for people who already have some experience.

If anyone has used Skillzifi recently, I’d appreciate hearing your honest thoughts and experiences.

From breadboard to PCB (by dewster)

"The reason to make the top side VCC as i understand is to avoid the long traces and make more room for the signal traces?" - ElGreco

Yes, it's mainly to lower the impedance of VCC by making it copper fill. Another trick is to do horizontal interconnect on one side and vertical interconnect on the other. This keeps the copper fill on both sides better connected to itself and more contiguous.

Setup for EV plus — amps (by josh craig)

If you do get the Yamaha's go with the HS8. The HS5 starts to roll off around 100hz and with the ESPE01 module, they won't be able to produce the full spectrum of sound you can get with the mod.

From breadboard to PCB (by ElGreco)

"I mean there is significant capacitance from sensitive nodes to the surrounding copper fill.

Yes I understand what you mean. The reason to make the top side VCC as i understand is to avoid the long traces and make more room for the signal traces?

From breadboard to PCB (by dewster)

"When you say capacitance sensitive you mean the tank capacitors? Should I make a keep out zone as well?" - ElGreco

I mean there is significant capacitance from sensitive nodes to the surrounding copper fill. The main thing to use copper fill for is to establish very low impedance ground and VCC. For a 2 layer board, I would probably make one side ground and the other VCC, and would do most of the interconnect on the VCC side. You have to watch out that the pour doesn't get choked off by the interconnect, though this is easier with through hole components.

I would definitely make the entire areas occupied by the oscillators copper fill keep-out zones. And I would beef up the interconnect widths. Also, try to keep the coils physically separate, particularly those that are heterodyning together.

From breadboard to PCB (by ElGreco)

A more close view of the schematic

https://ibb.co/6Jv0vv4B

https://ibb.co/XMCSWnC

From breadboard to PCB (by ElGreco)

The antennas connect in collector of each oscillator.
The software is KiCAD
When you say capacitance sensitive you mean the tank capacitors? Should I make a keep out zone as well?
Thanks for the advice

From breadboard to PCB (by dewster)

Welcome ElGreco!

I only took a brief view of your images, but have these observations / comments:

Schematic:
1. It's not clear to me where your antennas connect? Are they in parallel with significant capacitance?
2. The schematic is rather low resolution, so it's difficult to tell crossovers from connections.
3. Use a conventional voltage regulator for the entire circuit, voltage stability is very important for oscillator stability. You might use a separate regulator for each oscillator to isolate them via VCC coupling. A ferrite bead before the regulator would help decouple at higher frequencies.

PCB layout:
1. Looks like KiCAD?
2. It looks like both sides are ground, with many connecting vias?
3. The VCC traces are extremely thin and snake all over the board.
4. Connecting traces are too thin as well. Use a bare minimum of 0.25mm width here, much wider if space allows.
5. Consider making one side VCC and the other side ground.
6. Be very careful with copper fill around capacitance sensitive sections of the circuitry. Make keep-out sections as necessary, or don't use fill at all.