Triad Alliance Podcast

Triad Alliance Podcast #4, August 15, 2005

reid@triadsemi.com (Reid Wender) — Sat, 13 Aug 2005 06:34:00 -0700

This Episode #4 - An introduction to Triad's Sensor Processor Design Idea.

Welcome back everyone. Sorry for the delay in getting Episode #4 posted. I've been on the road quite abit and I've had some technical problems trying to record on the road. I'm looking to get those fixed (with Bert's help) so that even if I'm out visiting customers we can still get the podcast recorded and published.

(Download Triad Alliance PodcastEpisode#4 for August 13, 2005)

(clickthis button to automatically subscribe to the podcast via iTunes)

!!!!! MAJOR ANNOUNCEMENT !!!!!

We are moving servers for the podcast and the blog for the next show.

If you subscribe to the show through iTunes, iPodder, or Odeo hopefully everything will get taken care of automatically but it you find out that by next weekend you podcast catcher software hasn't downloaded the latest show you may need to manually resubscribe to the show through those programs.

Our new podcast/blog server address where you can get our RSS podcast feed will be:

http://triadsemi.com/?feed=rss2&category_name=podcast

Sorry for this inconenience. We are switching over from Blogger to Wordpress because Wordpress integrated directly with our website, supports podcasting enclosures directly, and will allow us to get information out with better formatting in the future.

I will post a message to the old RSS feed location giving you audio directions on how to find the new show so if you get the "here's how to find the new show message" then you aren't pointing to the new feed. The Triad Alliance Newsletter for the week of Aug 15 will also contain directions for getting the new podcast feed setup.

Contest
Seems like a lot of you are having a good time with the decode contest so I'll keep it running for at least one more show. Refer to previous posts and podcasts to determine how to download the wave file and what you need to do to win a T-Shirt.

Congradulations to Ray Silva our latest contest winner.

TSX-SP Sensor Processor

The TSX-SP is a Design Idea. We haven't committed the design to silicon yet but all of the pieces for the Sensor Processor are in place within silicon. This one of the most exciting things about Triad's solution to me. As I talked about on Epsiode #3, our reusable analog and digital intellectual property (IP) allows us to quickly realize new mixed-signal products. The TSX-SP Sensor Processor is a very powerfull Sensor-to-Information computation unit. The analog front end (AFE) is the analog section from our in production TSX1 standard product combined with a complete microprocessor subsystem that we have integrated. I've always found it easy integrated new digital features into an FPGA flow. Now, you can do the same with analog and digital features together. After looking at the TSX-SP design idea you might say:

"hmmm....that's close...I like the idea but I wish it had 7 analog acquisition channels instead of 3"

Well, using the TSX-SP design as a starting point you could quickly and easily create schematics for a 7-input OpAmp section followed by a 7-1 analog mux and you'd have a 7-channel sensor interface design. By leveraging proven building blocks you can get started with software development using an FPGA for the microprocessor subsystem while your team designs the analog sections. We are literally talking days and weeks here - Not months and years.

TSX-SP Sensor Processor

reid@triadsemi.com (Reid Wender) — Sat, 13 Aug 2005 06:25:00 -0700

TSX-SP Sensor Processor

General Description
The Sensor Processor, TSX-SP, combines an accelerated 8051 processor, math coprocessors, a Cordic math engine, a 16-bit Sigma-Delta ADC, 3 programmable gain instrumentation OpAmp sensor interfaces, 3 DACs, SPI or IIC interfaces.

The Sensor Processor is a powerful, flexible single-chip solution for processing a wide variety of sensor types. The on-board DACs can be used to provide excitation waveforms to various sensor configurations.

Via-Only Customizaton Options

Via-Mask ROM - 8051 program, linearization tables, and math look-up tables.

User Analog Configuration Area - Add custom analog functions to the TSX-SP through easyAnalog™ via-only configuration.

User Logic Configuration Area - Add custom logic functions to the TSX-SP.

Portable Medical Devices

Mobile Phones and PDA's

Tilt-Compensated Compasses

Magnetometers

Thermistors

Resistance Temperature Detectors and Thermocouples

Automotive

Liquid Flow Sensing

Sensor Mesh Networks

Process Monitoring/Control

Strain, Force, and Load Sensors

Technology
The device is implemented in 0.35 CMOS utilizing Triad Semiconductor's patented Mixed Signal Structured Array (MSSA) via-only configuration process.
Status & Support
The TSX-SP Product Idea is known to be realizable on the Triad MSSA -1platform.

Features

Accelerated, Pipelined 8051 Processor

8-bit Instruction decoder

Up to 12x reduction in cycle time

Multiply - Divide Unit

16 x 16 bit Multiplication

32 / 16 and 16/ 16 bit division

32 bit L/R shift and normalization

Cordic Math Engine

18KB Via-Programmable ROM

7KB SRAM

2 8-bit DACs, 1 10-bit DAC

SPI and IIC Interface

16-bit Sigma-Delta ADC

3 Programmable Gain Instrumentation Amplifiers (independent gain / channel)

Programmable Frequency Switched Capacitor Low-Pass Filter

Uncommited OpAmp

Via-Programmable Analog User Area

Via-Programmable Logic User Area

-40 C to 85 C temperature range

2.5V to 5V Operation

Triad Alliance Podcast #3, July 28, 2005 - FREE Analog IP

reid@triadsemi.com (Reid Wender) — Mon, 1 Aug 2005 04:48:00 -0700

FREE Reusable Analog IP

(Download Triad Alliance Podcast Episode #3)

Triad Alliance Podcast #3, July 28, 2005

reid@triadsemi.com (Reid Wender) — Fri, 29 Jul 2005 08:10:00 -0700

Today's Show
This is episode #3 of the Triad Alliance Podcast and on today's show our "guest" will be Programmable Gain Instrumentation Amplifier (PGIA). Stay tuned to learn more about Reusable Analog IP on Triad MSSA platforms.

(Download Triad Alliance Podcast Episode #3)

Announcements
New version of the website is online. Be sure and visit Triad's website to become a registered user. Once you are registered you get:

Ability to post to the online forum
Receive the weekly Triad Alliance Newsletter (you can opt-out at anytime)
Download the MSSA Design Kit (MDK)
Request that your company be listed in the Triad Alliance Member's directory
And, of course, be eligible to win the ultimate Triad Alliance Gear (we like to call it Ligerwear)

Also, new info is being added to the website daily and weekly so visit often to stay up todate on the latest developments at Triad Semi.

Contest
The Triad Audio Decryption Contest is still going on...

(see early podcast for wave file to download)

Hint: Get rid of a sine wave at a particular frequency

I used Goldwave to create and encode the message. You can use Goldwave or a similar program to analyze and decode the message. The first 5 people to decode the message win a T-Shirt from the Triad Alliance. Once you have the answer, send an email to reid@triadsemi.com with the answer and if you are one of the first 5 to respond with the right answer I will send you a T-Shirt.

Triad Alliance News
Welcome our newest Triad Alliance Member:

Carilion Biomedical Institute

Carilion Biomedical Institute is dedicated to improving the health and lives of people worldwide by partnering with scientists, researchers, and the medical and business communities to create major advances in healthcare. CBI fosters biomedical research at the University of Virginia and Virginia Polytechnic Institute and State University (popularly known as Virginia Tech) and...(read more)...

FREE Reusable Analog IP

Triad MSSA analog circuits are designed out of our fine to medium-grained analog building blocks such as:

OTA (Operational Transconductance Amplifiers)
Output Stages
OpAmps (General Purpose, Low Power, Wideband)
Resistors
Capacitors
Switches
Individual Transistors

The functions are not designed at the GDSII (polygon) level -- we've already done that for you -- You design your circuit by interconnecting these elements at the schematic level and then spice and mixed-signal simulating the design.

Once your design pass simulation you now have a reusable piece of Analog IP.

On today's show we discuss an analog macro or analog IP block the:

Programmable Gain Instrumentation Amplfier or (PGIA)

The PGIA has 8 digitally controlled gain settings ranging from -6 dB to +30 dB. The gain is selected by a 3-bit digital word. This is a good first IP block to release and review because not only is it a usefull functional block but also because it isn't overly complex. If you look thru the PGIA Analog IP Documentation on the Triad website, I think that you will get a pretty good idea of what it takes to design a function using the Triad approach. The online documentation gives you an overview of the macro and shows how much of the MSSA's available resources are utilized to create the PGIA (not much). Other pages in the PGIA area show the schematics and Verilog code used to implement the PGIA. In a couple of days we will post the Mentor Design Architect schematics and spice models for the PGIA. I will let you know when that information is available.

Triad Alliance Podcast #2, July 21, 2005

reid@triadsemi.com (Reid Wender) — Thu, 21 Jul 2005 17:23:00 -0700

Today’s Show
Stay tuned for Triad Alliance News and we will talk about Triad MSSA technology in a some more detail.

(Download Triad Alliance July21, 2005 Episode #2)

Website Location
If you are new to the show be sure and visit our website at www.triadsemi.com

If you have questions or comments about the show please email me at reid@triadsemi.com

Announcements
Wow – I wasn’t sure anybody would actually listen to the show.

Thanks for all the feedback…If there are things you like to hear about or change good or bad email me or give me a call on Gizmo (rwender).

Good week here in Knoxville – hot but nice.

My 7 year-old and are building a little Parallax robot. My son loves it. So, a call out to Chip Gracey, president of Parallax – thanks for the design kit. Chip’s definitely an engineer that loves what he is doing and man he sure has the coolest toys!

Contest
Hey no pressure here EEs but my brother the mechanical engineer "crank-head" downloaded the wave file and decoded it so get cracking and decode audio message.

(Download Contest wav file)

I used Goldwave to create and encode the message. You can use Goldwave or a similar program to analyze and decode the message. The first 5 people to decode the message win a T-Shirt from the Triad Alliance. I’ll put up a link to the wav file that you can download and decode (filter). Once you have the answer, send an email to reid@triadsemi.com with the answer and if you are one of the first 5 to respond with the right answer I will send you a T-Shirt.

Triad Alliance News
We will be launching a new version of the website in the next few days and we will be rapidly adding more Alliance information in the coming days and weeks.

Welcome to new Triad Alliance Member

Pegasus Technology – Specialists in RF and analog design. (visit www.pegasustech.com)
Telesensors – Analog and Mixed-Signal ASIC design group focused on medical and homeland security semiconductor designs. (visit www.telesensors.com)

If you’d like to be featured as an Alliance member let me know and we can setup an interview.

MSSA Technology Overview
We are making a website change so for now the information talked about in this section can be found in the show notes.

http://www.siligraphy.com/page/Mixed-Signal-Architecture

Next Week’s Show
Be sure and listen next week…we will be talking about the first analog IP block that we will be releasing to Alliance Members. The IP block is a Programmable Gain Instrumentation Amplifier that you can use and modify for your designs for FREE.

Thanks for listening..

Contact info
Reid Wender:
Visit: http://www.triadsemi.com/ for show notes.
Email me at reid@triadsemi.com
Skype or Gizmo me at: rwender

Just a simple post to claim my feed a Odeo

reid@triadsemi.com (Reid Wender) — Fri, 15 Jul 2005 04:46:00 -0700

My Odeo Channel

Triad Alliance Podcast #1, July 14, 2005

reid@triadsemi.com (Reid Wender) — Thu, 14 Jul 2005 10:40:00 -0700

Hello everyone, I’m Reid Wender, and welcome to the Triad Alliance Podcast. The podcast dedicated to mixed signal ASIC development using Triad Semiconductor’s Mixed Signal Structured ASIC technology.

To listen to the Triad Alliance Podcast, Episode #1, for July 13, 2005:

(download Episode #1 - MP3 format)

Website Location

If you are new to the show be sure and visit our website at www.triadsemi.com

If you have questions or comments about the show please email me at reid@triadsemi.com (that’s r-e-i-d @triadsemi.com).

Here on our first show I will introduce you to

· Triad Semiconductor

· The Triad Alliance – Just what is it

· And, a little bit about myself, Reid Wender, the host of the Triad Alliance Podcast

· Triad Alliance Show Format (every Thursday)

Contest

I used Goldwave to create and encode the message. You can use Goldwave or a similar program to analyze and decode the message. The first 5 people to decode the message win a T-Shirt from the Triad Alliance. Once you have the answer, send an email to reid@triadsemi.com with the answer and if you are one of the first 5 to respond with the right answer I will send you a T-Shirt.

(download contest.wav file)

The Triad Alliance – Just what is it

In a nutshell - Start your own Fabless Semiconductor company
Resource to learn more about mixed signal structured ASICs
Forum and community of Triad users sharing development ideas and solutions
Portal where you can list your mixed signal company and offer your services, products, IP.
Network with other companies in the alliance to solve problems efficiently
IP Marketplace
Online store where alliance members and customers can purchase your mixed signal ICs that you develop with Triad technology.

And, Reid Wender, your host

ASIC Designer for the past 17 years
FPGA user for 17 years
First ASIC – a 3500 gate Onscreen Display Processor
Last ASIC – 4 million gate 3D wavelet image compression CODEC
Living and working in East Tennessee and at the Triad offices in Winston-Salem, NC

(enough about me…I’ll give you more bio information on a slow news day in the future)

Format

Interviews with Alliance Members
Tips & Techniques for Mixed Signal ASIC Design
Analog IP, Mixed Signal IP, & Digital IP
Access to low-cost and even free development tools
Introduce new products developed by Alliance members
Contests, Humors, and Funs
Featured Engineer Music

Closing remarks

Thanks for listening..

Contact info

Reid Wender:

Visit: www.triadsemi.com.

Email me at reid@triadsemi.com

Skype me at: rwender

Triad Alliance Launch

reid@triadsemi.com (Reid Wender) — Wed, 13 Jul 2005 07:32:00 -0700

The Triad Alliance helps you get mixed signal designs to market!

At the Triad Allianced we are focused on bringing together developers, IP providers, tool providers, and 3rd party resources to enable you to get your new and innovative mixed signal designs to market quickly, with lowered costs, reduced risks, and we will help you get the word out about your products.

Welcome to Triad Semiconductor

reid@triadsemi.com (Reid Wender) — Fri, 18 Mar 2005 05:34:00 -0800

Hello,
My name is Reid Wender. Here at Triad Semiconductor my title is "Manager - MSSA Design" but my friends just call me the Triad Evangelist.

What is MSSA Design you ask?

Mixed Signal Structured Array (MSSA) from Triad Semiconductor (site)

Triad Semiconductor makes the world's only Via-Programmable Mixed Signal Structured Array.

Okay, but I still want to know what a MSSA is?...

Okay, let me back up...

ASIC or Application Specific Integrated Circuit, semiconductor, IC, or just 'chip' are common names for miniature electronic designs placed on small pieces of Silicon. Well, I've been making these 'chips' for over 17 years and we have kept adding more and more transistors to these chips every year. In fact, there is a law (sort of) in our industry known as "Moore's Law", after Mr. Moore of course, that states that roughly every 18 months to 2 years you can put twice as many transistors in the same area of Silicon. This doubling of transistors per unit area is achieved by reducing the "feature size" of the transistors on the Silicon every 18 months or so. Back when I started digital ASIC design we were designing a 1.2 microns (micro meters) for features sizes. Over the past 20 years feature sizes have decreased (every 18 months or so remember) down to 1.0 micron, 0.7, 0.35, 0.25, 0.18, 0.13, and now 0.09 microns or 90 nano-meters as we like to say.

All this advance in technology and reduction in feature size is great for cramming more transistors and logic gates on to the same sized piece of Silicon.

Let me digress for a second - This is why electronics products keep getting cheaper over time. Every couple of years Intel and others are able to put out computer chips that are twice as fast and less expensive than previous generations.

Back to our story...

Feature size reduction is great for packing transistors onto Silicon but the downside is that as the feature size of the transistors get smaller the process required to make the ICs gets more and more expensive. In the old days you could get a 1.0 micron chip produced for $40,000 (we call it fab'ed - short for fabricated). Well todays 0.13 micron mask sets cost $800,000 (yep there is an extra zero in there).

Lots of companies have trouble forking over $800K to make a chip. Why does it cost $800K for a 0.13 micron fab versus $40K for a 1.0 micron fab. Well, a lot of the cost is in the "Mask Set" the mask set is a group of reticules that are used to expose the Silicon wafer to create the various layers of a semiconductor that make it act like transistors and logic gates. Many CMOS fabrication processes require 20 mask layers. As the features sizes get smaller and smaller the precision and time required to make each mask goes up.

Somebody, had the great idea that if you could reduce the number of masks required to make an ASIC you could reduce the fab cost. In fact, if you could make an ASIC with only ONE MASK LAYER you could reduce the cost by about a factor of 20. Instead of spending $800K on masks for a 0.13 micron chip you could then fab the chip for $40K.

Great idea but how do you do it?...

Now, I'll tell you about Structured Arrays
A structured array is a semiconductor with 19 of the 20 layers of the chip predefined with logic gates, memory, and routing. The one undefined layer or the layer that the customer defines is the via layer. This via layer allows vias (fancy name for a metal to metal connection in an ASIC - actually more complicated than that but this is a good definition for our discussions) to connect different transistors and logic gates to each other to form logic circuits. When it comes time to fabricate the chip the via layer mask is produced, and the chip fab'ed.

(more on structured arrays next time and we haven't even touched MSSA yet...)