Verification Blog

Cadence's Labs on Cloud

2010-06-24T22:35:00.002+05:30

Have you ever wanted to try out any Cadence tools or VIPs evaluation without going through the process of getting evaluation licenses, software download and installation and all that logistic stuff? Now you can do all that without all that hassles. Cadence has tied with Xuropa for their cloud computing platform so that all you need is high speed broadband for any Cadence tools/VIPs evaluation.

Using Xuropa Online Labs, you can run an evaluation using the Incisive Enterprise simulator, following instructions for a self-paced demo. All the software runs on Xuropa servers, and there is nothing to purchase, license, install, download, or upload.

You can read more about it at at Cadence's Community Blog Post

Generic/Parameter support in Mixed HDL Hierarchy Code Generator

2010-05-08T16:40:00.002+05:30

I hope this small utility is helpful. I've thought one small enhancement to it. Now, you can select whether you need VHDL Generic or Verilog Parameterized examples code by selecting the checkbox. Please feel free to comment/enhancement. You can visit http://www.sandipgor.com/hdl_gen.html

Mixed HDL Hierarchy Code Generator

2010-04-09T18:38:00.004+05:30

Sometime back, I wanted to experiment Specman environment with Mixed HDL (Verilog + VHDL) design. I wanted to have a simple 4 level hierarchical design with simple port connections. It took some time for me to build it as I need to refer VHDL and Verilog syntax. That time one thought came to my mind to have simple utility which can build this env very quickly so that I don't need to invest time to clean up the compilation errors.

Keeping this simple requirement in mind, I decided to build such a simple online tool which can be used by everybody.

I've created one Javascript based tool which can generate Mixed HDL Hierarchical design.Its link is http://www.sandipgor.com/hdl_ gen.html

I've tried to keep it simple. You can use "Add VHDL" and "Add Verilog" buttons to add VHDL or Verilog instance into hierarchy. "Level Up" and "Level Down" buttons can be used to increase/decrease current level where you want to add instances. Finally "Generate" button can be used to dump the hierarchical HDL code into the two text box placed right side of the window. I've also kept "Clear Code" and "Clear Hierarchy" buttons to clean up the relevent data. "Undo" button is useful to undo the last change. Remember, there is no "Redo" button though.

I hope you will find it useful. Please feel free to use it.

Any suggestion/feedback is welcome.

DigitalVerification Blog is noticed by Verification Community

2009-07-10T11:30:00.002+05:30

I am glad and thankful to the verification community for appreciating my small contribution towards the verification world. This blog has been noticed by Cadence Team Specman and recoginized as useful resource.
ChipDesignMag.com also recognized this blog saying "if you live and breathe in this world, here’s an additional resource"
I'll keep posting and contributing to the verification world.

IntelliGen - Introduction

2009-06-25T12:50:00.015+05:30

IntelliGen is around for quite a while, but I've observed that most of the Specman users are less interested in/aware of it. Probably they are very comfortable with old generation engine known as PGen. Even I am quite comfortable with PGen and I am used to think generation in PGen way. But, when I went through IntelliGen, it also looked conviencing. But it will take some time to penetrate and Cadence has to push it hard so that people start thinking about generation IntelliGen way. :)

IntelliGen is a new generation engine introduced in Specman 6.1 version onwards. It is a new generation engine which uses different generation algorithm from Specman's original generation engine PGen. Though PGen remains default generation engine, user can switch to IntelliGen by setting a configuration flag before loading any code.

Specman>config gen -default_generator=IntelliGen

IntelliGen is easier to use as there is no generation dependencies on the fields declaration order. In PGen, fields which are declared first are generated first unless there are specific generation order mentioned using "keep gen before" or "readonly()". With a new and powerful debugger, its very easy to debug generation errors for IntelliGen. The messages which are displayed when any generation errors occur are more informative than whatever is displayed for PGen. Cadence also claims that performance can be increased by 2 to 5 times compared to PGen. IntelliGen solves some constraint more logically and intelligently compared to PGen. We will see all these in few examples.

Generation Order Independence

In the code shown below, we want to generate addr based on addr_hi_lo value. So you put constraint over addr_hi_lo and addr. But since addr is declared first, it will be generated first in PGen generation engine. Due to that, there are very little chance that it is either equal to addr_hi or addr_lo. So, either of the constraint on addr_hi_lo does not satisfy and PGen will not be able to solve it. Though the constraint is bidirectional, since addr is declared first, it is generated first and that makes constraint unidirectional.

Same code will not cause any generation error if IntelliGen is used because, there is not generation dependency on declaration order.

define addr_hi 0xFF;

define addr_lo 0x05;

type addr_kind : [LO, HI];

extend sys

{

addr : list of uint (bits: 8);

addr_hi_lo : addr_kind;

keep addr.size() == 10;

keep for each in (addr)

{

addr_hi_lo == HI => it == addr_hi;

addr_hi_lo == LO => it == addr_lo;

};

post_generate() is also { print addr; };

};

Results with PGen:

*** Error: Contradiction:
A contradiction has occurred when generating sys-@0.addr_hi_lo :
Previous constraints reduced its range of possible values,
then the following constraint contradicted these values:
addr_hi_lo == LO => it == addr_lo; at line 20 in @temp
Reduced: sys-@0.addr_hi_lo into []
To see details, reload and rerun with "collect gen"

Results with IntelliGen:

addr = (10 items, dec):
5 5 5 5 5 5 5 5 5 5 .0

Better Solvability

Further to that, IntelliGen takes good care of soft and soft select constraints. When soft select constraints are added for a field which already has soft constraint defined previously, PGen will ignore all the previously defined soft constraints even there are no contradiction between soft and soft select constraints. Whereas IntelliGen takes care of both constraints as long as they do not contradict. If they contradict, then IntelliGen ignores soft constraint over soft select. Take a look at the following example and results generated using PGen and IntelliGen.

type addr_kind : [LO, HI, OTHERS];

struct operation_s

{

addr_hi_lo : addr_kind;

keep soft addr_hi_lo in [HI, LO];

};

extend operation_s

{

keep soft addr_hi_lo == select

{

10 : LO;

80 : OTHERS;

10 : HI;

};

extend sys

{

op : list of operation_s;

keep op.size() == 10;

post_generate() is also { print op; };

};

Results with PGen:

op =
item type addr_hi_lo

0. operation* OTHERS
1. operation* OTHERS
2. operation* OTHERS
3. operation* OTHERS
4. operation* HI
5. operation* OTHERS
6. operation* OTHERS
7. operation* HI
8. operation* HI
9. operation* OTHERS

Results with IntelliGen:

op =
item type addr_hi_lo

0. operation* LO
1. operation* LO
2. operation* HI
3. operation* HI
4. operation* LO
5. operation* HI
6. operation* HI
7. operation* LO
8. operation* LO
9. operation* LO

Better Distribution

Because of improved constraint solving ability, IntelliGen gives better distribution of generated values within the range.

define addr_hi 0xFF;

define addr_lo 0x05;

type op_kind : [LO, HI, OTHERS];

struct operation_s

{

addr : uint (bits: 8);

op_hi_lo : op_kind;

keep op_hi_lo == HI => addr == addr_hi;

keep op_hi_lo == LO => addr == addr_lo;

keep op_hi_lo == OTHERS => addr in [addr_lo+1..addr_hi-1];

};

extend sys

{

op : list of operation_s;

keep op.size() == 10;

post_generate() is also { print op; };

};

Results with PGen:

op =
item type addr op_hi_lo

0. operation* 0x57 OTHERS
1. operation* 0x12 OTHERS
2. operation* 0x80 OTHERS
3. operation* 0xbe OTHERS
4. operation* 0x7f OTHERS
5. operation* 0x64 OTHERS
6. operation* 0x0f OTHERS
7. operation* 0xab OTHERS
8. operation* 0x6e OTHERS
9. operation* 0xcd OTHERS

Results with IntelliGen:

op =
item type addr op_hi_lo

0. operation* 0xff HI
1. operation* 0xc3 OTHERS
2. operation* 0xff HI
3. operation* 0x05 LO
4. operation* 0x05 LO
5. operation* 0x05 LO
6. operation* 0x1d OTHERS
7. operation* 0x6a OTHERS
8. operation* 0x1a OTHERS
9. operation* 0xff HI

Better Debug Information

When any generation error occurs, IntelliGen issues elaborated generation error message which is very useful to pin point the problematic area of the code. Look at the below code.

type addr_kind : [LO, HI, OTHERS];

struct operation_s

{

addr_hi_lo : addr_kind;

keep addr_hi_lo in [HI, LO];

};

extend sys

{

op : list of operation_s;

keep op.size() == 10;

keep for each in (op)

{

index in [0] => it.addr_hi_lo == LO;

index in [1..8] => it.addr_hi_lo == OTHERS;

index in [9] => it.addr_hi_lo == HI;

};

post_generate() is also { print op; };

};

Error Message with PGen:

*** Error: ERR_GEN_OR_WITH_NO_GEN_ALT: After static analysis, the following constraint
consists of non-enforceable constraints only:
index in [1..8] => it.addr_hi_lo == OTHERS; at line 19 in @temp

Error Message with IntelliGen:

*** Error: Contradiction when generating sys

No set of values exists for:
op[0x0..0xffffffff].addr_hi_lo

that obey the constraints:
keep addr_hi_lo in [0x0..0x1] at line 7 in @temp ,
index in [0x1..0x8] => it.addr_hi_lo == OTHERS at line 19 in @temp

with the input:
index = 0x1

By now, you might have realized the improvement of IntelliGen over PGen. I hope this is useful basic information about IntelliGen. I'll cover IntelliGen Technical Concepts in my next post.

Specman/Verification Books

2009-06-15T10:57:00.009+05:30

Specman Books

Design Verification with e
Author :	Samir Palnitkar
ISBN	0131413090
Publisher	Prentice Hall Professional Technical Reference
Publish Date	Auguts, 2003
Page	416
Preview

The e-Hardware Verification Language
Author :	Sasan Iman and Sunita Joshi
ISBN	1402080239
Publisher	Kluwer Academic Publishers
Publish Date	May, 2004
Page	349
Preview

Aspect-Oriented Programming with the e Verification Language: A Pragmatic Guide for Testbench Developers
Author :	David Robinson
ISBN	0123742102
Publisher	Morgan Kaufmann Publishers
Publish Date	August, 2007
Page	244
Preview

Verification Books

Metric Driven Design Verification: An Engineer's and Executive's Guide to First Pass Success
Author :	Hamilton B. Carter; Shankar G. Hemmady
ISBN	0387381511
Publisher	Springer Verlag
Publish Date	May, 2007
Page	361
Preview

Writing Testbenches: Functional Verification of HDL Models
Author :	Janick Bergeron
ISBN	1402074018
Publisher	Kluwer Academic Publishers
Publish Date	February, 2003
Page	512
Preview

Effective Functional Verification: Principles and Processes
Author :	Srivatsa Vasudevan
ISBN	0387286012
Publisher	Springer Verlag
Publish Date	June, 2006
Page	256
Preview

Principles of Functional Verification
Author :	Andrea S. Meyer
ISBN	0750676175
Publisher	Newnes
Publish Date	November, 2003
Page	240
Preview

SystemVerilog Books

Step-by-step Functional Verification with SystemVerilog and OVM
Author :	Sasan Iman
ISBN	0981656218
Publisher	Hansen Brown Publishing
Publish Date	May, 2008
Page	520
Preview

SystemVerilog for Verification: A Guide to Learning the Testbench Language Features
Author :	Spear, Chris
ISBN	0387270361
Publisher	Springer
Publish Date	June, 2007
Page	429
Preview

Verification Methodology Manual For Systerm Verilog
Author :	Andy Nightingale, Alan Hunter, Eduard Cerny and Janick Bergeron
ISBN	0387255389
Publisher	Springer-Verlag New York Inc
Publish Date	2005
Page	503
Preview

Writing Testbenches Using SystemVerilog
Author :	Janick Bergeron
ISBN	0387292217
Publisher	Springer-Verlag New York Inc
Publish Date	2006
Page	412
Preview

A Practical Guide for System Verilog Assertions
Author :	Srikanth Vijayaraghavan and Meyyappan Ramanathan
ISBN	0387260498
Publisher	Springer Verlag
Publish Date	2005
Page	334
Preview

Hardware Verification With SystemVerilog: An Object-oriented Framework
Author :	Mike Mintz and Robert Ekendahl
ISBN	0387717382
Publisher	Springer
Publish Date	May, 2007
Page	314
Preview

randc kind of implementation in e

2009-05-25T16:38:00.004+05:30

When I went through SystemVerilog constructs, one of the unique construct I found out was randc. Cyclic randomization sometimes helps you generating all unique combinations before repeating it. One classic usage example of randc is to inject all the sequences into DUT at least once without repeating it again. So, I was wondering if it is possible to implement it in e. I realized that though you can not generate the item based on its previously generated values, you can have some workaround for that using list psudo methods. There are all_values() and is_a_permutation() psudo methods which can be used for this purpose.

Let me explain the logic to implement that classic usage example to inject all the sequences into DUT without repeating it. If we somehow generate a list of unique sequence kinds randomly, we can take that list items one-by-one and generate the sequence based on that kind. So, to generate the unique yet random list of sequence kind, we can use above mentioned two list psudo methods. Take a look at the following code snippet.

type seq_type_t : [SEQ_A, SEQ_B, SEQ_C, SEQ_D, SEQ_E, SEQ_F, SEQ_G];

extend MAIN my_sequence_s

{

seq_randc : list of seq_type_t;

keep seq_randc.is_a_permutation(all_values(seq_type_t));

!seq : my_sequence_s;

body() @driver.clock is only

{

gen_seq_randc();

for i from 0 to seq_randc.size() - 1

{

do seq { keeping .kind == seq_randc[i]; }

};

all_values(seq_type_t) statement will return a list which will have all the unique values of scaler type seq_type_t. is_a_permutation() will make sure that seq_ranc list has random but all the fields of the list returned by all_values(seq_type_t) statement. Thus, we have a list which has all the random values of the sequence kind. Now, we can loop through this list one by one and generate a seq and push it to the DUT.

Less known and less used Specman commands

2009-05-22T14:27:00.024+05:30

There are quite a few Specman commands which are handy when it comes to debugging. Here I tried to summarize few less known but useful Specman commands. Here we go.

If you have verification environment loaded on Specman and one method is extended in multiple files and you want to see all the extension of that method in a single place, "collect" command is what you are looking for.

Specman> collect sys.mystruct.monitor

Specman> collect sys.run

File temp.erld - created by collecting:

sys.run (after module specman)

----------------------- Reset sys.run:

extend sys {

run(

) is as was after specman;

};

----------------------- From temp.e at line 6:

extend sys {

run() is also

{

var x : mystruct_s;

gen x;

};

----------------------- End of sys.run

If you want to debug temporal expression, you would like to visualise how different events are triggered. Event chart is basic but sometimes useful for debugging temporal expressions. To see the events you first have to collect events you are interested in by using "collect events" Specman command.

Specman> collect events *.*
Specman> collect events sys.mystruct.* //collects all events for the instance sys.mystruct
Specman> collect events mystruct_s.* //collects all the events of struct mystruct_s

If you want to see the events triggered during simulation, you can use Specman command "show events" after collecting the events as mentioned above.

Specman> show events
Specman> show events 100 //This command shows events since time 100
Specman> show events 100..150 //This command shows events in the time range 100..150
Specman> show events -chart //Pops up event chart

If you want to have a summarized report about the events count, if it is associated with cover group, its source etc, you can use "show events def" command.

Specman> show events def sys.any

count echo col covr name source
------------------------------------------------------------------
0 10000 FALSE TRUE FALSE sys.any @sn_te_tick

Executing actions on command line. You can define variables or call methods or start a TCMs. (you can not call a TCM on command line). Remember, you can not give "gen" action on command line, but you can call a method which has gen action in it.

Specman> var x : uint(bits: 4) = 5;
Specman> var y : uint = x + 10;
Specman> print x + y;
Specman> sys.non_tcm()
Specman> start sys.tcm()
Specman> sys.non_tcm_with_arg(4, TRUE)

You can search/grep within the loaded files using "search" command

Specman> search mystruct_s

You can open a file (known as "module" in Specman terms) in source browser by using "source" command. It will open a source browser with that perticular line number into focus.

syntax: source

Specman> source mystruct.e 50

You can run unix commands using "shell" command.

syntax: shell

Specman> shell echo $SPECMAN_PATH
Specman> shell pwd

You can also get the value of define by issuing "show define" command.

syntax: show define [-v] [-e]

Specman> show define -v "*WIDTH*"

If you want to know what are the modules that are loaded you can use "show modules" command.

Specman> show modules

You can get unix environment variables value within your e code by using get_symbol() method.

my_method() is

{

outf ("SPECMAN_PATH=%s",get_symbol("SPECMAN_PATH"));

};

12. If you wish to execute specman command in e code, then you can use specman() method as shown below.

pre_generate() is

{

specman("break on error");

};

If you wish to execute unix command from your e code, you can use output_from() method.

my_method() is

{

var list_of_files: string;

list_of_files = output_from("ls");

print list_of_files;

};

If you want to uderstand port binding in Specman, use "show ports" command.

You can use "trace bind' to follow the binding process

If you have executed a set of commands and want to see the history of executed commands, you can use "show redo" command.

Specman> show redo
show redo
The redo buffer (default is 'redo 0..') =
0. "restore specman.esv"
1. "load temp.e"
2. "test"
3. "clear screen; restore; reload; test"

Once you know the hisotry of executed command, you can reexecute them by issueing "redo" Specman command.

Specman> redo 3 //this will execute command 3 (clear screen; restore; reload; test)
Specman> redo 0..2 //this will execute command 0 to 2 (restore specman.esv, load temp.e, test)

If you have wave command executed to view e fields into waveform and want to dump all these wave tracing commands into a file, you can use "write wave" command.

syntax: write wave to

Specman> write wave to trace_wave.ecom

19. To debug, packing and unpacking, you can use "show pack" and "show unpack" command as shown below.

Specman> var x : uint (bits: 3) = 3
Specman> var y : uint (bits: 7) = 5
Specman> show pack(packing.low, x, y);

|9 8 7 6 5 4 3|2 1 0| +0
+-------------+-----|
|0 0 0 0 1 0 1|0 1 1|
+-------------+-----|
|y |x |

Specman> var x : packet_s
Specman> var data : list of bit = {1;1;0;1;0;0;0;1;1;1;0;1}
Specman> show unpack(packing.low, data, x)

|1 0 9 8 7 6 5 4|3 2 1 0| +0
+---------------+-------|
|1 0 1 1 1 0 0 0|1 0 1 1|
+---------------+-------|
|x.addr |x.len |

Debugging packing and unpacking in Specman

2009-05-21T13:03:00.014+05:30

Hello readers, I am back after a loooooong break. It has been quite a some time since I posted something here as I was too busy with my personal life and responsibilities. I try to be regular now. So with this note, let me start something from today itself.

While using packing/unpacking in your environment, you might have gone through some debugging troubles due to silly mistakes. So here are few tips to avoid errors for packing and unpacking.
So starting with Unpacking, there can be 2 kind of problems you may face while unpacking a list into struct

You run out of data while unpacking (i.e. list is shorter than total length of physical fields of a struct)
Unpacking is finished but you have bits/bytes left over (i.e. list is bigger than total length of physical fields of struct)

If you have situation 1, it will be flagged as run-time error by Specman. But, if you have situation 2, you might not even aware of it as Specman does not issue even a warning for this. For situation 1, if you want to suppress run-time error, you can use 'try' action.

tcm() @clk is {

try {

unpack(packing.low, my_list, my_struct);

} else {

message (LOW, "Unpacking failed");

};

To debug packing/unpacking issues, you can use Specman command 'trace packing'. It shows how packing/unpacking is performed. Following example shows the result of 'trace packing' command performed for unpacking.

Following example shows the result of 'trace packing' command performed for packing

If unpacking is unsuccessful (ran out of data in the list), you normally get following message on Specman STDOUT.

*** Error: Ran out of data while trying to unpack (use 'trace packing' for further details)
at line 19 in @packing_unpacking_debug
unpack(packing.low, lob_u, x);

But if you use 'trace packing' Specman command, you see where unpacking stopped.

> ----- Starting an unpack() at line 19 in @packing_unpacking_debug ----

> ----------- Unpacking 'x': x_s
> Unpacking 'x.a': uint (bits: 4)
8 .0
> 'x.a': uint (bits: 4) = 8
> Unpacking 'x.b': uint (bits: 8)
0 5 .0
> 'x.b': uint (bits: 8) = 5
> Unpacking 'x.c': list of byte
*** Error: Ran out of data while trying to unpack into 'x.c'
at line 19 in @packing_unpacking_debug
unpack(packing.low, lob_u, x);

One of the very common cause of the unpacking failure is the unsized list. If the target struct has unsized list as a physical field, all the bits/bytes of the source list will be absorbed by this unsized list and there will be no data left for the next physical field and Specaman will issue an error. So it is always advisable not to have unsized list in the target struct.

Another reason for unpacking failure could be subtype physical fields. If you have few physical fields defined under 'when' subtype of a struct, your need to make sure which subtype to pick while unpacking.

One more reason for the unpacking to give errorneous result is the order of the physical fields in a struct. If physical fields of a struct is defined in the multiple files, then import order of that file becomes crucial because based on the order, physical fields will be treated differently during unpacking. Take a look at the following example.

Job openings at Cadence Design Systems, India (Bangalore and Noida)

2008-12-17T12:19:00.003+05:30

In this tough time, there are some openings at Cadence Design Systems for its India centers (Bangalore and Noida). Please have a look at the openings for more details here.

Verification Engineer required for Cadence Design Systems, Bangalore or Noida

2008-10-15T12:29:00.004+05:30

Experience: 4 to 5 years

Location: India, Bangalore or Noida

Job Requirement:

This engineer’s primary role will be to work in a team oriented environment to deliver digital logic design and verification methodologies, customised design environments and design implementation solutions that align with client goals. He/she will interact and work with other engineers on the worldwide D&V VCAD delivery team.
Responsibilities will include creating and customising design environments, design and verification methodologies.
Ideally the canddate should be able to assist with the optimisation of acceleration and emulation technologies using the Cadence Incisive verification flows including the Palladium and Xtreme hardware.
The engineer must have a solid background in logic design and verification experience with Cadence technology in the digital domain.
The client should have at least a basic understanding of modeling (e.g. Architecture or system), and both block and system level verification experiance, preferably with coverage driven methodologies.
The candidate should possess the necessary engineering and consultancy skills, i.e. that he/she is technically mature with the necessary communication skills to be able to consult effectively with clients, e.g. to talk to, coach and advise Customers.
The engineer must have a solid background in the electronics industry with at least 4 to 5 years experience, and should be willing to learn new technical and consulting skills.

Key Accountabilities:

Execution on VCAD Customer support projects, e.g. Implementation and functional verification of design systems.
Development of customer specific verification environments including components, methodology support, operation and maintenance.
Be prepared to provide design and verification support in VCAD Customer design projects, both remotely and onsite.
Ability to handle all design environment implementation tasks and architectural tasks with the minimum support or through working in a joint team of Cadence and Customer engineers.
Work on multi person projects of varying complexity, working especially in a multi-site/multi-cultural project. The latter requires excellent communication skills in English.
Acquire a basic understanding of the (service) business environment of Cadence within 6 months including pre sales support.

Contact: getjobsinindia2007@gmail.com

DFT Engineer required for Cadence Design Systems, Bangalore

2008-10-15T12:16:00.004+05:30

Experience: 3 to 6 Years

Location: Bangalore, India

Skill Sets: Scan, Jtag, Atpg, Tester interface.

Good to have skills: Exposure to ATPG tools like Encounter Test

Job Description:

This engineer’s primary role will be to work in a team oriented environment to deliver DFT activities for implementation services. He/she will interact and work with other engineers on the worldwide delivery team.
This engineer is expected to provide services using the following technical skills: Scan, JTAG, ATPG, Logic Synthesis, Static Timing Analysis, and to interface with designers / testing team.
In addition to the technical skills they will be expected to operate effectively in project teams delivering the design of leading edge. Additional responsibilities include customer interactions and pre-sales activities.

Key Accountabilities:

Ability to handle all design environment implementation tasks assigned, either personally or through supervising other Cadence and Customer engineers.
Work on multi person projects of varying complexity, working especially in a multi-site/multi-cultural project. The latter requires excellent communication skills in English.
Acquire a basic understanding of the (service) business environment of Cadence including pre sales support.

Contact: getjobsinindia2007@gmail.com

OVM 2.0 Webinar on 16th Oct, 2008

2008-10-15T11:57:00.005+05:30

There is a OVM 2.0 Webinar organized on 16th Oct, 2008.

Details of webinar is mentioned below.

Date : Thursday, October 16th, 2008
Time : 10:00 AM - 11:00 AM (Pacific Daylight Time)
Location : Online via Microsoft Office Live Meeting (details provided upon registration)

For more information and registration, please click here.

OVM 2.0 update contains some technical advances. Few of are listed bellow

Unified sequence mechanism
OVM User Guide
Improved debugging and expanded use of parametrized classes
Driver/sequencer communication enhancements

IEEE Working Group Announces Updated e Language Standard

2008-05-26T12:22:00.002+05:30

The e Functional Verification Language Working Group (eWG) was formed to define a standard for the e language, and the initial 1647-2006 standard was published in September 2006. And now, IEEE has approved a revision to IEEE 1647, Standard for the Functional Verification Language e. This revision is called 1647-2008 e Language Standard

Please see following link for more details.
http://standards.ieee.org/announcements/IEEE1647_eLanguageStandard.html

OVM Seminars at Hyderabad and Bangalore

2008-03-13T10:57:00.008+05:30

There is an OVM semniar held at Hyderabad on Thursday, March 25, 2008 between 8:30 am to 2:30 pm (IST) and at Bangalore on Thursday, March 27, 2008 between 8:30 am to 2:30 pm (IST).

For registeration, please visit http://www.ovmworld.org/seminars.php

Here are the topics covered in the seminar.

OVM Overview

Planning for Verification
Testbench Architecture
Transaction-Level Modeling (TLM) in Verification

Stimulus and Coverage

Transaction-Level Stimulus
Decoupling Stimulus from the Design
Sequential Stimulus Specification
Layered Stimulus
Transaction-Level Layered Coverage

Planning for Verification Reuse

Flexible Instantiation – Using the Factory
Configuring Verification Components for Reuse
Hierarchical Encapsulation & Reuse

Putting it All Together

OVM Moving Forward

About generation of do-not-generate fields

2008-02-13T16:08:00.020+05:30

Say a parent struct is having two fields inside it. One is an ungenerated (with do-not-generate sign) child struct and another ungenerated field is of pre defined data types (like uint, bool etc.).

When this parent struct is generated

1) ungenerated field of pre defined data types will get their initial value (0 for scalars, NULL for structs, empty list for lists).

2) ungenerated field whose value is a range (such as [0..100]) gets the first value in the range.

3) ungenerated field of user defined data types (like sturcts) will not be allocated and none of the fields in it will be generated.

Take a look at following code.

struct child_s

{

!a : uint (bits: 4);

b : uint (bits: 4);

};

struct top_s

{

!child : child_s;

!x : uint (bits: 3);

!y : uint (bits: 3);

keep x in [2..5];

};

extend sys

{

top : top_s;

};

In this example, top_s struct has one ungenerated struct and two ungenerated fields of uint (bits: 3). When top is generated inside the sys

1) y will be generated and will get any random value between 0 and 7

2) x will be generated with value of 2 as it is a range bound ungenerated field.

3) child field will not be generated as it is defined as ungenerated struct. So, the fields a and b of child struct will not be generated as well.

By default MAIN sequence is not empty

2008-02-12T16:30:00.000+05:30

By default, body method of MAIN sequence is not empty. It contains a loop which executes random number of times creating the sequence field (randomly unless constrained). The generated/created driver contains an instance of the MAIN sequence, which is started automatically upon run().

So, in your environment, if body method of MAIN sequence of any eVC is not made empty, it will start executing some random sequences at 0 simulation time. This might have adverse effect on the behavior of the stimulus given to the design if you are using virtual sequence, because user defined sequence (executed inside virutal sequence) and MAIN sequence might be running parallely and might be driving same signals and causing undesirable stimulus.

Debugging this will become difficult. You might be wondering why some other sequences are being executed even though you are calling perticular sequence only in virtual sequence?

So, if you are an eVC developer, always provide sequence library with body of MAIN sequence made empty. And if you are verifying any DUT and if you are using virtual sequence and not using MAIN sequence of any eVC, make body method of all MAIN sequences empty.

Take a look at this e code to check that how MAIN sequence is executing a loop which creates and executes the random sequence. Load this e code and give test command with random seed. You will see that even though body method of MAIN sequence is not extended, MAIN sequence is executing random sequneces (TEST1, TEST2, SIMPLE).

OVM available on its new site

2008-01-14T15:00:00.000+05:30

Open Verification Methodology (OVM) is now available on its new site http://www.ovmworld.org

Checker implementation dilema

2008-01-08T12:14:00.000+05:30

Ever encountered the checker implementation dilemma? How to implement it? Using temporal expressions or using methods? Once in a lifetime, every verification engineer comes to a stage where they have to take decision about the implementation of a checker. Once, I made a wrong decision and implemented a complex event-based checker in temporal expressions using "expect" statement. After that I was introduced to the hell of debugging temporal expressions in Specman. Event chart is a junk feature in the Specman. Filtering of the events, having full path of the events are not so easy to see in the events chart. Even, when-subtypes' events can not be viewed separately.

After having a lot of trouble debugging temporal expressions, I re-wrote the entire checker in the methods format using "check that" and "if else" construct. Debugging of method based checker is such an easy task in Specman, as Specman has a beautiful and reliable debugger. Lot of features, though might be basic, are quiet useful when it comes to debug the method based checkers. In Specman debugger, one can put conditional and unconditional breakpoints, can see the hierarchy of the threads, can add watch points on e fields and a lot more. I will discuss about debugging in Specman for the beginners in the separate post.

After that experience, I concluded following things for the checker implementation.

Write down the checker in the simple english to understand its complexity.
If checker is simple, I mean, just contains 2 to 3 basic events to check, then go for temporal expressions for the checker implementation.
If checker is even a bit complex having more than 3 events, just go for the method based checker implementation. You will save a hell lot of time which might be lost in the debugging temporal expressions.

Method based checker implementation looks more readable, even though it requires extra codes to implement and it's a bit slower than temporal expressions based checkers. But at the end, you are going to save lot of time having clean checker.

Specman Verification Questions - Part III

2008-01-04T10:06:00.000+05:30

Question 1: What will be the output if following code is loaded and test command is issued into Specman ?

struct x

{

y : uint;

keep soft y == 8;

};

extend sys

{

run() is also

{

var x : x;

gen x;

var a : uint = 2;

outf ("a = %d x.y = %d\n", a, x.y);

update_field(a);

update_struct(x);

outf ("a = %d x.y = %d\n", a, x.y);

};

update_field(a: uint) is

{

a = 4;

};

update_struct(x: x) is

{

x.y = 4;

};

Answer:

a = 2 x.y = 8

a = 2 x.y = 4

Here, variable uint a is not updated and struct x is updated. Why is so? Because in specman, unlike user defined data types (e.g. structs, units), all variables with standard data types are passed by value in the methods. All user defined data types (like structs) are passed by reference. So, whenever, called methods update the passed structs, it is actually updating the original struct and not its copy.

If one wants user defined data types to be passed by value then he/she can use deep_copy to copy the existing variable and pass it to the method as shown below.

struct x

{

y : uint;

keep soft y == 8;

};

extend sys

{

run() is also

{

var x : x;

gen x;

var a : uint = 2;

outf ("a = %d x.y = %d\n", a, x.y);

update_field(a);

update_struct(deep_copy(x));

outf ("a = %d x.y = %d\n", a, x.y);

};

update_field(a: uint) is

{

a = 4;

};

update_struct(x: x) is

{

x.y = 4;

};

Question 2: What is the difference between inheritance implemented by "when" construct and implemented by "like" construct?

Answer:

like inheritance is the concept of the object oriented programming (OOP) where as when inheritance is the concept of aspect oriented programming (AOP). For more detail on AOP, please refer Aspect-Oriented Programming with the e Verification Language book written by David Robinson (Verilab).

like construct is used when someone wants to derive a child object from the already defined struct/unit. This derived child will have new struct/unit name. When someone derive the child object using when construct, the base name of the child will remain the same.

Another difference between like and when construct is that, once the child is derived using like inheritance, one can not add extra fields in the parent struct/unit, wherease, if child is derived using when construct, parent struct/unit can have extra fields.

Take a look at the following example. packet_valid field is added in the parent struct packet_s after the child is derived using like inheritance. This is not allowed and Specman will issue an error during loading phase.

type packet_type_t : [GOOD, BAD, UGLY];

struct packet_s

{

kind : packet_type_t;

};

struct good_packet_s like packet_s

{

packet_size : uint (bits: 5);

};

extend packet_s

{

packet_valid : bool;

ack() is

{

outf ("NOTE :: This is packet %s\n", me);

};

extend sys

{

packet : packet_s;

good_packet : good_packet_s;

};

Specman will issue following error.

*** Error: Cannot add new field 'packet_valid' to struct 'packet_s': it has like children (e.g. 'good_packet_s') with fields.

Note that ack() method will be added in the parent struct packet_s even though child is derived using like inheritance.

IEEE standard draft for e available for review

2007-12-27T12:49:00.000+05:30

Individuals interested in functional verification languages are invited by eWG (e Work Group) to take part in the standardizing the e functional verification language. The eWG is sponsored by the IEEE Design Automation Standards Committee called DASC.

Read more about eWG and its activity here.

IEEE Standard P1647 draft for functional verification language e is also available for review. Click here to see the draft..

My Toon

2007-12-24T18:36:00.000+05:30

Raised Objection Report

2007-12-24T17:47:00.000+05:30

Any raised objection will prohibit your simulation to stop. And In large environments, it may be painfull to find the one objection still raised using the SN commands 'show objections' or 'trace objections'.

You may just load follwoing e-code in your test and you'll be able to get a short report of all raised objections by typing 'sys.report_raised_objections(TEST_DONE)'

extend sys

{

report_raised_objections(kind : objection_kind) is

{

// usage: sys.report_raised_objections(TEST_DONE)

var obj_units : list of any_unit = get_all_units(any_unit).all(.get_objection_counter(kind) > 0);

outf("-----------------------------------------------\n");

outf("Objection Report:\n");

outf("Counter Total Env e path\n");

outf("------- ----- ---- ------\n");

for each (u) in obj_units

{

outf("%-7d %-5s %-7s \n", u.get_objection_counter(kind), u is an any_env ? u.short_name() : "", u.e_path());

};

// just to print the command in the sn window

run() is also

{

outf("-----------------------------------------------\n");

outf("REPORT_RAISED_OBJECTIONS loaded\n");

outf("usage: sys.report_raised_objections(TEST_DONE)\n");

outf("------------------------------------------------\n");

};

Are You Reporting Wrong Coverage Number?

2007-12-14T16:31:00.001+05:30

If you are not giving weight to your items in your coverage groups, the overall functional coverage number you get on Specman coverage report might be wrong. Let me explain it using an example. Take a look at following code.

struct coverage_example

{

event cover_e;

a : bool;

b : uint (bits: 2);

cover cover_e is

{

item a;

item b;

cross a, b;

};

run() is also

{

emit cover_e;

};

extend sys

{

cov_ex : coverage_example;

keep soft cov_ex.a == TRUE;

keep soft cov_ex.b == 0;

};

If you load above code, issue a test command and see the coverage report, it will show you 28%, which is wrong in fact. Specman calculates the overall coverage numbers hierarchical. For the above code, it calculates as following.

For item a:
total bucket = 2
total hit = 1
So, coverage number = 50%

For item b:
total bucket = 4
total hit = 1
So, coverage number = 25%

For cross a, b:
total bucket = 4*2 = 8
total hit = 1
So, coverage number = 12.5%

For Overall:
total bucket = 3 (item a, item b and cross a,b)
total hit = (50 + 25 + 12.5) = 87.5
So, coverage number = 29.166% (87.5/3)

But, in fact, it should be calculated as following.

Total bucket in the coverage group = 2 + 4 + 8 = 14
Total hit = 1 + 1 + 1 = 3
So, overall coverage should be (3*100/14 = 21.4285%)

This wrong calculation can be avoided by doing following modification in the code. See highlighted "green" code below.

struct coverage_example

{

event cover_e;

a : bool;

b : uint (bits: 4);

cover cover_e is

{

//Weight is total number of buckets

item a using weight=2;

item b using weight=4;

cross a,b using weight=8;

};

run() is also

{

emit cover_e;

};

extend sys

{

cov_ex : coverage_example;

keep soft cov_ex.a == TRUE;

keep soft cov_ex.b == 0;

};

But, all the time, applying weight to every item is not possible, as some code may be imported from third party vendor or some code might be read-only to the user. Also whenever the number of buckets change, user needs to update the weight of particular item. This might not be feasible sometimes.

To avoid this, there is a utility called bucket_counter which was delivered by Clemens Mueller from Cadence. This e code will report total number of buckets in each item and total number of bucket hits. This simple utility will help you calculate the exact number of functional coverage you have.

Please click here to download the code.

Just load the ecode along with your environment and read the coverage file. Then issue "sys.report_buckets()". It will report total number of buckets in each item, and total number of hits, as shown below.

Valid Space size for item a is 2 buckets
Valid Space size for item b is 4 buckets
Valid Space size for item cross__a__b is 8 buckets
total coverage buckets: 14
total coverage buckets hit: 3

Nice Papers on AOP and Verification

2007-12-13T17:23:00.000+05:30

Here are 3 nice paper written by David Robinson from Verilab on following topics.

1) An Introduction to Aspect Oriented Programming in e
2) Simplify SoC Verification using a Generic Approach
3) Simplify SoC Verification using a Generic Approach - NMI