Insights

This guide highlights 5 critical mistakes engineers make when verification planning.

April 22, 2026

Articles

#verification #planning

This paper presents pragmatic solutions for verifying complex mathematical algorithms implemented in hardware in an efficient and effective manner.

October 14, 2024

Presentations

#verification #algorithms #KAT #UVM #SystemVerilog #RADAR

Vanessa revisits her PhD dissertation, a study evaluating Bayesian optimization and reinforcement learning to optimize constraints in a UVM environment. (Vanessa Cooper)

April 13, 2023

Presentations

#ML #UVM

In this lecture-style workshop, we will address some common problems we have seen faced by verification teams, and provide techniques and guidelines based on extensive project experience. ( Jeff McNeal, Jeff Vance, Paul Marriott )

March 3, 2022

Presentations

#DVCON_US #PLANNING

The e Toolkit (etk) is a free perl script that we've developed to help you analyse e code. You can use it to ask questions about a testbench. ( David Robinson )

October 4, 2009

Other Downloads

#SPECMAN

A Specman/e package that provides a memoization utility for methods. ( Thorsten Dworzak )

May 9, 2013

Other Downloads

#SPECMAN

Getting Started with UVM: A Beginner's Guide is an introductory text for digital verification (and design) engineers who need to ramp up on the Universal Verification Methodology quickly. (Vanessa Cooper)

May 22, 2013

Books

#UVM

Takes a look at the new Multi-Stream Scenario features Verilab developed for Synopsys, to upgrade the VMM's capabilities. ( Jason Sprott , Sumit Dhamanwala )

October 7, 2008

#VMM #VERA #SNUG

In this paper, we will demonstrate the use of e verification components (eVCs) in a SystemVerilog/VMM testbench. ( JL Gray, Adiel Khan [Synopsys] )

April 12, 2010

Presentations

#VMM #SPECMAN #SNUG

Presents a case study on how the Open Verification Methodology (OVM) was successfully applied to implement a SystemVerilog simulation-based conformance test environment for next generation FlexRayTM 3.0 Automotive Communications System controllers. ( Mark Litterick )

June 20, 2011

Presentations

#FLEXRAY #OVM #AUTOMOTIVE #VERIFICATIONHORIZONS

Presents a case study on how the Open Verification Methodology (OVM) was successfully applied to implement a SystemVerilog simulation-based conformance test environment for next generation FlexRayTM 3.0 Automotive Communications System controllers. ( Mark Litterick )

June 21, 2011

Presentations

#FLEXRAY #OVM #AUTOMOTIVE

Presents a case study on how the Open Verification Methodology (OVM) was successfully applied to implement a SystemVerilog simulation-based conformance test environment for next generation FlexRayTM 3.0 Automotive Communications System controllers. ( Mark Litterick )

June 22, 2011

Presentations

#FLEXRAY #OVM #AUTOMOTIVE #MENTORU2U

This presentation addresses the requirements for verification of complex FPGAs using a mixture of simulation and design-for-verification approaches to establish correctness of the complex control-based functionality allowing for on-the-bench testing of full operational modes, data and traffic throughput. ( Mark Litterick )

May 22, 2002

Presentations

#FPGA #VERIFICATION #MENTORU2U

NMI Verification Network Event Feb. 2006 ( David Robinson )

February 1, 2006

Presentations

#SPECMAN #NMI

An e-language package that provides some utility macros+methods. ( Thorsten Dworzak )

July 13, 2015

Other Downloads

#SPECMAN #OPENSOURCE #UTILS

svlib is a free, open-source library of utility functions for SystemVerilog. It includes file and string manipulation functions, full regular expression search/replace, easy reading and writing of configuration files, access to environment variables and wall-clock time, and much more. ( Jonathan Bromley , Winkelmann, Andre )

January 4, 2015

Other Downloads

#SYSTEMVERILOG #DVCON_US #OPENSOURCE

This paper proposes a generic window handler as a solution to overcome transaction level checks during windows of time when signal values are hard to predict. ( Jeff Vance )

September 23, 2014

Presentations

#SYSTEMVERILOG #SNUG

A guide for knowledgeable SystemVerilog users who need to use Specman and the e language on their job but already have an understanding of constrained-random verification. ( Thorsten Dworzak )

May 12, 2020

Articles

#SPECMAN #SYSTEMVERILOG

This presentation covers the basics of building a UVM testbench, creating stimulus, creating a register model, and interacting with legacy code. ( Vanessa Cooper )

December 12, 2012

Presentations

#UVM #TUTORIAL #MTV

This paper discusses the existing message handlers in UVM 1.1 and previews the implementation coming in UVM 1.2. ( Gordon McGregor )

September 1, 2013

Presentations

#UVM #SNUG #AWARD