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<channel>
	<title>Verilab Blog</title>
	
	<link>http://www.verilab.com/blog</link>
	<description>Verilab</description>
	<pubDate>Thu, 02 Feb 2012 07:20:55 +0000</pubDate>
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	<language>en</language>
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		<title>Verilab hiring in Austin</title>
		<link>http://feedproxy.google.com/~r/VerilabBlog/~3/-z5Rk81X3uk/</link>
		<comments>http://www.verilab.com/blog/2012/02/verilab-hiring-in-austin/#comments</comments>
		<pubDate>Thu, 02 Feb 2012 07:20:55 +0000</pubDate>
		<dc:creator>JL Gray</dc:creator>
		
		<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://www.verilab.com/blog/?p=154</guid>
		<description><![CDATA[We&#8217;re hiring in Austin. Check out our LinkedIn job advert for details.
]]></description>
			<content:encoded><![CDATA[<p>We&#8217;re hiring in Austin. Check out our <a href="http://www.linkedin.com/jobs?viewJob=&#038;jobId=2456465">LinkedIn job advert</a> for details.</p>
<img src="http://feeds.feedburner.com/~r/VerilabBlog/~4/-z5Rk81X3uk" height="1" width="1"/>]]></content:encoded>
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		<item>
		<title>Verilab at DVCon 2012</title>
		<link>http://feedproxy.google.com/~r/VerilabBlog/~3/ygDCcnB3GoU/</link>
		<comments>http://www.verilab.com/blog/2012/02/verilab-at-dvcon-2012/#comments</comments>
		<pubDate>Thu, 02 Feb 2012 03:11:17 +0000</pubDate>
		<dc:creator>JL Gray</dc:creator>
		
		<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://www.verilab.com/blog/?p=144</guid>
		<description><![CDATA[Come join us at DVCon 2012 in San Jose, CA. Several of us from Verilab will be involved in the following activities:

Monday, February 27 - UVM: Ready, Set, Deploy. Vanessa Cooper presenting.
Tuesday, February 28 - Industry Leaders Panel: The Resurgence of Chip Design. Moderator: JL Gray
Tuesday, February 28 - A 30-Minute Project Makeover Using Continuous [...]]]></description>
			<content:encoded><![CDATA[<p>Come join us at DVCon 2012 in San Jose, CA. Several of us from Verilab will be involved in the following activities:</p>
<ul>
<li>Monday, February 27 - <a href="http://dvcon.org/eventdetails?id=131-2-T">UVM: Ready, Set, Deploy</a>. Vanessa Cooper presenting.</li>
<li>Tuesday, February 28 -<a href="http://dvcon.org/eventdetails?id=131-121"> Industry Leaders Panel: The Resurgence of Chip Design</a>. Moderator: JL Gray</li>
<li>Tuesday, February 28 - <a href="http://dvcon.org/eventdetails?id=131-7">A 30-Minute Project Makeover Using Continuous Integration</a>. JL Gray and Gordon McGregor</li>
</ul>
<p>Verilab will also be sponsoring this year&#8217;s best paper award. We look forward to seeing you there!</p>
<img src="http://feeds.feedburner.com/~r/VerilabBlog/~4/ygDCcnB3GoU" height="1" width="1"/>]]></content:encoded>
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		<item>
		<title>Verilab Canada</title>
		<link>http://feedproxy.google.com/~r/VerilabBlog/~3/OCc-dohHwVI/</link>
		<comments>http://www.verilab.com/blog/2012/01/verilab-canada/#comments</comments>
		<pubDate>Thu, 26 Jan 2012 00:00:46 +0000</pubDate>
		<dc:creator>JL Gray</dc:creator>
		
		<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://www.verilab.com/blog/?p=150</guid>
		<description><![CDATA[Rumor has it we&#8217;ve been staffing a team in Canada with engineers in Ottawa and Montreal. If you&#8217;re interested in joining go ahead and submit an application today!
]]></description>
			<content:encoded><![CDATA[<p>Rumor has it we&#8217;ve been staffing a team in Canada with engineers in Ottawa and Montreal. If you&#8217;re interested in joining go ahead and <a href="http://www.verilab.com/careers/join-us/">submit an application</a> today!</p>
<img src="http://feeds.feedburner.com/~r/VerilabBlog/~4/OCc-dohHwVI" height="1" width="1"/>]]></content:encoded>
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		<item>
		<title>SNUG 2009 Multi-Stream Scenario Paper Now Available</title>
		<link>http://feedproxy.google.com/~r/VerilabBlog/~3/1oRYigV_WZ0/</link>
		<comments>http://www.verilab.com/blog/2009/04/snug-2009-multi-stream-scenario-paper-now-available/#comments</comments>
		<pubDate>Sat, 18 Apr 2009 22:58:10 +0000</pubDate>
		<dc:creator>JL Gray</dc:creator>
		
		<category><![CDATA[News]]></category>

		<category><![CDATA[SystemVerilog]]></category>

		<guid isPermaLink="false">http://www.verilab.com/blog/?p=101</guid>
		<description><![CDATA[Verilab&#8217;s award-winning paper entitled &#8220;Using the New Features in VMM 1.1 for Multi-Stream Scenarios&#8221; is now available for download from the Verilab website.  Please let us know if you have any questions!
]]></description>
			<content:encoded><![CDATA[<p>Verilab&#8217;s award-winning paper entitled &#8220;Using the New Features in VMM 1.1 for Multi-Stream Scenarios&#8221; is now <a href="http://www.verilab.com/resources/papers-and-presentations/#SNUG+2009%3A+Using+the+New+Features+in+VMM+1.1+for+Multi-Stream+Scenarios">available for download</a> from the Verilab website.  Please let us know if you have any questions!</p>
<img src="http://feeds.feedburner.com/~r/VerilabBlog/~4/1oRYigV_WZ0" height="1" width="1"/>]]></content:encoded>
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		<feedburner:origLink>http://www.verilab.com/blog/2009/04/snug-2009-multi-stream-scenario-paper-now-available/</feedburner:origLink></item>
		<item>
		<title>Verilab OCP uVC added to OCP-IP Library</title>
		<link>http://feedproxy.google.com/~r/VerilabBlog/~3/r_hY0tzQAts/</link>
		<comments>http://www.verilab.com/blog/2009/04/verilab-ocp-uvc-added-to-ocp-ip-library/#comments</comments>
		<pubDate>Thu, 16 Apr 2009 20:35:48 +0000</pubDate>
		<dc:creator>Jason Sprott</dc:creator>
		
		<category><![CDATA[News]]></category>

		<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://www.verilab.com/blog/?p=96</guid>
		<description><![CDATA[
Verilab have added their OCP uVC verification component to the OCP-IP Library.


The Verilab OCP uVC is a mixed language verification component for the Open Core Protocol (OCP) implemented using SystemVerilog and e verification languages. It can be used as an Open Verification Methodology (OVM) Verification Component (OVC) in SystemVerilog-only applications without the Specman layer (or [...]]]></description>
			<content:encoded><![CDATA[<p>
Verilab have added their OCP uVC verification component to the <a href="http://www.ocpip.org/library/ip/#Test">OCP-IP Library</a>.
</p>
<p>
The Verilab OCP uVC is a mixed language verification component for the Open Core Protocol (OCP) implemented using SystemVerilog and e verification languages. It can be used as an Open Verification Methodology (OVM) Verification Component (OVC) in SystemVerilog-only applications without the Specman layer (or license), or it can be used in Specman-based verification environments as a regular e Verification Component (eVC).
</p>
<p>
The datasheet for the OCP uVC can be downloaded <a href="http://www.verilab.com/files/vlab_ocp_data_sheet.pdf">here</a></p>
<img src="http://feeds.feedburner.com/~r/VerilabBlog/~4/r_hY0tzQAts" height="1" width="1"/>]]></content:encoded>
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		<feedburner:origLink>http://www.verilab.com/blog/2009/04/verilab-ocp-uvc-added-to-ocp-ip-library/</feedburner:origLink></item>
		<item>
		<title>Verilab OCP article picked up by EDA Designline</title>
		<link>http://feedproxy.google.com/~r/VerilabBlog/~3/2qoSxNFG9sE/</link>
		<comments>http://www.verilab.com/blog/2009/01/verilab-ocp-article-picked-up-by-eda-designline/#comments</comments>
		<pubDate>Tue, 13 Jan 2009 21:01:10 +0000</pubDate>
		<dc:creator>Jason Sprott</dc:creator>
		
		<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://www.verilab.com/blog/?p=89</guid>
		<description><![CDATA[Mark Litterick&#8217;s &#8220;Architecting the OCP uVC verification component&#8221; article written about in a previous blog has also been picked up by EDA Designline
]]></description>
			<content:encoded><![CDATA[<p>Mark Litterick&#8217;s &#8220;Architecting the OCP uVC verification component&#8221; article written about in a previous <a href="http://www.verilab.com/blog/2009/01/littericks-ocp-ip-newletter-article-uses-verilabs-ocp-uvc-vip-as-an-example/trackback/">blog </a>has also been <a href="http://www.edadesignline.com/howto/212900106;jsessionid=OG5DN40HRIFHCQSNDLOSKHSCJUNN2JVN">picked up</a> by <a href="http://www.edadesignline.com/">EDA Designline</a></p>
<img src="http://feeds.feedburner.com/~r/VerilabBlog/~4/2qoSxNFG9sE" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://www.verilab.com/blog/2009/01/verilab-ocp-article-picked-up-by-eda-designline/feed/</wfw:commentRss>
		<feedburner:origLink>http://www.verilab.com/blog/2009/01/verilab-ocp-article-picked-up-by-eda-designline/</feedburner:origLink></item>
		<item>
		<title>Litterick’s OCP-IP newsletter article uses Verilab’s OCP uVC VIP as an example</title>
		<link>http://feedproxy.google.com/~r/VerilabBlog/~3/35nURAeLQ7g/</link>
		<comments>http://www.verilab.com/blog/2009/01/littericks-ocp-ip-newletter-article-uses-verilabs-ocp-uvc-vip-as-an-example/#comments</comments>
		<pubDate>Wed, 07 Jan 2009 12:18:11 +0000</pubDate>
		<dc:creator>Jason Sprott</dc:creator>
		
		<category><![CDATA[Info]]></category>

		<category><![CDATA[News]]></category>

		<category><![CDATA[SystemVerilog]]></category>

		<guid isPermaLink="false">http://www.verilab.com/blog/?p=79</guid>
		<description><![CDATA[Mark Litterick&#8217;s OCP-IP December 2008 newsletter article demonstrates how two key aspects of OCP – profiles and transactions — were adopted as fundamental building blocks for the architecture of a verification component targeted at constrained-random validation of OCP components and systems.
The article uses the Verilab OCP uVC as an example. This uVC is a mixed-language [...]]]></description>
			<content:encoded><![CDATA[<p>Mark Litterick&#8217;s <a href="http://www.ocpip.org">OCP-IP</a> December 2008 newsletter <a href="http://www.verilab.com/files/ocp_newsletter_Dec08_vol7_final.pdf">article </a>demonstrates how two key aspects of OCP – profiles and transactions — were adopted as fundamental building blocks for the architecture of a verification component targeted at constrained-random validation of OCP components and systems.</p>
<p>The article uses the Verilab OCP uVC as an example. This uVC is a mixed-language OCP compliant verification component that supports a major subset of Open Core Protocol Specification 2.2. The OCP uVC is implemented using SystemVerilog and e verification languages and complies with both the Open Verification Methodology (OVM) and e Reuse Methodology (eRM). The verification component can be used in SystemVerilog only applications without the Specman layer (or license), or it can be used in Specman-based verification environments as a regular eVC.</p>
<p>The OCP-IP article can be downloaded <a href="http://www.verilab.com/files/ocp_newsletter_Dec08_vol7_final.pdf">here</a></p>
<p>The full whitepaper can be downloaded <a href="https://www.verilab.com/files/vlab_ocp_whitepaper_Dec08_vol7_full_version_1.pdf">here</a></p>
<img src="http://feeds.feedburner.com/~r/VerilabBlog/~4/35nURAeLQ7g" height="1" width="1"/>]]></content:encoded>
			<wfw:commentRss>http://www.verilab.com/blog/2009/01/littericks-ocp-ip-newletter-article-uses-verilabs-ocp-uvc-vip-as-an-example/feed/</wfw:commentRss>
		<feedburner:origLink>http://www.verilab.com/blog/2009/01/littericks-ocp-ip-newletter-article-uses-verilabs-ocp-uvc-vip-as-an-example/</feedburner:origLink></item>
		<item>
		<title>DAC 2008 Presentations Now Posted</title>
		<link>http://feedproxy.google.com/~r/VerilabBlog/~3/6AfqKaieme0/</link>
		<comments>http://www.verilab.com/blog/2008/07/dac-2008-presentations-now-posted/#comments</comments>
		<pubDate>Wed, 30 Jul 2008 15:37:50 +0000</pubDate>
		<dc:creator>JL Gray</dc:creator>
		
		<category><![CDATA[Conferences]]></category>

		<category><![CDATA[Methodology]]></category>

		<category><![CDATA[News]]></category>

		<category><![CDATA[SystemVerilog]]></category>

		<guid isPermaLink="false">http://www.verilab.com/blog/2008/07/dac-2008-presentations-now-posted/</guid>
		<description><![CDATA[Just a quick FYI&#8230; both David Robinson and I have posted our DAC presentations on Verification Planning and SystemVerilog Interoperability on the Verilab website.  Please check them out and let us know if you have any questions or comments!
]]></description>
			<content:encoded><![CDATA[<p>Just a quick FYI&#8230; both David Robinson and I have posted our DAC presentations on Verification Planning and SystemVerilog Interoperability on the <a href="http://www.verilab.com/resources/papers-and-presentations/">Verilab website</a>.  Please check them out and let us know if you have any questions or comments!</p>
<img src="http://feeds.feedburner.com/~r/VerilabBlog/~4/6AfqKaieme0" height="1" width="1"/>]]></content:encoded>
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		<feedburner:origLink>http://www.verilab.com/blog/2008/07/dac-2008-presentations-now-posted/</feedburner:origLink></item>
		<item>
		<title>Response to Mentor CDC Whitepaper</title>
		<link>http://feedproxy.google.com/~r/VerilabBlog/~3/YAEDI1e7ZxE/</link>
		<comments>http://www.verilab.com/blog/2008/03/mentor-cdc-whitepaper-response/#comments</comments>
		<pubDate>Sat, 22 Mar 2008 20:26:06 +0000</pubDate>
		<dc:creator>Kevin Johnston</dc:creator>
		
		<category><![CDATA[Methodology]]></category>

		<category><![CDATA[News]]></category>

		<guid isPermaLink="false">http://www.verilab.com/blog/2008/03/mentor-cdc-whitepaper-flaws/</guid>
		<description><![CDATA[There was a recent surge of discussions about asynchronous clock domain crossings and metastability handling in Verilab email: Two people asked Mark Litterick essentially the same question just hours apart, and then a day later Jason Sprott noticed a Mentor CDC Verification paper that referenced Mark&#8217;s &#8220;Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and [...]]]></description>
			<content:encoded><![CDATA[<p>There was a recent surge of discussions about asynchronous clock domain crossings and metastability handling in Verilab email: Two people asked Mark Litterick essentially the same question just hours apart, and then a day later Jason Sprott noticed a <a href="http://www.mentor.com/techpapers/fulfillment/upload/mentorpaper_36758.pdf">Mentor CDC Verification paper</a> that referenced <a href="http://www.verilab.com/files/sva_cdc_paper_dvcon2006.pdf">Mark&#8217;s &#8220;Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter using SystemVerilog Assertions,&#8221; paper</a> (Best Paper at DVCon 2006).</p>
<p>One particular statement in the Mentor paper caught my eye: &quot;this model can still generate false errors: the waveforms show that input sequence A, B, C, D, E, F can result in output sequence A, B, E, E, E, where two consecutive inputs, C and D, are skipped&quot;. And this statement bothered me: I had spent a long time figuring out Mark&#8217;s model some while back, and while it was not at all intuitive to me, I did convince myself that it could never generate a simulated output sequence that was impossible in real hardware. So if the Mentor paper was correct, then I had missed something about Mark&#8217;s model, and I&#8217;ll be honest, I didn&#8217;t relish going back and studying it again.</p>
<p>Obviously I was just going to have to find a mistake in the Mentor paper instead. And to my considerable relief, I did. In fact, I found two:</p>
<ol>
<li>The schematic (Fig 8, p.9) of Mark&#8217;s synchronizer model is missing a small but important feature. </li>
<li>The waveform (Fig 9, p.9) of data signal values input to the model is a somewhat misleading representation of an async input. </li>
</ol>
<p><span id="more-63"></span></p>
<p>In the Mentor paper, the select inputs to both muxes are simply &quot;$random()&quot;. In Mark&#8217;s original model (Fig 11, p.5), the select input of the input mux is indeed just &quot;$random()&quot;, but the select input of the output mux is &quot;@(m2 or m3) $random()&quot;.</p>
<p>The result of the modified select term is to make the &quot;A,B,E,E,E&quot; behavior impossible except under specific conditions. But under the right conditions, it is indeed a possible behavior in hardware.</p>
<p>The waveform of the d input signal in Fig 9 of the Mentor paper gives a false impression that d is actually synchronous, rather than asynchronous, to the sampling clock clk. The stability of a transitioning async input cannot be inferred forward or backward from the sampling clock. If two consecutive samples are not equal, it is unknown when the transition occurred - it is only known that a transition occurred. So if the sampled values B, C, D, E in simulation were 0, 1, 1, 0, it is entirely possible for hardware to exhibit the output sequence 0, 0, 0, 0.</p>
<p>The fact that samples C and D were both 1 in simulation does not mean that d was stable for two complete clk periods, as implied in Fig 9: The 0-&gt;1 transition B-&gt;C could have occurred momentarily before the C sampling clock edge, and the 1-&gt;0 transition D-&gt;E could have occurred momentarily after the D sampling clock edge. And if both transitions violated the sampling setup/hold window, then the metastability could settle to the B value at the C clock edge, and the E value at the D clock edge.</p>
<img src="http://feeds.feedburner.com/~r/VerilabBlog/~4/YAEDI1e7ZxE" height="1" width="1"/>]]></content:encoded>
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		<item>
		<title>SystemVerilog Gotcha: (when copying) a struct is not a class by another name</title>
		<link>http://feedproxy.google.com/~r/VerilabBlog/~3/EOQqsnpxYFI/</link>
		<comments>http://www.verilab.com/blog/2008/01/gotcha-when-copying-a-struct-is-not-a-class-by-a-different-name/#comments</comments>
		<pubDate>Sun, 20 Jan 2008 10:24:01 +0000</pubDate>
		<dc:creator>Jason Sprott</dc:creator>
		
		<category><![CDATA[News]]></category>

		<category><![CDATA[SystemVerilog]]></category>

		<guid isPermaLink="false">http://www.verilab.com/blog/2008/01/gotcha-when-copying-a-struct-is-not-a-class-by-a-different-name/</guid>
		<description><![CDATA[SystemVerilog has two &#8220;similar&#8221; data types that allow variables to be grouped together in a handy package: the struct and the class. I&#8217;ve heard it often said, when explaining what a class (an object-oriented data type)  is, that it is just like a C struct with functions. I used to have no problem with [...]]]></description>
			<content:encoded><![CDATA[<p>SystemVerilog has two &#8220;similar&#8221; data types that allow variables to be grouped together in a handy package: the struct and the class. I&#8217;ve heard it often said, when explaining what a class (an object-oriented data type)  is, that it is just like a C struct with functions. I used to have no problem with that, until, when reviewing and debugging testbench code,  I started seeing some problems related to the way classes have to be treated differently to structs. One of the most common errors I&#8217;ve found is when data structures composed of classes are copied. </p>
<p>Consider the following:  <span id="more-62"></span></p>
<pre>
class FooDataClass;
   integer D1;
   integer D2;
endclass

struct {
   integer D1;
   integer D2;
} FooDataStruct;

program test;
   FooDataClass  X[]  = new[5]; // array of classes
   FooDataClass  Y[];           // array of classes
   FooDataStruct A[]  = new[5]; // array of structs
   FooDataStruct B[];           // array of structs
   ...
   Y = X; // copy array of classes
   B = A; // copy array of structs
   ...
endprogram
</pre>
<p>In the case of the struct, it&#8217;s possible to copy the dynamic array A[] to B[], sizing B to the same as A automatically. It&#8217;s equivalent to:	</p>
<pre>
B = new[A.size()];
foreach(A[i]) begin
   B[i].D1 = A[i].D1; // copy value of A[i].D1 to B[i].D1
   B[i].D2 = A[i].D2; // copy value of A[i].D2 to B[i].D2
end
</pre>
<p>Importantly,  B[] has it&#8217;s very own copy of the values of variables D1 and D2 for each element in the array. So, if A[2].D1 was modified, B[2].D1 would not be.</p>
<p>In the case of the class, when we copy the dynamic array X[] to Y[], Y is still sized to the same as X automatically, but something subtly different happens (that often catches people out), with D1 and D2. When arrays of classes are copied, the references (aka handles) to the class are copied, not the values of the class members themselves.  It&#8217;s equivalent to:</p>
<pre>
Y = new[X.size()];
foreach(X[i]) begin
   Y[i] = X[i]; // copy reference to class X[i] into Y[i]
end
</pre>
<p>This means that Y[] does not have its own copy of the values of variables D1 and D2 for each element in the array. If X[2].D1 was modified Y[2].D1 would also be modified. In fact they are the same variable, pointed to by the reference Y[2],  which is equal to X[2]. That&#8217;s, most often times, not the desired behavior of the code. Coding errors like this can be tricky to track down and may stay hidden for some time.</p>
<p>Once you&#8217;ve created a class, people might start using it all over the place. People, who might not have access to modify your class code, only use it. This has an impact on the above mentioned difference between classes and structs. If you want to enable people to make copies of the data values, as opposed to just the references, then you (as the developer of the class), should provide a mechanism to &#8220;deep copy&#8221; the class. So with FooDataClass  we might do:</p>
<pre>
function void FooDataClass::copy(FooDataClass c);
   this.D1 = c.D1;
   this.D2 = c.D2;
endfunction
</pre>
<p>Here we copy the values of another class of the same type into our class. It is now possible to make Y[] have its very own copy of the values of variables D1 and D2 for each element in the array. So, if X[2].D1 was modified, Y[2].D1 would not be. However, we still have to do something different for classes than we do for structs. Something like:</p>
<pre>
// copy of values of values in X[] to Y[]
foreach(X[i]) begin
   Y[i] = new;   // create new instance of the class
   Y[i].copy(X[i]); // copies *values* in class from X to Y
end
</pre>
<p>So, when you are reviewing code, it&#8217;s always prudent to look for places where classes or things containing classes are explicitly or implicitly copied.</p>
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