tag:blogger.com,1999:blog-28406468741609010502026-02-28T19:43:52.723+05:30Verilog Coding Tips and TricksGet interesting tips and tricks in Verilog programmingvipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.comBlogger45110tag:blogger.com,1999:blog-2840646874160901050.post-9123647504430441142020-12-15T09:40:00.000+05:302020-12-15T09:40:17.455+05:30Synthesizable Clocked Square Root Calculator In Verilog    Long back I had shared a Verilog module for finding the square root of a number. This function too was synthesisable, but as it was implemented with a conventional 'for' loop, it was purely combinatorial. If you want to find the square root of a relatively larger number, then the resource usage was very high.    In such cases, it makes sense to use a clocked vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com1tag:blogger.com,1999:blog-2840646874160901050.post-46759376384687951722020-12-14T16:52:00.001+05:302020-12-14T16:52:16.776+05:30Synthesizable Polynomial Equation Calculator in Verilog      A polynomial equation is an equation which is formed with variables, coefficients and exponents. They can be written in the following format:                        y =anxn + an-1xn-1 + ... +a1x + a0 .Here an, an-1  ... , a1 ,a0vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com2tag:blogger.com,1999:blog-2840646874160901050.post-27718897582921621082020-12-13T17:38:00.001+05:302020-12-13T17:38:24.099+05:30Generic Verilog Code for Binary to Gray and Gray to Binary converter     Few years back I had written a 4 bit converter for conversion between Gray and Binary codes. After receiving much positive response I decided to write a generic version of the same.Let me share the codes...Binary to Gray Code Converter://Binary to Gray code Converter//The 'parameter' keyword below is how we give&vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com1tag:blogger.com,1999:blog-2840646874160901050.post-65341316834657840742020-12-12T13:46:00.004+05:302020-12-12T13:46:55.873+05:30Synthesizable Matrix Multiplication in Verilog     Long back I had posted a simple matrix multiplier which works well in simulation but couldn't be synthesized. But many people had requested for a synthesizable version of this code. So here we go.    The design takes two matrices of 3 by 3 and outputs a matrix of 3 by 3. Each element is stored as 8 bits. This is not a generic multiplier, but if vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com0tag:blogger.com,1999:blog-2840646874160901050.post-90633987603816479232020-12-11T13:34:00.001+05:302020-12-11T13:34:53.419+05:30Quaternary Signed Digit (QSD) Based Fast Adder In Verilog     Quaternary Signed Digit is a base-4 number system where a number is represented by one of the following 7 digits : -3,-2,-1,0,1,2,3. The advantage of this number system is that it allows carry free addition, thus speeding up the addition process.    Fast adders based on QSD are typical and there are several papers on this. In this post I have written Verilog vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com0tag:blogger.com,1999:blog-2840646874160901050.post-18058884885769116302017-11-05T15:53:00.000+05:302017-11-05T15:53:24.723+05:30File Reading and Writing(line by line) in Verilog - Part 2 File reading and writing is a very useful thing to know in Verilog. The possibility to read test input values from files, and write output values for later verification makes testbench codes easy to write and understand. There are few ways to read or write files in Verilog. I have already explained one method in my last post, File Reading and Writing in Verilog - Part 1. The method vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com6tag:blogger.com,1999:blog-2840646874160901050.post-38866924842861613212017-11-05T13:36:00.000+05:302017-11-05T13:36:37.806+05:30File Reading and Writing in Verilog - Part 1 File reading and writing is a very useful thing to know in Verilog. The possibility to read test input values from files, and write output values for later verification makes testbench codes easy to write and understand. There are few ways to read or write files in Verilog. So I will explain the whole thing in few different posts. In this first part we will learn the following things, How to vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com1tag:blogger.com,1999:blog-2840646874160901050.post-18644613363104631952017-11-04T13:36:00.001+05:302017-11-04T13:36:32.311+05:30Count the number of 1's in a Binary number - Verilog Implementation with Testbench Suppose you have a binary number, how do you count the number of one's in it? There are more than one way to do it. We will see two ways to do it and compare their performances. Let's take a 16 bit binary number. The output of our design will have a width of 5 bits, to include the maximum value of output, which is 16("10000"). For example, Input = "1010_0010_1011_0010" =>  vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com12tag:blogger.com,1999:blog-2840646874160901050.post-13090820622827314172017-11-03T12:51:00.001+05:302017-11-03T13:03:46.120+05:30Verilog code for Carry Save Adder with Testbench Carry save adder is very useful when you have to add more than two numbers at a time. Normally if you have three numbers, the method would be to add the first two numbers together and then add the result to the third one. This causes so much delay. In this post I have implemented a 4 bit carry save adder which adds three numbers at a time. You might want to see page 1 and 2 of this paper&vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com2tag:blogger.com,1999:blog-2840646874160901050.post-72724924433601321432017-11-03T12:10:00.000+05:302017-11-03T13:16:59.821+05:30Verilog code for Carry Look Ahead adder with Testbench The simplest form of adder is Ripple carry adder. But sometimes we might need adders which are faster than that. That is when Carry look ahead adders come to the rescue. By calculating all the carry's in advance, this type of adder achieves lower propagation delays and thus higher performance. The disadvantage comes from the fact that, as the size of inputs goes beyond 4 bits, the adder vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com3