Technology Simplified

Website is being updated with new UI!

2014-09-03T19:17:00.001+05:30

Hi Everyone,
Pardon me. It took me very long to get back on managing this website. You all during some part of a time in your life, you get so busy that you forget what you actually need to do to keep up.

I am moving whole code database on Github so you all will never face any problem with finding codes. Feel free to follow me on Github for updates.

My Github: https://github.com/prasadp4009

Stay tuned for updates.

Thank you all.

Blu ShopMart

2013-03-19T11:21:00.003+05:30

A Bluetooth and RFID based Shopping trolly concept designed for today's world. If any company wants to have this product, contact me on: prasadp4009@gmail.com

BluHome v1.2: Home Automation with Voice commands using Android and Arduino with Bluetooth

2012-12-27T00:42:00.001+05:30

Hello Everyone,
Here I come with another development in BluHome project. I have added a Speech or Voice command support to it.

So if you say, "turn on the lights" it will switch on the light and "turn on the fan" for fan.
Right now I am using ICS Android. It uses online Google Voice Recognition, but in Jelly Bean 4.2 Google has given Offline Voice Recognition, which will make it fast and easy. Hoping for the best to come...

Let me know the projects you want me to work on. Will work and post them for you.

Mail me on: prasadp4009(AtGmailDotCom)

Home Automation using Android, Bluetooth, AVR.. I call it Jarvis Switch

2012-11-04T22:08:00.000+05:30

Just completed the circuit for Wireless AC device interface to be controlled via bluetooth. Software part is yet to be ready. Will post the Video Soon.. Started feeling like Tony Stark..(a bit though..)

Video is Online..!!.

Designed my Own Oscilloscope using Arduino and GLCD..!!

2012-10-29T18:51:00.000+05:30

Just designed my Oscilloscope as I wished to buy one. Its working Awesome..!! gives all waveforms on GLCD, you can control the Time/Div. Also gives the Peak to Peak voltage.

Will post video soon...!!

VHDL Keyboard and LCD and 7seg project coming.. Keep visiting for updates.

Video:

16x2 LCD Controller in VHDL

2012-10-01T21:40:00.000+05:30

Hello Everybody. The LCD 16x2 code is ready. Just one bug which is still not recognized. You need to program code 2 times on board to see it work. I dont know why its behaving like that.

The text data is stored in a HEX file and is loaded onto the ROM of 32x8 byte size. It can be reconfigured easily.

I will be uploading code in short of time with some new features.

And after that be ready for a BMP decoder. Get ready with your pic to be seen on Monitor via FPGA.

Updated:

I didnt made changes to code, if you program fpga 2 times without turning it off the code works(It worked on my DE1 board)
I have uploaded project compiled for DE1 board, mail me your quiries, and if anyone finds bug in code.

Project zip Download: LCD_TEST.zip

Another VHDL game... PacMan

2012-09-28T23:59:00.002+05:30

Hello Everybody, hope you must have liked the PONG and Alarm Clock codes.

This is another video of PacMan game I designed, with storing the sprite images of fruit and PacMan in ROM and retrieving them accordingly. Heres video of it. Enjoy VHDL.

More Codes ahead.

Keep Following..!!

RTC Clock with Alarm in VHDL

2012-09-20T02:25:00.003+05:30

This is the code for RTC clock with manual setting and Alarm fuction. The video is uploaded on youtube. You can follow it for operation details.

The code is standard with 24MHz input clk. It also has AMPM function which can be set while setting clock. The clock is free running and Alarm can be set on go. It is a new corrected code over Manual Set problem in previous code.

The code files are given below: (The .sof file is precompiled for DE1 board and can be directly programmed to it.)

Project Archieve: DigiClock.zip

Video:

PONG Game in VHDL

2012-09-20T02:10:00.000+05:30

Hello Everybody. So after getting so many requests about PONG, I made it OPEN-SOURCE now. Its my first game and completely working. I have uploaded the video already, you can check it on youtube.

I have compiled the project, for DE1 board users a pre-compiled file is with name Ballm.sof.
All the vhdl files required are given, the system clock frequency is 50MHz. A PLL is used for generation of 25MHz as clock to VGAsync. (I have added modified VGAS_DE2 file for DE2 users whose VGA controller has "blank" pin.)

So Enjoy PONG then. And yes donate me if you like my projects. In India the paypal Donate facility is disabled so you can send on my mail prasadp4009@gmail.com if you wish to.

If you face any problems working with codes, feel free to mail me at prasadp4009@gmail.com

More projects on way.

Enjoy Programming..!!

The game files are as below.

Compiled file for DE1 users: Ballm.sof
Top level entity: PONG.vhd
Component files: sec_clk.vhd, seg7.vhd, manu_clk.vhd
VGAsync files: VGAS_DE2.vhd, VGAS.vhd

Project Zip: Pong.zip

Video:

Additional info about Clock Divider

2012-06-22T15:07:00.001+05:30

Hello Coders.
Its a long time I am posting. Busy in some things actually so didnt got time to update.

Anyway. I am posting this for our fellow coders who were encountering problem while simulating the code.

Problem: Getting slight diffrence in frequency (a bit lower) than desired.

Reason: The reason of this is the propogation delay of logic gates. As we are using adder and comparator in code for dividing frequency. This adds a slight delay at o/p. This can be easily observed in simulator.

Solution: Manipulate your input constant by some factor and simulate till you get desired result as we cant avoid propogation delay.

Hope you got it. If still not, mail me.

August will be a month of New Exciting projects. Includes all Hacking Arduino software. Android programming and VHDL. KEEP CHECKING.....

HAVE A GREAT TIME.

0 to 9999 Up Down Counter with diffrent logic.

2012-01-15T21:09:00.001+05:30

The code is designed using the 'VHDL function' to convert integer to bcd, more specifically binary to bcd.

Features:

Clock based as well as manual count
Up and down count controlled using switch
Push button to count manually
LED to display count mode
Asynchronous reset

Post your comments, queries and suggestions

[Download links for project files are given below]
Check Download Section or download from below.

DE1 complete project: BCDUDOWNCOUNTER.zip

Main entity: bcd_up_down_counter.vhd

Components: manu_clk.vhd
seg7.vhd

Knowing your AVR ATmega or ATtiny microcontroller

2011-12-28T16:16:00.001+05:30

Posting after a long break.

Anyway, I suppose you are a bit familier with microcontrollers and what they do. So this post is all about choosing microcontroller for your project.

See, before selecting any microcontroller you should point out some things:

The pin numbers and device interfaced:

Number of Inputs and Outputs required.
Types of Input and Output. (Analog, PWM, Digital)

       This is the first thing you should check that what kind of sensors you are using, LCDs, Buttons, Speakers etc. This gives you idea about the number of pins required.
       Ex. Say you are using POT as Analog input (1 ADC pin required) and connected it to a Speaker which has PWM as input(1 PWM pin required). For this you can choose ATtiny45 or 85 which has 8 pin interface with 6 pin usable. Theres no need to select ATmega controllers.

   2. The SPEED and POWER funda:

Speed required for your project. Like if it is using math library and you are using Multiplication in your code. You should select the higher speed controllers. For simple button interface any low speed grade controller will work.
Here theres a twist, ATmel provides wide variety in selection of controller. Say your application works on low voltage and you still want speed.
For Ex. If you want a 16MHz at 5v and you buy ATmega8L (L stands for low voltage compaitability). Then you are going to face probelm as ATmega8 supports 16MHz at 5v. But ATmega8L supports only 12MHz at 5v and 8 MHz at 3.3v. And also ATmega8 dont work at 3.3v logic.

        Another example say you want 16MHz at 3.3v then theres another child in ATmega8 family i.e. ATmega8A (A for Advanced(may be :P)) which works at 16MHz and at 3.3v logic.

So before selecting and buying microcontrollers just go to ATmel site check all the datasheets for the childs of family and you will be able to select perfect one for your project.

One more thing to be noted is, when you buy a uC it comes with 1MHz internal clock pre-programmed. So, if you want to use 8MHz internal RC oscillator you have to set the fuses of uC. Similary for external crystal too.

    3. Another is SPACE:

       Here we concider 3 main Memories.

FLASH
EEPROM
SRAM

Flash memory for your program size. If its big try to optimize it first. If doesnt reduce further dont worry ATmel developed some fat babies like ATmega128 or ATmega256 for that.

EEPROM memory. If you are reusing too much data and storing it again you should keep check on the amount of data you are using and then the EEPROM to store it. (Use EEPROM only when you are storing Database values as the memory access time is higher.)

SRAM. If you dealing with big Strings or Floating point numbers choose the uC who have enough RAM to process your data readily.

SO thats all about Selection. We will start work Shortly. Till then Enjoy..!! :)

VHDL Tutorials

2011-11-10T10:56:00.001+05:30

Hello Coders. I am uploading a step by step tutorials for VHDL and working with Altera boards.. Which includes basic projects from this site.. Compiling them.. Using onboard components..

Do check them out on my youtube page.

Here's the link for Tutorial Playlist: http://www.youtube.com/watch?v=x3sgK2HuCQg

Suggest any modifications. I am going slow at some starting so everyone gets in phase easily.

Mail your Queries @: prasadp4009@gmail.com

Universal VGA Timing and Synchronizing Code

2011-10-03T01:48:00.000+05:30

I have just found this code which is used by Columbia University Students in their projects. i would like to share it with you.

It works probably with all Terasic Altera FPGA boards, Xilinx FPGA boards etc.
The code is predesigned concidering 640x480 VGA resolution at 60Hz. But you can easily modify it using the VGA timing information from the site specified.

Here are the links:

For VGA timing : http://martin.hinner.info/vga/timing.html
VGA_Timing.vhd : http://www.4shared.com/file/wdYoDlvR/vga_timing.html

Don't forget to vote on polls. Mail me if you have any querries or want to do project at prasadp4009@vhdlcodes.com or prasadp4009@gmail.com.

Enjoy Programming..!!

New Videos Check them Out..!!

2011-09-03T09:39:00.000+05:30

Mail me if you have any querries: prasadp4009@gmail.com

The First Video is: Digital Alarm Clock

2) Calculator using 16x2 LCD and Keyboard:

3) PONG GAME:

4) Mario Bouncing on monitor;

Frequency counter in VHDL (Synthesizeble)

2011-05-19T12:25:00.004+05:30

Its Done...!! The Frequency Counter or Measurer is ready. You can measure any I/P frequency from 3Hz to 95KHz i.e. (95,000 Hz for DE1 board Cyclone II FPGA).(This can be diffrent for difrent FPGAs according to their propogation delays and other time factors). Above this value the FPGA gets unstable and show at-random values.

There are 3 levels of Accuracy

Hz.
(displayed value) x 10 Hz.
(displayed value) x 100 Hz.

I have put a reset button, which is Pushbutton when clicked initiate the frequency measurement process. It then holds the value for user to read.

Right now the free-reading i.e. without any initialization, feature is not added. I will add that soon.

Now, working with code :-

To make the code easy I have used my 0 to 9999 counter code and just made some small changes in it. The Clk freq used is 24MHz.

I created 4 files likewise,

freqcount.vhd (Top-level Entity)
sec_clk.vhd (To generate the time window, which is used for accuracy)
sec_clktry.vhd (Here I added this file for demo so as to generate frequency in circuit itself)
seg7.vhd (Integer to 7-seg converter)
freqcount.sof (Quartus II file only for DE1 board)

Now, if you are measuring freq. which is below 9999 then follow the steps.

In sec_clk.vhd file, keep the max_count=48000000.
This will generate a 2 sec window (As i/p clock freq is 24MHz) in which the First second will be High i.e. '1' and Another second will be '0'.
So the code I designed it as, when there is high i.e. '1' then for the i/p of freq to be measured for every high of that freq there is a count.
When the time window goes to Low level i.e. '0' the counting stops. The counted value is then displayed on Seven seg and is in Hz.
If you have querries about how I generated the time window check my Clock Divider project here.
To generate any freq to be measured follow the formula given below:

The time window is of 1 sec i.e. as the i/p clock is of 24MHz i.e.(24000000Hz) then for generation of 1 sec it should count till 24000000. Now say you want to generate freq of 90 Hz then,

replace the max_count value in sec_clktry by

max_count = 24000000/(freq you want at o/p)

max_count = 24000000/90

Then, max_count = 266666.66

Put max_count = 266666 in sec_clktry for 90Hz freq.

Now, when you run the code then the sec_clktry freq will be given to freq counter and it then gives you at o/p.

If you want to measure any external freq. Then comment out the clki signal and sec_clktry component and portmap in architecture. And re instantiate the clki i/p in entity ports.

Now for measuring freq more than 9999 just change the value of max_count in sec_clk as follows,

For freq x 10Hz accuracy, change max_count = 4800000 in sec_clk.vhd (This will generate 0.2 sec window).
For freq x 100 Hz accuracy, change max_count = 480000 in sec_clk.vhd (This will generate 0.02 sec window).

I soon will upload video with full description. If you have any querries mail me at

prasadp4009@gmail.com

prasadp4009@vhdlcodes.com

Download links:

freqcount.vhd
sec_clk.vhd
sec_clktry.vhd
seg7.vhd
freqcount.sof (For DE1 board only,Clock freq is 24MHz and I/P freq to be measured is set at 93hz. i.e. max_count in sec_clktry is 258064.)

Enjoy Programming...!! Keep looking, more projects on way.

Video:

Initializing M4K blocks for RAM. (For Altera FPGA users)

2011-03-10T21:24:00.003+05:30

Hello Everybody.

It seems you are having problem about how to initialize on-board memory using Megafunction Library and M4K blocks. (I am using Quartus II 10.1 SP1, but procees will be similar all other versions)

So here are the steps of the solution:

Start Quartus II and open new project.

Open the MegaFunction Wizard

Select the 'Create New megaFunction' Option

Select the Memory Compiler from list

Select RAM 1 Port and give name to output file

After clicking Next, select the no. of bits per block (In this case its 4 bits)

Select no. of words or blocks of 4-bits you want (In this case 32 blocks, I use 'blocks' though 'words' is proper term)

Select the memory block type as M4K (It doesnt matter if you keep that Auto)

Click Next. Dont change anything on this page

Now select the second option if you want to enter data in memory before programming

To create hex file keep the MegaFunction window as it is and click on the File>New>Intel-hex File in Quartus II window

Then make the proper changes in words and wordsize field

Add whatever data you want in the respective blocks (It will only take a 4 bit no. as we have set the word size as 4)

Save the file be any relevant name you want and then open the MegaFunction window and select the file

Click Next till you get the this window and select the Instantiation file option

Click finish and then open the Instantiation and Component file from File>Open>(Your destination of project)>*_inst.vhd and *.cmp

Then add the Code as follows and make necessary changes to the Port Map field as per your project specifications

If you want to, then you can follow the process rather can use the process with my SRAM interface example project. It will make you more perfect. You can check necessary changes required for my project in .vhd file I attached. Mail me your querries or suggestions on prasadp4009@gmail.com

Enjoy programming...!!

Interfacing (RAM) Onboard M4K memory blocks of Cyclone II Altera De1 board

2011-02-14T10:51:00.005+05:30

This code shows how to store or interface the SRAM with any of your code. You can integrate this code in your projects for storing data. I will upload the interface of RAM with RTC code I designed for storing Date.

In this code I used the on-board M4K memory blocks on Altera DE1 board as RAM in 32 words i.e. 32 address locations of 4-bit. The RAM is initialized through Altera's MegaFunction IP Library. Comment if you don't know how to initialize RAM on any Altera board. I stored some variables like 2,4,6,8 on some starting locations to check if its working. I also added feature of manual address incrementation and data i/p.

For manual data entry you have to use four switches on Altera De1 board viz.

SW0 --LSB
SW1
SW2
SW3 --MSB

To write data press KEY3 and to increment address location press KEY0.

Read operation will be done Automatically, as I have interfaced the BCD to 7SEG (modified seg7.vhd in my previous posts) decoder directly to data out of RAM. You will get to see the stored digit on 7Seg display no.1.

You can directly interface the write enable, I/P and O/P of data and address in your code with only some minor changes.

If you have any qurries feel free to Comment directly on post instead of mailing me so other people will also get some help from it. You still can mail me your querries and Ideas at prasadp4009@gmail.com.

Download liks:

Main Entity sram_test.vhd : sram_test.vhd
Altera DE1 Quartus .sof file : sram.sof
Megafunction file : srm.vhd
Seg7 modified : seg7.vhd

Video:

RTC on FPGA with manual set synthesizeble VHDL code.

2011-01-24T02:37:00.007+05:30

Hey there, cheers to VHDL. I successfully added manual set feature in my previous RTC project. I am not going to copy whole code here. I am just adding the links of .vhd files. I also added the pre-compiled .sof file only for DE1 boards. There is a very small bug that while clicking the set button to enable min and hr set, it increments the hr or min value unintentionally. Else everything is working great.

(Input freq 24MHz., top-level entity DigiClock)

On DE1 board: Push button functions.

Key0: Reset
Key1: Hour set (Key3 kept pressed)
Key2: Minute set (Key3 kept pressed)
Key3: Set enable.

Download links:

DigiClock.sof --DE1 board .sof file
DigiClock.vhd
manu_clk.vhd
sec_clk.vhd
min_clk.vhd
seg7.vhd
DigicClock.pof --DE1 board only (ActiveSerial Prog. file with EPCS4 device selected)

Video :

Do test the codes. If you have any querries do comment or mail me at prasadp4009@gmail.com.

Enjoy Programming..!!

Display on VGA Monitor by FPGA(VHDL code Synthesizable, 640X480 resol, 60Hz)

2010-11-11T09:12:00.004+05:30

This code is for displaying a simple ball bouncing on your monitor screen. As the monitor requires 60 Hz refresh rate i.e. to replace each pixel 60 times, it requires approx 40 ns. So to synchronize it with the FPGA processing speed, I used PLL with 50 MHz i/p clock dividing it to 25 MHz which scans each pixel in 40 ns.

The Video Synchronization file I created is VGAS which has 5 o/ps viz.

red_out
green_out
blue_out
horiz_sync_out
vert_sync_out

These are connected to the VGA controller which must have be present on your FPGA board (present on all DE series board of Altera, I dont know about Xilinx).
For the pins check the your board manual.

The VGAS.vhd file can be used as common file for all your FPGA projects(for dividing 50Hz clock as I have used PLL which is already present on DE1 board. So if you have DE1 board its well and good you can directly use the code with the syncclk.vhd included. If dont just a minor modification in i/p clock signal with 25MHz in VGAS.vhd and removing syncclk.vhd and its component in VGAS.vhd will work.)

The Ballm.vhd is used to create display on Monitor. For DE1 users you can diretly program the SOF file i hav provided in download links.

Post your replies and comments. For the projects or querries you have you can mail me on prasadp4009@gmail.com .

Be the follower, if you like my posts.

Enjoy programming.

Video link: http://www.youtube.com/watch?v=QcCdkWG-rmM

Download links for files:

http://www.4shared.com/file/_7V3nyj9/Ballm.html
http://www.4shared.com/file/8pE2Yhz2/Ballm.html
http://www.4shared.com/file/mqnCQJs0/sycclk.html
http://www.4shared.com/file/JsUb67B4/VGAS.html

Synthesizable RTC in VHDL

2010-09-05T14:49:00.006+05:30

The code given is only for clock digit incrementation. For components in clock like min_clk and sec_clk, refer my previous codes.

VHDL code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clk12 is
port(
      clk: in std_logic;
      rst: in std_logic;
      op: out std_logic;
      op0,op1,op2,op3: out std_logic_vector(6 downto 0)
      );

end clk12;

architecture clock of clk12 is

component sec_clk
Port (
           clk : in std_logic;
           op : out std_logic
     );
    end component;

component min_clk
Port (
           clk : in std_logic;
           rst : in std_logic;
           op : out std_logic
     );
    end component;


component seg7
port(m: in integer range 0 to 10;
     num: out std_logic_vector(6 downto 0));
end component;

signal flag: std_logic;
signal sflag: std_logic;

signal a: integer range 0 to 10;
signal b: integer range 0 to 6;
signal c: integer range 0 to 10;
signal d: integer range 0 to 3;

begin

c1: sec_clk port map(clk,sflag);
c2: min_clk port map(sflag,rst,flag);
op<=sflag;

process(flag,rst)

variable m0: integer range 0 to 10:=0;
variable m1: integer range 0 to 6:=0;
variable m2: integer range 0 to 10:=2;
variable m3: integer range 0 to 3:=1;

begin
     a<=m0;
     b<=m1;
     c<=m2;
     d<=m3;
     if rst='0' then
     m0:=0;
     m1:=0;
     m2:=2;
     m3:=1;
     elsif rising_edge(flag) then
     if m0/=9 then
        m0:= m0+1;
        elsif m0=9 and m1/=5 then
        m0:=0;
        m1:= m1+1;
        elsif m0=9 and m1=5 and m2/=9 and m3=0 then
        m0:=0;
        m1:=0;
        m2:= m2+1;
        elsif m0=9 and m1=5 and m2=9 and m3=0 then
        m0:=0;
        m1:=0;
        m2:=0;
        m3:=1;
        elsif m3=1 and m2/=2 and m1=5 and m0=9 then
        m2:= m2+1;
        elsif m3=1 and m2=2 and m1=5 and m0=9 then
        m0:=0;
        m1:=0;
        m2:=1;
        m3:=0;
        end if;
        end if;

    end process;

    z0: seg7 port map(a,op0);
    z1: seg7 port map(b,op1);
    z2: seg7 port map(c,op2);
    z3: seg7 port map(d,op3);

end clock;

Note: The clock cant be set manually. It starts from 12:00. I tried my best to add the manual set function but didnt succeed. But I assure that manual set will also be there in couple of time. Suggetions are most welcome.

Video link: http://www.youtube.com/watch?v=1dbTi2PMgcU

Quartus SOF file for DE1 board only: Digiclk(for DE1 board only).SOF

Check the new code with hr and min manual set: RTC with maual set

Enjoy Programming.

0 to 9999 bcd counter on seven segment(VHDL code) Synthesizeble

2010-08-06T13:48:00.003+05:30

--Note: while building Project do include sec_clk and seg7 files which i posted

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;

entity c09 is
port( rst,clk: in std_logic;
      op0,op1,op2,op3: out std_logic_vector(6 downto 0));
end c09;

architecture count of c09 is

component sec_clk
Port (
           clk             : in std_logic;
           rst : in std_logic;
           op : out std_logic
           );
    end component;

component seg7
port(m: in integer range 0 to 15;
     num: out std_logic_vector(6 downto 0));
end component;

signal flag: std_logic;
signal a: integer range 0 to 10;
signal b: integer range 0 to 10;
signal c: integer range 0 to 10;
signal d: integer range 0 to 10;
begin

c1: sec_clk port map(clk,rst,flag);

process(rst,flag)
variable m0: integer range 0 to 10:=0;
variable m1: integer range 0 to 10:=0;
variable m2: integer range 0 to 10:=0;
variable m3: integer range 0 to 10:=0;

begin

if rst='0' then
m0:=0;
m1:=0;
m2:=0;
m3:=0;
elsif flag'event and flag='1' then
a<=m0;
b<=m1;
c<=m2;
d<=m3;
if m0 /= 9 then
m0:= m0 + 1;
elsif m0=9 and m1 /= 9 then
m0:=0;
m1:= m1 + 1;
elsif m1=9 and m2 /= 9 and m0=9 then
m1:=0;
m0:=0;
m2:= m2 + 1;
elsif m2=9 and m3/= 9 and m0=9 and m1=9 then
m1:=0;
m0:=0;
m2 :=0;
m3 := m3 + 1;
elsif m3=9 then
m0:=0;
m1:=0;
m2:=0;
m3:=0;
end if;
end if;

end process;

z0: seg7 port map(a,op0);
z1: seg7 port map(b,op1);
z2: seg7 port map(c,op2);
z3: seg7 port map(d,op3);

end count;

here is my youtube video of above project: http://www.youtube.com/watch?v=RrPzS5FLz3k

bcd to seven seg decoder (modified using integer data type) in vhdl(synthesizable)

2010-08-06T10:17:00.003+05:30

This code is generally used as component:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity seg7 is

port(m: in integer range 0 to 15; -- m is decleared as INTEGER
num: out std_logic_vector(6 downto 0));
end seg7;

architecture s7 of seg7 is
begin
process(m)
begin
case m is
when 0 => num<="1000000";
when 1 => num<="1111001";
when 2 => num<="0100100";
when 3 => num<="0110000";
when 4 => num<="0011001";
when 5 => num<="0010010";
when 6 => num<="0000010";
when 7 => num<="1111000";
when 8 => num<="0000000";
when 9 => num<="0010000";
when 10 => num<="0001000"; -- hex(a)
when 11 => num<="0000011"; -- hex(b)
when 12 => num<="1000110"; -- hex(c)
when 13 => num<="0100001"; -- hex(d)
when 14 => num<="0000110"; -- hex(e)
when 15 => num<="0001110"; -- hex(f)
when others=> num<="1111111";
end case;
end process;
end s7;

bcd to seven seg decoder in vhdl(synthesizable)

2010-08-06T10:15:00.003+05:30

library ieee;
use ieee.std_logic_1164.all;

entity seg7 is

port(m: in std_logic_vector(3 downto 0);
num: out std_logic_vector(6 downto 0));
end seg7;

architecture sseg of seg7 is
begin
process(m)
begin
if(m="0000") then
num<="1000000";
elsif(m="0001") then
num<="1111001";
elsif(m="0010") then
num<="0100100";
elsif(m="0011") then
num<="0110000";
elsif(m="0100") then
num<="0011001";
elsif(m="0101") then
num<="0010010";
elsif(m="0110") then
num<="0000010";
elsif(m="0111") then
num<="1111000";
elsif(m="1000") then
num<="0000000";
elsif(m="1001") then
num<="0010000";
else
num<="1111111";
end if;
end process;
end sseg;

VHDL code for Clock Divider

2010-08-06T10:12:00.006+05:30

This is a clock divider code, just set the max-count value as per your requirenment.

For ex. If I want 1Hz freq. set the max count to i/p freq value viz.
1sec = 1Hz
Then, to get time period of 1sec i.e. 1 Hz frequency set max-count to 240000 as shown below:

1sec = 24000000 -- for i/p frequency of 24 MHz.

To get your desired frequency just calculate the maxcount with the formula given below:

max_count = 24000000 * (1/your required frequency)

CODE:

library IEEE;

 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.numeric_std.all;

 entity clk_div is
    Port (
          Clk   : in std_logic;
          rst   : in std_logic;
          op    : out std_logic
    );
 end clk_div;


 architecture behavioral of clk_div is

    constant max_count : natural := 24000000;

-- I used 24MHz clock

  

 begin

  process(Clk,rst)
        variable count : natural range 0 to max_count;

    begin

        if rst = '0' then
            count := 0;
            op    <= '1';
        elsif rising_edge(Clk) then
            if count < (max_count/2)-1 then
                op    <='1';
                count := count + 1;
            elsif count < max_count-1 then
                op    <='0';
                count := count + 1;
            else
                count := 0;
                op    <='1';
            end if;
     end if;

  end process;

 end behavioral;