VHDL coding tips and tricks

Extension of Digital Clock Project with 7 segment Decoder

2022-04-05T13:22:00.003+05:30

In the last post I shared a Digital Clock VHDL code with you along with its testbench. Even though it was synthesizable, it would have been a bit cumbersome to test it on a FPGA board as it was. Because the timer outputs were of unsigned type, you would need to use LED's or something like that to see the time. But who would want a LED digital clock!?

Many FPGA boards have 7 segment displays in them. And this post is to take advantage of such boards. We will take the initial steps to display the time on 7 segment displays. Of course the codes here would need some additional modifications, based on the type of 7 segment displays available on the board and if they share a common bus etc.. But as I mentioned, this is just an initial step.

Without further ado, let me share the codes with you. I have commented the codes plus have uploaded an YouTube video explaining the code. If its useful to you in some way please like and comment on the video. As this helps me with the future direction this blog/YouTube channel will take.

Digital Clock: digital_clock.vhd

You can get it from my last post: Digital Clock VHDL code

Binary to BCD Converter: bin2bcd.vhd

--Library declaration
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

--Binary to BCD Converter
entity bin2bcd is
port(	binary_in : in unsigned(5 downto 0);
	bcd_out : out unsigned(7 downto 0)	--8 bits(4 bits each for 2 digits)
	);
end bin2bcd;

architecture Behavioral of bin2bcd is

--actual value=0.0001100110011001101, so divide by 2^19.
constant one_by_ten : unsigned(15 downto 0) := "1100110011001101"; 
signal result_div_by_ten : unsigned(21 downto 0);
signal msb_digit : unsigned(3 downto 0);

begin

--divide the input by 10. In VHDL, division by a constant is 
--easily done by multiplication by its inverse.
result_div_by_ten <=  binary_in*one_by_ten;	
--get the decimal part of the result. Bits 18:0 are fractional part
msb_digit <= '0' & result_div_by_ten(21 downto 19);	
bcd_out(7 downto 4) <= msb_digit;	--assign it to MSB part of output 
--subtract the product, 10*msb_digit, from the input binary number to get LSB digit.
bcd_out(3 downto 0) <= to_unsigned(to_integer(binary_in) - to_integer(msb_digit)*10, 4);  

end Behavioral;

Top Module: digital_clock_topmodule.vhd

--Libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

--Top module which instantiates and connect together the 3 components:
--Digital clock, Binary to BCD converter, BCD to 7 segment code converter
entity digital_clock_topmodule is
 --frequency of the clock passed as a generic parameter.
generic( 
		CLOCK_FREQ : integer := 50000000
		); 
port(	
		Clock : in std_logic;  --system clock
		reset : in std_logic;  --resets the time
		inc_secs : in std_logic;  --set a pulse here to increment the seconds by 1.
		inc_mins : in std_logic;  --set a pulse here to increment the minutes by 1.
		inc_hrs : in std_logic;  --set a pulse here to increment the hours by 1.
		secs_7seg1 :out unsigned(6 downto 0);  --seconds LSB digit
		secs_7seg10 :out unsigned(6 downto 0);  --seconds MSB digit
		mins_7seg1 :out unsigned(6 downto 0);  --minutes LSB digit
		mins_7seg10 :out unsigned(6 downto 0);  --minutes MSB digit
		hrs_7seg1 :out unsigned(6 downto 0);  --hours LSB digit
		hrs_7seg10 :out unsigned(6 downto 0)  --hours MSB digit
		);
end digital_clock_topmodule;

architecture Behavioral of digital_clock_topmodule is

	--Digital clock component
	COMPONENT digital_clock
	GENERIC( CLOCK_FREQ : integer := 50000000);
	PORT(
		Clock : IN  std_logic;
		reset : IN  std_logic;
		inc_secs : IN  std_logic;
		inc_mins : IN  std_logic;
		inc_hrs : IN  std_logic;
		seconds : OUT  unsigned(5 downto 0);
		minutes : OUT  unsigned(5 downto 0);
		hours : OUT  unsigned(4 downto 0)
		);
	END COMPONENT;
	 
	--Binary to BCD converter component
	COMPONENT bin2bcd is
	PORT(
		binary_in : in unsigned(5 downto 0);
		bcd_out : out unsigned(7 downto 0)
		);
	END COMPONENT;
	
	--Function to convert a BCD digit into a 7 segment code
	--Source: https://vhdlguru.blogspot.com/2010/03/vhdl-code-for-bcd-to-7-segment-display.html
	--The function is created by converting the code from the above link.
	function bcd2seg7(bcd_in : unsigned(3 downto 0)) return unsigned is
		variable segment7 : unsigned(6 downto 0);
	begin
		case bcd_in is
			when "0000"=> segment7 :="0000001";  -- '0'
			when "0001"=> segment7 :="1001111";  -- '1'
			when "0010"=> segment7 :="0010010";  -- '2'
			when "0011"=> segment7 :="0000110";  -- '3'
			when "0100"=> segment7 :="1001100";  -- '4'
			when "0101"=> segment7 :="0100100";  -- '5'
			when "0110"=> segment7 :="0100000";  -- '6'
			when "0111"=> segment7 :="0001111";  -- '7'
			when "1000"=> segment7 :="0000000";  -- '8'
			when "1001"=> segment7 :="0000100";  -- '9'
			 --nothing is displayed when a number more than 9 is given as input.
			when others=> segment7 :="1111111";
		end case;
		return segment7;
	end bcd2seg7;
	
	
	--Declare internal signals	
	signal seconds : unsigned(5 downto 0);
	signal minutes : unsigned(5 downto 0);
	signal hours : unsigned(4 downto 0);
	signal bcd_secs,bcd_mins,bcd_hrs : unsigned(7 downto 0);
	signal hours_extended : unsigned(5 downto 0);

	
begin

-- Instantiate the Digital Clock component
	uut: digital_clock 
		GENERIC MAP(CLOCK_FREQ => CLOCK_FREQ)
		PORT MAP (
			Clock => Clock,
			reset => reset,
			inc_secs => inc_secs,
			inc_mins => inc_mins,
			inc_hrs => inc_hrs,
			seconds => seconds,
			minutes => minutes,
			hours => hours
			);

	--convert binary to BCD for seconds
	bin2bcd_secs : bin2bcd 
		port map(
			binary_in => seconds,
			bcd_out => bcd_secs
			);

	--convert binary to BCD for minutes
	bin2bcd_mins : bin2bcd 
		port map(
			binary_in => minutes,
			bcd_out => bcd_mins
			);

	hours_extended <= '0' & hours;	--just make it the same size as seconds and minutes.
	--convert binary to BCD for hours
	bin2bcd_hrs : bin2bcd 
		port map(
			binary_in => hours_extended,
			bcd_out => bcd_hrs
			);
			
	--Call the bcd2seg7 function to convert each BCD digit into a

  --format which can be used on the 7 segment display
	secs_7seg1 <= bcd2seg7(bcd_secs(3 downto 0));
	secs_7seg10 <= bcd2seg7(bcd_secs(7 downto 4));
	mins_7seg1 <= bcd2seg7(bcd_mins(3 downto 0));
	mins_7seg10 <= bcd2seg7(bcd_mins(7 downto 4));
	hrs_7seg1 <= bcd2seg7(bcd_hrs(3 downto 0));
	hrs_7seg10 <= bcd2seg7(bcd_hrs(7 downto 4));

end Behavioral;

Testbench for the top module: tb_digitalClock_topModule.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
--the below library is used for finishing the simulation after we are done.

--Otherwise it will run continously.
library std;
use std.env.finish;
 
ENTITY tb_digitalClock_topModule IS
END tb_digitalClock_topModule;
 
ARCHITECTURE behavior OF tb_digitalClock_topModule IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT digital_clock_topmodule is
	 --frequency of the clock passed as a generic parameter.
		generic( 
			CLOCK_FREQ : integer := 50000000
			); 
		port(	
			Clock : in std_logic;  --system clock
			reset : in std_logic;  --resets the time
			inc_secs : in std_logic;  --set a pulse here to increment the seconds by 1.
			inc_mins : in std_logic;  --set a pulse here to increment the minutes by 1.
			inc_hrs : in std_logic;  --set a pulse here to increment the hours by 1.
			secs_7seg1 :out unsigned(6 downto 0);  --seconds LSB digit
			secs_7seg10 :out unsigned(6 downto 0);  --seconds MSB digit
			mins_7seg1 :out unsigned(6 downto 0);  --minutes LSB digit
			mins_7seg10 :out unsigned(6 downto 0);  --minutes MSB digit
			hrs_7seg1 :out unsigned(6 downto 0);  --hours LSB digit
			hrs_7seg10 :out unsigned(6 downto 0)  --hours MSB digit
			);
		end COMPONENT;    

   --Inputs
   signal Clock : std_logic := '0';
   signal reset : std_logic := '0';
   signal inc_secs : std_logic := '0';
   signal inc_mins : std_logic := '0';
   signal inc_hrs : std_logic := '0';

 	--Outputs
   signal secs_7seg1,secs_7seg10 : unsigned(6 downto 0);

   signal mins_7seg1,mins_7seg10 : unsigned(6 downto 0);

   signal hrs_7seg1,hrs_7seg10 : unsigned(6 downto 0);

   -- Clock period definitions
   constant Clock_period : time := 10 ns;
	
	--Clock frequency in Hz. Use a smaller value for testbench.

  --When testing on board it need to be set as 50 million, 100 million etc.
	constant CLOCK_FREQ : integer := 10;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: digital_clock_topmodule 
		GENERIC MAP(CLOCK_FREQ => CLOCK_FREQ)
		PORT MAP (
          Clock => Clock,
          reset => reset,
          inc_secs => inc_secs,
          inc_mins => inc_mins,
          inc_hrs => inc_hrs,
          secs_7seg1 => secs_7seg1,
			 secs_7seg10 => secs_7seg10,
			 mins_7seg1 => mins_7seg1,
			 mins_7seg10 => mins_7seg10,
			 hrs_7seg1 => hrs_7seg1,
			 hrs_7seg10 => hrs_7seg10
        );

   -- Clock process definitions
   Clock_process :process
   begin
		Clock <= '0';
		wait for Clock_period/2;
		Clock <= '1';
		wait for Clock_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
		reset <= '1';
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		reset <= '0';
      wait for Clock_period*CLOCK_FREQ*60*60*25;  --run the clock for 25 hours
		
		--increment seconds
		inc_secs <= '1';	wait for Clock_period;
		inc_secs <= '0';

    wait for Clock_period*CLOCK_FREQ*5;	--wait for 5 secs after incrementing seconds once.
		
		--increment seconds 60 times
		inc_secs <= '1';	wait for Clock_period*60;
		inc_secs <= '0';

    wait for Clock_period*CLOCK_FREQ*5;	--wait for 5 secs after incrementing seconds.
		
		--increment minutes
		inc_mins <= '1';	wait for Clock_period;
		inc_mins <= '0';

    wait for Clock_period*CLOCK_FREQ*5;	--wait for 5 mins after incrementing minutes once.
		
		--increment minutes 60 times
		inc_mins <= '1';	wait for Clock_period*60;
		inc_mins <= '0';

    wait for Clock_period*CLOCK_FREQ*5;	--wait for 5 mins after incrementing minutes.
		
		--increment hours
		inc_hrs <= '1';	wait for Clock_period;
		inc_hrs <= '0';

    wait for Clock_period*CLOCK_FREQ*5;	--wait for 5 hours after incrementing hours once.
		
		--increment hours 25 times
		inc_hrs <= '1';	wait for Clock_period*25;
		inc_hrs <= '0';

    wait for Clock_period*CLOCK_FREQ*5;	--wait for 5 hours after incrementing hours.
		
		--apply reset
		reset <= '1';
		
		--wait for 100 Clock cycles and then finish the simulation.
		--with the current settings it will run around 9 ms of simualtion time. 
		wait for Clock_period*100;
		finish;  
   end process;

END;

Top Level Block Diagrams:

The code was synthesized in Xilinx ISE 14.7. And the top level block diagram is shown below:




The inside view of the top module looks like this:

Digital Clock (With ability to Set time) And Testbench in VHDL

2022-04-03T11:58:00.000+05:30

More than a decade back I had written a Digital Clock module in this blog, which was when I just started learning VHDL. Obviously it had its own shortcomings and through this post, I wanted to rectify these shortcomings. Plus add the ability to set time.

The codes are shared below. They are commented to help you understand the logic. For a detailed understanding watch the video. Also please make sure to like the video if it was helpful and subscribe to my YouTube channel for more such videos in the future.

Digital Clock:

--Declare the libraries
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;  --we need this one because we are using "unsigned" data type.


entity digital_clock is
 --frequency of the clock passed as a generic parameter.
generic( CLOCK_FREQ : integer := 50000000	); 
port(	
		Clock : in std_logic;  --system clock
		reset : in std_logic;  --resets the time
		inc_secs : in std_logic;  --set a pulse here to increment the seconds by 1.
		inc_mins : in std_logic;  --set a pulse here to increment the minutes by 1.
		inc_hrs : in std_logic;  --set a pulse here to increment the hours by 1.
		seconds :out unsigned(5 downto 0);  --seconds output
		minutes :out unsigned(5 downto 0);  --minutes output
		hours :out unsigned(4 downto 0)  --hours output
		);
end digital_clock;

architecture Behavioral of digital_clock is

--temperory signals as we cant directly perform arithmetic operations on outputs
signal secs, mins, hrs : integer := 0;

--counter used for getting the 1 sec duration from the system Clock.
signal counter : integer := 0;  

begin

process(Clock, reset)
begin
	if(reset = '1') then	--reset the time.
		secs <= 0;
		mins <= 0;
		hrs <= 0;
		counter <= 0;
	elsif(rising_edge(Clock)) then
		--increment the seconds. also increment mins and hours if needed.
		if(inc_secs = '1') then
			if(secs = 59) then
				secs <= 0;
				if(mins = 59) then
					mins <= 0;
					if(hrs = 23) then
						hrs <= 0;
					else
						hrs <= hrs+1;
					end if;
				else
					mins <= mins+1;
				end if;
			else
				secs <= secs + 1;
			end if;
		--increment the minutes. also increment hours if needed.
		elsif(inc_mins = '1') then
			if(mins = 59) then
				mins <= 0;
				if(hrs = 23) then
					hrs <= 0;
				else
					hrs <= hrs+1;
				end if;
			else
				mins <= mins+1;
			end if;
		--increment the hours. 
		elsif(inc_hrs = '1') then
			if(hrs = 23) then
				hrs <= 0;
			else
				hrs <= hrs+1;
			end if;
		end if;
		
		--regular operation of the clock
		if(counter = CLOCK_FREQ-1) then	--counting CLOCK_FREQ times takes 1 second. 
			counter <= 0;
			--check and change values of secs, mins and hours
			if(secs = 59) then
				secs <= 0;
				if(mins = 59) then
					mins <= 0;
					if(hrs = 23) then
						hrs <= 0;
					else
						hrs <= hrs+1;
					end if;
				else
					mins <= mins+1;
				end if;
			else
				secs <= secs + 1;
			end if;
		else
			counter <= counter+1;
		end if;
	end if;
	
end process;

--The internal integer signals are converted into unsigned format. 
--The size of the output unsigned signal is assigned via the 2nd parameter(5 or 6 bits)

seconds <= to_unsigned(secs, 6);
minutes <= to_unsigned(mins, 6);
hours <= to_unsigned(hrs, 5);

end Behavioral;

Testbench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
--the below library is used for finishing the simulation after we are done.

--Otherwise it will run continuously.
library std;
use std.env.finish;
 
ENTITY tb_digitalClock IS
END tb_digitalClock;
 
ARCHITECTURE behavior OF tb_digitalClock IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT digital_clock
    generic( CLOCK_FREQ : integer := 50000000	); 
    PORT(
         Clock : IN  std_logic;
         reset : IN  std_logic;
         inc_secs : IN  std_logic;
         inc_mins : IN  std_logic;
         inc_hrs : IN  std_logic;
         seconds : OUT  unsigned(5 downto 0);
         minutes : OUT  unsigned(5 downto 0);
         hours : OUT  unsigned(4 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal Clock : std_logic := '0';
   signal reset : std_logic := '0';
   signal inc_secs : std_logic := '0';
   signal inc_mins : std_logic := '0';
   signal inc_hrs : std_logic := '0';

 	--Outputs
   signal seconds : unsigned(5 downto 0);
   signal minutes : unsigned(5 downto 0);
   signal hours : unsigned(4 downto 0);

   -- Clock period definitions
   constant Clock_period : time := 10 ns;
	
	--Clock frequency in Hz. Use a smaller value for testbench.

  --When testing on board it need to be set as 50 million, 100 million etc.
	constant CLOCK_FREQ : integer := 10;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: digital_clock 
		GENERIC MAP(CLOCK_FREQ => CLOCK_FREQ)
		PORT MAP (
          Clock => Clock,
          reset => reset,
          inc_secs => inc_secs,
          inc_mins => inc_mins,
          inc_hrs => inc_hrs,
          seconds => seconds,
          minutes => minutes,
          hours => hours
        );

   -- Clock process definitions
   Clock_process :process
   begin
		Clock <= '0';
		wait for Clock_period/2;
		Clock <= '1';
		wait for Clock_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
		reset <= '1';
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		reset <= '0';
      wait for Clock_period*CLOCK_FREQ*60*60*25;  --run the clock for 25 hours
		
		--increment seconds
		inc_secs <= '1';	wait for Clock_period;
		inc_secs <= '0';

    wait for Clock_period*CLOCK_FREQ*5;	--wait for 5 secs after incrementing seconds once.
		
		--increment seconds 60 times
		inc_secs <= '1';	wait for Clock_period*60;
		inc_secs <= '0';

    wait for Clock_period*CLOCK_FREQ*5;	--wait for 5 secs after incrementing seconds.
		
		--increment minutes
		inc_mins <= '1';	wait for Clock_period;
		inc_mins <= '0';

    wait for Clock_period*CLOCK_FREQ*5;	--wait for 5 secs after incrementing minutes once.
		
		--increment minutes 60 times
		inc_mins <= '1';	wait for Clock_period*60;
		inc_mins <= '0';

    wait for Clock_period*CLOCK_FREQ*5;	--wait for 5 secs after incrementing minutes.
		
		--increment hours
		inc_hrs <= '1';	wait for Clock_period;
		inc_hrs <= '0';

    wait for Clock_period*CLOCK_FREQ*5;	--wait for 5 secs after incrementing hours once.
		
		--increment hours 25 times
		inc_hrs <= '1';	wait for Clock_period*25;
		inc_hrs <= '0';

    wait for Clock_period*CLOCK_FREQ*5;	--wait for 5 secs after incrementing hours.
		
		--apply reset
		reset <= '1';
		
		--wait for 100 Clock cycles and then finish the simulation.
		--with the current settings it will run around 9 ms of simualtion time. 
		wait for Clock_period*100;
		finish;  
   end process;

END;

So what next?

As an extension of this project I want to show you how you can convert the time into BCD format and then connect a BCD to 7 segment converter to it. This will be useful for those who want to try this clock on a real FPGA board. Look forward to it in the next post.

So until next time...

Image Processsing: RGB to Gray scale Converter in VHDL

2020-12-20T17:57:00.003+05:30

Implementing image processing algorithms in VHDL is a scary thing for many. Though I agree that its much more difficult to do it in VHDL than in a high level programming language like C, Matlab etc, it needn't be that scary.

In this post I am going to share the code for a simple image processing algorithm - A RGB to Gray scale image converter.

There are many ways, from simple to complex, in which you can do this. I have done it in a way, which makes sense to me. Touching upon few topics related to this subject. For example reading the image data from a text file, storing it in RAM and accessing the data within the code and then manipulating them etc...

I have used the standard Matlab image Lenna.bmp for this. The original image was 512*512*3 pixels in size. This takes a long time to load and run in Modelsim. So I first reduced its size to 1/8th of its original size, making it a 64*64*3 pixel image. Each pixel ranges from 0 to 255 and the dimension "3" indicates the presence of Red, Green and Blue components.

VHDL text file operations aren't ideal for reading multiple pixels from the same row. So I converted the 3 Dimensional image data into a 1 Dimensional matrix. And then used dlmwrite Matlab command to write it to a text file named rgb.txt. This will be our input image.

In Matlab, I manually converted the above RGB image into a gray scale image using the formula:

Grayscale Image = ( (0.3 * R) + (0.59 * G) + (0.11 * B) ).

The above grayscale pixels were converted to a 1-D matrix and written to a text file called gray.txt. This text file would be read by our VHDL testbench to verify that the results from our VHDL design is the same as the ideal result obtained from Matlab.

The Matlab program which I used for achieving all this is shared below:

I=imread('Lenna.bmp'); %read the image into memory

I=imresize(I,1/8); %reduce the size by 8 times.

%convert image to 1-D array and write it to a text file.

dlmwrite('rgb.txt',reshape(I,64*64*3,1,1));

I4=double(I); %convert it to double format

%convert rgb pixels to gray manually as per formula.

for i=1:64

for j=1:64

I2(i,j) = I4(i,j,1)*0.3 + I4(i,j,2)*0.59 + I4(i,j,3)*0.11;

end

%the converted image is changed to 1-D and then written to a text file.

I3=reshape(I2,64*64,1);

dlmwrite('gray.txt',I3);

The standard RGB format Lenna image, the resized version of it and the converted Grayscale image are shared below:

Now that we have prepared the above basic data to work with, we can go and explore the VHDL designs. There are three VHDL files in this project:

1) im_ram.vhd:

The input RGB image is internally stored in a RAM. The RAM is declared and initialized with the pixel values from the text file rgb.txt. The std.textio library is used, to do the file reading operations.

--RAM entity for storing the image.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--the below libraries are needed for reading text file.
library std;
use std.textio.all;

entity im_ram is
    generic(
        ADDR_WIDTH : integer := 16; --Address bus size of the Image Ram.
        IM_SIZE_D1 : integer := 64; --Size along Dimension 1
        IM_SIZE_D2 : integer := 64  --Size along Dimension 2
    );
    port (
        Clk : in std_logic;
        addr_in : in unsigned(ADDR_WIDTH-1 downto 0);   --Address bus to the Image Ram.
        rgb_out : out std_logic_vector(23 downto 0) --24 bit RGB pixel output
    );
end im_ram;

architecture Behav of im_ram is

--custom array declaration.
type im_ram_type is array (0 to  IM_SIZE_D1*IM_SIZE_D2-1) of std_logic_vector(23 downto 0);

--function for reading the image pixels from text file and use
--it to initialize the RAM.
impure function im_ram_initialize return im_ram_type is
    variable line_var : line;
    file text_var : text;
    variable pixel : integer;
    variable image_pixels : im_ram_type;
begin        
    --Open the file in read mode.
    file_open(text_var,"rgb.txt",read_mode);    
    while(NOT ENDFILE(text_var)) loop   --until end of file is reached
        for k in 1 to 3 loop    --through R, G and B.
            for j in 0 to IM_SIZE_D2-1 loop
                for i in 0 to IM_SIZE_D1-1 loop
                    readline(text_var,line_var);   --read one row. Each row contains one pixel.
                    read(line_var,pixel);   --From the read line, read the integer value.
                    --save the pixel in the RAM.
                    image_pixels(i*IM_SIZE_D2+j)(k*8-1 downto k*8-8) := std_logic_vector(to_unsigned(pixel,8));
                end loop;
            end loop;
        end loop;
    end loop;
    file_close(text_var); --close the file after reading.
    return image_pixels;    
end function;

--declare and initialize the image ram.
signal ram : im_ram_type := im_ram_initialize;

begin

--read the R,G and B pixels from RAM with the addr_in input.
rgb_out <= ram(to_integer(addr_in));

end architecture;

2) rgb2gray.vhd:

This is the top level entity which converts the image from RGB format to Grayscale. The RAM block is instantiated as a component inside this entity.

--Convert a internally stored RGB image into gray image.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity rgb2gray is
    generic(
        ADDR_WIDTH : integer := 16; --Address bus size of the Image Ram.
        IM_SIZE_D1 : integer := 64; --Size along Dimension 1
        IM_SIZE_D2 : integer := 64  --Size along Dimension 2
    );
    port (
        Clk : in std_logic;
        reset : in std_logic;   --active high asynchronous reset
        data_valid : out  std_logic;    --High when gray_out has valid output.
        gray_out : out unsigned(7 downto 0) --8 bit gray pixel output
    );
end rgb2gray;

architecture Behav of rgb2gray is

    component im_ram is
        generic(
            ADDR_WIDTH : integer := 16; --Address bus size of the Image Ram.
            IM_SIZE_D1 : integer := 64; --Size along Dimension 1
            IM_SIZE_D2 : integer := 64  --Size along Dimension 2
        );
        port (
            Clk : in std_logic;
            addr_in : in unsigned(ADDR_WIDTH-1 downto 0);   --Address bus to the Image Ram.
            rgb_out : out std_logic_vector(23 downto 0) --24 bit RGB pixel output
        );
    end component;

    signal rgb_out : std_logic_vector(23 downto 0);
    signal addr_in : unsigned(ADDR_WIDTH-1 downto 0);

begin

    --Instantiation of Image RAM. Internally stored image.
    image_ram : im_ram generic map(ADDR_WIDTH,  IM_SIZE_D1 ,IM_SIZE_D2)
        port map(Clk, addr_in, rgb_out);

    --Process to convert RGB to Gray image.
    CONVERTER_PROC : process(Clk,reset)
        --temperary variables
        variable temp1,temp2,temp3,temp4 : unsigned(15 downto 0);
    begin
        if(reset = '1') then    --active high asynchronous reset
            addr_in <= (others => '0');
            data_valid <= '0';
        elsif rising_edge(Clk) then
            --output is ready when the last address in the ram has reached.
            if(to_integer(addr_in) = IM_SIZE_D1*IM_SIZE_D2-1) then  
                addr_in <= (others => '0');
                data_valid <= '0';
            else    --otherwise keep incrementing the address value.
                addr_in <= addr_in + 1;
                data_valid <= '1';  --indicates output is ready
            end if;
            --Gray pixel = 0.3*Red pixel + 0.59*Green pixel + 0.11*Blue pixel
            --the 24 bit value is split into R,G and B components and multiplied
            --with their respective weights and then added together.
            temp1 := "01001100" * unsigned(rgb_out(7 downto 0));        --(0.3 * R)  
            temp2 := "10010111" * unsigned(rgb_out(15 downto 8));       --(0.59 * G) 
            temp3 := "00011100" * unsigned(rgb_out(23 downto 16));  --(0.11 * B)
            temp4 := temp1 + temp2 + temp3;
            --Most significant bit of the LSB portion is added to the MSB portion. 
            --To round off the result.
            gray_out <= temp4(15 downto 8) + ("0000000" & temp4(7));
        end if;
    end process;

end architecture;

3) tb.vhd:

This is the testbench for testing our main designs. The output image is received from the main design and compared with the actual result. Previously using Matlab, we have saved the actual result in a file called gray.txt .

--Testbench
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--the below libraries are needed for reading text file.
library std;
use std.textio.all;

--Testbench entity is always empty.
entity tb is
end tb;

architecture sim of tb is

    --the generic parameters are declared and initialized as constants here.
    constant IM_SIZE_D1: integer := 64;
    constant IM_SIZE_D2: integer := 64; --we have a 64*64 image.
    constant ADDR_WIDTH: integer := 12; --64*64=4096 which needs 12 bits.
    
    --this array is used to store the output gray pixels.
    type image_type is array (1 to  IM_SIZE_D1, 1 to  IM_SIZE_D2) of integer;
    signal image_pixels : image_type := (others => (others => 0));

    --component declaration.
    component rgb2gray is
        generic(
            ADDR_WIDTH : integer := 16;
            IM_SIZE_D1 : integer := 64;
            IM_SIZE_D2 : integer := 64
        );
        port (
            Clk : in std_logic;
            reset : in std_logic;
            data_valid : out  std_logic;
            gray_out : out unsigned(7 downto 0)
        );
    end component;

    --temperory signal declarations.
    signal Clk,reset,data_valid : std_logic := '0';
    signal gray_out : unsigned(7 downto 0);
    constant Clk_period : time := 10 ns;    --clock period.

begin

    --generate the clock signal.
    Clk <= not Clk after Clk_period/2;

    --Instantiate the Unit under test.
    UUT : rgb2gray generic map(ADDR_WIDTH, IM_SIZE_D1, IM_SIZE_D2)
            port map(Clk, reset, data_valid, gray_out);


    --Process where we apply inputs, read outputs and verify the result.        
    STIMULUS_PROC : process
        variable i,j : integer := 1;    --loop indices.
        variable line_var : line;
        file text_var : text;
        variable pixel : integer;
        variable error : integer := 0;  --this value should be zero at the end of simulation.
        variable diff : image_type := (others => (others => 0));    
    begin
        reset <= '1';
        wait for Clk_period;
        reset <= '0';   --reset is applied for one clock cycle.
        wait until data_valid = '1';    --wait for valid data at the output port.
        while(data_valid = '1') loop
            wait until (falling_edge(Clk)); --sample outputs at the falling edge of clock
            image_pixels(i,j) <= to_integer(gray_out);  --save pixel as integer.
            --generate indices to save the pixels in the correct place.
            if(j = IM_SIZE_D2) then
                j := 1;
                if(i = IM_SIZE_D1) then
                    i := 1;
                else
                    i := i+1;
                end if;
            else
                j := j+1;
            end if; 
            wait until (rising_edge(Clk));  --pause until rising edge of the clock 
        end loop;
        --all output gray pixels are read. Activate reset again.
        reset <= '1';

        --Now check if the results are the same as in Matlab
        --Open the file in read mode. gray.txt contains pixels calculated using Matlab.
        file_open(text_var,"gray.txt",read_mode);   
        while(NOT ENDFILE(text_var)) loop   --until end of file is reached
            for j in 1 to IM_SIZE_D2 loop
                for i in 1 to IM_SIZE_D1 loop
                    readline(text_var,line_var);   --read one row. Each row contains one pixel.
                    read(line_var,pixel);
                    --calculate the difference between actual gray pixels from Matlab
                    --and pixel values from our rgb2gray VHDL design.
                    diff(i,j) := abs(image_pixels(i,j) - pixel);
                    --If the difference is 2 or more then, we take it as an error
                    --and increment the variable 'error' by 1.
                    if(diff(i,j) > 1) then
                        error := error+1;
                    end if;
                    wait for 1 ns;  --pause for 1 ns. 
                end loop;
            end loop;
        end loop;
        file_close(text_var); --close the file after reading.

        wait;   --wait eternally after finishing simulation.
    end process;

end architecture;   --End of Testbench

Note that IM_SIZE_D1 and IM_SIZE_D2 are the number of rows and columns respectively of the image matrix. You can read it as a short form for "Image size along dimension 1 (or) 2".

In the testbench we have a variable matrix called "diff". This matrix contains the absolute value of difference between gray image pixels, from Matlab and VHDL. A difference of "1" is considered okay, as binary multiplications can cause some loss of least significant bits. But more than a difference of "1" is considered as an error. We can see that at the end of simulation, we didn't get any "error".

There is no address output from the top level entity rgb2gray. In our design, I thought it was unnecessary, because the pixel outputs were coming out in a sequential manner. So the testbench "knew" where to place each output pixel.

I hope this post was helpful for you and gave you some ideas on how to do image processing using VHDL.

You can Download the VHDL codes, images etc from Here.

Synthesizable Clocked Square Root Calculator In VHDL

2020-12-08T22:57:00.003+05:30

Long back I had shared VHDL function for finding the square root of a number. This function too was synthesisable, but as it was a function, it was purely combinatorial. If you want to find the square root of a relatively larger number, then the resource usage was very high.

In such cases, it makes sense to use a clocked design. Such a clocked design enables us to reuse one set of resources over and over. The advantage of such a design is that it uses far less resources while the disadvantage being the low speed.

For example, in the design I have shared in this post, to find the square root of a N-bit number, you need to wait N/2 clock cycles.

The code is written based on Figure (8) from this paper: A New Non-Restoring Square Root Algorithm and Its VLSI Implementations.

The codes are well commented, so I wont write much about how it works here. Please refer to the block diagram from the paper in case you have some doubts.

Let me share the codes now:

square_root.vhd:

--Synthesisable Design for Finding Square root of a number.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity square_root is
    generic(N : integer := 32);
    port (
        Clk : in std_logic;     --Clock
        rst : in std_logic;     --Asynchronous active high reset.
        input : in unsigned(N-1 downto 0);  --this is the number for which we want to find square root.
        done : out std_logic;   --This signal goes high when output is ready
        sq_root : out unsigned(N/2-1 downto 0)  --square root of 'input'
    );
end square_root;

architecture Behav of square_root is

begin

    SQROOT_PROC : process(Clk,rst)
        variable a : unsigned(N-1 downto 0);  --original input.
        variable left,right,r : unsigned(N/2+1 downto 0):=(others => '0');  --input to adder/sub.r-remainder.
        variable q : unsigned(N/2-1 downto 0) := (others => '0');  --result.
        variable i : integer := 0;  --index of the loop. 
    begin
        if(rst = '1') then  --reset the variables.
            done <= '0';
            sq_root <= (others => '0');
            i := 0;
            a := (others => '0');
            left := (others => '0');
            right := (others => '0');
            r := (others => '0');
            q := (others => '0');
        elsif(rising_edge(Clk)) then
            --Before we start the first clock cycle get the 'input' to the variable 'a'.
            if(i = 0) then  
                a := input;
                done <= '0';    --reset 'done' signal.
                i := i+1;   --increment the loop index.
            elsif(i < N/2) then --keep incrementing the loop index.
                i := i+1;  
            end if;
            --These statements below are derived from the block diagram.
            right := q & r(N/2+1) & '1';
            left := r(N/2-1 downto 0) & a(N-1 downto N-2);
            a := a(N-3 downto 0) & "00";  --shifting left by 2 bit.
            if ( r(N/2+1) = '1') then   --add or subtract as per this bit.
                r := left + right;
            else
                r := left - right;
            end if;
            q := q(N/2-2 downto 0) & (not r(N/2+1));
            if(i = N/2) then    --This means the max value of loop index has reached. 
                done <= '1';    --make 'done' high because output is ready.
                i := 0; --reset loop index for beginning the next cycle.
                sq_root <= q;   --assign 'q' to the output port.
                --reset other signals for using in the next cycle.
                left := (others => '0');
                right := (others => '0');
                r := (others => '0');
                q := (others => '0');
            end if;
        end if;    
    end process;

end architecture;

Testbench: tb.vhd

--Testbench for out square root calculator design.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

--empty entity as its a testbench
entity tb is
end tb;

architecture sim of tb is

    --Declare the component which we want to test.
    component square_root is
        generic(N : integer := 32);
        port (
            Clk : in std_logic;
            rst : in std_logic;
            input : in unsigned(N-1 downto 0);
            done : out std_logic;
            sq_root : out unsigned(N/2-1 downto 0)
        );
    end component;

    constant clk_period : time := 10 ns;    --set the clock period for simulation.
    constant N : integer := 16;    --width of the input.
    signal Clk,rst,done : std_logic := '0';
    signal input : unsigned(N-1 downto 0) := (others => '0');
    signal sq_root : unsigned(N/2-1 downto 0) := (others => '0');
    signal error : integer := 0;    --this indicates the number of errors encountered during simulation.
    

begin

    Clk <= not Clk after clk_period / 2;    --generate clock by toggling 'Clk'.

    --entity instantiation.
    DUT : entity work.square_root generic map(N => N)
             port map(Clk,rst,input,done,sq_root);

    --Apply the inputs to the design and check if the results are correct. 
    --The number of inputs for which the results were wrongly calculated are counted by 'error'.     
    SEQUENCER_PROC : process
        variable actual_result,i : integer := 0;
    begin
        --First we apply reset input for one clock period.
        rst <= '1';
        wait for clk_period;
        rst <= '0';
        --Test the design for all the combination of inputs.
        --Since we have (2^16)-1 inputs, we test all of them one by one. 
        while(i <= 2**N-1) loop
            input <= to_unsigned(i,N);  --convert 'i' from integer to unsigned format.
            wait until done='1';    --wait until the 'done' output signal goes high.
            wait until falling_edge(Clk);   --we sample the output at the falling edge of the clock.
            actual_result := integer(floor(sqrt(real(i)))); --Calculate the actual result.
            --if actual result and calculated result are different increment 'error' by 1.
            if (actual_result /= to_integer(sq_root)) then  
                error <= error + 1;
            end if; 
            i := i+1;   --increment the loop index.
        end loop;
        reset <= '1';   --all inputs are tested. Apply reset
        input <= (others => '0');   --reset the 'input'
        wait;
    end process;

end architecture;

Simulation Waveform from ModelSim:

To reach the end of the testbench, you need to simulate only for 5.5 msec of simulation time.

Synthesizable Polynomial Equation Calculator in VHDL

2020-12-07T19:22:00.000+05:30

A polynomial equation is an equation which is formed with variables, coefficients and exponents. They can be written in the following format:

y =a_nxⁿ + a_n-1x^n-1 + ... +a₁x + a₀ .

Here a_n,a_n-1... , a_{1 ,}a₀are coefficients,

n, n-1, ... etc are exponents and x is the variable.

In this post, I want to share, VHDL code for computing the value of 'y' if you know the value of 'x' and coefficients forming the polynomial.

Directly calculating the polynomial with the above equation is very inefficient. So, first we reformat the equation as per Horner's rule:

y =(((a_nx + a_n-1)x + a_n-2)x + a_n-3)x + ... )x +a₀ .

This modified equation can be represented by the following block diagram:

There are 3 sub-entities in the above block diagram.

1) Block number 1:

This block keep generating successive powers of input x.

In the first clock cycle it generates x^0 = 1.

In the 2ndclock cycle it generates x^1.

In the 3rd clock cycle it generates x^2.

In the nth clock cycle it generates x^(n-1).

Every clock cycle, the previous outputs are multiplied with 'x' to get the next power of x.

2)Block number 2:

The powers of x generated in the first block are multiplied with the corresponding coefficients of the polynomial in Block numbered 2. The coefficients are declared and initialized in the top level entity and can be changed easily.

3)Block number 4:

This block is basically an accumulative adder which accumulates all the products generated by the multiplier. Once it does 'n' additions, we have the final result available in output 'y'. An output 'done' is set as high to indicate that the output is ready.

Let me share the VHDL codes for these entities along with the testbench.

1) power_module.vhd

--This module generates successive powers of input x in each clock cycle.
--For example 1,x,x^2,x^3,x^4 etc. 
--The output from the previous cycle is multiplied again by x to get the next power.
--The output from this entity is passed to the multiplier module, where it gets
--multiplied by the corresponding coefficient.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity power_module is
    generic(N : integer := 32);
    port (
        Clock : in std_logic;
        reset : in std_logic;
        x : in signed(N-1 downto 0);
        x_powered : out signed(N-1 downto 0)
    );
end power_module;

architecture Behav of power_module is

    signal x_pow : signed(N-1 downto 0) := to_signed(1,N);

begin

    POWER_PROC : process(Clock,reset)
        variable temp_prod : signed(2*N-1 downto 0);
    begin
        if (reset='1') then
            x_pow <= to_signed(1,N);
        elsif(rising_edge(Clock)) then
            temp_prod := x*x_pow;
            --The MSB half of the result is ignored. We assume that all intermediate powers of x
            --can be represented by a max of N bits.
            x_pow <= temp_prod(N-1 downto 0);
        end if;
    end process;

    x_powered <= x_pow;

end architecture;

2) multiplier.vhd

--The successive powers of x are multiplied by the corresponding coeffcients here. 
--The results are sent to the adder module which acts as an "accumulator".
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity multiplier is
    generic(N : integer := 32);
    port (
        Clock : in std_logic;
        x,y : in signed(N-1 downto 0);
        prod : out signed(N-1 downto 0)
    );
end multiplier;

architecture Behav of multiplier is

begin

    MULT_PROC : process(Clock)
        variable temp_prod : signed(2*N-1 downto 0) := (others => '0');
    begin
        if(rising_edge(Clock)) then
            temp_prod := x*y;
            --The MSB half of the result is ignored. We assume that all intermediate numbers
            --be represented by a max of N bits.
            prod <= temp_prod(N-1 downto 0);
        end if;    
    end process;
    

end architecture;

3) adder.vhd

--The output from multiplier module is received by this module and accumulated to
--form the output. If the polynomial equation has a degree of 'n' then 'n' additions has to take place
--to get the final result.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity adder is
    generic(N : integer := 32);
    port (
        Clock : in std_logic;
        reset : in std_logic;
        x : in signed(N-1 downto 0);
        sum : out signed(N-1 downto 0)
    );
end adder;

architecture Behav of adder is

    signal temp_sum : signed(N-1 downto 0) := (others => '0');

begin

    ADDER_PROC : process(Clock,reset)
    begin
        if (reset = '1') then
            temp_sum <= (others => '0');
        elsif(rising_edge(Clock)) then
            temp_sum <= temp_sum + x;
        end if;
    end process;

    sum <= temp_sum;

end architecture;

4) Top Level Entity : poly_eq_calc.vhd

--This is the top level entity for the polynomial equation calculator.
--The power_module, multiplier and adders entities are instantiated inside this top level block.
--When the output signal done is High, the output available at the 'y' output is the result we want.
--Ignore all other values of 'y' when done is Low.
--We have assumed that all the intermediate numbers calculated to reach the final result, can be represented
--by a maximum of N bits. This simplifies the design very much.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity poly_eq_calc is
    generic(N : integer := 32);
    port (
        Clock : in std_logic;
        reset : in std_logic;
        x : in signed(N-1 downto 0);
        y : out signed(N-1 downto 0);
        done : out std_logic
    );
end poly_eq_calc;

architecture Behav of poly_eq_calc is

    component power_module is
        generic(N : integer := 32);
        port (
            Clock : in std_logic;
            reset : in std_logic;
            x : in signed(N-1 downto 0);
            x_powered : out signed(N-1 downto 0)
        );
    end component;

    component multiplier is
        generic(N : integer := 32);
        port (
            Clock : in std_logic;
            x,y : in signed(N-1 downto 0);
            prod : out signed(N-1 downto 0)
        );
    end component;

    component adder is
        generic(N : integer := 32);
        port (
            Clock : in std_logic;
            reset : in std_logic;
            x : in signed(N-1 downto 0);
            sum : out signed(N-1 downto 0)
        );
    end component;

    signal x_powered,coeff,product_from_mult : signed(N-1 downto 0) := (others => '0');
    constant NUM_COEFFS : integer := 4; --Change here to change the degree of the polynomial. 
    type arr_type is array (0 to  NUM_COEFFS-1) of signed(N-1 downto 0);  
     --Eq : 3*x^3 - 2*x^2 - 4*x + 5;
    --The coefficients belonging to higher powers of x are stored in higher addresses in Coeffs array.
    signal Coeffs : arr_type := (to_signed(5,N),  --change coefficients here. 
                                to_signed(-4,N),
                                to_signed(-2,N),
                                to_signed(3,N));
 
    signal reset_adder :  std_logic := '0';

begin

    --Instantiate the 3 sub-entities.    
    calc_power_of_x : power_module generic map(N => N)
        port map(Clock,reset,x,x_powered);

    multiply : multiplier  generic map(N => N)
        port map(Clock,x_powered,coeff,product_from_mult);

    add : adder  generic map(N => N)
        port map(Clock,reset_adder,product_from_mult,y);

    --The process controlling the 3 sub-entities and also supplying them with coefficients.    
    MAIN_PROC : process(Clock,reset)
        variable coeff_index : integer := 0;  
    begin
        if(reset = '1') then
            done <= '0';
            coeff_index := 0;
            coeff <= Coeffs(0);
            reset_adder <= '1';
        elsif(rising_edge(Clock)) then
            reset_adder <= '0'; --the disabling of 'reset of adder' gets noticed by adder entity in the next clock cycle.
            if(coeff_index < NUM_COEFFS-1) then
                coeff_index := coeff_index+1;
                coeff <= Coeffs(coeff_index);   --send the coefficients one by one to the multiplier entity. 
            elsif(coeff_index = NUM_COEFFS-1) then
                coeff_index := coeff_index+1;
            else
                done <= '1';    --The final result is available in 'y' now.
            end if;    
        end if;
    end process;

end architecture;

5) Testbench : tb_poly_eq_calc.vhd

--Testbench code.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

--The testbench entity is always empty.
entity tb_poly_eq_calc is
end tb_poly_eq_calc;

architecture sim of tb_poly_eq_calc is

    constant clk_period : time := 10 ns; --set the clock period here.

    signal Clk : std_logic := '1';
    signal reset : std_logic := '1';
    constant N : integer := 32; --change the width of input and output here.
    signal x,y : signed(N-1 downto 0) := (others => '0');
    signal done : std_logic := '0';

begin

    Clk <= not Clk after clk_period / 2;    --generate clock

    --Instantiating Design Under Test.
    DUT : entity work.poly_eq_calc generic map(N => N)
        port map (Clk, reset, x, y, done);

    --Apply inputs here. Only 'x' can be changed here. 
    --To change coefficients and degree of polynomial edit the top level entity directly.
    SEQUENCER_PROC : process
    begin
        --first input.
        reset <= '1';
        wait for clk_period * 2.5;
        reset <= '0';
        x <= to_signed(4, N);
        wait for clk_period;
        wait until done='1';    --wait for result to be out.
        wait for clk_period;

        --second input.
        reset <= '1';
        wait for clk_period;
        reset <= '0';
        x <= to_signed(7, N);
        wait for clk_period;
        wait until done='1';   --wait for result to be out.
        wait for clk_period;

        --third input.
        reset <= '1';
        wait for clk_period;
        reset <= '0';
        x <= to_signed(15, N);
        wait for clk_period;
        wait until done='1';   --wait for result to be out.
        wait for clk_period;

        --fourth input.
        reset <= '1';
        wait for clk_period;
        reset <= '0';
        x <= to_signed(-9, N);
        wait for clk_period;
        wait until done='1';   --wait for result to be out.
        wait for clk_period;
        reset <= '1';

        wait;
    end process;

    --Check if the results are correct and report the result.
    CHECK_RESULTS_PROC : process(Clk)
        variable actual_res : integer := 0;
        variable input_num,x_int : integer := 0;
    begin
        if(rising_edge(Clk)) then
            if(done = '1') then
                x_int := to_integer(x);
                --Change this equation if you change the polynomial eq inside the top level entity.
                actual_res := 3*x_int*x_int*x_int - 2*x_int*x_int - 4*x_int + 5;  
                input_num := input_num+1;
                if(actual_res = to_integer(y)) then
                    report "Input number "  & integer'image(input_num) & " Worked Well";
                else
                    report "Input number "  & integer'image(input_num) & " Has Error"; 
                end if;   
            end if;                   
        end if;
    end process;

end architecture;

The code was simulated successfully using Modelsim 10.4a version. The simulation waveform below shows the signals for the first two set of inputs:

The design was synthesized successfully using Vivado 2020.2 version.

Generic VHDL Code for Binary to Gray and Gray to Binary converter

2020-12-05T13:08:00.002+05:30

Few years back I had written a 4 bit converter for conversion between Gray and Binary codes. After receiving much positive response I decided to write a generic version of the same.

Let me share the codes...

Binary to Gray Code Converter:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity bin2gray is
    generic(N : integer := 4);
port(   bin : in std_logic_vector(N-1 downto 0);  --binary input
        G : out std_logic_vector(N-1 downto 0)  --gray code output
        );
end bin2gray;

architecture gate_level of bin2gray is 

begin

G(N-1) <= bin(N-1);
--generate xor gates.
xor_gates : for i in N-2 downto 0 generate
    G(i) <= bin(i+1) xor bin(i);
end generate;    

end;

Gray Code to Binary Converter:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity gray2bin is
    generic(N : integer := 4);
port(   G : in std_logic_vector(N-1 downto 0);    --gray code input
        bin : out std_logic_vector(N-1 downto 0)  --binary output
        );
end gray2bin;

architecture gate_level of gray2bin is 

signal temp : std_logic_vector(N-1 downto 0);

begin

temp(N-1) <= G(N-1);
--generate xor gates.
xor_gates : for i in N-2 downto 0 generate
    temp(i) <= temp(i+1) xor G(i);
end generate;    

bin <= temp;

end;

Testbench:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity tb is
end tb;
 
architecture behavior of tb is 
 
    -- component declaration for the unit under test's (uut) 
component bin2gray is
    generic(N : integer := 4);
port(   bin : in std_logic_vector(N-1 downto 0);  --binary input
        G : out std_logic_vector(N-1 downto 0)  --gray code output
        );
end component;

component gray2bin is
    generic(N : integer := 4);
port(   G : in std_logic_vector(N-1 downto 0);    --gray code input
        bin : out std_logic_vector(N-1 downto 0)  --binary output
        );
end component;

constant N : integer := 16;  --Change this to control the number of bits in the input/output.
signal bin,g,bin_out : std_logic_vector(N-1 downto 0) := (others => '0');
signal error : integer := 0; 
begin
    -- Both the converters are connected back to back to see the binary input going to the
    --first entity is the same as the output coming out of the second entity.
   uut1: bin2gray generic map (N => N) port map (
          bin => bin,
          g => g
        );
 
   uut2: gray2bin generic map (N => N) port map (
          g => g,
          bin => bin_out
        );
          
   -- stimulus process
   --this tests for all the input combinations.
   stim_proc: process
   begin        
        for i in 0 to 2**N-1 loop   --loop through all the  available inputs 
            bin <= std_logic_vector(to_unsigned(i,N)); --convert integer to std_logic_vector.
            wait for 5 ns;
             --Count the number of errors. Should be zero at the end of simulation.
            if(bin /= bin_out) then 
                error <= error + 1;
            end if;
            wait for 5 ns;
        end loop;    
        wait;
   end process;

end;

The codes were tested using Modelsim 10.4a version. Simply change the value of the constant 'N' in the testbench to test for different sized converters.

Writing a Gate Level VHDL design (and Testbench) from Scratch

2020-11-29T11:02:00.000+05:30

In this video I want to show you how you can take a logic circuit diagram and write the corresponding VHDL code along with its testbench.

The VHDL codes presented in the video are given below:

xor_gate.vhd:

library ieee;
use ieee.std_logic_1164.all;

entity xor_gate is
    port (
        A,B : in std_logic;
        C : out std_logic
    );
end entity;


architecture gate_level of xor_gate is

signal An,Bn,t1,t2 : std_logic := '0';

begin

An <= not A;
Bn <= not B;
t1 <= An and B;
t2 <= Bn and A;

C <= t1 or t2;

end architecture;

tb_xor.vhd:

library ieee;
use ieee.std_logic_1164.all;

entity tb_xor is
end entity;

architecture behav of tb_xor is

component xor_gate is
    port (
        A,B : in std_logic;
        C : out std_logic
    );
end component;

signal A,B,C : std_logic := '0';

begin

UUT : xor_gate port map (A,B,C);

stimulus : process
begin
    A <= '0';
    B <= '0';
    wait for 100 ns;
    A <= '0';
    B <= '1';
    wait for 100 ns;
    A <= '1';
    B <= '0';
    wait for 100 ns;
    A <= '1';
    B <= '1';
    wait;
end process;    

end architecture;

The Logic circuit diagram is given below:

Simulation Waveform from Modelsim:

Synthesizable Matrix Multiplier in VHDL

2020-11-28T10:55:00.001+05:30

Long back I had posted a simple matrix multiplier which works well in simulation but couldn't be synthesized. But many people had requested for synthesizable version of this code. So here we go.

The design takes two matrices of 3 by 3 and outputs a matrix of 3 by 3. Each element is stored as unsigned 8 bits. This is not a generic multiplier, but if you watch the video explaining the code, you might be able to extend it to a different sized multiplier.

Each matrix has 9 elements, each of which is 8 bits in size. So I am passing the matrix as a 72 bit 1-Dimensional array in the design. The following table shows how the 2-D elements are mapped into the 1-D array.

Row	Column	Bit’s Position in 1-D array
0	0	7:0
0	1	15:8
0	2	23:16
1	0	31:24
1	1	39:32
1	2	47:40
2	0	55:48
2	1	63:56
2	2	71:64

Let me share the codes now...

matrix_mult.vhd:

--3 by 3 matrix multiplier. Each element of the matrix is 8 bit wide. 
--Inputs are called A and B and output is called C. 
--Each matrix has 9 elements each of which is 8 bit wide. So the inputs is 9*8=72 bit long.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all; 

entity matrix_mult is
    port (  Clock: in std_logic; 
            reset : in std_logic;   --active high reset
            start : in std_logic;   --A '1' starts the matrix multiplication process.
            A,B : in unsigned(71 downto 0);
            C : out unsigned(71 downto 0);
            done : out std_logic    --a '1' indicates that multiplication is done and result is availble at C.
            );
end entity;

architecture Behav of matrix_mult is

type matType is array(0 to 2,0 to 2) of unsigned(7 downto 0);
signal matA, matB, matC : matType := (others => (others => X"00"));
type state_type is (init,do_mult,apply_outputs);
signal state : state_type := init;
signal i,j,k : integer := 0;

begin 

sm : process (Clock,reset)    --process implementing the state machine for multiplying the matrices.
variable temp : unsigned(15 downto 0) := (others => '0');
begin
    if(reset = '1') then
        state <= init;
        i <= 0;
        j <= 0;
        k <= 0;
        done <= '0';
        matA <= (others => (others => X"00"));
        matB <= (others => (others => X"00"));
        matC <= (others => (others => X"00"));
    elsif rising_edge(Clock) then
        case state is
            when init =>    --the matrices which are in a 1-D array are converted to 2-D matrices first.
                if(start = '1') then
                    for i in 0 to 2 loop    --run through the rows
                        for j in 0 to 2 loop    --run through the columns
                            matA(i,j) <= A((i*3+j+1)*8-1 downto (i*3+j)*8);
                            matB(i,j) <= B((i*3+j+1)*8-1 downto (i*3+j)*8);
                        end loop;
                    end loop;
                    state <= do_mult;
                end if;
            when do_mult =>
                temp := matA(i,k)*matB(k,j);
                matC(i,j) <= matC(i,j) + temp(7 downto 0);
                if(k = 2) then
                    k <= 0;
                    if(j = 2) then
                        j <= 0;
                        if (i= 2) then
                            i <= 0;
                            state <= apply_outputs;
                        else
                            i <= i + 1;
                        end if;
                    else
                        j <= j+1;
                    end if;        
                else
                    k <= k+1;
                end if;     
            when apply_outputs =>   --convert 3 by 3 matrix into a 1-D matrix.
                for i in 0 to 2 loop    --run through the rows
                    for j in 0 to 2 loop    --run through the columnss
                        C((i*3+j+1)*8-1 downto (i*3+j)*8) <= matC(i,j);
                    end loop;
                end loop;   
                done <= '1';
                state <= init;  
        end case;
    end if;
end process;
 
end architecture;

tb_matrix_mult.vhd:

--Testbench for testing the 3 by 3 matrix multiplier.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all; 

entity tb_matrix_mult is  --testbench entity is always empty. No input or output ports.
end entity;

architecture behav of tb_matrix_mult is

component matrix_mult is
    port (  Clock: in std_logic; 
            reset : in std_logic;   --active high reset
            start : in std_logic;   --A '1' starts the matrix multiplication process.
            A,B : in unsigned(71 downto 0);
            C : out unsigned(71 downto 0);
            done : out std_logic    --a '1' indicates that multiplication is done and result is availble at C.
            );
end component;

signal A,B,C : unsigned(71 downto 0);
signal Clock,reset, start, done : std_logic := '0';
type matType is array(0 to 2,0 to 2) of unsigned(7 downto 0);
signal matC : matType := (others => (others => X"00")); 

begin

matrix_multiplier : matrix_mult port map (Clock, reset, start, A,B, C,done);

--generate a 50Mhz clock for testing the design.
Clk_generator : process
begin
    wait for 10 ns;
    Clock <= not Clock;
end process;

apply_inputs : process
begin
    reset <= '1';
    wait for 100 ns;
    reset <= '0';
    wait for 20 ns;
    A <= X"09" & X"08" & X"07" & X"06" & X"05" & X"04" & X"03" & X"02" & X"01";
    B <= X"01" & X"09" & X"08" & X"07" & X"06" & X"05" & X"04" & X"03" & X"02";
    start <= '1';
    wait for 20 ns;
    start <= '0';
    wait until done = '1';
    --The result C should be (93,150,126,57,96,81,21,42,36)
    wait for 5 ns;
    for i in 0 to 2 loop --run through the rows
        for j in 0 to 2 loop --run through the columnss
            matC(i, j) <= C((i * 3 + j + 1) * 8 - 1 downto (i * 3 + j) * 8);
        end loop;
    end loop;
    wait;
end process;

end behav;

Simulation Results:

The design was simulated successfully using Modelsim SE 10.4a version. Screenshots of the simulation waveform is shown below:

Please let me know if you are unable to get the code to work or if its not synthesisable. Good luck with your projects.

Signals and Variables in VHDL

2020-11-26T09:43:00.005+05:30

Every programming language has objects for storing values. VHDL too have them. Two of these object types are called Signals and Variables. They might look very similar for a beginner, but there are few fundamental differences between them.

Variables are assigned using the := operator. And signals are assigned with the <= operator.
Variables can be declared and used only within a process/function/procedure but Signals can be declared and used anywhere.

A very fundamental difference:

In a block of statements, the statements with variables immediately take their values. Very similar to how it works in programming languages like C. But in a group of statements with Signals on the left hand side, the signals does not take it's new value until the process has suspended (either hit the bottom or hit a wait statement).

This can be further explained with the following example scenario.

Suppose I want to implement a swapping function in VHDL using Signals.

I can simply write,

signal x,y : std_logic := 0;
process(Clk)
begin
if(rising_edge(Clk)) then
  x <= y;
  y <= x;
end if;
end process;

What happens above is that, though the 'x' is assigned the value of 'y' sequentially first, the new value isn't updated to 'x' until we "exit" the process. So from a practical point of looking at it, it looks like they happen in parallel.

Now if I have to use variables for implementing a swapping function, I need three statements. Like below:

process(Clk)
variable x,y,temp : std_logic := 0;
begin
if(rising_edge(Clk)) then
  temp := x;
  x := y;
  y := x;
end if;
end process;


    Since variables take the values assigned to them right away, we need a temporary variable to hold the value of 'x' before assigning 'y' to it.

Variables declared in different processes cannot communicate with each other. They are local to the process. On the other hand signals declared in a VHDL entity can be used anywhere in the entity.
You cannot declare or use a Signal inside a VHDL Function. Functions are purely combinatorial in VHDL and thus you have to have use variables.

If you want the code to be synthesised, then beware of the consequences of using a variable. Variables often create latches when implemented on a FPGA and synthesis tools often pass a warning to notify. If not needed its good to avoid latches in your design.

Though using variables might seem make the work easier, it might not pass the synthesis stage. For many, who come to VHDL from a C background, using variables is very tempting.

Be easy with the use of Variables:

Check this Matrix Multiplication code using Variables to see some of the dangers involved with them. Multiplication of two matrices requires a large number of multipliers and adders. In C, you would use some nested "for" loops to achieve this. And with the use of variables you can do the same thing in VHDL too like you can see from the link.

But using this same piece of code in a real FPGA is impossible to achieve. Either the design wont pass the synthesis stage or it will take days to get it done.

All those individual additions and multiplications gets done in "one" clock cycle. None of the adders and multipliers get reused and the loops get unfolded into a concatenated series of resources.

In such a case its necessary to use signals and spilt the whole operation over many clock cycles. This reduces the resource usage and more importantly you have a chance to get your design synthesised.

Simulating a VHDL/Verilog code using Modelsim SE

2020-11-22T21:23:00.002+05:30

This is a simple How-To video for ModelSim SE 10.4a version. If you are already familiar with this software tool then you may not need to watch this video.

In this video, I am trying to show you:

How to create a new project in ModelSim SE.
Add VHDL codes to this project.
Compile and simulate the codes.
Few tips on the simulation part of the tool.