VHDL coding tips and tricks

Synthesised code is too big for the fpga device - What to do?

2012-07-11T19:56:00.000+05:30

After lot of hard work you completed your HDL project. The simulation results verified that the code is functionally working. To check how it performs in hardware you synthesis the design. To your bad luck you realize that the code you just wrote is too big for the fpga. What can you do? Don't panic. There are few ways you can tackle this problem.

1)If possible choose a higher graded fpga device:

Its a simple but the easiest thing you can do. Check if the lab or a friend has a better fpga device which can afford your design. If you really don't want to test the design in hardware,but just want to see the synthesis results then simply select the largest device available in the list.

2)Is the fpga out of pins?

Some times the synthesis tool will give out an "Out of resources" warning if the design has too many signals in its port list that the device can't support. This happens when you try to input or output large arrays or vectors.
In such cases use a multiplexed input or output system. Rather than inputting everything in one go, do it step wise. Check it out here.

3)Changing synthesis tool settings:

By default, the synthesis tool try to optimize your design for both speed and resource usage. But you can change this setting so that the tool will optimize for less resource usage. This may reduce the speed a little, but may significantly reduce the resource usage.

4)Re-use of resources:

Analyze the design carefully and see if any parts of the design can use time-sharing of resources. To do this you have to synchronize the whole design with a clock.

Time sharing means using the same resource for similar kind of operations like addition, multiplication etc. Suppose you want to do an operation like,

y = a+b+c+d; which uses 3 adder circuits.

then split the above operation over 3 clock cycles like this,

y= a + b; --in first clock cycle.
y= y + c; --in second clock cycle.
y= y + d; --in third clock cycle.

this way only one adder will be used for the whole operation. This will increase the time for generating output, but reduces logic usage.

5) Look for any mathematical simplifications:

Analyze the mathematical formula you are implementing and look for any simplification. For instance take this operation,

y=x / 5;

In digital world, division circuit is bigger than multiplication circuit. So make a small change in the formula like this,

y = x * (1/5) = x * 0.2;

6)Simplify design based on nature of inputs:

The code may be written for a generic use. But in real cases, the range of inputs may be small and predictive in nature. In such cases you can further simply the formula.

One good example is multiplication and division of variables by a number which is power of 2. If the multiplicand or divisor is a power of 2, then you can implement it using a left shift or right shift operation respectively. This is an excellent optimization method in some cases.

How to Mix VHDL and Verilog files in your design

2012-06-28T14:38:00.001+05:30

Sooner or later you will come across this question in your FPGA design career. There are times you found the right modules in the web, but couldn't use it just because you are using a different HDL. But you dont need to be disappointed. Instantiating VHDL components in Verilog modules, or vice versa is a simple process. Let me show it with an example.

Case 1 - Instantiating VHDL components in Verilog modules:

For example sake, take the synchronous D flip flop vhdl code I have written some time before. Suppose I want to write a Verilog module in which I want to instantiate two D- flipflops. Without worrying, you can simply instantiate it like you do it for a verilog module. See the code:

module test(
  output [1:0] Q,
  input Clk,
  input CE,
  input RESET,
input SET,
  input [1:0] D
  );

example_FDRSE(Q[0],Clk,CE,RESET,D[0],SET);
example_FDRSE(Q[1],Clk,CE,RESET,D[1],SET);

endmodule

Case 2 -   Instantiating Verilog modules in VHDL components:

This case is also straightforward. You don't need to worry about anything. Just instantiate as you normally do it with a vhdl file.

Take this verilog module for instance,

module a1(
  output Q,
  input [1:0] D
  );

and(Q,D[0],D[1]);

endmodule

A simpe vhdl code for instantiating this Verilog code can look like this:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test is
port(
Q : out std_logic_vector(1 downto 0);
D :in  std_logic_vector(3 downto 0)
);
end test;

architecture Behavioral of test is

component a1 is
port(
Q : out std_logic;
D :in  std_logic_vector(1 downto 0)
);
end component;

begin

a11 : a1 port map(Q(0),D(1 downto 0));
a22 : a1 port map(Q(1),D(3 downto 2));

end Behavioral;

Never thought mixing vhdl and verilog files were so easy? But it is!

Not enough I/O pins in the FPGA board for your design?

2012-04-28T13:50:00.001+05:30

Thanks to all the hardwork you have done, you successfully completed writing your first vhdl code. It did great in the functional simulation part. Now its time to test it on a FPGA board.

But looking at the board in hand, you realize that there are not enough input or output pins on the board to test the design. As you may have seen most of the FPGA boards have 8 switch inputs, 4 push buttons, 8 led's. There are other ways to increase I/O by using features like seven segment display, VGA monitor, RS232, DAC and ADC etc. But these features may make the design pretty complex and time consuming.

In such cases we can simply use the basic led's or switches in a multiplexed manner. In this article I have shown how to tackle such a problem in case you are out of input pins. But the same concept apply for output pins also.

Our design is named as my_design which has a 32 bit input and 8 bit output. Considering a typical FPGA board, we dont have 32 switches or push buttons. Suppose we have 8 switches. The idea is to apply the input in four stages of 8 bit each. This is how you do it.

1st stage : Set switches for 1st byte(LSB), press the push button.
2nd stage : change switches for 2nd byte and press the push button again.
3rd stage : change switches for 3rd byte, press the push button again.
4th stage : change switches for 4th byte(MSB) and press the push button again.

The code for my_design:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity my_design is
Port ( input : in STD_LOGIC_VECTOR (31 downto 0);
output : out STD_LOGIC_VECTOR (7 downto 0));
end my_design;

architecture Behavioral of my_design is

begin

output <= input(31 downto 24) and input(23 downto 16)
and input(15 downto 8) and input(7 downto 0);

end Behavioral;

The code just does the AND operation between the 4 bytes of the 32 bit number entered.

Now the code for reducing the input numbers. I call this module as a wrapper module. This job of this module is to get the input in stages, concatenate it together and apply it to the instantiated my_design.

Code for wrapper module :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity wrapper is
Port ( Clk : in STD_LOGIC;
push : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (7 downto 0);
output : out STD_LOGIC_VECTOR (7 downto 0));
end wrapper;

architecture Behavioral of wrapper is

component my_design
port( input : in STD_LOGIC_VECTOR (31 downto 0);
output : out STD_LOGIC_VECTOR (7 downto 0));
end component;

--state machine type
type stype is (idle,get_byte,delay);
signal s : stype := idle;
signal c1,c2 : integer := 0;
signal temp_reg : std_logic_vector(31 downto 0) := (others => '0');

begin

uut : my_design port map
(input => temp_reg, --concatenated signal
output => output );

process(Clk)
begin
if(rising_edge(clk)) then
case s is
when idle =>
if(push = '1') then
s <= get_byte;
c1 <= c1+1;
end if;
when get_byte =>
temp_reg( (8*c1-1) downto (8*(c1-1)) ) <= input;
s <= delay;
when delay => --delay for a time gap.
--this delay is required to avoid the same byte getting
--registered into temp_reg for a single push button click.
c2 <= c2+ 1;
if(c2=25000000) then --for a 50 mhz clock, this generates a 0.5 sec delay.
c2 <= 0;
s <= idle;
if(c1=4) then
c1 <= 0;
end if;
end if;
end case;
end if;
end process;

end Behavioral;

I am using a state machine in the code, to get this done. The state machine has 3 stages.
1)idle - here system waits for a push button click.
2)get_byte - the system gets the switch inputs and stores in the temp_reg.
3)delay - system waits for a particular time(here 0.5 sec) doing nothing. This is to avoid duplicate registering of the same input.

A testbench was created for testing the design. The simulation waveforms are given below for your better understanding.

Note :- In a similar way you can also use multiplexed outputs.

Tips for an Error-free Functional Simulation

2012-04-22T17:31:00.000+05:30

Getting a VHDL code to work in the functional simulation is not always an easy task.This article will cover some tips to quickly point out the errors in the code and make your life easier.

Create a proper sensitivity list. Some times you may have to add other control signals too(other than clock) into you sensitivity list to get is working.
Initialize the signals and variables correctly. If they are not initialized(normally they are set to '0'), then these signals will appear as "U" in the simulation waveform.
If you see "X" in the waveform then that indicates concurrent writing to the same signal. A simple re-arrangement of the signal inside the process will normally take out this bug.
In case you have arrays in the design make sure to check for out of bound error. This happens when you read or write a different index than the one available within the range of array.
If elsif's are error prone. Always try to consider all the conditions of If elsif. If a particular condition is not considered then the value will remain unchanged. If you dont want this to happen then make sure you reset the signal, using an else condition.
Within a process, signal assignments can be written in any order. They will get executed concurrently. But for variables, the order matters. line 1 is executed first, line 2 second and so on...
One way to debug the code is to force one or more signals as constants and test the design. This will help you in localizing the error.
Writing a location in RAM requires a small time delay. Account for this, while reading and writing from the same location in the same clock cycle. The read data will be the one written in the last clock cycle.
Try synthesising the design. The synthesiser tool may give out some warnings or errors which will point you in the correct direction to solve the error in the functional simulation.
When using components in the design, use name instantiation, so that you don't accidentally assign wrong signals to the component ports.

Real data types and Synthesisability - Part 1

2012-01-19T16:46:00.000+05:30

First of all sorry that I haven't updated this blog for so long. To make up my negligence towards readers I have decided to write a post on the most common problem a vhdl coder may face. How to deal with real type signals in vhdl, when you have to create a synthesisable design?

The truth is that its not possible to make the code synthesisable if you use real type anywhere in your design. The only way to work around this problem is to first convert the real type into a equivalent binary format and then write custom functions to deal with it.

Generally,a real number can be represented in binary in two formats - Fixed point and Floating point formats. In this article I will talk about only fixed point formats.

When it comes to fixed point, I prefer the Q format. In Q format, we mention the number of integer bits and fractional bits. The number of these bits depends on the actual range and resolution of real numbers you want to deal with. A Q format, will be written as Qm.n where m represents the number integer bits and n represents the number of fractional bits. By default there will be a sign bit as the MSB(Most significant bit) which makes the total size of the binary number as m+n+1.

Range and resolution of a binary number in Qm.n format:

its range is [-2^m, 2^m - 2^-n]
its resolution is 2^-n

For example for a Q2.6 number,
range is [-2², 2² - 2^-6] = [-4 , 3.984375 ].
resolution is 2^-n= 2^-6= 0.015625.

Plan before you decide the value of m and n:

For accuracy and easiness in coding, its better to have a high values for m and n. But a higher value of m and n indicates that the size of your binary number will be high and hence more resource usage. For devices like Spartan 3 etc, its better to stick to a 8 bit binary if possible. Find your own optimized boundary between accuracy and size of design.

Examples for Q format.

3.5 in Q2.2 format = "0.11.10" = "01110".

3.5 in Q3.5 format = "0.011.10000" = "001110000".

3.4 in Q2.4 format = "0.11.0110" = "0110110".

3.4 in Q2.6 format = "0.11.011001" = "011011001".

How to easily convert a number to Q format?

As far as I know there is no software tool available for a general conversion between a real number and any sized Q format. Some calculators can do this job, but the fastest way is to write a vhdl snippet.

For this purpose we can use the fixed point package available in the ieee_proposed library. This package doesnt work with most of the synthesisers, but it can be used in the form of a testbench code to convert real numbers into Q format.

Follow these steps:

Store the real numbers, which you want to convert to Q format, in a text file.
Write a vhdl snippet to read the real numbers one by one and store in a variable array named, say r. See this post to know how to read and write a text file.
Now declare another array which have elements of sfixed type. One by one convert the values in r to this sfixed type using the to_sfixed function. See the below example:

variable r : real;
variable s : sfixed(m downto -n);
s := to_sfixed(r,s); --convert r to type of s and store it in variable s.
Write a vhdl snippet to write the values in s to another text file.

Matlab for file handling:

I use Matlab software to easily manipulate text files. Using Matlab you can read or write text files of csv format. Some times I have the real values stored in a MS Excel file. To convert it into a text file, I just have to save it as a csv file, use the Matlab Import feature and then use the dlmwrite command in Matlab to write the text file. This will save a lot of your time and frustration.

Note:- In the next part, I will talk about how to write, custom arithmetic functions for fixed point format numbers.

Reading and writing real numbers using Files - Part 3

2012-01-13T14:50:00.000+05:30

After the previous posts on file handling, now I have come up with another way to read and write files.

In this article I will show how to read a text file containing real numbers and store the square roots of these real numbers in another text file. The input file is named as "1.txt" and output file is named as "2.txt".

Contents of 1.txt:

12.23
34.4343
23.11
5.0
25.0
49.0
81.88
1000000.0
121.0
78.9

Contents of 2.txt:

3.497142e+00
5.868075e+00
4.807286e+00
2.236068e+00
5.000000e+00
7.000000e+00
9.048757e+00
1.000000e+03
1.100000e+01
8.882567e+00

VHDL code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
library std;
use std.textio.all;

entity file_handle is
end file_handle;

architecture Behavioral of file_handle is

type real_array is array(1 to 10) of real;

begin

process

variable line_var : line;
file text_var : text;
variable r : real_array;

begin

--Open the file in read mode.
file_open(text_var,"1.txt",read_mode);
--run the loop 10 times to read 10 real values from the file.
for i in 1 to 10 loop
--make sure its not the end of file.
if(NOT ENDFILE(text_var)) then
readline(text_var,line_var); --read the current line.
--extract the real value from the read line and store it in the variable.
read(line_var,r(i));
end if;
end loop;
file_close(text_var); --close the file after reading.

--Write the square root values of variable 'r' to another file.
file_open(text_var,"2.txt",write_mode);
--run the loop 10 times to write 10 real values to the file.
for i in 1 to 10 loop
write(line_var,sqrt(r(i))); --sqrt is a fucntion for finding square root.
writeline(text_var,line_var);
end loop;
file_close(text_var);

wait;

end process;

end Behavioral;

This way of reading and writing files is very helpful in many situations. In my next post I will show an example based on this code snippet.

Some tips on reducing power consumption in Xilinx FPGA's

2011-07-29T16:19:00.000+05:30

Power estimation and power reduction is an important part of any design. Especially in wireless devices, the reduction in power is a very important factor. In this article I will note down some points, on how to reduce the power consumption for xilinx based designs.

1)BRAM Enable signal:
Every BRAM has an enable signal which by default is high always. Most of the HDL coders never care to disable it even when the BRAM is not used. But when this enable signal is ON BRAM consumes a lot of power. It doesn't matter whether you change the address or write the data. So always have a control logic which will control the bram enable signal.

2)Low power option in coregen for BRAM's:
You can create a BRAM entity file using Xilinx's Core generator software. There are several options available in coregen to help you achieve what you want. For low power designs select the "Low power" option in coregen.

3)Decide on LUT or BRAM:
Suppose you want instantiate a memory in your design. Rather than going straight at BRAM or LUT, give it some thought. Xilinx says that for small memory blocks( less than 4 Kbits) LUT consumes less power than BRAM. Similarly for large memory blocks( more than 4 Kbits) BRAM uses less power for its operation than LUT-RAM. So from design to design, switch to LUT-RAM or BRAM depending on the size of memory block.

4)Global reset:
All FPGA devices have an internal global reset path. When the device is switched OFF and then ON, all the flip flops and memories are reset to their initial state. But when we define one more reset signal in the HDL code, Xilinx creates a second reset. This second reset is relatively low and hence not recommended. But if you still want to use them make sure it is synchronous, so that the number of the control signals in your design is low.

5)Initialization of Registers:
It is recommended that we initialize the registers in our design. Normally we do this for safe simulation purposes. But during synthesis, these initialization values will be connected to the INIT pin of the flip flops. Remember that this will work only for bits and bit vectors. It will not work for integer or natural types.

6)DSP slice Utilization:
Depending on how complex your FPGA is it will have some number of DSP slices. These components are highly efficient with low power consumption and high speed. All the DSP blocks in Xilinx FPGA are synchronous. So when we define asynchronous behavior for these operations, XST can't implement it using DSP slices. This will decrease the efficiency of your design.

Note:- I realized these tips after watching a Xilinx tutorial video recently. You can too watch it here.

Delay in VHDL without using a 'wait for' statement!

2011-07-29T14:55:00.000+05:30

Introducing a delay in VHDL is pretty easy with a wait for statement. But it has the disadvantage that it is not synthesisable. Most of the practical designs, so require another way to introduce a delay.
In this article I will use a counter and state machine to introduce the delay. We have an input signal, and we want to assign it to the output only after (say) 100 clock cycles. With this objective in my mind , first I have drawn a state machine.

There are two states in the state machine - idle and delay_c.
when the system is in idle state it waits for a valid input bit at the port data_in. whenever the data is valid, valid_data will go high. Upon receiving a valid data, the system moves to delay_c state where a counter, c is incremented every clock cycle till it reaches the maximum delay value(Here it is 100). Once the max count is reached system goes back to idle state and the input data will be assigned to output data. This process goes on and on.

I have written the VHDL codes and testbench code for the above state machine. See the below simulated result to see how it works:

The VHDL code is given below. It is well commented, so I wont be explaining it any further.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;

entity delay is
port( Clk : in std_logic;
valid_data : in std_logic; -- goes high when the input is valid.
data_in : in std_logic; -- the data input
data_out : out std_logic --the delayed input data.
);
end delay;

architecture Behaviora of delay is

signal c : integer := 0;
constant d : integer := 100; --number of clock cycles by which input should be delayed.
signal data_temp : std_logic := '0';
type state_type is (idle,delay_c); --defintion of state machine type
signal next_s : state_type; --declare the state machine signal.

begin

process(Clk)
begin
if(rising_edge(Clk)) then
case next_s is
when idle =>
if(valid_data= '1') then
next_s <= delay_c;
data_temp <= data_in; --register the input data.
c <= 1;
end if;
when delay_c =>
if(c = d) then
c <= 1; --reset the count
data_out <= data_temp; --assign the output
next_s <= idle; --go back to idle state and wait for another valid data.
else
c <= c + 1;
end if;
when others =>
NULL;
end case;
end if;
end process;

end Behaviora;

The following testbench code was used to test the code.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS

signal Clk : std_logic := '0';
signal valid_data : std_logic := '0';
signal data_in,data_out : std_logic := '0';
constant Clk_period : time := 5 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: entity work.delay PORT MAP (
Clk => Clk,
valid_data => valid_data,
data_in => data_in,
data_out => data_out
);

-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
wait for 100 ns;
valid_data <= '1';
data_in <= '1';
wait;
end process;

END;

The above design was successfully synthesized in Xilinx ISE software. Note that there are lot of different situations in which a delay can be introduced. But understanding the above concept well, will help you in most of the cases.

There is one limitation to this design. If the input value keep changing before the delay count is reached, then it will only take the first valid value. If you want a delay pipeline then you have to implement a FIFO whose size will depend on the amount of delay. In our case we will need a FIFO size of 100 bits. I will try to cover this in another article.

Some of these articles may be helpful:
Delay generator using a counter.
Clock frequency converter in VHDL.

Simple vending machine using state machines in VHDL

2011-07-05T09:47:00.000+05:30

A state machine, is a model of behavior composed of a finite number of states, transitions between those states, and actions.It is like a "flow graph" where we can see how the logic runs when certain conditions are met. state machines are used to solve complicated problems by breaking them into many simple steps.
There are many articles available in the web regarding this topic. I found sequential circuit design pretty useful. If you are new to state machines I suggest you read that article before proceeding here.
In the above said article they have explained a simple vending machine problem and how to create a state machine diagram to solve it. I am not going much into the theory behind it. I have written the VHDL code for the Mealy model they have given. Refer to Fig 11.10 for this.

The VHDL code is given below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity vend_mach is
port( Clk : in std_logic;
x,y : out std_logic;
i,j : in std_logic
);
end vend_mach;

architecture Behavioral of vend_mach is

--type of state machine and signal declaration.
type state_type is (a,b,c);
signal next_s : state_type;

begin

process(Clk)
begin
if(rising_edge(Clk)) then
case next_s is
when a =>
if(i='0' and j='0') then
x <= '0';
y <= '0';
next_s <= a;
elsif(i='1' and j='0') then
x <= '0';
y <= '0';
next_s <= b;
elsif(i='1' and j='1') then
x <= '0';
y <= '0';
next_s <= c;
end if;
when b =>
if(i='0' and j='0') then
x <= '0';
y <= '0';
next_s <= b;
elsif(i='1' and j='0') then
x <= '0';
y <= '0';
next_s <= c;
elsif(i='1' and j='1') then
x <= '1';
y <= '0';
next_s <= a;
end if;
when c =>
if(i='0' and j='0') then
x <= '0';
y <= '0';
next_s <= c;
elsif(i='1' and j='0') then
x <= '1';
y <= '0';
next_s <= a;
elsif(i='1' and j='1') then
x <= '1';
y <= '1';
next_s <= a;
end if;
end case;
end if;
end process;

end Behavioral;

The testbench code tests the functionality of the code:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS

signal Clk,x,y,i,j : std_logic := '0';
constant Clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: entity work.vend_mach PORT MAP (
Clk => Clk,
x => x,
y => y,
i => i,
j => j
);

-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;

-- Stimulus process(applying inputs 'i' and 'j').
stim_proc: process
begin
wait for Clk_period*2;
i <= '0';j <= '0'; wait for Clk_period*2;
i <= '0';j <= '1'; wait for Clk_period*1;
i <= '1';j <= '0'; wait for Clk_period*1;
i <= '1';j <= '1'; wait for Clk_period*1;

i <= '0';j <= '0'; wait for Clk_period*1;
i <= '0';j <= '1'; wait for Clk_period*2;
i <= '1';j <= '1'; wait for Clk_period*1;
i <= '1';j <= '0'; wait for Clk_period*1;

i <= '0';j <= '0'; wait for Clk_period*1;
i <= '0';j <= '1'; wait for Clk_period*1;
i <= '1';j <= '1'; wait for Clk_period*1;
i <= '1';j <= '1'; wait for Clk_period*1;

i <= '1';j <= '0'; wait for Clk_period*2;
i <= '1';j <= '1'; wait for Clk_period*1;
wait;
end process;

END;

The simulation waveform is attached below. Carefully go through the various signal values to see how the flow works.

The code is synthesisable. To get a clear understanding of the concepts take another problem on state machines from web and write the vhdl code for it using state machines.

I have written some other articles related to state machines. You can browse through them here.

Non-synthesisable VHDL code for 8 point FFT algorithm

2011-06-27T22:46:00.000+05:30

A Fast Fourier Transform(FFT) is an efficient algorithm for calculating the discrete Fourier transform of a set of data. A DFT basically decomposes a set of data in time domain into different frequency components. DFT is defined by the following equation:

A FFT algorithm uses some interesting properties of the above formula to simply the calculations. You can read more about these FFT algorithms here.
Many students have been asking doubts regarding vhdl implementation of FFT, so I decided to write a sample code. I have selected 8 point decimation in time(DIT) FFT algorithm for this purpose. In short I have wrote the code for this flow diagram of FFT.
This is just a sample code, which means it is not synthesisable. I have used real data type for the inputs and outputs and all calculations are done using the math_real library. The inputs can be complex numbers too.
To define the basic arithmetic operations between two complex numbers I have defined some new functions which are available in the package named fft_pkg. The component named, butterfly , contains the basic butterfly calculations for FFT as shown in this flow diagram.
I wont be going any deep into the theory behind FFT here. Please visit the link given above or Google for in depth theory. There are 4 vhdl codes in the design,including the testbench code, and are given below.

The package file - fft_pkg.vhd:

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.MATH_REAL.ALL;

package fft_pkg is

type complex is
record
r : real;
i : real;
end record;

type comp_array is array (0 to 7) of complex;
type comp_array2 is array (0 to 3) of complex;

function add (n1,n2 : complex) return complex;
function sub (n1,n2 : complex) return complex;
function mult (n1,n2 : complex) return complex;

end fft_pkg;

package body fft_pkg is

--addition of complex numbers
function add (n1,n2 : complex) return complex is

variable sum : complex;

begin
sum.r:=n1.r + n2.r;
sum.i:=n1.i + n2.i;
return sum;
end add;

--subtraction of complex numbers.
function sub (n1,n2 : complex) return complex is

variable diff : complex;

begin
diff.r:=n1.r - n2.r;
diff.i:=n1.i - n2.i;
return diff;
end sub;

--multiplication of complex numbers.
function mult (n1,n2 : complex) return complex is

variable prod : complex;

begin
prod.r:=(n1.r * n2.r) - (n1.i * n2.i);
prod.i:=(n1.r * n2.i) + (n1.i * n2.r);
return prod;
end mult;

end fft_pkg;

The top level entity - fft8.vhd:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;
library work;
use work.fft_pkg.ALL;

entity fft8 is
port( s : in comp_array; --input signals in time domain
y : out comp_array --output signals in frequency domain
);
end fft8;

architecture Behavioral of fft8 is

component butterfly is
port(
s1,s2 : in complex; --inputs
w :in complex; -- phase factor
g1,g2 :out complex -- outputs
);
end component;

signal g1,g2 : comp_array := (others => (0.0,0.0));
--phase factor, W_N = e^(-j*2*pi/N) and N=8 here.
--W_N^i = cos(2*pi*i/N) - j*sin(2*pi*i/N); and i has range from 0 to 7.
constant w : comp_array2 := ( (1.0,0.0), (0.7071,-0.7071), (0.0,-1.0), (-0.7071,-0.7071) );

begin

--first stage of butterfly's.
bf11 : butterfly port map(s(0),s(4),w(0),g1(0),g1(1));
bf12 : butterfly port map(s(2),s(6),w(0),g1(2),g1(3));
bf13 : butterfly port map(s(1),s(5),w(0),g1(4),g1(5));
bf14 : butterfly port map(s(3),s(7),w(0),g1(6),g1(7));

--second stage of butterfly's.
bf21 : butterfly port map(g1(0),g1(2),w(0),g2(0),g2(2));
bf22 : butterfly port map(g1(1),g1(3),w(2),g2(1),g2(3));
bf23 : butterfly port map(g1(4),g1(6),w(0),g2(4),g2(6));
bf24 : butterfly port map(g1(5),g1(7),w(2),g2(5),g2(7));

--third stage of butterfly's.
bf31 : butterfly port map(g2(0),g2(4),w(0),y(0),y(4));
bf32 : butterfly port map(g2(1),g2(5),w(1),y(1),y(5));
bf33 : butterfly port map(g2(2),g2(6),w(2),y(2),y(6));
bf34 : butterfly port map(g2(3),g2(7),w(3),y(3),y(7));

end Behavioral;

Butterfly component - butterfly.vhd:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.fft_pkg.ALL;

entity butterfly is
port(
s1,s2 : in complex; --inputs
w :in complex; -- phase factor
g1,g2 :out complex -- outputs
);
end butterfly;

architecture Behavioral of butterfly is

begin

--butterfly equations.
g1 <= add(s1,mult(s2,w));
g2 <= sub(s1,mult(s2,w));

end Behavioral;

Testbench code - tb_fft8.vhd:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library work;
use work.fft_pkg.all;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS
signal s,y : comp_array;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: entity work.fft8 PORT MAP (
s => s,
y => y
);

-- Stimulus process
stim_proc: process
begin
--sample inputs in time domain.
s(0) <= (-2.0,1.2);
s(1) <= (-2.2,1.7);
s(2) <= (1.0,-2.0);
s(3) <= (-3.0,-3.2);
s(4) <= (4.5,-2.5);
s(5) <= (-1.6,0.2);
s(6) <= (0.5,1.5);
s(7) <= (-2.8,-4.2);
wait;
end process;

END;

Copy and paste the above codes into their respective files and simulate. You will get the output in the output signal 'y'. Once again, the code is not synthesisable.

Hope the codes are helpful for you. In case you want a synthesisable version of the codes or want a customized FFT vhdl code then contact me.

VHDL code for a 4 tap FIR filter

2011-06-25T22:08:00.000+05:30

Finite Impulse Response(FIR) filters are one of the two main type of filters available for signal processing. As the name suggests the output of a FIR filter is finite and it settles down to zero after some time. For a basic FAQ on FIR filters see this post by dspguru.

A FIR filter output, 'y' can be defined by the following equation:

Here, 'y' is the filter output, 'x' in the input signal and 'b' is the filter coefficients. 'N' is the filter order. The higher the value of N is, the more complex the filter will be.

For writing the code in VHDL I have referred to the paper, VHDL generation of optimized FIR filters , available online. You can say I have coded the exact block diagram available in the paper, "Figure 2".

This is a 4 tap filter. That means the order of the filter is 4 and so it has 4 coefficients. I have defined the input as signed type of 8 bits wide. The output is also of signed type with 16 bits width. The design contains two files. One is the main file with all multiplications and adders defined in it, and another for defining the D flip flop operation.

The main file is given below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity fir_4tap is
port( Clk : in std_logic; --clock signal
Xin : in signed(7 downto 0); --input signal
Yout : out signed(15 downto 0) --filter output
);
end fir_4tap;

architecture Behavioral of fir_4tap is

component DFF is
port(
Q : out signed(15 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
D :in signed(15 downto 0) -- Data input from the MCM block.
);
end component;

signal H0,H1,H2,H3 : signed(7 downto 0) := (others => '0');
signal MCM0,MCM1,MCM2,MCM3,add_out1,add_out2,add_out3 : signed(15 downto 0) := (others => '0');
signal Q1,Q2,Q3 : signed(15 downto 0) := (others => '0');

begin

--filter coefficient initializations.
--H = [-2 -1 3 4].
H0 <= to_signed(-2,8);
H1 <= to_signed(-1,8);
H2 <= to_signed(3,8);
H3 <= to_signed(4,8);

--Multiple constant multiplications.
MCM3 <= H3*Xin;
MCM2 <= H2*Xin;
MCM1 <= H1*Xin;
MCM0 <= H0*Xin;

--adders
add_out1 <= Q1 + MCM2;
add_out2 <= Q2 + MCM1;
add_out3 <= Q3 + MCM0;

--flipflops(for introducing a delay).
dff1 : DFF port map(Q1,Clk,MCM3);
dff2 : DFF port map(Q2,Clk,add_out1);
dff3 : DFF port map(Q3,Clk,add_out2);

--an output produced at every positive edge of clock cycle.
process(Clk)
begin
if(rising_edge(Clk)) then
Yout <= add_out3;
end if;
end process;

end Behavioral;

VHDL code for the component DFF is given below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity DFF is
port(
Q : out signed(15 downto 0); --output connected to the adder
Clk :in std_logic; -- Clock input
D :in signed(15 downto 0) -- Data input from the MCM block.
);
end DFF;

architecture Behavioral of DFF is

signal qt : signed(15 downto 0) := (others => '0');

begin

Q <= qt;

process(Clk)
begin
if ( rising_edge(Clk) ) then
qt <= D;
end if;
end process;

end Behavioral;

I have written a small test bench code for testing the design. It contains 8 test inputs which are serially applied to the filter module. See below:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS

signal Clk : std_logic := '0';
signal Xin : signed(7 downto 0) := (others => '0');
signal Yout : signed(15 downto 0) := (others => '0');
constant Clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: entity work.fir_4tap PORT MAP (
Clk => Clk,
Xin => Xin,
Yout => Yout
);

-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
wait for Clk_period*2;
Xin <= to_signed(-3,8); wait for clk_period*1;
Xin <= to_signed(1,8); wait for clk_period*1;
Xin <= to_signed(0,8); wait for clk_period*1;
Xin <= to_signed(-2,8); wait for clk_period*1;
Xin <= to_signed(-1,8); wait for clk_period*1;
Xin <= to_signed(4,8); wait for clk_period*1;
Xin <= to_signed(-5,8); wait for clk_period*1;
Xin <= to_signed(6,8); wait for clk_period*1;
Xin <= to_signed(0,8);

wait;
end process;

END;

The simulation waveform is given below:

The code is synthesisable and with a few changes can be ported for a higher order filter.

VHDL code for a simple ALU

2011-06-23T08:06:00.000+05:30

ALU(Arithmetic Logic Unit) is a digital circuit which does arithmetic and logical operations. Its a basic block in any processor.
In this article I have shared vhdl code for a simple ALU. Note that this is one of the simplest architecture of an ALU. Most of the ALU's used in practical designs are far more complicated and requires good design experience.
The block diagram of the ALU is given below. As you can see, it receives two input operands 'A' and 'B' which are 8 bits long. The result is denoted by 'R' which is also 8 bit long. The input signal 'Op' is a 3 bit value which tells the ALU what operation to be performed by the ALU. Since 'Op' is 3 bits long we can have 2^3=8 operations.

Our ALU is capable of doing the following operations:

ALU Operation	Description
Add Signed	R = A + B : Treating A, B, and R as signed two's complement integers.
Subtract Signed	R = A - B : Treating A, B, and R as signed two's complement integers.
Bitwise AND	R(i) = A(i) AND B(i).
Bitwise NOR	R(i) = A(i) NOR B(i).
Bitwise OR	R(i) = A(i) OR B(i).
Bitwise NAND	R(i) = A(i) NAND B(i).
Bitwise XOR	R(i) = A(i) XOR B(i).
Biwise NOT	R(i) = NOT A(i).

These functions are implemented using a case statement. The ALU calculates the outputs at every positive edge of clock cycle. As soon as the outputs are calculated it is available at the port signal 'R'. See the code below, to know how it is done:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity simple_alu is
port( Clk : in std_logic; --clock signal
A,B : in signed(7 downto 0); --input operands
Op : in unsigned(2 downto 0); --Operation to be performed
R : out signed(7 downto 0) --output of ALU
);
end simple_alu;

architecture Behavioral of simple_alu is

--temporary signal declaration.
signal Reg1,Reg2,Reg3 : signed(7 downto 0) := (others => '0');

begin

Reg1 <= A;
Reg2 <= B;
R <= Reg3;

process(Clk)
begin

if(rising_edge(Clk)) then --Do the calculation at the positive edge of clock cycle.
case Op is
when "000" =>
Reg3 <= Reg1 + Reg2; --addition
when "001" =>
Reg3 <= Reg1 - Reg2; --subtraction
when "010" =>
Reg3 <= not Reg1; --NOT gate
when "011" =>
Reg3 <= Reg1 nand Reg2; --NAND gate
when "100" =>
Reg3 <= Reg1 nor Reg2; --NOR gate
when "101" =>
Reg3 <= Reg1 and Reg2; --AND gate
when "110" =>
Reg3 <= Reg1 or Reg2; --OR gate
when "111" =>
Reg3 <= Reg1 xor Reg2; --XOR gate
when others =>
NULL;
end case;
end if;

end process;

end Behavioral;

The testbench code used for testing the ALU code is given below:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS

signal Clk : std_logic := '0';
signal A,B,R : signed(7 downto 0) := (others => '0');
signal Op : unsigned(2 downto 0) := (others => '0');
constant Clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: entity work.simple_alu PORT MAP (
Clk => Clk,
A => A,
B => B,
Op => Op,
R => R
);

-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
wait for Clk_period*1;
A <= "00010010"; --18 in decimal
B <= "00001010"; --10 in decimal
Op <= "000"; wait for Clk_period; --add A and B
Op <= "001"; wait for Clk_period; --subtract B from A.
Op <= "010"; wait for Clk_period; --Bitwise NOT of A
Op <= "011"; wait for Clk_period; --Bitwise NAND of A and B
Op <= "100"; wait for Clk_period; --Bitwise NOR of A and B
Op <= "101"; wait for Clk_period; --Bitwise AND of A and B
Op <= "110"; wait for Clk_period; --Bitwise OR of A and B
Op <= "111"; wait for Clk_period; --Bitwise XOR of A and B
wait;
end process;

END;

This is the simulation waveform:

The code is sythesisable. I haven't used std_logic_vector in this code. You can read this post to know why.

The block diagram was adopted from this original article. To make sure you have understood the concepts well, try implementing the block diagram given in the original article.

Using real data types in VHDL

2011-06-16T15:31:00.000+05:30

Apart from the standard types like integer and std_logic_vector's VHDL also offer real data types. But a real data type has a big disadvantage. It is not synthesis-able. It can be used only for simulation purposes. This disadvantage limits its use to a large extend, but there are plenty of projects where we look only for simulation results.

Before starting the coding part of a VHDL project,one has to decide whether the project to be implemented on a real FPGA or just a computer simulation is required. If it has to be ran on FPGA, then forget about the real package and use only synthesis-able data types like std_logic,integer etc... Otherwise you can reduce the time and complexity of your project by using real data types.

The real data type is defined in the library called MATH_REAL. So you have to include the following line before the entity declaration in the code:
use ieee.math_real.all;

The math_real package also offers some elementary mathematical functions for real data types. You can see the math_real.vhd file at the following address.

See the below code to get an idea on how to use these functions:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.MATH_REAL.ALL;

entity real_demo is
end real_demo;

architecture Behavioral of real_demo is

--signals declared with the REAL data type.
--MATH_PI is a constant defined in the math_real package.
signal X : real := -MATH_PI/3.0; --A real variable X, initialized to pi/3(60 degreee).
signal sign_result,ceil_result,floor_result,round_result,trunc_result : real := 0.0;
signal max,min,root,cube,power1,power2,exp_result : real := 0.0;
signal log_result,log2_result,log10_result,log_result2,sine,cosine,tangent : real := 0.0;
signal sin_inv,cos_inv,tan_inv,sin_hyp,cos_hyp,tan_hyp : real := 0.0;
signal inv_sin_hyp,inv_cos_hyp,inv_tan_hyp : real := 0.0;

begin

process
begin

sign_result <= SIGN(X); --sign of X
ceil_result <= CEIL(X); --smallest integer value not less than X
floor_result <= FLOOR(X); --largest integer value not greater than X
round_result <= ROUND(X); --round to the nearest integer.
trunc_result <= TRUNC(X); --truncation.
max <= REALMAX(4.5,4.6); --return the maximum
min <= REALMIN(2.3,3.2); --return the minimum
root <= SQRT(4.0); --square root
cube <= CBRT(64.0); --cube root
power1 <= 2**3.0; --power of an integer
power2 <= 3.0**3.0; --power of a real
exp_result <= EXP(1.0); --returns e**X.
log_result <= LOG(2.73); --natural logarithm
log2_result <= LOG2(16.0); --log to the base 2.
log10_result <= LOG10(100.0); --log to the base 10.
log_result2 <= LOG(27.0,3.0); --log to the given base.
sine <= SIN(X); --sine of the given angle(in rad)
cosine <= COS(X);--cosine of the given angle(in rad)
tangent <= TAN(X);--tangent of the given angle(in rad)
sin_inv <= ARCSIN(SIN(X)); --sine inverse.
cos_inv <= ARCCOS(COS(X)); --cosine inverse.
tan_inv <= ARCTAN(TAN(X)); --tangent inverse.
sin_hyp <= SINH(X); --Hyperbolic sine
cos_hyp <= COSH(X); --Hyperbolic cosine.
tan_hyp <= TANH(X); --Hyperbolic tangent.
inv_sin_hyp <= ARCSINH(SINH(X)); --Inverse hyperbolic sine.
inv_cos_hyp <= ARCCOSH(COSH(X)); --Inverse hyperbolic cosine.
inv_tan_hyp <= ARCTANH(TANH(X)); --Inverse hyperbolic tangent.
wait;

end process;

end Behavioral;

Almost all the functions available in the real package are shown above and comments are provided on what they are used for. For your reference I have attached the simulation result below:

As you can see its a pretty useful library. Dont forget to use it if you have a simulation project in VHDL. Contact me for any kind of help. I always use this package when I need to convert a matlab code to corresponding VHDL(for just simulation). Using this package, helps me to write the vhdl code like a pseudo code.

Clock Frequency converter in VHDL

2011-03-09T14:30:00.000+05:30

In FPGA designs, there are situations where you want a clock signal with a small frequency(or high time period). But in most of FPGA boards the frequency of the crystal oscillators available are of the range of tens of MHz.

One solution to the above problem is to take the high frequency clock available on board and convert it to a lower frequency clock. This is called frequency down conversion. I have shared a code here for a general purpose clock down converter.

The entity clk_gen takes a high frequency clock, Clk and an integer value divide_value as inputs and produces the converted clock at Clk_mod. The divide_value is defined as follows:

divide_value = (Frequency of Clk) / (Frequency of Clk_mod).

For example if you want to convert a 100 MHz signal into a 2 MHz signal then set the divide_value port as "50".

Without much further explanation I will give you the code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity clk_gen is
port( Clk : in std_logic;
Clk_mod : out std_logic;
divide_value : in integer
);
end clk_gen;

architecture Behavioral of clk_gen is

signal counter,divide : integer := 0;

begin

divide <= divide_value;

process(Clk)
begin
if( rising_edge(Clk) ) then
if(counter < divide/2-1) then
counter <= counter + 1;
Clk_mod <= '0';
elsif(counter < divide-1) then
counter <= counter + 1;
Clk_mod <= '1';
else
Clk_mod <= '0';
counter <= 0;
end if;
end if;
end process;

end Behavioral;

The testbench code used for testing the code is given below:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;

ENTITY testbench IS
END testbench;

ARCHITECTURE behavior OF testbench IS

signal clk,clk_mod : std_logic;
signal divide_value : integer;
constant clk_period : time := 10 ns;

begin
-- Component Instantiation
uut: entity work.clk_gen PORT MAP(
clk => clk,
clk_mod => clk_mod,
divide_value => divide_value );

simulate : process
begin
divide_value <= 10; --divide the input clock by 10 to get 10(100/10) MHz signal.
wait for 500 ns;
divide_value <= 19; --divide the input clock by 19 to get 5.3(100/19) MHz signal.
wait;
end process;

clk_process :process --generates a 100 MHz clock.
begin
clk <= '0';
wait for clk_period/2; --for 5 ns signal is '0'.
clk <= '1';
wait for clk_period/2; --for next 5 ns signal is '1'.
end process;

END;

Note :- The code was simulated and synthesised successfully using Xilinx Webpack version 13.1. It should work fine under other tools as well.

File reading and writing in VHDL - Part 2

2011-02-17T09:51:00.000+05:30

I have published a post on file reading and writing using VHDL before. You can access it here. As you know file manipulation will help you to verify your design more effectively at the debugging stage of your design.

For file operation we use the library named textio in the STD directory. This library contains the in built functions for reading and writing files.

Reading Files in VHDL:

The below code reads a set of binary numbers from the file named read.txt and put them into a 4 bit std_logic_vector signal. The text file used with the code can be downloaded from here.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use STD.textio.all; --Dont forget to include this library for file operations.

ENTITY read_file IS
END read_file;

ARCHITECTURE beha OF read_file IS

signal bin_value : std_logic_vector(3 downto 0):="0000";

BEGIN

--Read process
process
file file_pointer : text;
variable line_content : string(1 to 4);
variable line_num : line;
variable j : integer := 0;
variable char : character:='0';
begin
--Open the file read.txt from the specified location for reading(READ_MODE).
file_open(file_pointer,"C:\read.txt",READ_MODE);
while not endfile(file_pointer) loop --till the end of file is reached continue.
readline (file_pointer,line_num); --Read the whole line from the file
--Read the contents of the line from the file into a variable.
READ (line_num,line_content);
--For each character in the line convert it to binary value.
--And then store it in a signal named 'bin_value'.
for j in 1 to 4 loop
char := line_content(j);
if(char = '0') then
bin_value(4-j) <= '0';
else
bin_value(4-j) <= '1';
end if;
end loop;
wait for 10 ns; --after reading each line wait for 10ns.
end loop;
file_close(file_pointer); --after reading all the lines close the file.
wait;
end process;

end beha;

The above VHDL code can also be downloaded from here. I have commented the codes so that you can understand the flow of the code. The values read from the file are represented by a signal named bin_value. The simulation waveform is given below:

The main points to be noted are:

Declare file pointers and other variables required as given in the above code.
file_open() to open the file. Change the path of the file depending on where your file is stored.
Use read and readline functions.
Finally after everything is over, close the file using file_close.

Writing Files in VHDL:

The following code is used for writing a file. Remember that these codes contain just examples and depending on what you have to write to the file the code should be changed. The code writes binary numbers from 0000 to 1111 to a file named write.txt.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
use STD.textio.all;

ENTITY write_file IS
END write_file;

ARCHITECTURE beha OF write_file IS

BEGIN

--Write process
process
file file_pointer : text;
variable line_content : string(1 to 4);
variable bin_value : std_logic_vector(3 downto 0);
variable line_num : line;
variable i,j : integer := 0;
variable char : character:='0';
begin
--Open the file write.txt from the specified location for writing(WRITE_MODE).
file_open(file_pointer,"C:\write.txt",WRITE_MODE);
--We want to store binary values from 0000 to 1111 in the file.
for i in 0 to 15 loop
bin_value := conv_std_logic_vector(i,4);
--convert each bit value to character for writing to file.
for j in 0 to 3 loop
if(bin_value(j) = '0') then
line_content(4-j) := '0';
else
line_content(4-j) := '1';
end if;
end loop;
write(line_num,line_content); --write the line.
writeline (file_pointer,line_num); --write the contents into the file.
wait for 10 ns; --wait for 10ns after writing the current line.
end loop;
file_close(file_pointer); --Close the file after writing.
wait;
end process;

end beha;

The above code can also be downloaded from here. Any file writing code should have the following structure:

Declare file pointers and other variables required as given in the above code.
file_open() to open the file. Change the path of the file depending on where your file is stored.
Use write and writeline functions.
Finally after everything is over, close the file using file_close.

Note:- The codes are tested successfully using Xilinx Webpack 12.1. Note that file reading is a part of testbench design. In actual FPGA you cannot read or write files. But for functional verification of your design this is a must know.

Be careful when using functions in your code.

2011-02-16T15:53:00.000+05:30

There are many coding styles in VHDL where the code which work well in the simulation will not work on the actual fpga. In this article I am going to talk about one such RTL coding style.

As you know VHDL programmers normally use functions to represent combinational logic. But using functions every where without much thinking may result in dangerous bugs in the code. One perfect example is a function which replaces the code for a latch.

See the below code, which doesn't use a function:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test is
port( en1,a,Clk : in std_logic;
output : out std_logic );
end test;

architecture BEHAVIORAL of test is

begin

process(Clk)
begin
if ( rising_edge(Clk) ) then
if(en1 = '1') then
output <= a;
end if;
end if;
end process;

end BEHAVIORAL;

In the above code, whenever signal en1 goes high, at the positive edge of Clk we assign a to output port. We don't specify what will happen when the value of en1 is '0'. So basically the code results in a latch.
When synthesised, XST(Xilinx synthesis tool) uses a FDE flip flop for implementing the code. If you check the link pointed by FDE, you can see the truth table of FDE flip flop. As expected, it works like a latch. Whenever CE is '0' the flip flop retains the previous output.

Now I am going re-write the above code using functions. I will replace some part of the combinational logic inside the process with a function. See the code below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity test is
port( en1,a,Clk : in std_logic;
output : out std_logic );
end test;

architecture BEHAVIORAL of test is

function latch (en1,a : std_logic ) return std_logic is
variable output : std_logic := '0';
begin
if(en1 = '1') then
output := a;
end if;
return output;
end latch;

begin

process(Clk)
begin
if ( rising_edge(Clk) ) then
output <= latch(en1,a);
end if;
end process;

end BEHAVIORAL;

At the first look the above code is same as the first code. To confirm both has the same functionality, I simulated them. The outputs are matching. So they indeed work the same way in the simulation. But wait a minute. How about the synthesis results?

I ran XST for the above code and checked the technology viewer to see the synthesised circuit. What I saw was, instead of a FDE flipflop, XST used a FDR flipflop this time. Go to the link pointed by FDR and check the truth table given there. You can see that its not a latch. When R is '1' the flipflop output is reset to '0' rather than maintaining the previous value. So both the codes are going to work differently on board.

How did this happen? This is because all functions are synthesised into pure combinational logic by the synthesis tool. This means that you cannot go on using functions every where you want without proper brain storming. If you do, then the pre and post synthesis results may vary.

Note:- Both the codes where simulated and synthesized using Xilinx Webpack 12.1. The results may a vary a little depending on the tool you are using.

How to stop using "buffer" ports in VHDL?

2011-02-15T20:29:00.000+05:30

Buffer ports are used when a particular port need to be read and written. This mode is different from inout mode. The source of buffer port can only be internal. For example if you need a signal to be declared as output, but at the same time read it in the design, then declare it as buffer type.

But buffer types are not recommended by Xilinx and they say if it possible try to reduce the amount of buffer usage. According to Xilinx, buffers may give some problems during synthesis. If a signal is used internally and as an output port then in every level in your hierarchical design, it must be declared as a buffer. So let me show how to reduce the amount of buffer usage with an example.

The following code uses a buffer. I am not going through the functionality of the code since it is very simple.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity with_buffer is
port( A : in unsigned(3 downto 0);
B : in unsigned(3 downto 0);
Clk : in std_logic;
C : buffer unsigned(3 downto 0) );
end with_buffer;

architecture BEHAVIORAL of with_buffer is

begin

process(Clk)
begin
if ( rising_edge(Clk) ) then
C <= A + B + C;
end if;
end process;

end BEHAVIORAL;

As you can see the signal C is used repetitively in the addition, and also its an output of the module. So we declared it as a buffer. Another way to code this same functionality without a buffer is given below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity without_buffer is
port( A : in unsigned(3 downto 0);
B : in unsigned(3 downto 0);
Clk : in std_logic;
C : out unsigned(3 downto 0) );
end without_buffer;

architecture BEHAVIORAL of without_buffer is

--intermediate signal to avoid the use of buffer.s
signal C_dummy : unsigned(3 downto 0);

begin
C <= C_dummy; --Assign the intermediate signal to output port.

process(Clk)
begin
if ( rising_edge(Clk) ) then
C_dummy <= A + B + C_dummy; --Use the intermediate signal in actual calculation.
end if;
end process;

end BEHAVIORAL;

What I have done is, I used an intermediate or dummy signal inside the process statement. The value of C is read from this dummy signal named C_dummy. And outside the process we assign the value of C_dummy to the output port C. This is how we reduce the buffer usage in vhdl. Avoiding buffer usage is very useful particularly in case of hierarchical designs.

Note:- Both the codes were synthesised successfully using Xilinx Webpack 12.1. The results may or may not vary for Altera FPGA's.

Difference between C and VHDL

2011-02-12T23:30:00.000+05:30

It is normally said that once you learn one programming language it is pretty easy to learn the other programming languages. This is because the concepts are almost same in most of the programming languages with some only syntax differences.

But if you ask a hardware engineer, he may have a totally different opinion. If you dont stop thinking from a C programmer's perspective, then life as VHDL programmer will drive you nuts. Because both the languages have many differences between them. Both are different from the basic level itself, though they seem to have many similarities.

So let me compile some of the basic differences between C programming and VHDL programming.

C is a middle level language. I mean its a mix of a high level language and an assembly language.
VHDL is a hardware description language(HDL) . It is used for implementing the hardware circuit.
C can only handle sequential instructions.
VHDL allows both sequential and concurrent executions.
A C program can be successfully written with pure logical or algorithmic thinking.
But a successful VHDL programmer needs thorough working knowledge of the hardware circuits. He should be able to predict how a given code will be implemented in hardware.
Normally we don't care about resource usage in C. This is because a C program is usually ran on a computer which uses a powerful processor with high speed. We also don't care about the memory usage.
But when it comes to VHDL a slightly complicated code can make you bent on your knees. The memory and other logic elements are limited in a FPGA(where you normally put the VHDL code in). This is why it is very difficult to implement image processing algorithms in VHDL than in C.

These are some of the main points. If you have anything to add, feel free to add them in the comment section.

What is pipelining? Explanation with a simple example in VHDL.

2011-01-24T18:24:00.000+05:30

   A pipeline is a set of data processing elements connected in series, so that the output of one element is the input of the next one. In most of the cases we create a pipeline by dividing a complex operation into simpler operations. We can also say that instead of taking a bulk thing and processing it at once, we break it into smaller pieces and process it one after another.

   If you are aware of microprocessor architectures then you may know about instruction pipelining. In microprocessors for executing an instruction there are many intermediate stages like getting instruction from memory, decode the instruction, get any other required data from memory, process the data and finally write the result back to memory. Without a pipeline a single instruction has to fully go through all these stages before the next instruction is fetched from the memory. But if we apply the concept of pipelining in this case, when an instruction is fetched from memory, the previous instruction must have already decoded. Go through the wiki definition for instruction pipelining, if you are interested in knowing more about the background theory.

   In this article I am not going to implement an instruction pipeline. It is kind of complicated and I don't want to confuse readers who are just learning VHDL. The below VHDL code, simply(without pipelining) implements the equation (a*b*c*data_in). Note that a,b and c are constants here and the variable 'data_in' changes every clock cycle. The result of the calculation will be available at the port names 'data_out'.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity normal is
port (Clk : in std_logic;
data_in : in integer;
data_out : out integer;
a,b,c : in integer
);
end normal;

architecture Behavioral of normal is

signal data,result : integer := 0;

begin

data <= data_in;
data_out <= result;

--process for calcultation of the equation.
PROCESS(Clk,a,b,c,data)
BEGIN
if(rising_edge(Clk)) then
--multiplication is done in a single stage.
result <= a*b*c*data;
end if;
END PROCESS;

end Behavioral;

The above code is nothing simple and easy to understand. I have written the pipelined version of the same design. Check it below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;

entity pipelined is
port (Clk : in std_logic;
data_in : in integer;
data_out : out integer;
a,b,c : in integer
);
end pipelined;

architecture Behavioral of pipelined is

signal i,data,result : integer := 0;
signal temp1,temp2 : integer := 0;

begin

data <= data_in;
data_out <= result;

--process for calcultation of the equation.
PROCESS(Clk)
BEGIN
if(rising_edge(Clk)) then
--Implement the pipeline stages using a for loop and case statement.
--'i' is the stage number here.
--The multiplication is done in 3 stages here.
--See the output waveform of both the modules and compare them.
for i in 0 to 2 loop
case i is
when 0 => temp1 <= a*data;
when 1 => temp2 <= temp1*b;
when 2 => result <= temp2*c;
when others => null;
end case;
end loop;
end if;
END PROCESS;

end Behavioral;

So what have I done different? Our design required 3 multiplications and in the normal version I did it all at once. But if you see the above code, I am doing it stepwise. The equation was broken down into 3 different multiplications and each operation is done on a different clock edge. If you are wondering about the difference between the two codes see the RTL schematic of the two designs:

Normal code(without pipelining)

Pipelined code-check the extra flip flops

   As you can see, the normal code is implemented by connecting 3 multipliers in a cascaded fashion with a flip flop at the end stage. For the pipelined code, we have flip flops after each multiplier. What does this mean? The extra flip flops reduces the delay through the combinatorial logic and hence pipelined code can operate at a higher frequency than the normal code.

   The 'normal' code takes less time to write and is mostly straight forward. But if you want your design to offer the highest speed possible, you have to think out of the box! The 'pipelined' code is little bit complicated to write. In this case we had to use case statements and a for loop to implement a small equation. But it gives higher speed. In large projects pipelined designs are very important for some blocks since it may act as a bottleneck for the performance of the whole design.

   On the other side there is a small disadvantage for pipelined designs. They introduce a small number of delay between input and output, in terms of clock cycle. For instance we have 3 stages in the pipelined code and hence the output comes only after 3 clock cycles, after the input is applied. But this disadvantage usually doesn't matter in most of the designs since after 3 clock cycles we can get continuous stream of output. This delay can be seen if you check the simulation waveforms of the two designs:

waveform for normal code-no delay at all.

waveform for pipelined code-3 clock cycle delay.

The testbench code used for testing the designs is given below. Remember to change the component name if you want to test the 'normal' entity.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;

-- entity declaration for your testbench.Dont declare any ports here
ENTITY test_tb IS
END test_tb;

ARCHITECTURE behavior OF test_tb IS

--declare inputs and initialize them
signal clk : std_logic := '0';
signal data_in,data_out,a,b,c : integer := 0;
-- Clock period definitions
constant clk_period : time := 10 ns;

BEGIN
-- Instantiate the Unit Under Test (UUT)
--Change the entity name below if you want to test the 'normal' entity.
uut: entity work.pipelined port map (Clk => Clk,
data_in => data_in,
data_out => data_out,
a => a,
b => b,
c => c
);

a <= 1;
b <= 2;
c <= 5;

-- Clock process definitions( clock with 50% duty cycle is generated here.
clk_process :process
begin
clk <= '0';
wait for clk_period/2; --for 5 ns signal is '0'.
clk <= '1';
wait for clk_period/2; --for next 5 ns signal is '1'.
end process;

-- Stimulus process
stim_proc: process
begin
wait for Clk_period;
data_in <= 1;
wait for Clk_period;
data_in <= 2;
wait for Clk_period;
data_in <= 3;
wait for Clk_period;
data_in <= 4;
wait for Clk_period;
data_in <= 5;
wait for Clk_period;
data_in <= 6;
wait for Clk_period;
data_in <= 7;
wait for Clk_period;
data_in <= 8;
wait for Clk_period;
data_in <= 9;
wait;
end process;

END behavior;

Note:- The codes where designed and tested using the Xilinx Webpack version 12.1. The codes are also synthesisable. They should work with other tools too.

If the design is complex, then always identify and break down it into smaller steps. And implement it in using the pipeline concept. This will increase the maximum clock frequency, reduce the time to synthesis the code and will also increase the throughput of the system.

Block and distributed RAM's on Xilinx FPGA's

2011-01-23T01:18:00.000+05:30

Distributed RAM's:

The configuaration logic blocks(CLB) in most of the Xilinx FPGA's contain small single port or double port RAM. This RAM is normally distributed throughout the FPGA than as a single block(It is spread out over many LUT's) and so it is called "distributed RAM". A look up table on a Xilinx FPGA can be configured as a 16*1bit RAM , ROM, LUT or 16bit shift register. This multiple functionality is not possible with Altera FPGA's.

For Spartan-3 series, each CLB contains upto 64 bits of single port RAM or 32 bits of dual port RAM. As indicated from the size, a single CLB may not be enough to implement a large memory. Also the most of this small RAM's have their input and output as 1 bit wide. For implementing larger and wider memory functions you can connect several distributed RAM's in parallel. Fortunately you need not know how these things are done, because the Xilinx synthesiser tool will infer what you want from your VHDL/ Verilog code and automatically does all this for you.

Block RAM's:

A block RAM is a dedicated (cannot be used to implement other functions like digital logic) two port memory containing several kilobits of RAM. Depending on how advance your FPGA is there may be several of them. For example Spartan 3 has total RAM, ranging from 72 kbits to 1872 kbits in size.While Spartan 6 devices have block RAM's of upto 4824 Kbits in size.

Difference between Distributed and Block RAM's:

As you can see from the definition distributed RAM, a large sized RAM is implemented using a parallel array of large number of elements. This makes distributed RAM, ideal for small sized memories. But when comes to large memories, this may cause a extra wiring delays.
But Block RAM's are fixed RAM modules which comes in 9 kbits or 18 kbits in size. If you implement a small RAM with a block RAM then its wastage of the rest of the space in RAM.
So use block RAM for large sized memories and distributed RAM for small sized memories or FIFO's.
Another notable difference is how they are operated. In both, the WRITE operation is synchronous(data is written to ram only happens at rising edge of clock). But for the READ operation, distributed RAM is asynchronous (data is read from memory as soon as the address is given, doesn't wait for the clock edge) and block RAM is synchronous.

How to tell XST which type of RAM you want to use?

When you declare a RAM in your code, XST(Xilinx synthesizer tool) may implement it as either block RAM or distributed RAM. But if you want, you can force the implementation style to use block RAM or distributed RAM resources. This is done using the ram_style constraint. See the following code to understand how it is done:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity ram_example is
port (Clk : in std_logic;
address : in integer;
we : in std_logic;
data_i : in std_logic_vector(7 downto 0);
data_o : out std_logic_vector(7 downto 0)
);
end ram_example;

architecture Behavioral of ram_example is

--Declaration of type and signal of a 256 element RAM
--with each element being 8 bit wide.
type ram_t is array (0 to 255) of std_logic_vector(7 downto 0);
signal ram : ram_t := (others => (others => '0'));

begin

--process for read and write operation.
PROCESS(Clk)
BEGIN
if(rising_edge(Clk)) then
if(we='1') then
ram(address) <= data_i;
end if;
data_o <= ram(address);
end if;
END PROCESS;

end Behavioral;

The above code declares and defines a single port RAM. Code is also written to specify how the read and write process is implemented. when we synthesis this design, XST uses the block RAM resources by default for implementing the memory. In certain cases you may want to change it. For instance, if I want the memory to be implemented using distributed RAM then add the following two lines before the begin statement in the architecture section:

attribute ram_style: string;

attribute ram_style of ram : signal is "distributed";

Here ram is the signal name. By changing the word distributed to block we can force XST to use block RAM resources. The default value of the attribute ram_style is Auto.

Notes:- The code was synthesized successfully using Xilinx Webpack version 12.1. The results may vary if you are using an older version of the XST.

Implementation of stack in VHDL

2011-01-13T12:16:00.000+05:30

I have been getting some requests for a Stack implementation in VHDL. This article is for all those readers.

A stack is simply a Last In First Out(LIFO) memory structure. Every stack has a stack pointer(SP) which acts as an address for accessing the elements. But normally the user of the stack is not concerned with the absolute address of the stack, he is only concerned with the PUSH and POP instructions. I am not going into theory of stack in detail, but for some basics check the wikipedia stack page.

There are basically 4 types of stacks:

Empty descending - Stack pointer(SP) points to the address where you can push the latest data. And after pushing the data, stack pointer(SP) is reduced by one till it becomes zero. Stack grows downwards here.
Empty ascending - Same as type (1) , but stack grows upwards here. After the PUSH operation, SP is incremented by one.
Fully descending - SP points to the last data which is pushed.Stack grows downward.
Fully ascending - SP points to the last data which is pushed, but stack grows upward here.

Out of the above 4 types I have implemented the first type, Empty descending in VHDL. The depth of the stack is 256 and width is 16 bits. That means using a single PUSH or POP operation you can only store or retrieve a maximum of 16 bits. Also the maximum number of elements which can be stored in the stack are 256. Of course, with a small edit you can change the width and depth of the stack. Check out the code below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity stack is
port( Clk : in std_logic; --Clock for the stack.
Enable : in std_logic; --Enable the stack. Otherwise neither push nor pop will happen.
Data_In : in std_logic_vector(15 downto 0); --Data to be pushed to stack
Data_Out : out std_logic_vector(15 downto 0); --Data popped from the stack.
PUSH_barPOP : in std_logic; --active low for POP and active high for PUSH.
Stack_Full : out std_logic; --Goes high when the stack is full.
Stack_Empty : out std_logic --Goes high when the stack is empty.
);
end stack;

architecture Behavioral of stack is

type mem_type is array (255 downto 0) of std_logic_vector(15 downto 0);
signal stack_mem : mem_type := (others => (others => '0'));
signal stack_ptr : integer := 255;
signal full,empty : std_logic := '0';

begin

Stack_Full <= full;
Stack_Empty <= empty;

--PUSH and POP process for the stack.
PUSH : process(Clk,PUSH_barPOP,Enable)
begin
if(rising_edge(Clk)) then
--PUSH section.
if (Enable = '1' and PUSH_barPOP = '1' and full = '0') then
--Data pushed to the current address.
stack_mem(stack_ptr) <= Data_In;
if(stack_ptr /= 0) then
stack_ptr <= stack_ptr - 1;
end if;
--setting full and empty flags
if(stack_ptr = 0) then
full <= '1';
empty <= '0';
elsif(stack_ptr = 255) then
full <= '0';
empty <= '1';
else
full <= '0';
empty <= '0';
end if;

end if;
--POP section.
if (Enable = '1' and PUSH_barPOP = '0' and empty = '0') then
--Data has to be taken from the next highest address(empty descending type stack).
if(stack_ptr /= 255) then
Data_Out <= stack_mem(stack_ptr+1);
stack_ptr <= stack_ptr + 1;
end if;
--setting full and empty flags
if(stack_ptr = 0) then
full <= '1';
empty <= '0';
elsif(stack_ptr = 255) then
full <= '0';
empty <= '1';
else
full <= '0';
empty <= '0';
end if;

end if;

end if;
end process;

end Behavioral;

Let me explain little bit about the code. For using this stack entity in your project you need to apply a clock signal to the port Clk. For either PUSH or POP operation to happen, you have make the Enable signal high. Data can be pushed into the stack by applying the data at the Data_In port with '1' on the PUSH_barPOP port. Data can be popped from the stack by applying a '0' on the PUSH_barPOP port. The popped data will be available on the Data_Out port.
I have also included two status signals so that you can manage the stack better. Stack_Full goes high when the stack is full, and Stack_Empty goes high when there is no data available in the stack. The Enable signal should be controlled by checking these status signals so that stack overflow doesn't happen.

For testing the code I have written a testbench which I am sharing here:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY stack_tb IS
END stack_tb;

ARCHITECTURE behavior OF stack_tb IS
--Inputs and outputs
signal Clk,Enable,PUSH_barPOP,Stack_Full,Stack_Empty : std_logic := '0';
signal Data_In,Data_Out : std_logic_vector(15 downto 0) := (others => '0');
--temporary signals
signal i : integer := 0;
-- Clock period definitions
constant Clk_period : time := 10 ns;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: entity work.stack PORT MAP (
Clk => Clk,
Enable => Enable,
Data_In => Data_In,
Data_Out => Data_Out,
PUSH_barPOP => PUSH_barPOP,
Stack_Full => Stack_Full,
Stack_Empty => Stack_Empty
);

-- Clock process definitions
Clk_process :process
begin
Clk <= '0';
wait for Clk_period/2;
Clk <= '1';
wait for Clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
wait for clk_period*3; --wait for 3 clock periods(simply)
Enable <= '1'; --Enable the stack.
PUSH_barPOP <= '1'; --Set for push operation.
for i in 0 to 255 loop --Push integers from 0 to 255 to the stack.
Data_In <= conv_std_logic_vector(i,16);
wait for clk_period;
end loop;
Enable <= '0'; --disable the stack.
wait for clk_period*2;
Enable <= '1'; --re-enable the stack.
PUSH_barPOP <= '0'; --Set for POP operation.
for i in 0 to 255 loop --POP all elements from stack one by one.
wait for clk_period;
end loop;
Enable <= '0'; --Disable stack.

wait for clk_period*3;
Enable <= '1'; --Enable stack
PUSH_barPOP <= '1'; --Set for push operation.
Data_In <= X"FFFF"; --Push 65535 to stack.
wait for clk_period;
Data_In <= X"7FFF"; --Push 32767 to stack.
wait for clk_period;
PUSH_barPOP <= '0'; --POP the above pushed values.
wait for clk_period*2;
Enable <= '0';

wait;
end process;

END;

I am not including a waveform file because it is too lengthy to put up as a single image. The above codes where tested succussfully using the Xilinx Webpack 12.1. The code is also synthesisable.

Just as a side note, I got a More than 100% resources used error when I tried to synthesis the code for spartan 3. But for spartan 6 devices, there is no such error. So always check whether your device can handle this design. Usage of resources can also be decreased by using a less width and depth for the stack.

If you need variations of this stack design contact me. I help students to get their coding work done for a fee. Also I suggest for learning purposes, you implement the other 3 types of stacks too in VHDL.

Some more clarification on "Signal changing at both clock edges" matter

2011-01-10T18:12:00.000+05:30

Sorry for not posting for a long time. Recently I received a comment on one of my old posts which answers the question Can you change a signal at both positive and negative edges of the clock.

In the above post I said that a signal cannot be changed both at positive and negative edges. Basically the code will not synthesis. After reading the post,one of my reader, Arseni posted the following comment.

This post is an answer to his question. For making it a general case I have slightly changed the code Arseni posted. Here it is:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity test is
port (A : in std_logic;
B,D : in std_logic_vector(3 downto 0);
C : out std_logic_vector(3 downto 0)
);
end test;

architecture Behavioral of test is

begin

PROCESS(A, B)
BEGIN
if A = '1' then
C <= B;
else
C <= D;
end if;
END PROCESS;

end Behavioral;

In the code whenever the value of signal A is '1' B is assigned to C, otherwise D is assigned to C.
As the commenter indicates the signal C is changed irrespective of the value of A(whether it is low or high) here. So why did this code synthesis properly?

Because if you closely watch you can notice that the C is changed based on the level value of the signal A. 'C' is not changed by checking whether the value of 'A' changes from 1 to 0 or 0 to 1. It is concerned with only the value(whether it is 0 or 1). That means a flip flop is not used for synthesising the behavioral code given above.

The rule a signal cannot be changed at both clock edges is for edge triggered actions. Which means the output is through a flip flop and some kind of additional combinatorial logic.

In the code given above, the synthesis only uses some LUT-2 components. Its doesnt use any flip flops.

Note :- The code is simulated and synthesised successfully using the Xilinx ISE 12.1. But it will mostly work with other tools too.

Tips for running a successful simulation in Xilinx ISim.

2010-12-04T11:03:00.000+05:30

Though I have given enough examples for learning VHDL I didn't write much about using the software till now. In this article I will cover some basics about running your simulation in Xilinx ISim. This article will point out some basic mistakes people do when simulating their code in ISim.
For explaining, I have just used one of my earlier example in the post : Explaining testbench code using a counter design. Lets go step by step, see the images for easier understanding of the steps. Open the images in a new tab in your browser if they are not clear enough.

1)Once the coding is done( I mean both the testbench and the design to be tested) make sure you select the top entity(testbench code) in the Xilinx window as shown below. Many people just select any other file and click the compilation button.
Note down the red markings in the image below. Points to be noted are:

Choose View as simulation.
Select the top entity i.e. the testbench. If the wrong file is selected for simulation then the waveform in ISim will be blank and you will see no waveform.
Double click on the Behavioral check syntax for compiling the design or for finding out any syntax errors.
If the above step is successful then double click on Simulate Behavioral Model. If there are syntax errors in step 3 then you may have to check your code.

2)Now ISim will open in a new window with waveforms. Note down the toolbar at the bottom. Check the below image for knowing what each button does. You can also hover your mouse over the button and they will display the function of that button.

3)Mostly the signals in the wavforms will be displayed as binary numbers or integers. But you can change this basic setting. See the image below.

Click on the signal which you want to change the display format. Go to radix and then select the format. Some options available are Binary, Hexadecimal, octal etc. Note that depending on your code , you have to change the display format. My code was a counter, so unsigned decimal was the best format in this case.

4)Another interesting thing you can do is adding the internal signals to the waveform which is not displayed by default. By default ISim displays only the signals which are declared in the testbench code. But if there are many sub entities then you may need to see them for debugging purpose. See the image below for how to do it.

Go to the Instance and process names on the left side of the ISim window.
Select the Instance name whose internal signals you want to observe.
All the signals declared in that particular instance will be displayed on the immediate right tab now, under simulation objects.
Now select the signals you want to display. You can use keyboard short cuts like shift and Ctrl for selecting multiple signal names.
Now drag and drop these select signals into the immediate right tab under signal Name in waveform window.
For updating these signal values you have to restart the simulation and run it again.

5)You may have noticed that in ISim, all the additional signals you added in step (4) are reset when you close the ISim window. This is little bit annoying since you have to add all the internal signals again. But you need not worry about it. Follow the steps:

Add the required signals into the waveform as described in step 4.
Save the waveform file by clicking, Ctrl + S . Give an appropriate name to the wave file.
Now close ISim and go back to the Xilinx ISE window.
Right click on simulate behavioral model.
Choose the option Process properties.
A new window will open as shown below in the image.
Select the check box, Use custom waveform configuration file.
Choose the waveform file you just saved in the custom waveform configuration file.

Thats it for now. Hope these explain the things better. Thanks.

Synthesis Error : Wait for statement unsupported.

2010-11-08T08:42:00.000+05:30

This article is written as per the request of one of my readers who had some problem trying out the code given in this website. You may have seen this error in Xilinx ISE, "Wait for statement unsupported". And you may have wondered why the error is coming even after you are sure of writing a syntactically correct VHDL code.
Check out the below code. It is just a testbench plus design code for full adder. As you can see we have 3 input bits and we apply all the 8 combinations of inputs with a 1 ns delay between them. For applying this delay we use the "wait for" statement. This is supported by VHDL.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY tb IS
END tb;

ARCHITECTURE behavior OF tb IS
--Inputs
signal bit1 : std_logic := '0';
signal bit2 : std_logic := '0';
signal bit3 : std_logic := '0';
--Outputs
signal sum : std_logic;
signal carry : std_logic;

BEGIN

--Gates
gate_inst : process
begin
sum <= bit1 xor bit2 xor bit3;
carry <= (bit1 and bit2) or (bit3 and bit2) or (bit1 and bit3);
wait for 1 ns;
end process;

-- Stimulus process
stim_proc: process
begin
bit1<='0'; bit2<='0'; bit3<='0'; wait for 1 ns;
bit1<='0'; bit2<='0'; bit3<='1'; wait for 1 ns;
bit1<='0'; bit2<='1'; bit3<='0'; wait for 1 ns;
bit1<='0'; bit2<='1'; bit3<='1'; wait for 1 ns;
bit1<='1'; bit2<='0'; bit3<='0'; wait for 1 ns;
bit1<='1'; bit2<='0'; bit3<='1'; wait for 1 ns;
bit1<='1'; bit2<='1'; bit3<='0'; wait for 1 ns;
bit1<='1'; bit2<='1'; bit3<='1'; wait for 1 ns;
wait;
end process;

END;

   Now when you synthesize this code you will get the above mentioned error. This is just because of the simple fact that all VHDL codes which are syntactically right are need not synthesisable. Synthesis is the process of converting the logic described by your code in terms of actual digital circuit components.A statement like "wait for 1 ns" cannot be described in terms of real hardware and hence it is not synthesisable.
   You may ask why then such a keyword is available if it is not synthesisable.The reason is that there are plenty of situations where you just want to simulate( use the simulation software in your PC for verification, not running it in real FPGA hardware) the design. In those situations "wait for" statement is very useful, especially in case of testbench codes.
   Also, sometimes when you add a new source in Xilinx ISE ( i think versions after 12.1) its default property "View Association" is set as "Implementation".This makes the file invisible in the "simulation" mode in ISE. Once you change this "View association" to "All" the file will be visible under all the views. For this right click on the file name in Xilinx ISE window and click on "source properties". You can see the "View Association" option now. Now do "Behavioral Check syntax" under the "Simulation" view. The errors must have gone now.

I hope the things are clear now.

Sequence detector using state machine in VHDL

2010-10-31T18:37:00.000+05:30

Some readers were asking for more examples related with state machine and some where asking for codes related with sequence detector.This article will be helpful for state machine designers and for people who try to implement sequence detector circuit in VHDL.
I have created a state machine for non-overlapping detection of a pattern "1011" in a sequence of bits. The state machine diagram is given below for your reference.

The VHDL code for the same is given below. I have added comments for your easy understanding.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--Sequence detector for detecting the sequence "1011".
--Non overlapping type.
entity seq_det is
port( clk : in std_logic; --clock signal
reset : in std_logic; --reset signal
seq : in std_logic; --serial bit sequence
det_vld : out std_logic --A '1' indicates the pattern "1011" is detected in the sequence.
);
end seq_det;

architecture Behavioral of seq_det is

type state_type is (A,B,C,D); --Defines the type for states in the state machine
signal state : state_type := A; --Declare the signal with the corresponding state type.

begin

process(clk)
begin
if( reset = '1' ) then --resets state and output signal when reset is asserted.
det_vld <= '0';
state <= A;
elsif ( rising_edge(clk) ) then --calculates the next state based on current state and input bit.
case state is
when A => --when the current state is A.
det_vld <= '0';
if ( seq = '0' ) then
state <= A;
else
state <= B;
end if;
when B => --when the current state is B.
if ( seq = '0' ) then
state <= C;
else
state <= B;
end if;
when C => --when the current state is C.
if ( seq = '0' ) then
state <= A;
else
state <= D;
end if;
when D => --when the current state is D.
if ( seq = '0' ) then
state <= C;
else
state <= A;
det_vld <= '1'; --Output is asserted when the pattern "1011" is found in the sequence.
end if;
when others =>
NULL;
end case;
end if;
end process;

end Behavioral;

If you check the code you can see that in each state we go to the next state depending on the current value of inputs.So this is a mealy type state machine.
The testbench code used for testing the design is given below.It sends a sequence of bits "1101110101" to the module. The code doesnt exploit all the possible input sequences. If you want another sequence to be checked then edit the testbench code. If it is not working as expected, let me know.

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY blog_cg IS
END blog_cg;

ARCHITECTURE behavior OF blog_cg IS

signal clk,reset,seq,det_vld : std_logic := '0';
constant clk_period : time := 10 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: entity work.seq_det PORT MAP (
clk => clk,
reset => reset,
seq => seq,
det_vld => det_vld
);

-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process : Apply the bits in the sequence one by one.
stim_proc: process
begin
seq <= '1'; --1
wait for clk_period;
seq <= '1'; --11
wait for clk_period;
seq <= '0'; --110
wait for clk_period;
seq <= '1'; --1101
wait for clk_period;
seq <= '1'; --11011
wait for clk_period;
seq <= '1'; --110111
wait for clk_period;
seq <= '0'; --1101110
wait for clk_period;
seq <= '1'; --11011101
wait for clk_period;
seq <= '0'; --110111010
wait for clk_period;
seq <= '1'; --1101110101
wait for clk_period;
wait;
end process;

END;

The simulated waveform is shown below:

Note:- The code was simulated using Xilinx 12.1 version. The results may vary slightly depending on your simulation tool.