tag:blogger.com,1999:blog-20509621764043057052021-04-16T18:55:52.591+05:30VHDL coding tips and tricksGet interesting tips and tricks in VHDL programmingvipinhttp://www.blogger.com/profile/17675762038225600067noreply@blogger.comBlogger132110VhdlCodingTipsAndTrickshttps://feedburner.google.comtag:blogger.com,1999:blog-2050962176404305705.post-31720800074198325022020-12-20T17:57:00.003+05:302020-12-20T18:28:33.666+05:30Image Processsing: RGB to Gray scale Converter in VHDL Implementing image processing algorithms in VHDL is a scary thing for many. Though I agree that its much more difficult to do it in VHDL than in a high level programming language like C, Matlab etc, it needn't be that scary.
In this post I am going to share the code for a simple image processing algorithm - A RGB to Gray scale image converter.
There are many ways, from simple to complex, in which you can do this. I have done it in a way, which makes sense to me. Touching upon few topics related to this subject. For example reading the image data from a text file, storing it in RAM and accessing the data within the code and then manipulating them etc...
I have used the standard Matlab image Lenna.bmp for this. The original image was 512*512*3 pixels in size. This takes a long time to load and run in Modelsim. So I first reduced its size to 1/8th of its original size, making it a 64*64*3 pixel image. Each pixel...<br/>
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[[ This is a content summary only. Visit my website for full links, other content, and more! ]]<img src="http://feeds.feedburner.com/~r/VhdlCodingTipsAndTricks/~4/sLRqxu3JYcc" height="1" width="1" alt=""/>vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com0http://vhdlguru.blogspot.com/2020/12/image-processsing-rgb-to-gray-scale.htmltag:blogger.com,1999:blog-2050962176404305705.post-38778733134471916592020-12-08T22:57:00.003+05:302020-12-08T22:57:35.453+05:30Synthesizable Clocked Square Root Calculator In VHDL Long back I had shared VHDL function for finding the square root of a number. This function too was synthesisable, but as it was a function, it was purely combinatorial. If you want to find the square root of a relatively larger number, then the resource usage was very high.
In such cases, it makes sense to use a clocked design. Such a clocked design enables us to reuse one set of resources over and over. The advantage of such a design is that it uses far less resources while the disadvantage being the low speed.
For example, in the design I have shared in this post, to find the square root of a N-bit number, you need to wait N/2 clock cycles.
The code is written based on Figure (8) from this paper: A New Non-Restoring Square Root Algorithm and Its VLSI Implementations.
The codes are well commented, so I wont write much about how it works here. Please refer to the block diagram from...<br/>
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[[ This is a content summary only. Visit my website for full links, other content, and more! ]]<img src="http://feeds.feedburner.com/~r/VhdlCodingTipsAndTricks/~4/qxy4JtZcgf0" height="1" width="1" alt=""/>vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com0http://vhdlguru.blogspot.com/2020/12/synthesizable-clocked-square-root.htmltag:blogger.com,1999:blog-2050962176404305705.post-27070595734166962262020-12-07T19:22:00.000+05:302020-12-07T19:22:44.961+05:30Synthesizable Polynomial Equation Calculator in VHDL A polynomial equation is an equation which is formed with variables, coefficients and exponents. They can be written in the following format:
y =anxn + an-1xn-1 + ... +a1x + a0 .
Here an, an-1 ... , a1 ,a0 are coefficients,
n, n-1, ... etc are exponents and x is the variable.
In this post, I want to share, VHDL code for computing the value of 'y' if you know the value of 'x' and coefficients forming the polynomial.
Directly calculating the polynomial with the above equation is very inefficient. So, first we reformat the equation as per Horner's rule:
y =(((anx + an-1)x + an-2)x + an-3)x + ... )x +a0 .
This modified equation can...<br/>
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[[ This is a content summary only. Visit my website for full links, other content, and more! ]]<img src="http://feeds.feedburner.com/~r/VhdlCodingTipsAndTricks/~4/V0frmzAxWHo" height="1" width="1" alt=""/>vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com0http://vhdlguru.blogspot.com/2020/12/synthesizable-polynomial-equation.htmltag:blogger.com,1999:blog-2050962176404305705.post-6488638644140364222020-12-05T13:08:00.002+05:302020-12-05T13:08:51.232+05:30Generic VHDL Code for Binary to Gray and Gray to Binary converter Few years back I had written a 4 bit converter for conversion between Gray and Binary codes. After receiving much positive response I decided to write a generic version of the same.
Let me share the codes...Binary to Gray Code...<br/>
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[[ This is a content summary only. Visit my website for full links, other content, and more! ]]<img src="http://feeds.feedburner.com/~r/VhdlCodingTipsAndTricks/~4/cxpxLRmjCbU" height="1" width="1" alt=""/>vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com0http://vhdlguru.blogspot.com/2020/12/generic-vhdl-code-for-binary-to-gray.htmltag:blogger.com,1999:blog-2050962176404305705.post-80140564940726296242020-11-29T11:02:00.000+05:302020-11-29T11:02:11.654+05:30Writing a Gate Level VHDL design (and Testbench) from Scratch In this video I want to show you how you can take a logic circuit diagram and write the corresponding VHDL code along with its testbench.
The VHDL codes presented in the video are given below:xor_gate.vhd:
library ieee;
use ieee.std_logic_1164.all;
entity xor_gate is
port (
A,B : in std_logic;
C : out std_logic
);
end entity;
architecture gate_level of xor_gate is
signal An,Bn,t1,t2 : std_logic := '0';
begin
An <= not A;
Bn <= not B;
t1 <= An and B;
t2 <= Bn and A;
C <= t1 or t2;
end architecture;
tb_xor.vhd:
library ieee;
use ieee.std_logic_1164.all;
entity tb_xor is
end entity;
architecture behav of tb_xor is
component xor_gate is
port (
A,B : in std_logic;
C : out std_logic
);
end component;
signal A,B,C : std_logic := '0';
begin
UUT : xor_gate port map (A,B,C);
stimulus : process
begin
A <= '0';
B <= '0';
wait for 100 ns;
A <= '0';
B <= '1';
...<br/>
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[[ This is a content summary only. Visit my website for full links, other content, and more! ]]<img src="http://feeds.feedburner.com/~r/VhdlCodingTipsAndTricks/~4/lorgVkxYLPM" height="1" width="1" alt=""/>vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com0http://vhdlguru.blogspot.com/2020/11/writing-gate-level-vhdl-design-and.htmltag:blogger.com,1999:blog-2050962176404305705.post-61598215431317787482020-11-28T10:55:00.001+05:302020-11-28T10:55:44.091+05:30Synthesizable Matrix Multiplier in VHDL Long back I had posted a simple matrix multiplier which works well in simulation but couldn't be synthesized. But many people had requested for synthesizable version of this code. So here we go.
The design takes two matrices of 3 by 3 and outputs a matrix of 3 by 3. Each element is stored as unsigned 8 bits. This is not a generic multiplier, but if you watch the video explaining the code, you might be able to extend it to a different sized multiplier.
Each matrix has 9 elements, each of which is 8 bits in size. So I am passing the matrix as a 72 bit 1-Dimensional array in the design. The following table shows how the 2-D elements are mapped into the 1-D array.
Row Column Bitâ€™s Position in 1-D array 0 0 7:0 0 1 15:8 0 2 23:16 1 0 31:24 1 1 39:32 1 2 47:40 2 0 55:48 2 1 63:56 ...<br/>
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[[ This is a content summary only. Visit my website for full links, other content, and more! ]]<img src="http://feeds.feedburner.com/~r/VhdlCodingTipsAndTricks/~4/G8VJVXGklyg" height="1" width="1" alt=""/>vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com0http://vhdlguru.blogspot.com/2020/11/synthesizable-matrix-multiplier-in-vhdl.htmltag:blogger.com,1999:blog-2050962176404305705.post-40184805477993742032020-11-26T09:43:00.005+05:302020-12-04T22:13:48.747+05:30Signals and Variables in VHDL Every programming language has objects for storing values. VHDL too have them. Two of these object types are called Signals and Variables. They might look very similar for a beginner, but there are few fundamental differences between them.
Variables are assigned using the := operator. And signals are assigned with the <= operator.Variables can be declared and used only within a process/function/procedure but Signals can be declared and used anywhere.
A very fundamental difference:
In a block of statements, the statements with variables immediately take their values. Very similar to how it works in programming languages like C. But in a group of statements with Signals on the left hand side, the signals does not take it's new value until the process has suspended (either hit the bottom or hit a wait statement).
This can be further explained with the following example scenario.
Suppose I want to implement a swapping function in VHDL...<br/>
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[[ This is a content summary only. Visit my website for full links, other content, and more! ]]<img src="http://feeds.feedburner.com/~r/VhdlCodingTipsAndTricks/~4/mOZtzX757wQ" height="1" width="1" alt=""/>vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com0http://vhdlguru.blogspot.com/2020/11/signals-and-variables-in-vhdl.htmltag:blogger.com,1999:blog-2050962176404305705.post-35878513527492257182020-11-22T21:23:00.002+05:302020-11-22T21:23:30.146+05:30Simulating a VHDL/Verilog code using Modelsim SE This is a simple How-To video for ModelSim SE 10.4a version. If you are already familiar with this software tool then you may not need to watch this video.In this video, I am trying to show you:How to create a new project in ModelSim SE.Add VHDL codes to this project.Compile and simulate the codes.Few tips on the simulation part of the tool.
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[[ This is a content summary only. Visit my website for full links, other content, and more! ]]<img src="http://feeds.feedburner.com/~r/VhdlCodingTipsAndTricks/~4/sHUIK8_Z-ow" height="1" width="1" alt=""/>vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com0http://vhdlguru.blogspot.com/2020/11/simulating-vhdlverilog-code-using.htmltag:blogger.com,1999:blog-2050962176404305705.post-81694198472349875552020-11-06T21:09:00.002+05:302020-11-06T21:09:30.346+05:30Quaternary Signed Digit (QSD) Based Fast Adder In VHDL Quaternary Signed Digit is a base-4 number system where a number is represented by one of the following 7 digits : -3,-2,-1,0,1,2,3. The advantage of this number system is that it allows carry free addition, thus speeding up the addition process.
Fast adders based on QSD are typical and there are several papers on this. In this post I have written the VHDL code for a 4 digit(each input being 12 bits) QSD adder. With a bit of editing, this code can be extended to handle larger input numbers.
One thing to be careful about is that while checking online for information on QSD adders, I came upon several papers with some little mistakes here and there. Even though these typos are small, but it can take hours of your debugging time, as it did in my case. So I recommend cross checking any circuit diagram you see online across several references.
The Block diagram for the design is given below:
A QSD adder has two stages.
In the first...<br/>
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[[ This is a content summary only. Visit my website for full links, other content, and more! ]]<img src="http://feeds.feedburner.com/~r/VhdlCodingTipsAndTricks/~4/1-HFUXmcWyA" height="1" width="1" alt=""/>vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com0http://vhdlguru.blogspot.com/2020/11/quaternary-signed-digit-qsd-based-fast.htmltag:blogger.com,1999:blog-2050962176404305705.post-78883100912340891792020-02-05T17:44:00.000+05:302020-02-05T17:44:03.303+05:30Online Automatic Testbench Generator For VHDL and Simulation Using Xilinx VivadoHello guys, I am back here with another video.
If you are someone like me, who suddenly started using the Xilinx Vivado tool after using Xilinx ISE for a long time, then you might have noticed that Vivado currently doesn't support the Automatic testbench generation.
This is such a major disappointment for many of us. But luckily there are many online tools which does more or less the same. In this Video, I used the Doulos tool for creating testbenches for my VHDL designs. Once generated I tested the codes using the latest Vivado 2019.2 version.
Hope this is useful for you. Enjoy!
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[[ This is a content summary only. Visit my website for full links, other content, and more! ]]<img src="http://feeds.feedburner.com/~r/VhdlCodingTipsAndTricks/~4/enAVV2dxqX4" height="1" width="1" alt=""/>vipinhttp://www.blogger.com/profile/02146017720228354842noreply@blogger.com1http://vhdlguru.blogspot.com/2020/02/online-automatic-testbench-generator.html